WO2017121166A1

WO2017121166A1 - Apparatus and method for pixel data reodering

Info

Publication number: WO2017121166A1
Application number: PCT/CN2016/103315
Authority: WO
Inventors: Jing GU; Po-Yi Shih
Original assignee: Shanghai Jing Peng Invest Management Co., Ltd.
Priority date: 2016-01-13
Filing date: 2016-10-25
Publication date: 2017-07-20
Also published as: US20170200412A1; CN108604436A; EP3403256A4; EP3403257A1; CN108885855A; WO2016141777A3; WO2016141777A2; CN108604436B; EP3403257A4; US11176880B2; US20240071308A1; US20180293942A1; EP3403256A2; US11854477B2

Abstract

An apparatus includes a graphics pipeline and a pixel data reordering module. The graphics pipeline is configured to generate a plurality pieces of pixel data of a frame. The plurality pieces of pixel data of the frame are associated with a first order in which the plurality pieces of pixel data of the frame are to be provided to a display panel having an array of pixels. Each piece of pixel data of the frame corresponds to one pixel of the array of pixels. The array of pixels are divided into a plurality of groups of pixels. The pixel data reordering module is configured to cause the plurality pieces of pixel data of the frame to be obtained by the display panel in a second order. The second order is determined based on at least a manner in which the array of pixels are divided into the groups of pixels.

Description

APPARATUS AND METHOD FOR PIXEL DATA REODERING

CROSS REFERENCE TO RELATED APPLICATION

This application claims priority to International Application No. PCT/CN2016/070839, filed on January 13, 2016, entitled “DISPLAY DEVICE AND PIXEL CIRCUIT THEREOF, ” which is hereby incorporated by reference in its entirety.

BACKGROUND

The disclosure relates generally to display technologies, and more particularly, to pixel data processing.

Organic light emitting diode (OLED) , a self-light-emitting device, is emerging as a next-generation display because it does not require a backlight and has a high contrast, wide-viewing angle, fast response, and low power consumption. An active-array organic light emitting diode (AMOLED) display includes an active array of OLEDs generating light (luminescence) upon electrical activation that has been deposited or integrated onto a thin film transistor (TFT) array, which functions as a series of switches to control the current flowing to each individual light emitting element (subpixel) . Typically, this continuous current flow is controlled by a pixel circuit having at least two TFTs at each light emitting element to control emitting of light, with one TFT (aswitching transistor) to start and stop the charging of a storage capacitor and the second TFT (adriving transistor) to provide a supply voltage at the level needed to create a constant current to the OLED, thereby eliminating the need for the very high currents required for passive-array OLED operation.

In addition, a compensation circuit is usually needed for the pixel circuit for AMOLED because the brightness of the OLED changes very sensitive to the changes of currents. The driving transistor of each pixel circuit of an AMOLED display can have a different threshold voltage Vth from each other, which causes deterioration in the uniformity of brightness of display panels. Further, the IR-drop occurs with the supply voltage Vdd passing through each pixel circuit, so the brightness of the OLED gets poorer in the lower part of the display panel, which requires compensation as well. Various compensation circuit designs have been proposed and applied in known AMOLED displays, which all include extra transistors in addition to the switching and driving transistors. For example, FIGs. 47A-47B depict a circuit diagram and a timing diagram, respectively, of a known pixel circuit 4700 with a compensation circuit for driving an AMOLED display. Pixel circuit 4700 in FIG. 47A is one of the direct-charging type of pixel circuits in which the data signal is directly applied to the driving transistor when the switching transistor is turned on during the charging period. In FIG. 47A, in addition to a storage capacitor 4702, a switching transistor 4704, and a driving transistor 4706 for providing the driving current to an OLED 4708, five

more transistors

4710, 4712, 4714, 4716, 4718 form a compensation circuit to improve the uniformity of brightness of the AMOLED display. That is, seven transistors and one capacitor (7T1C) are used in the exemplary direct-charging type of pixel circuit 4700 of FIG. 47A for driving one OLED 4708.

Other known pixel circuits for an AMOLED display, e.g., 5T1C, 5T2C or 6T1C pixel circuits, also require a relative large number of transistors. For example, FIGs. 48A-48B depict a circuit diagram and a timing diagram, respectively, of a known pixel circuit 4800 with a compensation circuit for driving an AMOLED display. Pixel circuit 4800 in FIG. 48A is one of the coupling type of pixel circuits in which the data signal is coupled to the driving transistor via a capacitor during the charging period. In FIG. 48A, the data signal is coupled, via a storage capacitor 4802 when a switching transistor 4804 is turned on, to the gate electrode of a driving transistor 4806. In addition, five

more transistors

4810, 4812, 4814, 4816, 4818 form a compensation circuit to improve the uniformity of brightness of the AMOLED display. That is, seven transistors and one capacitor (7T1C) are used in the exemplary direct-charging type of pixel circuit 4800 of FIG. 48A for driving one OLED 4808.

In another example, FIGs. 49A-49B depict a circuit diagram and a timing diagram, respectively, of a known pixel circuit 4900 with a compensation circuit for driving an AMOLED display. Pixel circuit 4900 in FIG. 49A is another one of the coupling type of pixel circuits in which the data signal is coupled to the driving transistor via a capacitor during the charging period. In FIG. 49A, the data signal is coupled, via a coupling capacitor 4902 when a switching transistor 4904 is turned on, to the gate electrode of a driving transistor 4906. In addition to storage capacitor 4908, a coupling capacitor 4902, a switching transistor 4904, and a driving transistor 4906, three

more transistors

4912, 4914, 4916 form a compensation circuit to improve the uniformity of brightness of the AMOLED display. That is, five transistors and two capacitors (5T2C) are used in the exemplary direct-charging type of pixel circuit 4900 of FIG. 49A for driving one OLED 4910.

The extra transistors required in the compensation circuit for an AMOLED display can increase the complexity of pixels, which in turn causes low yield and small aperture ratio. The average number of transistors per OLED also becomes a bottleneck for continuously increasing the resolution and pixels per inch (PPI) of AMOLED display due to the large layout area, especially when competing with liquid crystal displays (LCDs) which only need one transistor per pixel in their pixel circuits.

Another parameter of AMOLED display or any other displays, such as LCD, is display latency (a. k. a. display lag) , which includes inter-frame latency and intra-frame latency. For example, low display latency (e.g., less than 20 ms) is desirable for virtual reality (VR) , augmented reality (AR) , and certain gaming applications to ensure good user experience. It is known to increase the refresh rate (a. k. a. display frequency, frame rate) to reduce the display latency. However, higher refresh rate in combination with the increasing of the resolution and PPI would dynastically increase the bandwidth of display data (e.g., pixel data) and thus, push the load on the graphics processor to its capacity limit, which becomes another bottleneck of modern display systems.

SUMMARY

In one example, an apparatus includes a graphics pipeline and a pixel data reordering module. The graphics pipeline is configured to generate a plurality pieces of pixel data of a frame. The plurality pieces of pixel data of the frame are associated with a first order in which the plurality pieces of pixel data of the frame are to be provided to a display panel having an array of pixels. Each piece of pixel data of the frame corresponds to one pixel of the array of pixels. The array of pixels are divided into a plurality of groups of pixels. The pixel data reordering module is configured to cause the plurality pieces of pixel data of the frame to be obtained by the display panel in a second order. The second order is determined based on at least a manner in which the array of pixels are divided into the groups of pixels.

In another example, an apparatus includes a graphics processing unit and control logic. The graphics processing unit includes a graphics pipeline and a pixel data reordering module. The graphics pipeline is configured to generate a plurality pieces of pixel data of a frame. The plurality pieces of pixel data of the frame are associated with a first order in which the plurality pieces of pixel data of the frame are to be provided to a display panel having an array of pixels. Each piece of pixel data of the frame corresponds to one pixel of the array of pixels. The array of pixels are divided into a plurality of groups of pixels. The pixel data reordering module is configured to cause the plurality pieces of pixel data of the frame to be obtained by the display panel in a second order. The second order is determined based on at least a manner in which the array of pixels are divided into the groups of pixels. The control logic is operatively coupled to the graphics processing unit and is configured to provide the plurality pieces of pixel data of the frame in the second order to the display panel.

In still another example, a display system includes a display panel, a graphics processing unit, and control logic. The display panel has an array of pixels divided into a plurality of groups of pixels . The graphics processing unit includes a graphics pipeline and a pixel data reordering module. The graphics pipeline is configured to generate a plurality pieces of pixel data of a frame. The plurality pieces of pixel data of the frame are associated with a first order in which the plurality pieces of pixel data of the frame are to be provided to the display panel. Each piece of pixel data of the frame corresponds to one pixel of the array of pixels. he pixel data reordering module is configured to cause the plurality pieces of pixel data of the frame to be obtained by the display panel in a second order. The second order is determined based on at least a manner in which the array of pixels are divided into the groups of pixels. The control logic is operatively coupled to the graphics processing unit and the display panel and is configured to provide the plurality pieces of pixel data of the frame in the second order to the display panel.

In yet another example, a system for VR or AR includes a display subsystem and a tracking subsystem. The display subsystem includes a display panel, a graphics processing unit, and control logic. The display panel has an array of pixels divided into a plurality of groups of pixels . The graphics processing unit includes a graphics pipeline and a pixel data reordering module. The graphics pipeline is configured to generate a plurality pieces of pixel data of a frame. The plurality pieces of pixel data of the frame are associated with a first order in which the plurality pieces of pixel data of the frame are to be provided to the display panel. Each piece of pixel data of the frame corresponds to one pixel of the array of pixels. he pixel data reordering module is configured to cause the plurality pieces of pixel data of the frame to be obtained by the display panel in a second order. The second order is determined based on at least a manner in which the array of pixels are divided into the groups of pixels. The control logic is operatively coupled to the graphics processing unit and the display panel and is configured to provide the plurality pieces of pixel data of the frame in the second order to the display panel. The tracking subsystem is operatively coupled to the display subsystem and is configured to track motion of a user of the system.

In a different example, a method of providing pixel data is provided. A plurality pieces of pixel data of a frame are provided. The plurality pieces of pixel data of the frame are associated with a first order in which the plurality pieces of pixel data of the frame are to be provided to a display panel having an array of pixels. Each piece of the plurality pieces of pixel data of the frame corresponds to one pixel of the array of pixels. The array of pixels are divided into a plurality of groups of pixels. A second order is determined based on at least a manner in which the array of pixels are divided into the plurality of groups of pixels. The plurality pieces of pixel data of the frame are caused to be obtained by the display panel in the second order.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments will be more readily understood in view of the following description when accompanied by the below figures and wherein like reference numerals represent like elements, wherein:

FIG. 1 is a block diagram illustrating an apparatus including a display and control logic in accordance with an embodiment；

FIGs. 2A-2C are side-view diagrams illustrating various example of the display shown in FIG. 1 in accordance with various embodiments；

FIGs. 3A-3C are depictions of various examples of dividing an array of subpixels into groups of subpixels in accordance with various embodiments；

FIG. 4 is a plan-view diagram illustrating the display shown in FIG. 1 including multiple drivers in accordance with an embodiment；

FIG. 5 is a block diagram illustrating the drivers shown in FIG. 4 in accordance with an embodiment；

FIG. 6 is a block diagram illustrating one example of the control logic shown in FIG. 1 in accordance with an embodiment；

FIG. 7 is a circuit diagram illustrating one example of a pixel circuit shared by two light emitting elements in accordance with an embodiment；

FIG. 8 is a timing diagram of the pixel circuit shown in FIG. 7 in accordance with an embodiment；

FIG. 9 is a circuit diagram illustrating a pixel circuit with a compensation circuit shared by two light emitting elements in the same column in accordance with an embodiment；

FIG. 10 is a timing diagram of the pixel circuit shown in FIG. 9 in accordance with an embodiment；

FIG. 11 is a depiction of an example of dividing a display frame into two sub-frames in the scan direction in accordance with an embodiment；

FIG. 12 is a depiction of an example of dividing a 6×3 subpixel array into two subpixel groups in the scan direction in accordance with an embodiment；

FIG. 13 is a timing diagram of pixel circuits for driving the 6×3 subpixel array shown in FIG. 12 in accordance with an embodiment；

FIG. 14 is a circuit diagram illustrating a light emitting circuit for providing light emitting signals for driving the 6×3 subpixel array shown in FIG. 12 in accordance with an embodiment；

FIGs. 15A-15B are circuit diagrams illustrating various examples of a light emitting control circuit for providing light emitting control signals for driving the 6×3 subpixel array shown in FIG. 12 in accordance with various embodiments；

FIG. 16 is another timing diagram of pixel circuits for driving the 6×3 subpixel array shown in FIG. 12 in accordance with an embodiment；

FIG. 17 is a circuit diagram illustrating a gate scanning driver for providing scan signals for scanning the 6×3 subpixel array shown in FIG. 12 in accordance with an embodiment；

FIG. 18 is a depiction of an example of dividing a 6×3 subpixel array into three subpixel groups in the scan direction in accordance with an embodiment；

FIG. 19 is a circuit diagram illustrating a pixel circuit with a compensation circuit shared by three light emitting elements in the same column in accordance with an embodiment；

FIG. 20 is a timing diagram of pixel circuits for driving the 6×3 subpixel array shown in FIG. 18 in accordance with an embodiment；

FIG. 21 is a circuit diagram illustrating a light emitting circuit for providing light emitting signals for driving the 6×3 subpixel array shown in FIG. 18 in accordance with an embodiment；

FIGs. 22A-22B are circuit diagrams illustrating various examples of a light emitting control circuit for providing light emitting control signals for driving the 6×3 subpixel array shown in FIG. 18 in accordance with various embodiments；

FIG. 23 is another timing diagram of pixel circuits for driving the 6×3 subpixel array shown in FIG. 18 in accordance with an embodiment；

FIG. 24 is a circuit diagram illustrating a gate scanning driver for providing scan signals for scanning the 6×3 subpixel array shown in FIG. 18 in accordance with an embodiment；

FIG. 25 is still another timing diagram of pixel circuits for driving the 6×3 subpixel array shown in FIG. 18 in accordance with an embodiment；

FIG. 26 is a depiction of an example of dividing a 6×3 subpixel array into six subpixel groups in the scan direction in accordance with an embodiment；

FIG. 27 is a circuit diagram illustrating a pixel circuit with a compensation circuit shared by six light emitting elements in the same column in accordance with an embodiment；

FIG. 28 is a timing diagram of pixel circuits for driving the 6×3 subpixel array shown in FIG. 26 in accordance with an embodiment；

FIG. 29 is a circuit diagram illustrating a light emitting circuit for providing light emitting signals for driving the 6×3 subpixel array shown in FIG. 26 in accordance with an embodiment；

FIGs. 30A-30B are circuit diagrams illustrating various examples of a light emitting control circuit for providing light emitting control signals for driving the 6×3 subpixel array shown in FIG. 26 in accordance with various embodiments；

FIG. 31 is another timing diagram of pixel circuits for driving the 6×3 subpixel array shown in FIG. 26 in accordance with an embodiment；

FIG. 32 is a circuit diagram illustrating a gate scanning driver for providing scan signals for scanning the 6×3 subpixel array shown in FIG. 26 in accordance with an embodiment；

FIGs. 33A-33C are depictions of various examples of dividing a display frame into multiple sub-frames in the scan direction in accordance with various embodiments；

FIGs. 34A-34C are depictions of various examples of dividing a 2×6 subpixel array into multiple subpixel groups in the data direction in accordance with various embodiments；

FIG. 35 is a depiction of an example of dividing a display frame into four sub-frames in the scan and data directions in accordance with an embodiment；

FIG. 36 is a depiction of dividing a 6×2 subpixel array into four subpixel groups in the scan and data directions in accordance with an embodiment；

FIG. 37 is a circuit diagram illustrating a pixel circuit with a compensation circuit shared by four light emitting elements in a 2×2 subpixel block in accordance with an embodiment；

FIG. 38 is a timing diagram of pixel circuits for driving the 6×2 subpixel array shown in FIG. 36 in accordance with an embodiment；

FIG. 39 is a circuit diagram illustrating a light emitting circuit for providing light emitting signals for driving the 6×2 subpixel array shown in FIG. 36 in accordance with an embodiment；

FIGs. 40A-40B are circuit diagrams illustrating various examples of a light emitting control circuit for providing light emitting control signals for driving the 6×2 subpixel array shown in FIG. 36 in accordance with various embodiments；

FIG. 41 is another timing diagram of pixel circuits for driving the 6×2 subpixel array shown in FIG. 36 in accordance with an embodiment；

FIG. 42 is a circuit diagram illustrating a gate scanning driver for providing scan signals for scanning the 6×2 subpixel array shown in FIG. 36 in accordance with an embodiment；

FIG. 43 is a circuit diagram illustrating another example of a pixel circuit shared by two light emitting elements in accordance with an embodiment；

FIG. 44 is a circuit diagram illustrating one example a pixel circuit with a compensation circuit shared by multiple light emitting elements in accordance with an embodiment；

FIG. 45 is a circuit diagram illustrating another example of a pixel circuit with a compensation circuit shared by multiple light emitting elements in accordance with an embodiment；

FIG. 46 is a flow chart of a method for driving a display having an array of subpixels in accordance with an embodiment；

FIG. 47A-47B are circuit diagram and timing diagram, respectively, illustrating one example of a prior art pixel circuit with a compensation circuit for driving an AMOLED display；

FIG. 48A-48B are circuit diagram and timing diagram, respectively, illustrating another example of a prior art pixel circuit with a compensation circuit for driving an AMOLED display；

FIG. 49A-49B are circuit diagram and timing diagram, respectively, illustrating still another example of a prior art pixel circuit with a compensation circuit for driving an AMOLED display；

FIG. 50 is a block diagram illustrating one example of the processor shown in FIG. 1 in accordance with an embodiment；

FIG. 51 is a block diagram illustrating another example of the control logic shown in FIG. 1 in accordance with an embodiment；

FIG. 52 is a block diagram illustrating a VR/AR system in accordance with an embodiment；

FIG. 53 is a flow chart of a method for processing pixel data in accordance with an embodiment；

FIG. 54 is a flow chart of one example of a method for reordering pixel data in accordance with an embodiment；

FIG. 55 is a flow chart of another example of a method for reordering pixel data in accordance with an embodiment；

FIG. 56 is a flow chart of still another example of a method for reordering pixel data in accordance with an embodiment；

FIGs. 57A and 57B are depictions of pixel data reordering from a first pixel data order at a frame buffer to a second pixel data order at a display panel in accordance with an embodiment； and

FIG. 58 illustrates one example of a message including a plurality pieces of pixel data in a frame in accordance with an embodiment.

DETAILED DESCRIPTION

In the following detailed description, numerous specific details are set forth by way of examples in order to provide a thorough understanding of the relevant disclosures. However, it should be apparent to those skilled in the art that the present disclosure may be practiced without such details. In other instances, well known methods, procedures, systems, components, and/or circuitry have been described at a relatively high-level, without detail, in order to avoid unnecessarily obscuring aspects of the present disclosure.

Throughout the specification and claims, terms may have nuanced meanings suggested or implied in context beyond an explicitly stated meaning. Likewise, the phrase “in one embodiment/example” as used herein does not necessarily refer to the same embodiment and the phrase “in another embodiment/example” as used herein does not necessarily refer to a different embodiment. It is intended, for example, that claimed subject matter include combinations of example embodiments in whole or in part.

In general, terminology may be understood at least in part from usage in context. For example, terms, such as “and” , “or” , or “and/or, ” as used herein may include a variety of meanings that may depend at least in part upon the context in which such terms are used. Typically, “or” if used to associate a list, such as A, B or C, is intended to mean A, B, and C, here used in the inclusive sense, as well as A, B or C, here used in the exclusive sense. In addition, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

As will be disclosed in detail below, among other novel features, the display system and pixel circuit thereof disclosed herein provide the ability to reduce the average number of transistors (e.g., TFTs) required for each light emitting element (e.g., OLED) while maintaining the same compensation effect for brightness uniformity of displays. For example, in this present disclosure, the array of light emitting elements can be divided into multiple groups, each of which emits lights in a respective sub-frame in one frame period； multiple light emitting elements from each group can thus share the same pixel circuit. The frame-division and pixel circuit-sharing scheme disclosed herein is suitable for a variety of applications, including but not limited to, displays for VR/AR devices and handheld devices. Compared with known solutions, the yield and display resolution/PPI can be increased by the frame-division and pixel circuit-sharing scheme disclosed herein. Because the complexity of gate scanning driver and light emitting driver can be simplified and/or the number of wires connecting the gate scanning and light emitting drivers with the pixel circuits can be reduced, the display edges’ area for handheld devices can also be reduced. In one embodiment of the present disclosure, the array of light emitting elements can be divided in the scan direction. In other words, each group of light emitting elements includes one or more rows of light emitting elements. As a result, the charging time for each light emitting element is not decreased compared with the known solutions.

In addition to reducing the average number of transistors in each pixel circuit of a display panel, the apparatus and method disclosed herein can also reduce the display latency of a display system without increasing the refresh rate. For OLED displays such as an AMOLED display, a gate driver, e.g., a gate driver on array (GOA) , and a light emitting driver, e.g., an emission driver on array (EOA) , are used to control each OLED to be charged and subsequently emit a light in each frame. For example, for a full high-definition (FHD) display with a resolution of 1920×1080 and a refresh rate of 60 Hz, each frame is 16.7 ms and each scan is 8.7 μs. That is, in one frame, each OLED is first scanned and charged for 8.7 ns and then emits light during the rest of the frame period until it is refreshed in the subsequent frame. Because the charging period (i.e., the scan period of 8.7 μs) is much shorter compared to the frame period (16.7 ms) , each OLED can be considered emitting a light during the entire frame period in the traditional AMOLED display. However, in some emerging display applications, it may not be always necessary to turn on each subpixel during the whole frame period. For example, for certain VR displays (e.g., in the VR headsets) , after being charged during the scan, each subpixel is only turned on to emit light for 15％of the entire frame period. All the subpixels may be turned on during the same light emitting period or one after another in different display modes of the VR displays. Nevertheless, the light emitting time period is only a portion of the entire frame period. This so called “black frame insertion” (BFI) method has been used by VR displays to reduce motion blur.

The present disclosure recognizes that because each subpixel is not always necessarily turned on during the entire frame period (e.g., because of BFI in VR displays) , the array of subpixels or pixels on the display can be divided into groups so that each group can sequentially emit lights in a respective light emitting period with a frame period. That is, an entire frame period can include a number of light emitting periods, each of which can be used by one of a number of subpixels to emit a light. Thus, those subpixels can share the same pixel circuit to reduce the average transistor per subpixel and layout area. For example, for the VR displays in which the light emitting time period is 15％of the entire frame period, a maximum of six light emitting time periods can be included in one frame period and thus, a maximum of six subpixels can share the same pixel circuit. In other words, each frame can be divided into sub-frames, and each group of subpixels sequentially emits lights in a respective sub-frame period within a frame period. As a result, both the number of pixel circuits (and transistors and capacitors therein) required in a display panel and the display latency are reduced by the frame-division and pixel circuit-sharing scheme disclosed herein.

It is to be appreciated that the frame-division and pixel circuit-sharing scheme is not only applicable for VR displays. Even for the traditional displays in which a longer light emitting period is desired to ensure the sufficient brightness of the display images, the frame-division and pixel circuit-sharing scheme is also feasible. For example, the driving current for each OLED in an AMOLED display can be increased to compensate for the reduction of brightness due to the shorter light emitting period. It is also to be appreciated that the frame-division scheme may be applicable for other display types, such as but not limited to LCD, as well for reducing the display latency without increasing the load on the graphics processor.

Additional novel features will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following and the accompanying drawings or may be learned by production or operation of the examples. The novel features of the present disclosure may be realized and attained by practice or use of various aspects of the methodologies, instrumentalities, and combinations set forth in the detailed examples discussed below.

FIG. 1 illustrates an apparatus 100 including a display 102 and control logic 104. Apparatus 100 may be any suitable device, for example, a VR/AR device (e.g., VR headset, etc.) , handheld device (e.g., dumb or smart phone, tablet, etc. ) , wearable device (e.g., eyeglasses, wrist watch, etc. ) , automobile control station, gaming console, television set, laptop computer, desktop computer, netbook computer, media center, set-top box, global positioning system (GPS) , electronic billboard, electronic sign, printer, or any other suitable device. In this example, display 102 is operatively coupled to control logic 104 and is part of apparatus 100, such as but not limited to, a head-mounted display, computer monitor, television screen, dashboard, electronic billboard, or electronic sign. Display 102 may be an OLED display, liquid crystal display (LCD) , E-ink display, electroluminescent display (ELD) , billboard display with LED or incandescent lamps, or any other suitable type of display.

Control logic 104 may be any suitable hardware, software, firmware, or combination thereof, configured to receive display data 106 and render the received display data 106 (e.g., pixel data) into control signals 108 for driving the subpixels on display 102. Control signals 108 are used for controlling writing of data to the subpixels and directing operations of display 102. For example, subpixel rendering algorithms for various subpixel arrangements may be part of control logic 104 or implemented by control logic 104. As described in detail below with respect to FIG. 6, control logic 104 in one example may include a control signal generating module 602 having a timing controller (TCON) 608 and a clock generator 610, a data converting module 604 having a storing unit 612, and a data reconstructing unit 614, and a data interface 606. Control logic 104 may include any other suitable components, such as an encoder, a decoder, one or more processors, controllers, and storage devices. Control logic 104 may be implemented as a standalone integrated circuit (IC) chip, such as an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA) . Apparatus 100 may also include any other suitable component such as, but not limited to, a speaker 110 and an input device 112, e.g., a mouse, keyboard, remote controller, handwriting device, camera, microphone, scanner, etc.

In one example, apparatus 100 may be a laptop or desktop computer having a display 102. In this example, apparatus 100 also includes a processor 114 and memory 116. Processor 114 may be, for example, a graphic processor (e.g., GPU) , an application processor (AP) , a general processor (e.g., APU, accelerated processing unit； GPGPU, general-purpose computing on GPU) , or any other suitable processor. Memory 116 may be, for example, a discrete frame buffer or a unified memory. Processor 114 is configured to generate display data 106 in display frames and temporally store display data 106 in memory 116 before sending it to control logic 104. Processor 114 may also generate other data, such as but not limited to, control instructions 118 or test signals, and provide them to control logic 104 directly or through memory 116. Control logic 104 then receives display data 106 from memory 116 or from processor 114 directly.

In another example, apparatus 100 may be a television set having display 102. In this example, apparatus 100 also includes a receiver 120, such as but not limited to, an antenna, radio frequency receiver, digital signal tuner, digital display connectors, e.g., high-definition multimedia interface (HDMI) , digital visual interface (DVI) , DisplayPort (DP) , universal serial bus (USB) , Bluetooth, WiFi receiver, or Ethernet port. Receiver 120 is configured to receive display data 106 as an input of apparatus 100 and provide the native or modulated display data 106 to control logic 104.

In still another example, apparatus 100 may be a handheld or VR/AR device, such as a smart phone, a tablet, or a VR headset. In this example, apparatus 100 includes processor 114, memory 116, and receiver 120. Apparatus 100 may both generate display data 106 by processor 114 and receive display data 106 through receiver 120. For example, apparatus 100 may be a handheld or VR/AR device that works as both a mobile television and a mobile computing device. In any event, apparatus 100 at least includes display 102 and control logic 104 as described below in detail.

FIG. 2A is a side-view diagram illustrating one example of display 102 including a group of

subpixels

202, 204, 206, 208. Display 102 may be any suitable type of display, for example, OLED displays, such as an AMOLED display, or any other suitable display. Display 102 may include a display panel 210 operatively coupled to control logic 104. The example shown in FIG. 2A illustrates a side-by-side (a. k. a. lateral emitter) OLED color patterning architecture in which one color of light-emitting material is deposited through metal shadow mask while the other color areas are blocked by the mask.

In this example, display panel 210 includes a light emitting layer 214 and a driving circuit layer 216. As shown in FIG. 2A, light emitting layer 214 includes a plurality of light emitting elements (e.g., OLEDs in this example) 218, 220, 222, 224, corresponding to a plurality of

subpixels

202, 204, 206, 208, respectively. A, B, C, and D in FIG. 2A denote OLEDs in different colors, such as but not limited to, red, green, blue, yellow, cyan, magenta, or white. Light emitting layer 214 also includes a black array 226 disposed between

OLEDs

218, 220, 222, 224, as shown in FIG. 2A. Black array 226, as the borders of

subpixels

202, 204, 206, 208, is used for blocking lights coming out from the parts outside

OLEDs

218, 220, 222, 224. Each

OLED

218, 220, 222, 224 in light emitting layer 214 can emit a light in a predetermined color and brightness.

In this example, driving circuit layer 216 includes a plurality of

pixel circuits

228, 230, 232, 234, each of which includes one or more thin film transistors (TFTs) , corresponding to OLEDs 218, 220, 222, 224 of

subpixels

202, 204, 206, 208, respectively.

Pixel circuits

228, 230, 232, 234 may be individually addressed by control signals 108 from control logic 104 and configured to drive corresponding

subpixels

202, 204, 206, 208, by controlling the light emitting from

respective OLEDs

218, 220, 222, 224, according to control signals 108. Driving circuit layer 216 may further include one or more drivers (not shown) formed on the same substrate as

pixel circuits

228, 230, 232, 234. The on-panel drivers may include circuits for controlling light emitting, gate scanning, and data writing as described below in detail. Scan lines and data lines are also formed in driving circuit layer 216 for transmitting scan signals and data signals, respectively (as part of control signals 108) , from the drivers to each

pixel circuit

228, 230, 232, 234. Display panel 210 may include any other suitable component, such as one or more glass substrates, polarization layers, or a touch panel (not shown) as known in the art.

Pixel circuits

228, 230, 232, 234 and other components in driving circuit layer 216 in this example are formed on a low temperature polycrystalline silicon (LTPS) layer deposited on a glass substrate, and the TFTs in each

pixel circuit

228, 230, 232, 234 are p-type transistors (e.g., PMOS LTPS-TFTs) . In some embodiments, the components in driving circuit layer 216 may be formed on an amorphous silicon (a-Si) layer, and the TFTs in each pixel circuit may be n-type transistors (e.g., NMOS TFTs) . In some embodiments, the TFTs in each pixel circuit may be organic TFTs (OTFT) or indium gallium zinc oxide (IGZO) TFTs.

As shown in FIG. 2A, each

subpixel

202, 204, 206, 208 is formed by at least an

OLED

218, 220, 222, 224 driven by a corresponding

pixel circuit

228, 230, 232, 234. Each OLED may be formed by a sandwich structure of an anode, an organic light-emitting layer, and a cathode, as known in the art. Depending on the characteristics (e.g., material, structure, etc. ) of the organic light-emitting layer of the respective OLED, a subpixel may present a distinct color and brightness. Each

OLED

218, 220, 222, 224 in this example is a top-emitting OLED. In some embodiments, the OLED may be in a different configuration, such as a bottom-emitting OLED. In one example, one pixel may consist of three adjacent subpixels, such as subpixels in the three primary colors (red, green, and blue) to present a full color. In another example, one pixel may consist of four adjacent subpixels, such as subpixels in the three primary colors (red, green, and blue) and the white color. In still another example, one pixel may consist of two adjacent subpixels. For example, subpixels A 202 and B 204 may constitute one pixel, and subpixels C 206 and D 208 may constitute another pixel. Here, since the display data 106 is usually programmed at the pixel level, the two subpixels of each pixel or the multiple subpixels of several adjacent pixels may be addressed collectively by subpixel rendering to present the appropriate brightness and color of each pixel, as designated in display data 106 (e.g., pixel data) , with the help of subpixel rendering. However, it is to be appreciated that, in some embodiments, display data 106 may be programmed at the subpixel level such that display data 106 can directly address individual subpixel without the need of subpixel rendering. Because it usually requires three primary colors (red, green, and blue) to present a full color, specifically designed subpixel arrangements are provided for display 102 in conjunction with subpixel rendering algorithms to achieve an appropriate apparent color resolution.

The example shown in FIG. 2A illustrates a side-by-side patterning architecture in which one color of light-emitting material is deposited through metal shadow mask while the other color areas are blocked by the mask. In another example, a white OLEDs with color filters (WOLED+CF) patterning architecture can be applied to display panel 210. In the WOLED+CF architecture, a stack of light-emitting materials form a light emitting layer of white light. The color of each individual subpixel is defined by another layer of color filters in different colors. As the organic light-emitting materials do not need to be patterned through the metal shadow mask, the resolution and display size can be increased by the WOLED+CF patterning architecture. FIG. 2B illustrates an example of a WOLED+CF patterning architecture applied to display panel 210. Display panel 210 in this example includes driving circuit layer 216, a light emitting layer 236, a color filter layer 238, and an encapsulating layer 239. In this example, light emitting layer 236 includes a stack of light emitting sub-layers and emits the white light. Color filter layer 238 may be comprised of a color filter on array having a plurality of

color filters

240, 242, 244, 246 corresponding to

subpixels

202, 204, 206, 208, respectively. A, B, C, and D in FIG. 2B denote four different colors of filters, such as but not limited to, red, green, blue, yellow, cyan, magenta, or white.

Color filters

240, 242, 244, 246 may be formed of a resin film in which dyes or pigments having the desired color are contained. Depending on the characteristics (e.g., color, thickness, etc. ) of the respective color filter, a subpixel may present a distinct color and brightness. Encapsulating layer 239 may include an encapsulating glass substrate or a substrate fabricated by the thin film encapsulation (TFE) technology. Driving circuit layer 216 may be comprised of an array of pixel circuits including LTPS, IGZO, or OTFT transistors. Display panel 210 may include any other suitable component, such as polarization layers, or a touch panel (not shown) as known in the art.

In still another example, a blue OLEDs with transfer color filters (BOLED+transfer CF) patterning architecture can be applied to display panel 210 as well. In the BOLED+transfer CF architecture, a light-emitting material of blue light is deposited without a metal shadow mask, and the color of each individual subpixel is defined by another layer of transfer color filters for different colors. FIG. 2C illustrates an example of a BOLED+transfer CF patterning architecture applied to display panel 210. Display panel 210 in this example includes driving circuit layer 216, a light emitting layer 248, a color transfer layer 250, and an encapsulating layer 251. Light emitting layer 248 in this example emits the blue light and can be deposited without a metal shadow mask. It is to be appreciated that in some embodiments, light emitting layer 248 may emit other colors of light. Color transfer layer 250 may be comprised of a transfer color filters on array having a plurality of

transfer color filters

252, 254, 256, 258 corresponding to

subpixels

202, 204, 206, 208, respectively. A, B, C, and D in FIG. 2C denote four different colors of transfer color filters, such as but not limited to, red, green, blue, yellow, cyan, magenta, or white. Each type of transfer color filter may be formed of a color changing material. Depending on the characteristics (e.g., color, thickness, etc. ) of the respective transfer color filter, a subpixel may present a distinct color and brightness. Encapsulating layer 251 may include an encapsulating glass substrate or a substrate fabricated by the TFE technology. Driving circuit layer 216 may be comprised of an array of pixel circuits including LTPS, IGZO, or OTFT transistors. Display panel 210 may include any other suitable component, such as polarization layers, or a touch panel (not shown) as known in the art.

The frame-division and pixel circuit-sharing scheme disclosed herein is suitable for any known OLED patterning architectures, including but not limited to, the side-by-side, WOLED+CF, and BOLED+CCM patterning architectures as described above. Although FIGs. 2A-2C are illustrated as an OLED display, it is to be appreciated that it is provided for an exemplary purpose only and without limitations.

FIGs. 3A-3C are depictions of various examples of dividing an array of subpixels into groups of subpixels in accordance with various embodiments. In FIG. 3A, a frame is divided into sub-frames in the scan direction (i.e., along the vertical direction of the display) . In other words, an array of subpixels is divided into a plurality of groups of subpixels in the scan direction. Each group of subpixels includes one or more rows of subpixels. Although only two sub-frames (groups of subpixels) are shown in FIG. 3A, it is to be appreciated that the number of sub-frames (groups of subpixels) can be k, where k is an integer larger than 1, e.g., 2, 3, 4, 5, 6, …. In some embodiments, the array of subpixels may be evenly divided into k groups of subpixels in the scan direction (i.e., each group of subpixels has the same number of rows of subpixels) . In those embodiments, k is the factor of the total number of rows of subpixels. In some embodiments, each group of subpixels may have different numbers of rows of subpixels so that k can be any integer larger than 1.

It is also understood that the manner in which the array of subpixels is divided into the groups of subpixels in the scan direction is not limited. In FIG. 3A, adjacent rows of subpixels are divided into different groups of subpixels. That is, one group of subpixels includes all the odd rows of subpixels, and the other group of subpixels includes all the even rows of subpixels. As a result, one subpixel from the first group of subpixels can share the same pixel circuit with another subpixel from the second group of subpixels. In some embodiments, the two subpixels sharing the same pixel circuit may be the subpixels having the minimum distance between each other in the two groups of subpixels in order to minimize the connection wires. For example, every two adjacent subpixels in the same column can share the same pixel circuit in the example shown in FIG. 3A. It is to be appreciated that for scan-direction-division, because subpixels in different rows may share the same pixel circuit, they can share the same scan line as well. Thus, the total number of scan lines can be reduced by the scan-direction-division. Furthermore, for scan-direction-division, the charging period for each subpixel is not reduced. In another example, for a display having N rows of subpixels, the first group of subpixels may include the top half of all rows of subpixels, i.e., 1st row to N/2th row, and the second group of subpixels may include the bottom half of all rows of subpixels, i.e., (N/2) +1th row to Nth row. As understood from the above-mentioned examples, the array of subpixels may be divided into groups of subpixels in the scan direction in various ways, as long as each group of subpixel includes one or more rows of subpixels. It is also understood that the array of subpixels is not physically divided, but is instead logically divided into groups of subpixels, so that each group of subpixels sequentially emits lights in a respective sub-frame period within a frame period as described below in detail.

In FIG. 3B, a frame is divided into sub-frames in the data direction (i.e., along the horizontal direction of the display) . In other words, an array of subpixels is divided into a plurality of groups of subpixels in the data direction. Each group of subpixels includes one or more columns of subpixels. Although only two sub-frames (groups of subpixels) are shown in FIG. 3B, it is to be appreciated that the number of sub-frames (groups of subpixels) can be k, where k is an integer larger than 1, e.g., 2, 3, 4, 5, 6, …. In some embodiments, the array of subpixels are evenly divided into k groups of subpixels in the data direction (i.e., each group of subpixels has the same number of columns of subpixels) . In those embodiments, k is the factor of the total number of columns of subpixels. In some embodiments, each group of subpixels may have different numbers of columns of subpixels, so that k can be any integer larger than 1.

It is also understood that the manner in which the array of subpixels is divided into the groups of subpixels in the data direction is not limited. In FIG. 3B, adjacent columns of subpixels are divided into different groups of subpixels. That is, one group of subpixels includes all the odd columns of subpixels, and the other group of subpixels includes all the even columns of subpixels. As a result, one subpixel from the first group of subpixel shares the same pixel circuit with one subpixel from the second group of subpixel. In some embodiments, the two subpixels sharing the same pixel circuit may be the subpixels having the minimum distance between each other in the two groups of subpixel in order to minimize the connection wires. For example, every two adjacent subpixels in the same row can share the same pixel circuit in the example shown in FIG. 3B. It is to be appreciated that for data-direction-division, because subpixels in different columns may share the same pixel circuit, they can share the same data line as well. Thus, the total number of data lines can be reduced by the data-direction-division. Furthermore, for data-direction-division, the charging period for each subpixel is reduced as well. In another example, for a display having M columns of subpixels, the first group of subpixels may include the left half of all columns of subpixels, i.e., 1st column to M/2th column, and the second group of subpixels may include the right half of all columns of subpixels, i.e., (M/2) +1th column to Mth column. As understood from the above-mentioned examples, the array of subpixels may be divided into groups of subpixels in the data direction in various ways, as long as each group of subpixel includes one or more columns of subpixels. It is also understood that the array of subpixels is not physically divided, but instead, is logically divided into groups of subpixels, so that each group of subpixels sequentially emits lights in a respective sub-frame period within a frame period as described below in detail.

In FIG. 3C, a frame is divided into sub-frames in both the scan direction and the data direction. In other words, an array of subpixels is divided into a plurality of groups of subpixels in the scan and data directions. Each group of subpixels includes a number of blocks of subpixels (e.g., a 2×2 subpixel block or a 2×3 subpixel block) . In FIG. 3C, the array of subpixels is divided into four groups of subpixels, each of which includes a number of 2×2 subpixel blocks. The example in FIG. 3C is suitable for subpixel arrangements in which one pixel consists of two subpixels because of the layout uniformity. Although only four sub-frames (groups of subpixels) are shown in FIG. 3C, it is to be appreciated that the number of sub-frames (groups of subpixels) can be k, where k is an integer larger than 1, e.g., 2, 3, 4, 5, 6, …, and each sub-frame (group of subpixels) includes a number of p×q subpixel blocks. In another example, the array of subpixels may be divided into six groups of subpixels, each of which includes a number of 2×3 subpixel blocks. The division in the above example is suitable for real RGB displays in which one pixel consists of red, green, and blue subpixels because of the layout uniformity. In some embodiments, the array of subpixels is evenly divided into k groups of subpixels in the scan and data directions. In those embodiments, p is the factor of the total number of rows of subpixels, and q is the factor of the total number of columns of subpixels.

It is also understood that the manner in which the array of subpixels is divided into the groups of subpixels in the scan and data directions is not limited. In another example, each of four groups of subpixels may be a quadrant of the array of subpixels, i.e., the top-left quarter, top-right quarter, bottom-left quarter, or bottom-right quarter. As understood from the above-mentioned examples, the array of subpixels may be divided into groups of subpixels in the scan and data directions in various ways, as long as each group of subpixels includes one or more blocks of subpixels. It is also understood that the array of subpixels is not physically divided, but instead, is logically divided into groups of subpixels, so that each group of subpixels sequentially emits lights in a respective sub-frame period within a frame period as described below in detail.

FIG. 4 is a plan-view diagram illustrating display 102 shown in FIG. 1 including multiple drivers in accordance with an embodiment. Display panel 210 in this example includes an array of subpixels 400 (e.g., OLEDs) , a plurality of pixel circuits (not shown) , and multiple on-panel drivers including a light emitting driver 402, a gate scanning driver 404, and a source writing driver 406. Array of subpixels 400 may be divided into k groups of subpixels, where k is an integer larger than 1. As described above, the division may be made in the scan direction, data direction, or scan and data directions. The pixel circuits are operatively coupled to array of subpixels 400 and on-

panel drivers

402, 404, and 406. Each pixel circuit may be shared by k subpixels from each of the k groups of subpixels. That is, each pixel circuit is configured to drive k corresponding subpixels. For example, if array of subpixels 400 is divided into two groups of subpixels in the scan direction as shown in FIG. 3A, then each pixel circuit may be shared by two adjacent subpixels in the same column (one subpixel from the first group of subpixels having all odd rows of subpixels, and one subpixel from the second group of subpixels having all even rows of subpixels) .

Light emitting driver 402 in this example is configured to cause each of the k groups of subpixels to sequentially emit lights in a respective one of k sub-frame periods within a frame period. Turning now to FIG. 5, in one example, light emitting driver 402 receives control signals 506 (as part of control signals 108) from control logic 104 and provides a set of light emitting control signals 510 and a set of light emitting signals 512 to the pixel circuits of array of subpixels 400. Control signals 506 may include one or more clock signals CKE and enable signals, such as the start emission STE signals. It is to be appreciated that although one light emitting driver 402 is illustrated in FIG. 4, in some embodiments, multiple light emitting drivers may work in conjunction with each other. Light emitting driver 402 in this example includes a light emitting control circuit 502 and a light emitting circuit 504, each of which may include one or more shift registers.

As described below in detail, light emitting circuit 504 in this example is configured to provide k sets of light emitting signals EM1-EMk for the k groups of subpixels, respectively, to the plurality of pixel circuits. Each of the k sets of light emitting signals EM1-EMk causes the subpixels in the respective group of subpixels to emit lights in the respective sub-frame period within a frame period. In this example, light emitting circuit 504 provides light emitting signals 512 based on the clock signals CKE and a set of start emission signals STE. Light emitting control circuit 502 in this example is configured to provide one or more light emitting control signals EMC1-EMCn to the plurality of pixel circuits. Each of the light emitting control signals EMC1-EMCn controls each of the k subpixels sharing the same pixel circuit to sequentially emit a light in the sub-frame period within a frame period. In this example, light emitting control circuit 502 provides light emitting control signals 510 based on the clock signals CKE and another start emission signals STE. The STE signal for light emitting control circuit 502 may be a logical disjunction of the set of STE signals for light emitting circuit 504. In one example, for PMOS pixel circuits, each of the plurality of light emitting signals EM1-EMk is low during a respective one of the light emitting periods within a frame period, and the corresponding light emitting control signal EMCn is low in each of the light emitting periods within the frame period. In another example, for NMOS pixel circuits, each of the plurality of light emitting signals EM1-EMk is high during a respective one of the light emitting periods within a frame period, and the corresponding light emitting control signal EMCn is high in each of the light emitting periods within the frame period.

In some embodiments as described below in detail with respect to FIGs. 15B, 22B, 30B, and 40B, the light emitting control signals EMC1-EMCn may be provided by light emitting control circuit 502 based on the light emitting signals EM1-EMk. In one example, for PMOS pixel circuits, light emitting control circuit 502 may include AND gates, each of which provides one of the light emitting control signals EMC1-EMCn based on two or more of the light emitting signals EM1-EMk depending on the frame-division manner. In another example, for NMOS pixel circuits, light emitting control circuit 502 may include OR gates, each of which provides one of the light emitting control signals EMC1-EMCn based on two or more of the light emitting signals EM1-EMk depending on the frame-division manner.

Returning to FIG. 4, gate scanning driver 404 in this example applies a plurality of scan signals, which are generated based on the control signals from control logic 104, to the scan lines (a.k.a. gate lines) for each row of subpixels in array of subpixels 400 in a sequence. For example, as shown in FIG. 5, gate scanning driver 404 receives control signals 508 (as part of control signals 108) from control logic 104 and provides a set of scan signals 514 to the pixel circuits of array of subpixels 400. Control signals 508 may include one or more clock signals CKV and enable signals, such as start vertical STV signals. As described below in detail, the scan signals S0-Sn are applied to the gate electrode of a switching transistor of each pixel circuit during the scan/charging period in each frame period to turn on the switching transistor so that the data signal for the corresponding subpixel can be written by source writing driver 406. In one example, each of the scan signals S0-Sn causes each of the k subpixels sharing the same pixel circuit to be sequentially charged in the respective sub-frame period within a frame period. As mentioned above, for scan-direction-division or scan/data-direction-division of array of subpixels 400, multiple rows of subpixels may share the same scan line, and thus, the total number of scan lines is less than the total number of rows of subpixels. It is to be appreciated that although one gate scanning driver 404 is illustrated in FIG. 4, in some embodiments, multiple gate scanning drivers may work in conjunction with each other to scan array of subpixels 400.

Source writing driver 406 in this example is configured to write display data received from control logic 104 into array of subpixels 400 in each frame. For example, source writing driver 406 may simultaneously apply data signals to data lines (a. k. a. source lines) for each column of subpixels. That is, source writing driver 406 may include one or more shift registers, digital-analog converter (DAC) , multiplexers (MUX) , and arithmetic circuit for controlling a timing of application of voltage to the source electrode of the switching transistor of each pixel circuit (i.e., during the scan/charging period in each frame period) and a magnitude of the applied voltage according to gradations of the display data. As each frame is divided into sub-frames, and groups of subpixels sequentially emit lights in the respective sub-frame period in a frame period, original (native) display data 106 received from processor 114 or receiver 120 may not be used directly by source writing driver 406. In one example, control logic 104 may convert original display data 106 into converted display data based on a manner in which array of subpixels 400 is divided into the k groups of subpixels (e.g., a sequence in which each row of subpixels is scanned within the frame period) , such that source writing driver 406 writes the converted display data into array of subpixels 400. As described above, for data-direction-division or scan/data-direction division of array of subpixels 400, multiple columns of subpixels may share the same data line, and thus, the total number of data lines is less than the total number of columns of subpixels. It is to be appreciated that although one source writing driver 406 is illustrated in FIG. 4, in some embodiments, multiple source writing drivers may work in conjunction with each other to apply the data signals to the data lines for each column of subpixels.

FIG. 6 is a block diagram illustrating one example of control logic 104 shown in FIG. 1 in accordance with an embodiment. In this example, control logic 104 is an integrated circuit (but may alternatively include a state machine made of discrete logic and other components) , which provides an interface function between processor 114/memory 116 and display 102. Control logic 104 may provide various control signals 108 with suitable voltage, current, timing, and de-multiplexing, to make display 102 to show the desired text or image. Control logic 104 may be an application-specific microcontroller and may include storage units such as RAM, flash memory, EEPROM, and/or ROM, which may store, for example, firmware and display fonts. In this example, control logic 104 includes a control signal generating module 602, a data converting module 604, and a data interface 606. Data interface 606 may be any serial or parallel interface, such as but not limited to, TTL, CMOS, RS-232, SPI, I²C, MIMP, eDP, I80/M68 series MCU interface, etc. Data interface 606 is configured to receive original display data 106 in multiple frames and any other control instructions 118 or test signals. Original display data 106 may be received in consecutive frames at any frame rate used in the art, such as 30, 60, or 72 Hz. The received original display data 106 is forwarded by data interface 606 to control signal generating module 602 and data converting module 604.

In this example, control signal generating module 602 provides the control signals 108 to on-

panel drivers

402, 404, 406. Control signals 108 control on-

panel drivers

402, 404, 406 to cause each group of subpixels to sequentially emit lights in the respective sub-frame periods within a frame period. Control signal generating module 602 may include a TCON 608 and a clock generator 610. TCON 608 may provide a variety of enable signals, including but not limited to, the STE and STV signals to light emitting driver 402 and gate scanning driver 404, respectively. Clock generator 610 may provide a variety of clock signals, including but not limited to, the CKE and CKV signals to light emitting driver 402 and gate scanning driver 404, respectively. As described above, control signal generating module 602 may provide a first set of control signals 506, including the CKE and STE signals, to light emitting driver 402 to control light emitting driver 402. Control signal generating module 602 may also provide a second set of control signals 508, including the CKV and STV signals, to the gate scanning driver 404 to control gate scanning driver 404. The details of the timing of each control signal 108 provided by control signal generating module 602 are described below in accordance with various embodiments of the present disclosure.

In this example, data converting module 604 provides converted display data 616 to source writing driver 406. Data converting module 604 is configured to convert original display data 106 into converted display data 616 based on a manner in which array of subpixels 400 is divided into the groups of subpixels. The original display data in one frame includes a plurality of data signals to be transmitted to each column of subpixels via a corresponding data line. The timing of each data signal is arranged according to the sequence of scanning each subpixel in the corresponding column. For example, the first level of original data signal 106 represents the data to be written to the subpixel in the first row, the second level of original data signal 106 represents the data to be written to the subpixel in the second row, and so on and so forth. As disclosed herein, since the array of subpixels is divided into groups of subpixels, each of which emit lights in a respective sub-frame in a frame period, the sequence of scanning the rows of subpixels is changed accordingly. In the example shown in FIG. 3A, the sequence of scanning the rows of subpixels is no longer following the pattern of 1st row, 2nd row, 3rd row, 4th row, 5th row, ..., Nth row. Instead, the scanning sequence becomes 1st row, 3rd row, 5th row, …, (N-1) th row, 2nd row, 4th row, 6th row, …, Nth row. Accordingly, the timing of each data signal is re-arranged (i.e., reordered) in converted display data 616 according to the new scanning sequence determined based on the manner of division.

Data converting module 604 in this example includes a storing unit 612 and a data reconstructing unit 614. Storing unit 612 is configured to receive original display data 106 and store original display data 106 in each frame because the conversion of display data is performed at the frame level. Storing unit 612 may be data latches that temporally store original display data 106 forwarded by data interface 606. Data reconstructing unit 614 is operatively coupled to storing unit 612 and configured to reconstruct, in each frame, original display data 106 into corresponding converted display data 616 based on the sequence in which the groups of subpixels emit lights within the frame period. For scan-direction-division, the sequence corresponds to the scanning sequence of the rows of subpixels. It is to be appreciated that in some embodiments, data converting module 604 may not be included in control logic 104. Instead, processor 114 may adjust the timing of original display data 106 by itself to accommodate the change of scanning sequence caused by the frame-division.

FIG. 7 is a circuit diagram illustrating one example of a pixel circuit 700 shared by two light emitting elements in accordance with an embodiment. Pixel circuit 700 in this example is shared by two light emitting elements D1, D2 representing two subpixels from different groups of subpixels. Pixel circuit 700 in this example includes a storage capacitor 702, a light emitting control transistor 704, a driving transistor 706, two light emitting transistors 708-1, 708-2, and a switching transistor 710. The light emitting elements D1, D2 may be OLEDs, such as top-emitting OLEDs, and each transistor may be a p-type transistor, such as a PMOS TFT. Pixel circuit 700 may be operatively coupled to gate scanning driver 404 via a scan line 714 and source writing driver 406 via a data line 716. Additionally or optionally, a compensation circuit 712 may be included in pixel circuit 700 to ensure the brightness uniformities between the light emitting elements D1, D2. Compensation circuit 712 can be in any configurations as known in the art, which includes one or more transistors and capacitors. Pixel circuit 700 is suitable for any configuration of the direct-charging type of pixel circuits because in pixel circuit 700, the data signal is directly applied to driving transistor 706 when switching transistor 710 is turned on during the charging period.

In this example, light emitting control transistor 704 includes a gate electrode operatively coupled to a light emitting control signal EMC, a source electrode operatively coupled to a supply voltage Vdd, and a drain electrode. The light emitting control signal EMC may be provided by light emitting control circuit 502 of light emitting driver 402. The light emitting control signal EMC in this example turns on light emitting control transistor 704 during each of the two light emitting periods for the two light emitting elements D1, D2 within a frame period. Driving transistor 706 includes a gate electrode operatively coupled to one electrode of storage capacitor 702, a source electrode operatively coupled to the drain electrode of light emitting control transistor 704, and a drain electrode. In each light emitting period (i.e., when light emitting control transistor 704 is turned on) , driving transistor 706 provides a driving current to one of the light emitting elements D1, D2 at a level determined based on the voltage level currently at storage capacitor 702.

Each light emitting transistor 708-1, 708-2 includes a gate electrode operatively coupled to a respective light emitting signal EM1, EM2, a source electrode operatively coupled to the drain electrode of driving transistor 706, and a drain electrode operatively coupled to the respective light emitting element D1, D2. It is to be appreciated that in the examples in which compensation circuit 712 is included in pixel circuit 700, the source electrode of each light emitting transistor 708-1, 708-2 may not directly connect to the drain electrode of driving transistor 706. In any event, during a light emitting period (i.e., when light emitting control transistor 704 is turned on) , a driving current path is formed through the supply voltage Vdd, light emitting control transistor 704, driving transistor 706, one of light emitting transistors 708-1, 708-2, and one of the light emitting elements D1, D2. Each light emitting signal EM1, EM2 turns on respective light emitting transistor 708-1, 708-2 during a respective one of the two light emitting periods within a frame period to cause the respective light emitting element D1, D2 to emit a light.

In this example, switching transistor 710 includes a gate electrode operatively coupled to scan line 714 transmitting a scan signal, a source electrode operatively coupled to data line 716 transmitting a data signal, and a drain electrode. The scan signal may turn on switching transistor 710 during each of the two charging periods within a frame period to cause storage capacitor 702 to be charged at a respective level in the data signal for the respective light emitting element D1, D2. As described above, the timing of the display data has been re-arranged in the converted display data to accommodate the frame-division and pixel circuit-sharing scheme disclosed herein. In this example, storage capacitor 702 is charged twice in one frame period for the two light emitting elements D1, D2, respectively. During each charging period, the light emitting control signal EMC turns off light emitting control transistor 704 to block the supply voltage Vdd.

FIG. 8 is a timing diagram of pixel circuit 700 shown in FIG. 7 in accordance with an embodiment. In this example, a frame period is divided into two sub-frames for each of the two light emitting elements D1, D2. The light emitting control signal EMC turns on light emitting control transistor 704 in each of the two sub-frames (i.e., light emitting control transistor 704 is turned on twice in the frame period) . Accordingly, the first light emitting signal EM1 turns on first light emitting transistor 708-1 during a first light emitting period 802-1 in the first sub-frame, and the second light emitting signal EM2 turns on second light emitting transistor 708-2 during a second light emitting period 802-2 in the second sub-frame. That is, the timings of the light emitting control signal EMC and the two light emitting signals EM1, EM2 are designed to coordinate with each other to create two subsequent light emitting periods 802-1, 802-2 within one frame period.

In FIG. 8, the scan signal Sn turns on switching transistor 710 to charge storage capacitor 702 with the data signal Data in each of the two sub-frames (i.e., storage capacitor 702 is charged twice in the frame period) before the light emitting control signal EMC turns on light emitting control transistor 704. That is, the scan signal Sn creates two charging periods 804-1, 804-2 in one frame period for the two light emitting elements D1, D2, respectively. During first charging period 804-1, storage capacitor 702 is charged with the data signal Data at the level for the first light emitting element D1. Then, during first light emitting period 802-1, the first light emitting element D1 emits a light at a brightness level determined based on the charged voltage level of storage capacitor 702. At second light emitting period 804-2, storage capacitor 702 is charged with the data signal Data at the level for the second light emitting element D2. Then, during second light emitting period 802-2, the second light emitting element D2 emits a light at a brightness level determined based on the charged voltage level of storage capacitor 702. In this example, the light emitting control signal EMC turns off light emitting control transistor 704 during charging periods 804-1, 804-2.

FIG. 9 and FIG. 10 are a circuit diagram and a timing diagram, respectively, of a pixel circuit 900 with a compensation circuit 902 shared by two light emitting elements in the same column in accordance with an embodiment. Compared with the exemplary direct-charging type pixel circuit 700 shown in FIG. 7, additional transistors and control signals (e.g., the reset signal Sn-1) are added to pixel circuit 900 to form compensation circuit 902, which eliminates the effect of non-uniformity of the mobility and threshold voltage Vth of the driving transistor. The two light emitting elements in this example may be adjacent OLEDs in the same column when the array of OLEDs is divided in the scan direction. In pixel circuit 900, seven transistors and one capacitor (7T1C) are used for driving two subpixels. The average number of transistors per subpixel in the direct-charging type pixel circuit 900 is reduced compared with the known solution, e.g., the direct-charging type pixel circuit 4700. As a result, the layout area of the direct-charging type pixel circuit 900 is about half of the layout area of the direct-charging type pixel circuit 4700 for driving the same number of subpixels.

FIG. 11 is a depiction of an example of dividing a display frame into two sub-frames in the scan direction in accordance with an embodiment. In this example, a display frame 1100 having a resolution of 6×4 pixels is evenly divided into a first sub-frame 1102 and a second sub-frame 1104 in the scan direction. Each sub-frame period is one half of a frame period. In this example, each pixel 1106 consists of three adjacent subpixels in the same row (e.g., R, G, and B subpixels) , each of which is a light emitting element. That is, a 6×12 array of subpixels is divided into two groups of subpixels in the scan direction. The first group of subpixels includes one half of the 6×12 subpixels, i.e., subpixels in the first, third, and fifth rows, and the second group of subpixels includes the other half of the 6×12 subpixels, i.e., subpixels in the second, fourth, and sixth rows. Taking the first column of pixels on display frame 1100 as an example shown in FIG. 12, a 6×3 subpixel array is divided into two subpixel groups in the scan direction.

FIG. 13 is a timing diagram of pixel circuits for driving the 6×3 subpixel array shown in FIG. 12 in accordance with an embodiment. In this example, the timings of light emitting control signals EMC1, EMC2, EMC3 and light emitting signals EM1-1, EM1-2, EM1-3, EM2-1, EM2-2, EM2-3 are illustrated. As the 6×3 subpixel array is divided into two subpixel groups in the scan direction, two sets of light emitting signals are provided: the first set of light emitting signals EM1-1, EM1-2, EM1-3 for controlling the light emission of subpixels in the first subpixel group, and the second set of light emitting signals EM2-1, EM2-2, EM2-3 for controlling the light emission of subpixels in the second subpixel group. Specifically, the light emitting signals EM1-1, EM1-2, EM1-3 in the first set control the subpixels in the first, third, and fifth rows, respectively, to emit lights during the first sub-frame period (Frame 1-1) and the light emitting signals EM2-1, EM2-2, EM2-3 in the second set control the subpixels in the second, fourth, and sixth rows, respectively, to emit lights during the second sub-frame period (Frame 1-2) subsequent to the first sub-frame period. As to the light emitting control signals EMC1, EMC2, EMC3, each of them controls the two subpixels sharing the same pixel circuit to sequentially emit a light in the respective sub-frame period (light emitting period) within a frame period. Specifically, the light emitting control signal EMC1 may control the subpixels from the first and second rows of subpixels, the light emitting control signal EMC2 may control the subpixels from the third and fourth rows of subpixels, and the light emitting control signal EMC3 may control the subpixels from the fifth and sixth rows of subpixels. As shown in FIG. 13, the light emitting control signal EMC1 coordinates with the light emitting signals EM1-1, EM2-1 so that the light emitting control signal EMC1 becomes low when any of the light emitting signals EM1-1, EM2-1 becomes low. Similarly, the light emitting control signal EMC2 coordinates with the light emitting signals EM1-2, EM2-2 so that the light emitting control signal EMC2 becomes low when any of the light emitting signals EM1-2, EM2-2 becomes low； the light emitting control signal EMC3 coordinates with the light emitting signals EM1-3, EM2-3 so that the light emitting control signal EMC3 becomes low when any of the light emitting signals EM1-3, EM2-3 becomes low.

FIG. 14 is a circuit diagram illustrating light emitting circuit 504 for providing light emitting signals for driving the 6×3 subpixel array shown in FIG. 12 in accordance with an embodiment. In this example, light emitting circuit 504 includes two shift registers 1402, 1404, each of which is configured to provide a respective set of light emitting signals. The first shift register 1402 includes three flip-flops providing the three light emitting signals EM1-1, EM1-2, EM1-3, respectively, in the first set of light emitting signals in response to the enable signal STE1 and clock signals CKE1, CKE2 provided by control logic 104. The second shift register 1404 includes three flip-flops providing the three light emitting signals EM2-1, EM2-2, EM2-3, respectively, in the second set of light emitting signals in response to the enable signal STE2 and clock signals CKE1, CKE2 provided by control logic 104. In this example, the clock signals CKE1, CKE2 are provided to the different clock inputs in first and second shift registers 1402, 1404. The timings of the light emitting signals EM1-1, EM1-2, EM1-3, EM2-1, EM2-2, EM2-3 and enable signals STE1, STE2 are shown in FIG. 13. Light emitting circuit 504 in this example is provided for driving the 6×3 subpixel array shown in FIG. 12. For a display having an N×M subpixel array, when the display frame is evenly divided into k sub-frames (i.e., k groups of subpixels) in the scan direction, the number of shift registers needed in light emitting circuit 504 is k. In other words, light emitting circuit 504 includes k shift registers for providing k sets of light emitting signals, respectively, and each shift register includes N/k flip-flops for providing N/k light emitting signals, respectively, in each set of light emitting signals.

FIG. 15A is a circuit diagram illustrating one example of light emitting control circuit 502 for providing light emitting control signals for driving the 6×3 subpixel array shown in FIG. 12 in accordance with an embodiment. In this example, light emitting control circuit 502 includes a shift register 1502 configured to provide the light emitting control signals EMC1, EMC2, EMC3 in response to the enable signal STE3 and clock signals CKE3, CKE4 provided by control logic 104. In this example, the enable signal STE3 is a logical disjunction of the enable signals STE1, STE2 provided to two shift registers 1402, 1404 in light emitting circuit 504. For example, the enable signal STE3 is low when any of the enable signals STE1, STE2 is low. The timings of the light emitting control signals EMC1, EMC2, EMC3 and enable signals STE1, STE2 are shown in FIG. 13. Shift register 1502 in this example includes three flip-flops outputting three light emitting control signals EMC1, EMC2, EMC3 for driving the 6×3 subpixel array shown in FIG. 12. For a display having an N×M subpixel array, when the display frame is evenly divided into k sub-frames (i.e., k groups of subpixels) in the scan direction, the shift register in light emitting control circuit 502 includes N/k flip-flops for providing N/k light emitting control signals, respectively.

FIG. 15B is a circuit diagram illustrating another example of a light emitting control circuit for providing light emitting control signals for driving the 6×3 subpixel array shown in FIG. 12 in accordance with an embodiment. In this example, light emitting control circuit 502 includes three AND gates 1504, 1506, 1508, each of which is configured to provide one of the light emitting control signals EMC1, EMC2, EMC3. Each AND gate 1504, 1506, 1608 provides a light emitting control signal EMC1, EMC2, EMC3, respectively, based on two of the six light emitting signals EM1-1, EM1-2, EM1-3, EM2-1, EM2-2, EM2-3. For each AND gate 1504, 1506, 1508, one of the input light emitting signals is from the first set of light emitting signals EM1-1, EM1-2, EM1-3, and the other one of the input light emitting signals is from the second set of light emitting signals EM2-1, EM2-2, EM2-3. The two input light emitting signals of the same AND gate 1504, 1506, 1508 are used for controlling the two subpixels sharing the same pixel circuit. Specifically, the light emitting signal EM1-1 from the first set of light emitting signals and the corresponding light emitting signal EM2-1 from the second set of light emitting signals are the inputs of the first AND gate 1504, and the light emitting control signal EMC1 is the output of the first AND gate 1504； the light emitting signal EM1-2 from the first set of light emitting signals and the corresponding light emitting signal EM2-2 from the second set of light emitting signals are the inputs of the second AND gate 1506, and the light emitting control signal EMC2 is the output of the second AND gate 1506； the light emitting signal EM1-3 from the first set of light emitting signals and the corresponding light emitting signal EM2-3 from the second set of light emitting signals are the inputs of the third AND gate 1508, and the light emitting control signal EMC3 is the output of the third AND gate 1508.

Light emitting control circuit 502 shown in FIG. 15B is suitable for PMOS pixel circuits. When any of the two input light emitting signals is low, the output light emitting control signal is low. Because the two input light emitting signals control the two light emitting elements sharing the same pixel circuit, respectively, the corresponding light emitting control signal turns on the p-type light emitting control transistor during each of the two light emitting periods (i.e., when any of the two light emitting signals is low) within a frame period. The timings of the output light emitting control signals EMC1, EMC2, EMC3 and the input light emitting signals EM1-1, EM1-2, EM1-3, EM2-1, EM2-2, EM2-3 are shown in FIG. 13. It is to be appreciated that in some embodiments in which the pixel circuits are NMOS pixel circuits, three OR gates can replace three AND gates 1504, 1506, 1508 in FIG. 15B. The corresponding light emitting signals with the reversed polarity are inputted to each OR gate, and the corresponding light emitting control signals with the reversed polarity are outputted from each OR gate. That is, when any of the two input light emitting signals is high, the output light emitting control signal is high. Because the two input light emitting signals control the two light emitting elements sharing the same pixel circuit, respectively, the corresponding light emitting control signal turns on the n-type light emitting control transistor during each of the two light emitting periods (i.e., when any of the two light emitting signals is high) within a frame period. For a display having an N×M subpixel array, when the display frame is evenly divided into k sub-frames (i.e., k groups of subpixels) in the scan direction, light emitting control circuit 502 with AND gates or OR gates includes N/k AND or OR gates for providing N/k light emitting control signals, respectively. Each of the N/k AND or OR gates has k input light emitting used for controlling the k subpixels sharing the same pixel circuit.

FIG. 16 is another timing diagram of pixel circuits for driving the 6×3 subpixel array shown in FIG. 12 in accordance with an embodiment. The timings of the scan signals S1-0, S1-1, S2-0, S2-1 are provided in the timing diagram with respect to the light emitting signals EM1-1, EM2-1. FIG. 17 is a circuit diagram illustrating a gate scanning driver for providing scan signals for scanning the 6×3 subpixel array shown in FIG. 12 in accordance with an embodiment. In this example, gate scanning driver 404 includes a shift register 1702 configured to provide the scan signals S0, S1, S2, S3 in response to the enable signal STV and clock signals CKV1, CKV2 provided by control logic 104. Shift register 1702 in this example includes four flip-flops outputting four scan signals S0, S1, S2, S3 to pixel circuits 900 with compensation circuit 902 shown in FIG. 9 for driving the 6×3 subpixel array shown in FIG. 12. For a display having an N×M subpixel array, when the display frame is evenly divided into k sub-frames (i.e., k groups of subpixels) in the scan direction, k rows of subpixels from the k subpixel groups can share the same scan line. Thus, the shift register in the gate scanning driver 404 includes N/k flip-flops for providing N/k scan signals, respectively, to pixel circuits without compensation circuits (e.g., pixel circuit 700 in FIG. 7) or includes (N/k) +1 flip-flops for providing (N/k) +1 scan signals, respectively, to pixel circuits with compensation circuits (e.g., pixel circuit 900 in FIG. 9 with the Sn-1 signal) .

FIG. 18 is a depiction of an example of dividing a 6×3 subpixel array into three subpixel groups in the scan direction in accordance with an embodiment. The first group of subpixels includes one third of the 6×3 subpixels, i.e., subpixels in the first and fourth rows, the second group of subpixels includes one third of the 6×3 subpixels, i.e., subpixels in the second and fifth rows, and the third group of subpixels includes the rest one third of the 6×3 subpixels, i.e., subpixels in the third and sixth rows.

FIG. 19 is a circuit diagram of a pixel circuit 1900 with a compensation circuit shared by three light emitting elements in the same column in accordance with an embodiment. Compared with the exemplary pixel circuit 900 shown in FIG. 9, one more light emitting transistor is included in pixel circuit 1900 to control the light emission of the third light emitting element in response to the third light emitting signal EM3-1. The three light emitting elements in this example may be adjacent OLEDs in the same column when the array of OLEDs is divided into three subpixel groups in the scan direction. In pixel circuit 1900, eight transistors and one capacitor (8T1C) are used for driving three subpixels. The average number of transistors per subpixel in pixel circuit 1900 is further reduced compared with the known solution, e.g., the direct-charging type pixel circuit 4700. As a result, the layout area of the direct-charging type pixel circuit 1900 is about one third of the layout area of the direct-charging type pixel circuit 4700 for driving the same number of subpixels.

FIG. 20 is a timing diagram of pixel circuits for driving the 6×3 subpixel array shown in FIG. 18 in accordance with an embodiment. In this example, the timings of light emitting control signals EMC1, EMC2, and light emitting signals EM1-1, EM1-2, EM2-1, EM2-2, EM3-1, EM3-2 are illustrated. As the 6×3 subpixel array is divided into three subpixel groups in the scan direction, three sets of light emitting signals are provided: the first set of light emitting signals EM1-1, EM1-2 for controlling the light emission of subpixels in the first subpixel group, the second set of light emitting signals EM2-1, EM2-2 for controlling the light emission of subpixels in the second subpixel group, and the third set of light emitting signals EM3-1, EM3-2 for controlling the light emission of subpixels in the third subpixel group. Specifically, the light emitting signals EM1-1, EM1-2 in the first set control the subpixels in the first and fourth rows, respectively, to emit lights during the first sub-frame period (Frame 1-1) , the light emitting signals EM2-1, EM2-2 in the second set control the subpixels in the second and fifth rows, respectively, to emit lights during the second sub-frame period (Frame 1-2) subsequent to the first sub-frame period, and the light emitting signals EM3-1, EM3-2 in the third set control the subpixels in the third and sixth rows, respectively, to emit lights during the third sub-frame period (Frame 1-3) subsequent to the second sub-frame period. As to the light emitting control signals EMC1, EMC2, each of them controls the three subpixels sharing the same pixel circuit to sequentially emit a light in the respective sub-frame period (light emitting period) within a frame period. Specifically, the light emitting control signal EMC1 may control the subpixels from the first, second, and third rows of subpixels, and the light emitting control signal EMC2 may control the subpixels from the fourth, fifth, and sixth rows of subpixels. As shown in FIG. 20, the light emitting control signal EMC1 coordinates with the light emitting signals EM1-1, EM2-1, EM3-1 so that the light emitting control signal EMC1 becomes low when any of the light emitting signals EM1-1, EM2-1, EM3-1 becomes low. Similarly, the light emitting control signal EMC2 coordinates with the light emitting signals EM1-2, EM2-2, EM3-2 so that the light emitting control signal EMC2 becomes low when any of the light emitting signals EM1-2, EM2-2, EM3-2 becomes low.

FIG. 21 is a circuit diagram illustrating light emitting circuit 504 for providing light emitting signals for driving the 6×3 subpixel array shown in FIG. 18 in accordance with an embodiment. In this example, light emitting circuit 504 includes three

shift registers

2102, 2104, 2106, each of which is configured to provide a respective set of light emitting signals. The first shift register 2102 includes two flip-flops providing the two light emitting signals EM1-1, EM1-2, respectively, in the first set of light emitting signals in response to the enable signal STE1 and clock signals CKE1, CKE2 provided by control logic 104. The second shift register 2104 includes two flip-flops providing the two light emitting signals EM2-1, EM2-2, respectively, in the second set of light emitting signals in response to the enable signal STE2 and clock signals CKE1, CKE2 provided by control logic 104. The third shift register 2106 includes two flip-flops providing the two light emitting signals EM3-1, EM3-2, respectively, in the third set of light emitting signals in response to the enable signal STE3 and clock signals CKE1, CKE2 provided by control logic 104. The timings of the light emitting signals EM1-1, EM1-2, EM2-1, EM2-2, EM3-1, EM3-2 and enable signals STE1, STE2, STE3 are shown in FIG. 20. Light emitting circuit 504 in this example is provided for driving the 6×3 subpixel array shown in FIG. 18. For a display having an N×M subpixel array, when the display frame is evenly divided into k sub-frames (i.e., k groups of subpixels) in the scan direction, the number of shift registers needed in light emitting circuit 504 is k. In other words, light emitting circuit 504 includes k shift registers for providing k sets of light emitting signals, respectively, and each shift register includes N/k flip-flops for providing N/k light emitting signals, respectively, in each set of light emitting signals.

FIG. 22A is a circuit diagram illustrating one example light emitting control circuit 502 for providing light emitting control signals for driving the 6×3 subpixel array shown in FIG. 18 in accordance with an embodiment. In this example, light emitting control circuit 502 includes a shift register 2202 configured to provide the light emitting control signals EMC1, EMC2 in response to the enable signal STE4 and clock signals CKE1, CKE2 provided by control logic 104. In this example, the enable signal STE4 is a logical disjunction of the enable signals STE1, STE2, STE3 provided to the three

shift registers

2102, 2102, 2104 in light emitting circuit 504. For example, the enable signal STE4 is low when any of the enable signals STE1, STE2, STE3 is low. The timings of the light emitting control signals EMC1, EMC2 and enable signals STE1, STE2, STE3 are shown in FIG. 20. The shift register 2202 in this example includes two flip-flops outputting two light emitting control signals EMC1, EMC2 for driving the 6×3 subpixel array shown in FIG. 18. For a display having an N×M subpixel array, when the display frame is evenly divided into k sub-frames (i.e., k groups of subpixels) in the scan direction, the shift register in light emitting control circuit 502 includes N/k flip-flops for providing N/k light emitting control signals, respectively.

FIG. 22B is a circuit diagram illustrating another example of light emitting control circuit 502 for providing light emitting control signals for driving the 6×3 subpixel array shown in FIG. 18 in accordance with an embodiment. In this example, light emitting control circuit 502 includes two AND

gates

2204, 2206, each of which is configured to provide one of the light emitting control signals EMC1, EMC2. Each AND

gate

2204, 2206 provides a light emitting control signal EMC1, EMC2, respectively, based on three of the six light emitting signals EM1-1, EM1-2, EM2-1, EM2-2, EM3-1, EM3-2. For each AND

gate

2204, 2206, one of the input light emitting signals is from the first set of light emitting signals EM1-1, EM1-2, one of the input light emitting signals is from the second set of light emitting signals EM2-1, EM2-2, and the other one of the input light emitting signals is from the third set of light emitting signals EM3-1, EM3-2. The three input light emitting signals of the same AND

gate

2204, 2206 are used for controlling the three subpixels sharing the same pixel circuit. Specifically, the light emitting signal EM1-1 from the first set of light emitting signals, the corresponding light emitting signal EM2-1 from the second set of light emitting signals, and the corresponding light emitting signal EM3-1 from the third set of light emitting signals are the inputs of the first AND gate 2204, and the light emitting control signal EMC1 is the output of the first AND gate 2204； the light emitting signal EM1-2 from the first set of light emitting signals, the corresponding light emitting signal EM2-2 from the second set of light emitting signals, and the corresponding light emitting signal EM3-2 from the third set of light emitting signals are the inputs of the second AND gate 2206, and the light emitting control signal EMC2 is the output of the second AND gate 2206.

Light emitting control circuit 502 shown in FIG. 22B is suitable for PMOS pixel circuits. When any of the three input light emitting signals is low, the output light emitting control signal is low. Because the three input light emitting signals control the three light emitting elements sharing the same pixel circuit, respectively, the corresponding light emitting control signal turns on the p-type light emitting control transistor during each of the three light emitting periods (i.e., when any of the three light emitting signals is low) within a frame period. The timings of the output light emitting control signals EMC1, EMC2, and the input light emitting signals EM1-1, EM1-2, EM2-1, EM2-2, EM3-1, EM3-2 are shown in FIG. 20. It is to be appreciated that in some embodiments in which the pixel circuits are NMOS pixel circuits, two OR gates can replace the two AND

gates

2204, 2206 in FIG. 22B. The corresponding light emitting signals with the reversed polarity are inputted to each OR gate, and the corresponding light emitting control signals with the reversed polarity are outputted from each OR gate. That is, when any of the three input light emitting signals is high, the output light emitting control signal is high. Because the three input light emitting signals control the three light emitting elements sharing the same pixel circuit, respectively, the corresponding light emitting control signal turns on the n-type light emitting control transistor during each of the three light emitting periods (i.e., when any of the three light emitting signals is high) within a frame period. For a display having an N×M subpixel array, when the display frame is evenly divided into k sub-frames (i.e., k groups of subpixels) in the scan direction, light emitting control circuit 502 with AND gates or OR gates includes N/k AND or OR gates for providing N/k light emitting control signals, respectively. Each of the N/k AND or OR gates has k input light emitting used for controlling the k subpixels sharing the same pixel circuit.

FIG. 23 is another timing diagram of pixel circuits for driving the 6×3 subpixel array shown in FIG. 18 in accordance with an embodiment. The timings of the scan signals S1-0, S1-1, S2-0, S2-1, S3-0, S3-1 are provided in the timing diagram with respect to the light emitting signals EM1-1, EM2-1, EM3-1. FIG. 24 is a circuit diagram illustrating gate scanning driver 404 for providing scan signals for scanning the 6×3 subpixel array shown in FIG. 18 in accordance with an embodiment. In this example, gate scanning driver 404 includes a shift register 2402 configured to provide the scan signals S0, S1, S2 in response to the enable signal STV and clock signals CKV1, CKV2 provided by the control logic 104. The shift register 2402 in this example includes three flip-flops outputting three scan signals S0, S1, S2 to pixel circuits 1900 with compensation circuits shown in FIG. 19 for driving the 6×3 subpixel array shown in FIG. 18. For a display having an N×M subpixel array, when the display frame is evenly divided into k sub-frames (i.e., k groups of subpixels) in the scan direction, k rows of subpixels from the k subpixel groups can share the same scan line. Thus, the shift register in gate scanning driver 404 includes N/k flip-flops for providing N/k scan signals, respectively, to pixel circuits without compensation circuits (e.g., pixel circuit 700 in FIG. 7) or includes (N/k) +1 flip-flops for providing (N/k) +1 scan signals, respectively, to pixel circuits with compensation circuits (e.g., pixel circuit 1900 in FIG. 19 with the Sn-1 signal) . FIG. 25 is still another timing diagram of pixel circuits for driving the 6×3 subpixel array shown in FIG. 18 in accordance with an embodiment. The timings of the scan signals S1-0, S1-1, S1-2, S2-0, S2-1, S2-2, S3-0, S3-1, S3-2 and clock signals CKV1, CKV2 are provided in the timing diagram with respect to the light emitting signals EM1-1, EM2-1, EM3-1.

FIG. 26 is a depiction of an example of dividing a 6×3 subpixel array into six subpixel groups in the scan direction in accordance with an embodiment. The first group of subpixels includes one sixth of the 6×3 subpixels, i.e., subpixels in the first row, the second group of subpixels includes one sixth of the 6×3 subpixels, i.e., subpixels in the second row, the third group of subpixels includes one sixth of the 6×3 subpixels, i.e., subpixels in the third row, the fourth group of subpixels includes one sixth of the 6×3 subpixels, i.e., subpixels in the fourth row, the fifth group of subpixels includes one sixth of the 6×3 subpixels, i.e., subpixels in the fifth row, and the sixth group of subpixels includes one sixth of the 6×3 subpixels, i.e., subpixels in the sixth row.

FIG. 27 is a circuit diagram illustrating a pixel circuit 2700 with a compensation circuit shared by six light emitting elements in the same column in accordance with an embodiment. Compared with the exemplary pixel circuit 1900 shown in FIG. 19, three more light emitting transistors are included in pixel circuit 2700 to control the light emission of the fourth, fifth, and sixth light emitting elements in response to the fourth light emitting signal EM4-1, fifth light emitting signal EM5-1, and sixth light emitting signal EM6-1, respectively. The six light emitting elements in this example may be adjacent OLEDs in the same column when the array of OLEDs is divided into six subpixel groups in the scan direction. In

pixel circuit

2700, 11 transistors and one capacitor (11T1C) are used for driving three subpixels. The average number of transistors per subpixel in the direct-charging type pixel circuit 2700 is further reduced compared with the known solution, e.g., the direct-charging type pixel circuit 4700. As a result, the layout area of the direct-charging type pixel circuit 2700 is about one sixth of the layout area of the direct-charging type pixel circuit 4700 for driving the same number of subpixels.

FIG. 28 is a timing diagram of pixel circuits for driving the 6×3 subpixel array shown in FIG. 26 in accordance with an embodiment. In this example, the timings of light emitting control signal EMC and light emitting signals EM1-1, EM1-2, EM1-3, EM1-4, EM1-5, EM1-6 are illustrated. As the 6×3 subpixel array is divided into six subpixel groups in the scan direction, six sets of light emitting signals are provided: the first set of light emitting signals EM1-1 for controlling the light emission of subpixels in the first subpixel group, the second set of light emitting signals EM1-2 for controlling the light emission of subpixels in the second subpixel group, the third set of light emitting signals EM1-3 for controlling the light emission of subpixels in the third subpixel group, the fourth set of light emitting signals EM1-4 for controlling the light emission of subpixels in the fourth subpixel group, the fifth set of light emitting signals EM1-5 for controlling the light emission of subpixels in the fifth subpixel group, and the sixth set of light emitting signals EM1-6 for controlling the light emission of subpixels in the sixth subpixel group. Specifically, the light emitting signal EM1-1 in the first set controls the subpixels in the first row to emit lights during the first sub-frame period (Frame 1-1) , the light emitting signal EM1-2 in the second set controls the subpixels in the second row to emit lights during the second sub-frame period (Frame 1-2) subsequent to the first sub-frame period, the light emitting signal EM1-3 in the third set controls the subpixels in the third row to emit lights during the third sub-frame period (Frame 1-3) subsequent to the second sub-frame period, the light emitting signal EM1-4 in the fourth set controls the subpixels in the fourth row to emit lights during the fourth sub-frame period (Frame 1-4) subsequent to the third sub-frame period, the light emitting signal EM1-5 in the fifth set controls the subpixels in the fifth row to emit lights during the fifth sub-frame period (Frame 1-5) subsequent to the fourth sub-frame period, and the light emitting signal EM1-6 in the sixth set controls the subpixels in the sixth row to emit lights during the sixth sub-frame period (Frame 1-6) subsequent to the fifth sub-frame period. The light emitting control signal EMC controls the six subpixels sharing the same pixel circuit to sequentially emit a light in the respective sub-frame period (light emitting period) within a frame period. Specifically, the light emitting control signal EMC may control the subpixels from the first to sixth rows of subpixels. As shown in FIG. 28, the light emitting control signal EMC coordinates with the light emitting signals EM1-1, EM1-2, EM1-3, EM1-4, EM1-5, EM1-6 so that the light emitting control signal EMC becomes low when any of the light emitting signals EM1-1, EM1-2, EM1-3, EM1-4, EM1-5, EM1-6 becomes low.

FIG. 29 is a circuit diagram illustrating light emitting circuit 504 for providing light emitting signals for driving the 6×3 subpixel array shown in FIG. 26 in accordance with an embodiment. In this example, light emitting circuit 504 includes six

shift registers

2902, 2904, 2906, 2908, 2910, 2912, each of which is configured to provide a respective set of light emitting signals. The first shift register 2902 includes a flip-flop providing the light emitting signal EM1-1 in the first set of light emitting signals in response to the enable signal STE1 and clock signals CKE1, CKE2 provided by control logic 104. The second shift register 2904 includes a flip-flop providing the light emitting signal EM2-1 in the second set of light emitting signals in response to the enable signal STE2 and clock signals CKE1, CKE2 provided by control logic 104. The third shift register 2906 includes a flip-flop providing the light emitting signal EM3-1 in the third set of light emitting signals in response to the enable signal STE3 and clock signals CKE1, CKE2 provided by control logic 104. The fourth shift register 2908 includes a flip-flop providing the light emitting signal EM4-1 in the fourth set of light emitting signals in response to the enable signal STE4 and clock signals CKE1, CKE2 provided by control logic 104. The fifth shift register 2910 includes a flip-flop providing the light emitting signal EM5-1 in the fifth set of light emitting signals in response to the enable signal STE5 and clock signals CKE1, CKE2 provided by control logic 104. The sixth shift register 2912 includes a flip-flop providing the light emitting signal EM6-1 in the sixth set of light emitting signals in response to the enable signal STE6 and clock signals CKE1, CKE2 provided by control logic 104. The timings of the light emitting signals EM1-1, EM1-2, EM1-3, EM1-4, EM1-5, EM1-6 are shown in FIG. 28. Light emitting circuit 504 in this example is provided for driving the 6×3 subpixel array shown in FIG. 26. For a display having an N×M subpixel array, when the display frame is evenly divided into k sub-frames (i.e., k groups of subpixels) in the scan direction, the number of shift registers needed in light emitting circuit 504 is k. In other words, light emitting circuit 504 includes k shift registers for providing k sets of light emitting signals, respectively, and each shift register includes N/k flip-flops for providing N/k light emitting signals, respectively, in each set of light emitting signals.

FIG. 30A is a circuit diagram illustrating one example of light emitting control circuit 502 for providing light emitting control signals for driving the 6×3 subpixel array shown in FIG. 26 in accordance with an embodiment. In this example, light emitting control circuit 502 includes a shift register 3002 configured to provide the light emitting control signals EMC in response to the enable signal STE7 and clock signals CKE1, CKE2 provided by control logic 104. In this example, the enable signal STE7 is a logical disjunction of the enable signals STE1, STE2, STE3, STE4, STE5, STE6 provided to the six

shift registers

2902, 2904, 2906, 2908, 2910, 2912 in light emitting circuit 504. For example, the enable signal STE7 is low when any of the enable signals STE1, STE2, STE3, STE4, STE5, STE6 is low. The timing of the light emitting control signal EMC is shown in FIG. 28. Shift register 3002 in this example includes a flip-flop outputting the light emitting control signal EMC for driving the 6×3 subpixel array shown in FIG. 26. For a display having an N×M subpixel array, when the display frame is evenly divided into k sub-frames (i.e., k groups of subpixels) in the scan direction, the shift register in light emitting control circuit 502 includes N/k flip-flops for providing N/k light emitting control signals, respectively.

FIG. 30B is a circuit diagram illustrating another example of light emitting control circuit 502 for providing light emitting control signals for driving the 6×3 subpixel array shown in FIG. 26 in accordance with an embodiment. In this example, light emitting control circuit 502 includes one AND gate 3004 configured to provide the light emitting control signal EMC based on the six light emitting signals EM1-1, EM1-2, EM1-3, EM1-4, EM1-5, EM1-6. The six input light emitting signals EM1-1, EM1-2, EM1-3, EM1-4, EM1-5, EM1-6 of AND gate 3004 are used for controlling the six subpixels sharing the same pixel circuit. Light emitting control circuit 502 shown in FIG. 30B is suitable for PMOS pixel circuits. When any of the six input light emitting signals is low, the output light emitting control signal is low. Because the six input light emitting signals control the six light emitting elements sharing the same pixel circuit, respectively, the corresponding light emitting control signal turns on the p-type light emitting control transistor during each of the six light emitting periods (i.e., when any of the six light emitting signals is low) within a frame period. The timings of the output light emitting control signal EMC and the input light emitting signals EM1-1, EM1-2, EM1-3, EM1-4, EM1-5, EM1-6 are shown in FIG. 28.

It is to be appreciated that in some embodiments in which the pixel circuits are NMOS pixel circuits, an OR gate can replace AND gate 3004 in FIG. 30B. The corresponding light emitting signals with the reversed polarity are inputted to each OR gate, and the corresponding light emitting control signals with the reversed polarity are outputted from each OR gate. That is, when any of the six input light emitting signals is high, the output light emitting control signal is high. Because the six input light emitting signals control the six light emitting elements sharing the same pixel circuit, respectively, the corresponding light emitting control signal turns on the n-type light emitting control transistor during each of the six light emitting periods (i.e., when any of the six light emitting signals is high) within a frame period. For a display having an N×M subpixel array, when the display frame is evenly divided into k sub-frames (i.e., k groups of subpixels) in the scan direction, light emitting control circuit 502 with AND gates or OR gates includes N/k AND or OR gates for providing N/k light emitting control signals, respectively. Each of the N/k AND or OR gates has k input light emitting used for controlling the k subpixels sharing the same pixel circuit.

FIG. 31 is another timing diagram of pixel circuits for driving the 6×3 subpixel array shown in FIG. 26 in accordance with an embodiment. The timings of the scan signals S1-0, S1-1, S2-0, S2-1, S3-0, S3-1, S4-0, S4-1, S5-0, S5-1, S6-0 are provided in the timing diagram with respect to the light emitting signals EM1-1, EM2-1, EM3-1. FIG. 32 is a circuit diagram illustrating gate scanning driver 404 for providing scan signals for scanning the 6×3 subpixel array shown in FIG. 26 in accordance with an embodiment. In this example, gate scanning driver 404 includes a shift register 3202 configured to provide the scan signals S0, S1 in response to the enable signal STV and clock signals CKV1, CKV2 provided by control logic 104. Shift register 3202 in this example includes two flip-flops outputting two scan signals S0, S1 to pixel circuit 2700 with compensation circuits shown in FIG. 27 for driving the 6×3 subpixel array shown in FIG. 26. For a display having an N×M subpixel array, when the display frame is evenly divided into k sub-frames (i.e., k groups of subpixels) in the scan direction, k rows of subpixels from the k subpixel groups can share the same scan line. Thus, the shift register in gate scanning driver 404 includes N/k flip-flops for providing N/k scan signals, respectively, to pixel circuits without compensation circuits (e.g., pixel circuit 700 in FIG. 7) or includes (N/k) +1 flip-flops for providing (N/k) +1 scan signals, respectively, to pixel circuits with compensation circuits (e.g., pixel circuit 2700 in FIG. 27 with the Sn-1 signal) .

FIGs. 33A-33C are depictions of various examples of dividing a display frame into multiple sub-frames in the scan direction in accordance with various embodiments. In addition to a display frame having each pixel consisted of real RGB subpixels as shown in FIGs. 11, 12, 18, and 26, the frame-division and pixel circuit-sharing scheme disclosed above is also applicable for any display frame having any subpixel arrangements as known in the art, including but not limited to, PenTile RGBG arrangement, PenTile RGBW arrangement, PenTile diamond pixels arrangement, Zigzag RGB arrangement (U.S. Patent Nos. 8,786,645 and 9,418,586) , RGBW arrangement (U.S. Patent No. 9,165,526) , Delta RGB arrangements (U.S. Patent Application Publication Nos. 2015/0339969 and 2016/0275846) , and other subpixel arrangements (e.g., PCT Patent Publication No. WO 2015/062110) . In FIG. 33A, a display frame with a specific subpixel arrangement is divided into two sub-frames in the scan direction. In FIG. 33B, a display frame with a specific subpixel arrangement is divided into three sub-frames in the scan direction. In FIG. 33C, a display frame with a specific subpixel arrangement is divided into six sub-frames in the scan direction. The pixel circuits and drivers described above with respect to FIGS. 11-32 can also be applied to the examples shown in FIGs. 33A-33C.

FIGs. 34A-34C are depictions of various examples of dividing a 2×6 subpixel array into multiple subpixel groups in the data direction in accordance with various embodiments. In FIG. 34A, the 2×6 subpixel array is evenly divided into two subpixel groups in the data direction. The first group of subpixels includes one half of the 2×6 subpixels, i.e., subpixels in the first, third, and fifth columns, and the second group of subpixels includes the other one half of the 2×6 subpixels, i.e., subpixels in the second, fourth, and sixth columns. In FIG. 34B, the 2×6 subpixel array is evenly divided into three subpixel groups in the data direction. The first group of subpixels includes one third of the 2×6 subpixels, i.e., subpixels in the first and fourth columns, the second group of subpixels includes one third of the 2×6 subpixels, i.e., subpixels in the second and fifth columns, and the third group of subpixels includes the rest one third of the 2×6 subpixels, i.e., subpixels in the third and sixth columns. In FIG. 34C, the 2×6 subpixel array is evenly divided into six subpixel groups in the data direction. The first group of subpixels includes one sixth of the 2×6 subpixels, i.e., subpixels in the first column, the second group of subpixels includes one sixth of the 2×6 subpixels, i.e., subpixels in the second column, the third group of subpixels includes one sixth of the 2×6 subpixels, i.e., subpixels in the third column, the fourth group of subpixels includes one sixth of the 2×6 subpixels, i.e., subpixels in the fourth column, the fifth group of subpixels includes one sixth of the 2×6 subpixels, i.e., subpixels in the fifth column, and the sixth group of subpixels includes the rest one sixth of the 2×6 subpixels, i.e., subpixels in the sixth column. The pixel circuits and drivers described above with respect to FIGS. 11-32 can also be applied to the data-direction-division examples in FIGs. 34A-34C. As mentioned above, for data-direction-division, because multiple subpixels share the same data line, the total number of data line and the scan/charging period are reduced compared with the known solutions and are depended on the number of sub-frames (groups of subpixels) and the number of subpixels forming a single pixel (e.g., the specific subpixel arrangement) .

FIG. 35 is a depiction of an example of dividing a display frame into four sub-frames in the scan and data directions in accordance with an embodiment. In this example, a display frame 3500 having a resolution of 6×4 pixels is evenly divided into a first sub-frame 3502, a second sub-frame 3504, a third sub-frame 3506, and a fourth sub-frame 3508 in the scan and data directions. Each sub-frame period is one fourth of a frame period. In this example, each pixel 3510, 3512 consists of two adjacent subpixels in the same row (e.g., R and G subpixels or G and B subpixels) , each of which is a light emitting element. That is, a 6×8 array of subpixels is divided into four groups of subpixels in the scan and data directions. The first group of subpixels includes one fourth of the 6×8 subpixels, i.e., all the red subpixels, the second group of subpixels includes one fourth of the 6×8 subpixels, i.e., one half of all the green subpixels, the third group of subpixels includes one fourth of the 6×8 subpixels, i.e., one half of all the green subpixels, and the fourth group of subpixels includes one fourth of the 6×8 subpixels, i.e., all the blue subpixels. Taking the first column of pixels on display frame 3500 as an example shown in FIG. 36, a 6×2 subpixel array is divided into four subpixel groups in the scan and data directions.

FIG. 37 is a circuit diagram illustrating a pixel circuit 3700 with a compensation circuit shared by four light emitting elements in a 2×2 subpixel block in accordance with an embodiment. Compared with the exemplary pixel circuit 1900 shown in FIG. 19, one more light emitting transistor is included in pixel circuit 3700 to control the light emission of the fourth light emitting element in response to the fourth light emitting signal EM4-1. The four light emitting elements in this example may be adjacent OLEDs in a 2×2 subpixel block when the array of OLEDs is divided into two subpixel groups in the scan and data directions. In pixel circuit 3700, nine transistors and one capacitor (9T1C) are used for driving four subpixels. The average number of transistors per subpixel in the direct-charging type pixel circuit 3700 is further reduced compared with the known solution, e.g., the direct-charging type pixel circuit 4700. As a result, the layout area of the direct-charging type pixel circuit 3700 is about one fourth of the layout area of the direct-charging type pixel circuit 4700 for driving the same number of subpixels.

FIG. 38 is a timing diagram of pixel circuits for driving the 6×2 subpixel array shown in FIG. 36 in accordance with an embodiment. In this example, the timings of light emitting control signals EMC1, EMC2, EMC3 and light emitting signals EM1-1, EM1-2, EM1-3, EM2-1, EM2-2, EM2-3 are illustrated. As the 6×2 subpixel array is evenly divided into four subpixel groups in the scan and data directions, two sets of light emitting signals are provided: the first set of light emitting signals EM1-1, EM1-2, EM1-3 for controlling the light emission of subpixels in the first and third subpixel groups and the second set of light emitting signals EM2-1, EM2-2, EM2-3 for controlling the light emission of subpixels in the second and fourth subpixel groups. Specifically, the light emitting signals EM1-1, EM1-2, EM1-3 in the first set control all the red subpixels to emit lights during the first sub-frame period (Frame 1-1) and one half of all the green subpixels to emit lights during the third sub-frame period (Frame 1-3) ； the light emitting signals EM2-1, EM2-2, EM2-3 in the second set control one half of all the green subpixels to emit lights during the second sub-frame period (Frame 1-2) subsequent to the first sub-frame period and all the blue subpixels to emit lights during the fourth sub-frame period (Frame 1-4) subsequent to the third sub-frame period. As to the light emitting control signals EMC1, EMC2, EMC3, each of them controls the four subpixels sharing the same pixel circuit (e.g., in each 2×2 subpixel block) to sequentially emit a light in the respective sub-frame period (light emitting period) within a frame period. As shown in FIG. 38, the light emitting control signal EMC1 coordinates with the light emitting signals EM1-1, EM2-1 so that the light emitting control signal EMC1 becomes low when any of the light emitting signals EM1-1, EM2-1 becomes low. Similarly, the light emitting control signal EMC2 coordinates with the light emitting signals EM1-2, EM2-2 so that the light emitting control signal EMC2 becomes low when any of the light emitting signals EM1-2, EM2-2 becomes low； the light emitting control signal EMC3 coordinates with the light emitting signals EM1-3, EM2-3 so that the light emitting control signal EMC3 becomes low when any of the light emitting signals EM1-3, EM2-3 becomes low.

FIG. 39 is a circuit diagram illustrating light emitting circuit 504 for providing light emitting signals for driving the 6×2 subpixel array shown in FIG. 36 in accordance with an embodiment. In this example, light emitting circuit 504 includes two shift registers 3902, 3904, each of which is configured to provide a respective set of light emitting signals. The first shift register 3902 includes three flip-flops providing the three light emitting signals EM1-1, EM1-2, EM1-3, respectively, in the first set of light emitting signals in response to the enable signal STE1 and clock signals CKE1, CKE2 provided by control logic 104. The second shift register 3904 includes three flip-flops providing the three light emitting signals EM2-1, EM2-2, EM2-3, respectively, in the second set of light emitting signals in response to the enable signal STE2 and clock signals CKE1, CKE2 provided by control logic 104. In this example, the clock signals CKE1, CKE2 are provided to the different clock inputs in the first and second shift registers 3902, 3904. The timings of the light emitting signals EM1-1, EM1-2, EM1-3, EM2-1, EM2-2, EM2-3 and enable signals STE1, STE2 are shown in FIG. 38. Light emitting circuit 504 in this example is provided for driving the 6×2 subpixel array shown in FIG. 36.

FIG. 40A is a circuit diagram illustrating one example of light emitting control circuit 502 for providing light emitting control signals for driving the 6×2 subpixel array shown in FIG. 36 in accordance with an embodiment. In this example, light emitting control circuit 502 includes a shift register 4002 configured to provide the light emitting control signals EMC1, EMC2, EMC3 in response to the enable signal STE3 and clock signals CKE3, CKE4 provided by control logic 104. In this example, the enable signal STE3 is a logical disjunction of the enable signals STE1, STE2 provided to two shift registers 3902, 3904 in light emitting circuit 504. For example, the enable signal STE3 is low when any of the enable signals STE1, STE2 is low. The timings of the light emitting control signals EMC1, EMC2, EMC3 and enable signals STE1, STE2 are shown in FIG. 38. The shift register 4002 in this example includes three flip-flops outputting three light emitting control signals EMC1, EMC2, EMC3 for driving the 6×2 subpixel array shown in FIG. 36.

FIG. 40B is a circuit diagram illustrating another example of light emitting control circuit 502 for providing light emitting control signals for driving the 6×2 subpixel array shown in FIG. 36 in accordance with an embodiment. In this example, light emitting control circuit 502 includes three AND

gates

4004, 4006, 4008, each of which is configured to provide one of the light emitting control signals EMC1, EMC2, EMC3. Each AND

gate

4004, 4006, 4008 provides a light emitting control signal EMC1, EMC2, EMC3, respectively, based on two of the six light emitting signals EM1-1, EM1-2, EM1-3, EM2-1, EM2-2, EM2-3. For each AND

gate

4004, 4006, 4008, one of the input light emitting signals is from the first set of light emitting signals EM1-1, EM1-2, EM1-3, and the other one of the input light emitting signals is from the second set of light emitting signals EM2-1, EM2-2, EM2-3. Light emitting control circuit 502 shown in FIG. 40B is suitable for PMOS pixel circuits. When any of the two input light emitting signals is low, the output light emitting control signal is low. The timings of the output light emitting control signals EMC1, EMC2, EMC3 and the input light emitting signals EM1-1, EM1-2, EM1-3, EM2-1, EM2-2, EM2-3 are shown in FIG. 38. It is to be appreciated that in some embodiments in which the pixel circuits are NMOS pixel circuits, three OR gates can replace three AND 4004, 4006, 4008 in FIG. 40B. The corresponding light emitting signals with the reversed polarity are inputted to each OR gate, and the corresponding light emitting control signals with the reversed polarity are outputted from each OR gate. That is, when any of the two input light emitting signals is high, the output light emitting control signal is high.

FIG. 41 is another timing diagram of pixel circuits for driving the 6×2 subpixel array shown in FIG. 36 in accordance with an embodiment. The timings of the scan signals S1-0, S1-1, S2-0, S2-1, S3-0, S3-1, S4-0, S4-1 are provided in the timing diagram with respect to the light emitting signals EM1-1, EM2-1. FIG. 42 is a circuit diagram illustrating gate scanning driver 404 for providing scan signals for scanning the 6×2 subpixel array shown in FIG. 36 in accordance with an embodiment. In this example, gate scanning driver 404 includes a shift register 4202 configured to provide the scan signals S0, S1, S2, S3 in response to the enable signal STV and clock signals CKV1, CKV2 provided by the control logic 104. Shift register 4202 in this example includes four flip-flops outputting four scan signals S0, S1, S2, S3 to pixel circuits 3700 with compensation circuits shown in FIG. 37 for driving the 6×2 subpixel array shown in FIG. 36.

FIG. 43 is a circuit diagram illustrating another example of a pixel circuit 4300 shared by two light emitting elements in accordance with an embodiment. Pixel circuit 4300 in this example is shared by two light emitting elements D1, D2 representing two subpixels from different groups of subpixels. Pixel circuit 4300 in this example includes a capacitor 4302, a light emitting control transistor 4304, a driving transistor 4306, two light emitting transistors 4308-1, 4308-2, and a switching transistor 4310. The light emitting elements D1, D2 may be OLEDs, such as top-emitting OLEDs, and each transistor may be a p-type transistor, such as a PMOS TFT. Pixel circuit 4300 may be operatively coupled to gate scanning driver 404 via a scan line 4314 and source writing driver 406 via a data line 4316. Additionally or optionally, a compensation circuit 4312 may be included in pixel circuit 4300 to ensure the brightness uniformities between the light emitting elements D1, D2. Compensation circuit 4312 can be in any configurations as known in the art, which includes one or more transistors and capacitors. Pixel circuit 4300 is suitable for any configuration of the coupling type of pixel circuits because in pixel circuit 4300 the data signal is coupled to the gate of driving transistor 4306 via capacitor 4302 when switching transistor 4310 is turned on during the charging period.

In this example, light emitting control transistor 4304 includes a gate electrode operatively coupled to a light emitting control signal EMC, a source electrode operatively coupled to a reference voltage Vref, and a drain electrode. The light emitting control signal EMC may be provided by light emitting control circuit 502 of light emitting driver 402. The light emitting control signal EMC in this example turns on light emitting control transistor 4304 during each of the two light emitting periods for the two light emitting elements D1, D2 within a frame period. The reference voltage Vref is provided for compensating the variations of the threshold voltage Vth of driving transistors, and the value of the reference voltage Vref may be determined based on the threshold voltage Vth of the driving transistors. Driving transistor 4306 includes a gate electrode operatively coupled to one electrode of capacitor 4302, a source electrode operatively coupled to the supply voltage Vdd, and a drain electrode. In each light emitting period (i.e., when light emitting control transistor 4304 is turned on) , driving transistor 4306 provides a driving current to one of the light emitting elements D1, D2 at a level determined based on the voltage level currently at a storage capacitor. In some embodiments, capacitor 4302 is the storage capacitor. In some embodiments, capacitor 4302 is a coupling capacitor, and pixel circuit 4302 includes another capacitor as the storage capacitor.

Each light emitting transistor 4308-1, 4308-2 includes a gate electrode operatively coupled to a respective light emitting signal EM1, EM2, a source electrode operatively coupled to the drain electrode of driving transistor 4306, and a drain electrode operatively coupled to the respective light emitting element D1, D2. During a light emitting period (i.e., when light emitting control transistor 4304 is turned on) , a driving current path is formed through the supply voltage Vdd, driving transistor 4306, one light emitting transistor 4308-1, 4308-2, and one of the light emitting elements D1, D2. Each light emitting signal EM1, EM2 turns on respective light emitting transistor 4308-1, 4308-2 during a respective one of the two light emitting periods within a frame period to cause the respective light emitting element D1, D2 to emit a light.

In this example, switching transistor 4310 includes a gate electrode operatively coupled to scan line 4314 transmitting a scan signal, a source electrode operatively coupled to data line 4316 transmitting a data signal, and a drain electrode. The scan signal may turn the switching transistor 4310 during each of the two charging periods within a frame period to cause the storage capacitor (e.g., capacitor 4302 in some embodiments) to be charged at a respective level in the data signal for the respective light emitting element D1, D2. As described above, the timing of the display data has been re-arranged in the converted display data to accommodate the frame-division and pixel circuit-sharing scheme disclosed herein. The storage capacitor (e.g., capacitor 4302 in some embodiments) may be charged twice in one frame period for the two light emitting elements D1, D2, respectively. During each charging period, the light emitting control signal EMC turns off light emitting control transistor 4304 to block the reference voltage Vref. The timings of various signals in pixel circuit 4300, e.g., EMC, EM1, EM2, Sn, Data, are the same as those shown in the timing diagram of FIG. 8.

FIG. 44 is a circuit diagram illustrating one example a pixel circuit 4400 with a compensation circuit shared by multiple light emitting elements in accordance with an embodiment. Compared with the exemplary coupling type pixel type circuit 4300 shown in FIG. 43, additional transistors and control signals (e.g., the reset signal Sn-1) are added to pixel circuit 4400 to form a compensation circuit, which eliminates the effect of non-uniformity of the mobility and threshold voltage Vth of the driving transistor. The multiple light emitting elements D1, …, DN in this example may be adjacent OLEDs in the same column when the array of OLEDs is divided in the scan direction. In the coupling type pixel circuit 4400, for example, eight transistors and one capacitor (8T1C) are used for driving two subpixels, and nine transistors and one capacitor (9T1C) are used for driving three subpixels. The average number of transistors per subpixel and the layout area of the coupling type pixel circuit 4400 is reduced compared with the known solutions, e.g., the coupling type pixel circuit 4800. The timings of various signals in pixel circuit 4400, e.g., EMC, EM1, …, EMN, Sn, Sn-1, Data, are the same as those shown in the timing diagrams of FIGs. 10, 13, 16, 20, 23, 25, 28, 31, 38, and 41.

FIG. 45 is a circuit diagram illustrating another example of a pixel circuit 4500 with a compensation circuit shared by multiple light emitting elements in accordance with an embodiment. Compared with the exemplary coupling type pixel circuit 4300 shown in FIG. 43, additional transistors, capacitors (e.g., the storage capacitor Cst) , and control signals (e.g., the reset signal Sn-1) are added to pixel circuit 4500 to form a compensation circuit, which eliminates the effect of non-uniformity of the mobility and threshold voltage Vth of the driving transistor. The multiple light emitting elements D1, …, DN in this example may be adjacent OLEDs in the same column when the array of OLEDs is divided in the scan direction. In the coupling type pixel circuit 4500, for example, six transistors and two capacitors (6T2C) are used for driving two subpixels, and seven transistors and two capacitors (7T2C) are used for driving three subpixels. The average number of transistors per subpixel and the layout area of the coupling type pixel circuit 4500 is reduced compared with the known solutions, e.g., the coupling type pixel circuit 4900.

FIG. 46 is a flow chart of a method for driving a display having an array of subpixels in accordance with an embodiment. It will be described with reference to the above figures. However, any suitable circuit, logic, unit, or module may be employed. Starting at 4602, original display data is received. At 4604, the original display data is stored in frames. 4602 and 4604 may be performed by the storing unit 612 of data converting module 604 of control logic 104. Proceeding to 4606, the original display data is converted into converted display data based on a manner in which an array of subpixels is divided into at least first and second groups of subpixels 4606.4606 may be performed by data reconstructing unit 614 of data converting module 604 of control logic 104. At 4608, in a first sub-frame period within a frame period, the first group of subpixels is scanned and caused to emit lights. At 4610, in a second sub-frame period within the frame period subsequent to the first sub-frame period, the second group of subpixels is scanned and caused to emit lights. 4608 and 4610 may be performed by light emitting driver 402 and gate scanning driver 404 in conjunction with

pixel circuits

700, 4300.

As described above with respect to FIG. 6, in some embodiments, control logic 104 may include data converting module 604 configured to reconstruct, in each frame, original display data 106 into corresponding converted display data 616 based on the order in which the groups of subpixels emit lights within the frame period. For scan-direction-division, the order corresponds to the scanning sequence of the rows of subpixels. In some embodiments, data converting module 604 may not be included in control logic 104. Instead, processor 114 may adjust the timing of original display data 106 by itself to accommodate the change of scanning sequence caused by the frame-division.

It is to be appreciated that because a number of subpixels (e.g., 2 or 3 subpixels) on display panel 210 may constitute one pixel, array of subpixels 400 on display panel 210 also form an array of pixels, and the division of array of subpixels 400 into groups of subpixels also causes the divisional of the array of pixels into groups of pixels. Moreover, as described above in some embodiments, display data 106 may be programmed at the pixel level. In the embodiments described below with respect to FIGs. 50-58, display data 106 will be referred as “pixel data, ” since each piece of display data 106 of a display frame corresponds to one pixel of the array of pixels on display panel 210. Accordingly, pixel data may be reordered by processor 114 based on the manner in which the array of pixels on display panel 210 is divided into the groups of pixels (i.e., frame-division) before the pixel data is received by control logic 104, as described below in detail with respect to FIGs. 50-58. Each group of pixels may include one or more rows of pixels according to scan-direction-division, one or more columns of pixels according to data-direction-division, and one or more blocks according to scan-data-direction-division, as described above in various embodiments of the present disclosure. The pixel data reordering apparatus and method in conjunction with the frame-division scheme disclosed herein can reduce the display latency without increasing the frame rate.

FIG. 50 is a block diagram illustrating one example of processor 114 shown in FIG. 1 in accordance with an embodiment. As described above, processor 114 may be any processor that can generate display data 118, e.g., pixel data 5000, in each frame and provide it to control logic 104. Processor 114 may be, for example, a GPU, AP, APU, or GPGPU. Processor 114 may also generate other data, such as but not limited to, control instructions 118 or test signals (not shown in FIG. 50) , and provide them to control logic 104. Pixel data 5000 in each frame provided by processor 114 is reordered from a native pixel data order to a rearranged pixel data order that is determined based on the manner in which the array of pixels is divided into groups of pixels, as described in any of the examples disclosed herein. For example, as described with respect to FIG. 3, the array of pixels on display panel 210 may be divided into groups of pixels in the scan direction (FIG. 3A) , in the data direction (FIG. 3B) , and in the scan and data directions (FIG. 3C) . In this example, processor 114 may include graphics pipelines 5002, a pixel data reordering module 5004, a frame buffer 5006, a data compressor 5008, and a data transmitter interface 5010.

Each graphics pipeline 5002 may be a 2D rendering pipeline or a 3D rendering pipeline that transfers 2D or 3D images having geometric primitives in the form of vertices into pieces of pixel data, each of which corresponds to one pixel on display panel 210. Graphics pipeline 5002 may be implemented as software (e.g., computing program) , hardware (e.g., processing units) , or combination thereof. Graphics pipeline 5002 may include multiple stages such as vertex shader for processing vertex data, rasterizer for converting vertices into fragments with interpolated data, pixel shader for computing lighting, color, depth, and texture of each piece of pixel data, and render output unit (ROP) for performing final processing (e.g., blending) to each piece of pixel data and write them into appropriate locations of frame buffer 5006. Each graphics pipeline 5002 may independently and simultaneously process a set of vertex data and generate the corresponding set of pixel data in parallel.

In this example, graphics pipelines 5002 may be configured to generate a plurality pieces of pixel data in a frame associated with a native pixel data order in which the plurality pieces of pixel data are to be provided to display panel 210. Each piece of pixel data may correspond to one pixel of the array of pixels on display panel 210. For example, for an FHD display panel with a resolution of 1920×1080, pixel data generated by graphics pipelines 5002 in each frame includes 1920×1080 pieces of pixel data, each of which represents a set of values of electrical signals to be applied to the respective pixel (e.g., consisting of a number of subpixels) . Pixel data in each frame generated by graphics pipelines 5002 may be stored in frame buffer 5006 before it can be provided to control logic 104. In some embodiments, frame buffer 5006 may store pixel data of each frame according to the native pixel data order in which the plurality pieces of pixel data are generated by graphics pipelines 5002. That is, the same order may be used for generating the plurality pieces of pixel data in a frame by graphics pipelines 5002 and for storing the plurality pieces of pixel data of the frame in frame buffer 5006.

In some embodiments, the native pixel data order may start at the upper-left pixel and ends at the lower-right pixel. Specifically, pixel data corresponding to the first row of pixels (top row) is provided first from left to right, and pixel data corresponding to the second row of pixels (the row below the top row) is then provided from left to right. Pixel data of other rows of pixels is subsequently provided from top to bottom until the pixel data corresponding to the last row of pixels (bottom row) is provided from left to right.

FIG. 58 illustrates one such example of a message 5800 including a plurality pieces of pixel data in a frame in accordance with an embodiment. As shown in FIG. 58, message 5800 starts with a vertical synchronization (VSYNC) signal, which is a timing signal used to reset the row pointer to the vertical edge (e.g., the top row of pixels) of display panel 210. That is, VSYNC may be indicative of the beginning of a new display frame. Following VSYNC, message 5800 includes a vertical back porch (VBP) field, which is used to specific the number of row clocks to insert at the beginning of each frame. Pixel data is then inserted into message 5800 after VBP and is arranged as a number of pixel rows 5802 that follows a pixel data order. In the example of the native pixel data order described above, pixel rows 5802 are arranged from the first row (top row) to the last row (bottom row) in sequence.

As shown in FIG. 58, each pixel row 5802 starts with a horizontal synchronization (HSYNC) signal, which is a timing signal used to reset the column pointer to the horizontal edge (e.g., the left column of pixels) of display panel 210. That is, HSYNC may be indicative of the beginning of a new pixel row 5802. Following HSYNC, pixel row 5802 includes a horizontal back porch (HBP) field, which is used to specific the number of dummy pixel clocks to insert at the beginning of each row of pixels. Pixel data of the corresponding pixel row 5802 is then inserted after HBP and is arranged as a number of pixel columns that follows the pixel data order. In the example of the native pixel data order described above, pixel columns are arranged from the first column (left column) to the last column (right column) in sequence. In this example, each pixel row 5802 ends at a horizontal front porch (HFP) field, which is used to specify the number of dummy pixel clocks to insert at the end of pixel row 5802. In other words, HFP may be indicative of the end of each pixel row 5802. Similarly, at the end of message 5800, a vertical front porch (VFP) field is used to specify the number of row clocks to insert at the end of the frame. In other words, VFP may be indicative of the end of message 5800 of each frame after all the pieces of pixel data of the frame are transmitted and/or stored.

In the example shown in FIG. 58, a plurality pieces of pixel data are arranged in series in a native pixel data order starting from the top row to the bottom row and starting from the left column to the right column within each row. Timing signals, such as VSYNC, HSYNC, VBP, HBP, VFP, and HVP, are used to organize and synchronize the stream of pixel data in each frame with the array of pixels on display panel 210. It is to be appreciated that in some embodiments, the native pixel data order may be different from the example shown in FIG. 58. For example, the native pixel data order may start from the bottom row to the top row and/or start from the right column to the left column within each row. It is also to be appreciated that in some embodiments, a larger, smaller, or different set of timing signals may be used to organize and synchronize the stream of pixel data in each frame with the array of pixels on display panel 210.

Referring back to FIG. 50, in this example, frame buffer 5006 may be operatively coupled to graphics pipelines 5002 and configured to store the plurality pieces of pixel data in each frame. Frame buffer 5006 may be any memory allocated for pixel data used to periodically refresh the display (i.e., display frame refreshed at a frame rate) . In some embodiments, the memory allocated to frame buffer 5006 may be shared with other devices, such as CPU core, direct memory access (DMA) , network, etc. Frame buffer 5006 may be organized as an array of pixel data cells, such as bits, bytes, half-words, or words, depending on, for example, the selected color depth and color bit organization. In some embodiments, pixel data may be packed bits (e.g., eight pixels/byte) , bytes (up to 256 colors) , 16-bit half-words (up to 64K colors) , or 24-bit words (up to 16 million colors) . Accordingly, the size of frame buffer 5006 may be computed based on the number of pixels (i.e., calculated based on the display resolution) and the size of each piece of pixel data. For example, for a display panel with a resolution of 800×600 and a color depth of 16 bits per pixel (bpp) , the size of the corresponding frame buffer is 960K bytes. In some embodiments, 24-bit data may be stored in a 32-bit field, tossing the high byte for each pixel. In this example, each piece of pixel data may be stored in RGB color space format. In other words, red, green, and blue components may be bit fields of one piece of pixel data’s color values, which are usually referred as bpp. The size of each bit field may vary in different examples, such as 8 bbp organized as a byte, 16 bpp organized as a half-word, and 24 bpp organized as a word in frame buffer 5006.

As described above, in some embodiments, the order in which the plurality pieces of pixel data in each frame are stored in frame buffer 5006 may be the same as the native pixel data order. FIG. 57A is a depiction of a frame buffer pixel map 5702 showing pixel data stored in frame buffer 5006 in the native pixel data order. Each block of frame buffer pixel map 5702 corresponds to a data cell storing a piece of pixel data, which in turn corresponds to a pixel on display panel 210. Each data cell of a piece of pixel data may store color values of red, green, and blue components. In this example, frame buffer pixel map 5702 has 54 data cells used to store 54 pieces of pixel data in each frame for a display panel having an array of 9×6 pixels. The native pixel data order begins at the upper-left data cell (I-1) and ends at the lower-right data cell (IX-6) . In this example, the native pixel data order follows the same top-to-bottom and left-to-right sequence as described above with respect to FIG. 58. That is, the native pixel data order begins at the upper-left data cell (I-1) and continues for the rest of the data cells in the first row (1) from the left column (I) to the right column (IX) . The data cell following the last data cell of the first row (IX-1) is the left column data cell of the second row (I-2) . The same sequence is then repeated for the rest of the data cells until the last data cell (IX-6) at the lower-right of frame buffer pixel map 5702.

Returning to FIG. 50, in this example, data compressor 5008 may be operatively coupled to frame buffer 5006 and configured to encode the plurality pieces of pixel data of each frame received from frame buffer 5006. Data compressor 5008 may apply any suitable encoding algorithms, such as but not limited to VESA display stream compression (DSC) algorithm, various Huffman coding algorithms, run-length encoding (RLE) algorithm, differential pulse code modulation (DPCM) algorithm, various lossy compression algorithms, or the like, to compress pixel data in order to reduce bandwidth and power consumption. It is to be appreciated that in some embodiments, pixel data compression may not be necessary, and data compressor 5008 may be omitted.

In this example, data transmitter interface 5010 may be operatively coupled to data compressor 5008 and configured to transmit pixel data 5000, either encoded or non-encoded, including the plurality pieces of pixel data of each frame. Data transmitter interface 5010 may be any suitable display interface between processor 114 and control logic 104, such as but not limited to display serial interface (DSI) , display pixel interface (DPI) , and display bus interface (DBI) by the Mobile Industry Processor Interface (MIPI) Alliance, unified display interface (UDI) , DVI, HDMI, and DP. In addition to transmitting pixel data 5000 to control logic 104, data transmitter interface 5010 may also transmit other control data (e.g., commands/instructions) or status information to control logic 104 and/or receive information (e.g., status or pixel information) from control logic 104 or display panel 210. For example, the manner in which the array of pixels are divided into groups of pixels (i.e., information related to frame-division scheme) may be communicated between processor 114 and control logic 104 or processor and display panel 210 via data transmitter interface 5010. As described above, based on the specific interface standard adopted by data transmitter interface 5010, pixel data 5000 may be transmitted in series in the corresponding data format along with any suitable timing signals, such as the ones shown in FIG. 58. Although in FIG. 58, data transmitter interface 5010 receives pixel data from data compressor 5008, it is to be appreciated that in some embodiments, data compressor 5008 may be omitted, and data transmitter interface 5010 may receive non-encoded pixel data from frame buffer 5006.

In this example, pixel data reordering module 5004 may be operatively coupled to frame buffer 5006, data compressor 5008, and data transmitter interface 5010. Pixel data reordering module 5004 may be configured to cause the plurality pieces of pixel data of a frame to be obtained by display panel 210 reordered from the native pixel data order to a rearranged pixel data order, which is determined based on the manner in which the array of pixels on display panel 210 are divided into groups of pixels. In other words, pixel data reordering module 5004 may control various components in processor 114, e.g., frame buffer 5006, data compressor 5008, and/or data transmitter interface 5010, to change the pixel data order to adapt the frame-division scheme on display panel 210, as described above in various embodiments. As a result, pixel data 5000 provided by processor 114 may include a plurality pieces of pixel data in the rearranged pixel data order, as opposed to the native pixel data order, for each frame. The frame-division scheme, i.e., the manner in which the array of pixels on display panel 210 are divided, may be preset and stored in pixel data reordering module 5004 or dynamically updated and provided to pixel data reordering module 5004 from display panel 210 and/or control logic 104 via data transmitter interface 5010. In some embodiments, pixel data reordering module 5004 may be adapted to various types of display panels 210 with different frame-division schemes by receiving the frame-division scheme information via data transmitter interface 5010. In some embodiments, even for the same display panel 210, the frame-division scheme may be dynamically changed from time to time and/or in view of certain events, and pixel data reordering module 5004 may be adapted to the dynamically-changed frame-division scheme at runtime by receiving the frame-division scheme update information via data transmitter interface 5010. In some embodiments, pixel data reordering module 5004 may cause the information of the frame-division, i.e., the manner in which the array of pixels are divided, to be transmitted to control logic 104 via data transmitter interface 5010 as part of the status information. For example, the frame-division information may be used by control logic 104 to decode the encoded pixel data based on the rearranged pixel data order. It is to be appreciated that in some embodiments, frame-division information may be provided by display panel 210 to control logic 104 or already stored in control logic 104 so that transmission of frame-division information from processor 114 becomes unnecessary.

In this embodiment, pixel data reordering module 5004 may be further configured to determine the rearranged pixel data order based on the obtained frame-division scheme either offline or at runtime. FIG. 57B illustrates a frame-division scheme of a display panel pixel array 5704 and the rearranged pixel data order determined by pixel data reordering module 5004 based on the frame-division scheme. In this example, display panel pixel array 5704 includes 54 pixels arranged in nine columns and six rows. In this example, scan-direction-division is applied to divide display panel pixel array 5704 into two groups of pixels: the first

group including rows

1, 3, and 5, and the second

group including rows

2, 4, and 6. As described above, each of

rows

1 and 2,

rows

3 and 4, and

rows

5 and 6 can share the same pixel circuits and emit during subsequent two sub-frame periods, respectively, in a frame period, thereby reducing the area and complexity of pixel circuits and the display latency without increasing the frame rate. According to the scan-direction-divisional, pixel data reordering module 5004 can determine the corresponding rearranged pixel data order as shown in FIG. 57B. The rearranged pixel data order may follow the scan sequence of display panel 210 adapted to the scan-direction-division scheme (row 1, row 3, row 5, row 2, row 4, and row 6) . That is, after the pixel in the last column of the first row (IX-1) , instead of the pixel in the first column of the second row (I-2) as in the native pixel data order, it is followed by the pixel in the first column of the third row (I-3) , which is in the same pixel group as the first row of pixels. After the last pixel of the first pixel group (IX-5) , it is followed by the first pixel of the second pixel group (I-2) and continued in the same manner until the last pixel of the second pixel group (IX-6) . Compared to the native pixel data order as shown in FIG. 57A, due to the scan-direction-division applied to display panel pixel array 5704, the rearranged pixel data order follows an interlaced manner of the odd and even rows of pixels, respectively. Within each row of pixels, the rearranged pixel data order may be the same as the native pixel data order, both of which may be from the left column to the right column. As described above, the purpose of reordering pixel data is to adapt the frame-division scheme applied to display panel 210 so that the desired images and videos can still be correctly presented on display panel 210 despite the change of scan and emitting sequences of each subpixel on display panel 210.

In some embodiments, pixel data reordering module 5004 may control frame buffer 5006 to provide the plurality pieces of pixel data of each frame in the rearranged pixel data order. As described above with respect to FIG. 57A, the plurality pieces of pixel data of each frame may be stored in frame buffer 5006 according to frame buffer pixel map 5702 that follows the native pixel data order. When the stored pixel data of each frame is retrieved from frame buffer 5006, pixel data reordering module 5004 may control frame buffer 5006 to output the pixel data in the rearranged pixel data order, for example as shown in FIG. 57B, which adapts the frame-division scheme of display panel pixel array 5704. Data compressor 5008 then may receive the plurality pieces of pixel data in each frame in the rearranged pixel data order from frame buffer 5006 and encode the received pixel data based on the rearranged pixel data order. It is to be appreciated that certain encoding algorithms may rely on the manner in which the stream of pixel data is arranged (e.g., the pixel data order) to encode data. Thus, the encoding results of the same stream of pixel data in the native pixel data order and in the rearranged pixel data order may be different.

In some embodiments, pixel data reordering module 5004 may not control frame buffer 5006 to provide the plurality pieces of pixel data of each frame in the rearranged pixel data order, and the stored pixel data of each frame may be retrieved from frame buffer 5006 in the native pixel data order. Instead, the reordering may occur at data compressor 5008. For example, data compressor 5008 may receive the plurality pieces of pixel data of each frame in the native pixel data order, and pixel data reordering module 5004 may control data compressor 5008 to encode the received pixel data of each frame based on the rearranged pixel data order. That is, pixel data reordering and encoding may be performed together by data compressor 5008 in conjunction with pixel data reordering module 5004. It is to be appreciated that as certain compression algorithms may rely on the manner in which the stream of pixel data is arranged (e.g., the pixel data order) to encode data, in some embodiments, pixel data reordering module 5004 may control data compressor 5008 to dynamically select a compression algorithm that is suitable for the adapted frame-division scheme. For example, if the frame-division scheme is scan-direction-divisional, meaning that the pixel data in the rearranged pixel data order does not match the pixel arrangement on display panel 210 in the scan direction (in columns) , then a compression algorithm that does not rely on pixel arrangement in the scan direction (in columns) may be selected for encoding. In another example, if the frame-division scheme is scan-data-direction-divisional (i.e., each pixel group including blocks of pixels) , then a compression algorithm that is based on pixel blocks may be selected for encoding.

In some embodiments, pixel data reordering module 5004 may not control frame buffer 5006 to provide the plurality pieces of pixel data of each frame in the rearranged pixel data order, and processor 114 may not include data compressor 5008. Thus, the plurality pieces of pixel data of each frame in the native pixel data order may be received by data transmitter interface 5010. Pixel data reordering module 5004 then may control data transmitter interface 5010 to transmit the plurality pieces of pixel data of each frame in the rearranged pixel data order. That is, pixel data reordering and transmission may be performed together by data transmitter interface 5010 in conjunction with pixel data reordering module 5004. It is to be appreciated that in some embodiments, data transmitter interface 5010 may receive the plurality pieces of pixel data of each frame in the native pixel data order directly from graphics pipelines 5002 instead of from frame buffer 5006.

FIG. 51 is a block diagram illustrating another example of control logic 104 shown in FIG. 1 in accordance with an embodiment. Control logic 104 may be configured to provide the plurality pieces of pixel data of each frame in the rearranged pixel data order to display panel 210. In this example, control logic 104 may include a data receiver interface 5102 and a data decompressor 5104. It is to be appreciated that control logic 104 may include additional components, such as control signal generating module 602, as described above with respect to FIG. 6.

In this example, data receiver interface 5102 may be configured to receive pixel data 5000 including the plurality pieces of pixel data of each frame in the rearranged order from data transmitter interface 5010. Data receiver interface 5102 may be any suitable display interface between processor 114 and control logic 104, such as but not limited to DSI, DPI, and DBI by the MIPI Alliance, UDI, DVI, and DP. In some embodiments, control data and status information including information related to frame-division scheme, may be received by data receiver interface 5102 from data transmitter interface 5010 as well.

In some embodiments, if pixel data 5000 has been encoded by data compressor 5008, data decompressor 5104 may decode the encoded plurality pieces of pixel data of each frame based on the rearranged pixel data order so that the plurality pieces of pixel data of each frame can be decompressed and provided in the rearranged pixel data order to display panel 210. Any suitable decoding algorithm corresponding to the encoding algorithm used by data compressor 5008 may be implemented by data decompressor 5104, such as VESA DSC algorithm, various Huffman coding algorithms, RLE algorithm, or differential pulse code modulation DPCM algorithm.

FIG. 52 is a block diagram illustrating a VR/AR system 5200 in accordance with an embodiment. VR/AR system 5200 may include a display subsystem 5202 and a tracking subsystem 5204. Display subsystem 5202 may include processor 114, control logic 104, and display panel 210, which implement the frame-division and pixel circuit-sharing scheme disclosed herein. As a result, high resolution display (e.g., FHD) with low display latency (e.g., less than 20 ms) can be provided by display subsystem 5202 to meet the requirement of VR/AR system 5200. In this example, tracking subsystem 5204 may be operatively coupled to display subsystem 5202 and configured to track motion of a user of VR/AR system 5200, such as motion of eyeballs, facial expression, body movement, and hand gesture. For example, tracking subsystem 5204 may include an inertial sensor, a camera, an eye tracker, a GPS, or any other suitable tracking device.

FIG. 53 is a flow chart of a method for processing pixel data in accordance with an embodiment. It will be described with reference to the above figures. However, any suitable circuit, logic, unit, or module may be employed. The method can be performed by any suitable circuit, logic, unit, or module that can comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc. ) , software (e.g., instructions executing on a processing device) , or a combination thereof. It is to be appreciated that not all steps may be needed to perform the disclosure provided herein. Further, some of the steps may be performed simultaneously, or in a different order than shown in FIG. 53, as will be understood by a person of ordinary skill in the art.

Starting at 5302, pixel data of a frame is generated. The pixel data of the frame is associated with a first order (native pixel data order) in which the pixel data is to be provided to display panel 210. Display panel 210 has an array of pixels, and each piece of pixel data of the frame corresponds to one pixel of the array of pixels. The array of pixels are divided into multiple groups of pixels. 5302 may be performed by graphics pipelines 5002 of processor 114. At 5304, a second order (rearranged pixel data order) is determined based on the manner in which the array of pixels is divided into the multiple groups of pixels. For example, each group of pixels may include one or more rows, columns, and/or blocks of pixels. 5304 may be performed by pixel data reordering module 5004 of processor 114. At 5306, the pixel data of the frame is caused to be obtained by display panel 210 in the second order. That is, the order in which the pixel data is obtained by display panel 210 is changed from the first order to the second order to accommodate the division of the pixel array on display panel 210.5306 may be performed by pixel data reordering module 5004 alone or in conjunction with any other components of processor 114 and control logic 104.

FIG. 54 is a flow chart of one example of a method for reordering pixel data in accordance with an embodiment. It will be described with reference to the above figures. However, any suitable circuit, logic, unit, or module may be employed. The method can be performed by any suitable circuit, logic, unit, or module that can comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc. ) , software (e.g., instructions executing on a processing device) , or a combination thereof. It is to be appreciated that not all steps may be needed to perform the disclosure provided herein. Further, some of the steps may be performed simultaneously, or in a different order than shown in FIG. 54, as will be understood by a person of ordinary skill in the art.

Starting at 5402, the pixel data of a frame is stored by a frame buffer, such as frame buffer 5006 of processor 114. At 5404, the frame buffer is controlled, for example by pixel data reordering module 5004 of processor 114, to provide the pixel data of the frame in the second order. At 5406, the pixel data of the frame is received in the second order from the frame buffer, for example, by data compressor 5008 of processor 114. At 5408, the pixel data of the frame is encoded based on at least the second order. 5408 may be performed by data compressor 5008 of processor 114. That is, in this example, the pixel data is reordered before it is compressed, and the compression is performed on reordered pixel data.

FIG. 55 is a flow chart of another example of a method for reordering pixel data in accordance with an embodiment. It will be described with reference to the above figures. However, any suitable circuit, logic, unit, or module may be employed. The method can be performed by any suitable circuit, logic, unit, or module that can comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc. ) , software (e.g., instructions executing on a processing device) , or a combination thereof. It is to be appreciated that not all steps may be needed to perform the disclosure provided herein. Further, some of the steps may be performed simultaneously, or in a different order than shown in FIG. 55, as will be understood by a person of ordinary skill in the art.

Starting at 5502, the pixel data of a frame is received by a data transmitter interface, such as data transmitter interface 5010 of processor 114, in the first order. At 5504, the data transmitter interface is controlled, for example by pixel data reordering module 5004 of processor 114, to transmit the pixel data of the frame in the second order. That is, in this example, the pixel data is not reordered until it is being transmitted.

FIG. 56 is a flow chart of still another example of a method for reordering pixel data in accordance with an embodiment. It will be described with reference to the above figures. However, any suitable circuit, logic, unit, or module may be employed. The method can be performed by any suitable circuit, logic, unit, or module that can comprise hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc. ) , software (e.g., instructions executing on a processing device) , or a combination thereof. It is to be appreciated that not all steps may be needed to perform the disclosure provided herein. Further, some of the steps may be performed simultaneously, or in a different order than shown in FIG. 56, as will be understood by a person of ordinary skill in the art.

Starting at 5602, the pixel data of a frame is received by a data compressor, such as data compressor 5508 of processor 114, in the first order. At 5604, the data compressor is controlled, for example by pixel data reordering module 5004 of processor 114, to encode the pixel data of the frame based on at least the second order. That is, in this example, the pixel data is not reordered until it is being compressed.

Also, integrated circuit design systems (e.g. work stations) are known that create wafers with integrated circuits based on executable instructions stored on a computer-readable medium such as but not limited to CDROM, RAM, other forms of ROM, hard drives, distributed memory, etc. The instructions may be represented by any suitable language such as but not limited to hardware descriptor language (HDL) , Verilog or other suitable language. As such, the logic, units, and circuits described herein may also be produced as integrated circuits by such systems using the computer-readable medium with instructions stored therein.

For example, an integrated circuit with the aforedescribed logic, units, and circuits may be created using such integrated circuit fabrication systems. The computer-readable medium stores instructions executable by one or more integrated circuit design systems that causes the one or more integrated circuit design systems to design an integrated circuit. In one example, the designed integrated circuit includes a control signal generating module and a data converting module. The integrated circuit controls driving of an array of subpixels divided into k groups of subpixels, where k is an integer larger than 1. The control signal generating module is configured to provide a plurality of control signals to one or more drivers. The plurality of control signals control the one or more drivers to cause each of the k groups of subpixels to sequentially emit lights in a respective one of k sub-frame periods within a frame period. The data converting module is configured to convert original display data into converted display data based on a manner in which the array of subpixels is divided into the k groups of subpixels. The k groups of subpixels emit lights based on the converted display data.

In another example, the designed integrated circuit includes a graphics pipeline and a pixel data reordering module. The graphics pipeline is configured to generate a plurality pieces of pixel data of a frame. The plurality pieces of pixel data of the frame are associated with a first order in which the plurality pieces of pixel data of the frame are to be provided to a display panel having an array of pixels. Each piece of pixel data of the frame corresponds to one pixel of the array of pixels. The array of pixels are divided into a plurality of groups of pixels. The pixel data reordering module is configured to cause the plurality pieces of pixel data of the frame to be obtained by the display panel in a second order. The second order is determined based on at least a manner in which the array of pixels are divided into the groups of pixels.

The above detailed description of the disclosure and the examples described therein have been presented for the purposes of illustration and description only and not by limitation. It is therefore contemplated that the present disclosure cover any and all modifications, variations or equivalents that fall within the spirit and scope of the basic underlying principles disclosed above and claimed herein.

Claims

A apparatus, comprising:

a graphics pipeline configured to generate a plurality pieces of pixel data of a frame, wherein

the plurality pieces of pixel data of the frame are associated with a first order in which the plurality pieces of pixel data of the frame are to be provided to a display panel having an array of pixels,

each piece of the plurality pieces of pixel data of the frame corresponds to one pixel of the array of pixels, and

the array of pixels are divided into a plurality of groups of pixels； and

a pixel data reordering module configured to cause the plurality pieces of pixel data of the frame to be obtained by the display panel in a second order, wherein the second order is determined based on at least a manner in which the array of pixels are divided into the plurality of groups of pixels.
The apparatus of claim 1, wherein each group of the plurality of groups of pixels comprises one or more rows of pixels.
The apparatus of claim 1, wherein each group of the plurality of groups of pixels comprises one or more columns of pixels.
The apparatus of claim 1, wherein each group of the plurality of groups of pixels comprises one or more blocks of pixels.
The apparatus of claim 1, wherein the pixel data reordering module is further configured to determine the second order based on at least the manner in which the array of pixels are divided into the plurality of groups of pixels.
The apparatus of claim 1, wherein the pixel data reordering module is further configured to cause information related to the manner in which the array of pixels are divided into the plurality of groups of pixels to be transmitted to control logic operatively coupled to the display panel.
The apparatus of claim 1, further comprising:

a frame buffer, operatively coupled to the graphics pipeline and the pixel data reordering module, configured to store the plurality pieces of pixel data of the frame,

wherein the pixel data reordering module is further configured to control the frame buffer to provide the plurality pieces of pixel data of the frame in the second order.
The apparatus of claim 7, further comprising:

a data compressor, operatively coupled to the frame buffer, configured to receive the plurality pieces of pixel data of the frame in the second order from the frame buffer and encode the plurality pieces of pixel data of the frame based on at least the second order.
The apparatus of claim 1, further comprising:

a data transmitter interface, operatively coupled the pixel data reordering module, configured to receive the plurality pieces of pixel data of the frame in the first order,

wherein the pixel data reordering module is further configured to control the data transmitter interface to transmit the plurality pieces of pixel data of the frame in the second order.
The apparatus of claim 1, further comprising:

a data compressor, operatively coupled to the pixel data reordering module, configured to receive the plurality pieces of pixel data of the frame in the first order and encode the plurality pieces of pixel data of the frame； and

wherein the pixel data reordering module is further configured to control the data compressor to encode the plurality pieces of pixel data of the frame based on at least the second order.
A apparatus, comprising:

a graphics processing unit comprising:

a graphics pipeline configured to generate a plurality pieces of pixel data of a frame, wherein

the plurality pieces of pixel data of the frame are associated with a first order in which the plurality pieces of pixel data of the frame are to be provided to a display panel having an array of pixels,

each piece of the plurality pieces of pixel data of the frame corresponds to one pixel of the array of pixels, and

the array of pixels are divided into a plurality of groups of pixels, and

a pixel data reordering module configured to cause the plurality pieces of pixel data of the frame to be obtained by the display panel in a second order, wherein the second order is determined based on at least a manner in which the array of pixels are divided into the plurality of groups of pixels； and

control logic, operatively coupled to the graphics processing unit, configured to provide the plurality pieces of pixel data of the frame in the second order to the display panel.
The apparatus of claim 11, wherein each group of the plurality of groups of pixels comprises one or more rows of pixels.
The apparatus of claim 11, wherein each group of the plurality of groups of pixels comprises one or more columns of pixels.
The apparatus of claim 11, wherein each group of the plurality of groups of pixels comprises one or more blocks of pixels.
The apparatus of claim 11, wherein the pixel data reordering module is further configured to determine the second order based on at least the manner in which the array of pixels are divided into the plurality of groups of pixels.
The apparatus of claim 11, wherein the pixel data reordering module is further configured to cause information related to the manner in which the array of pixels are divided into the plurality of groups of pixels to be transmitted from the graphics processing unit to the control logic.
The apparatus of claim 11, wherein the graphics processing unit further comprises:

a frame buffer, operatively coupled to the graphics pipeline and the pixel data reordering module, configured to store the plurality pieces of pixel data of the frame,

wherein the pixel data reordering module is further configured to control the frame buffer to provide the plurality pieces of pixel data of the frame in the second order.
The apparatus of claim 17, wherein

the graphics processing unit further comprises a data transmitter interface, operatively coupled to the frame buffer, configured to receive the plurality pieces of pixel data of the frame in the second order from the frame buffer and transmit the plurality pieces of pixel data of the frame in the second order to the control logic； and

the control logic further comprises a data receiver interface configured to receive the plurality pieces of pixel data of the frame in the second order from the data transmitter interface.
The apparatus of claim 17, wherein

the graphics processing unit further comprises a data compressor, operatively coupled to the frame buffer, configured to receive the plurality pieces of pixel data of the frame in the second order from the frame buffer and encode the plurality pieces of pixel data of the frame based on at least the second order； and

the control logic further comprises a data decompressor configured to decode the encoded plurality pieces of pixel data of the frame based on at least the second order and provide the plurality pieces of pixel data of the frame in the second order.
The apparatus of claim 11, wherein

the graphics processing unit further comprises a data transmitter interface, operatively coupled to the pixel data reordering module, configured to receive the plurality pieces of pixel data of the frame in the first order, wherein the pixel data reordering module is further configured to control the data transmitter interface to transmit the plurality pieces of pixel data of the frame in the second order to the control logic； and

the control logic further comprises a data receiver interface configured to receive the plurality pieces of pixel data of the frame in the second order from the data transmitter interface.
The apparatus of claim 11, wherein

the graphics processing unit further comprises a data compressor, operatively coupled to the pixel data reordering module, configured to receive the plurality pieces of pixel data of the frame in the first order and encode the plurality pieces of pixel data of the frame, wherein the pixel data reordering module is further configured to control the data compressor to encode the plurality pieces of pixel data of the frame based on at least the second order； and

the control logic further comprises a data decompressor configured to decode the encoded plurality pieces of pixel data of the frame based on at least the second order and provide the plurality pieces of pixel data of the frame in the second order.
A display system, comprising:

a display panel having an array of pixels divided into a plurality of groups of pixels；

a graphics processing unit comprising:

a graphics pipeline configured to generate a plurality pieces of pixel data of a frame, wherein the plurality pieces of pixel data of the frame are associated with a first order in which the plurality pieces of pixel data of the frame are to be provided to the display panel, and each piece of the plurality pieces of pixel data of the frame corresponds to one pixel of the array of pixels, and

a pixel data reordering module configured to cause the plurality pieces of pixel data of the frame to be obtained by the display panel in a second order, wherein the second order is determined based on at least a manner in which the array of pixels are divided into the plurality of groups of pixels； and

control logic, operatively coupled to the graphics processing unit and the display panel, configured to provide the plurality pieces of pixel data of the frame in the second order to the display panel.
The display system of claim 22, wherein each group of the plurality of groups of pixels comprises one or more rows of pixels.
The display system of claim 22, wherein each group of the plurality of groups of pixels comprises one or more columns of pixels.
The display system of claim 22, wherein each group of the plurality of groups of pixels comprises one or more blocks of pixels.
The display system of claim 22, wherein the pixel data reordering module is further configured to determine the second order based on at least the manner in which the array of pixels are divided into the plurality of groups of pixels.
The display system of claim 22, wherein the pixel data reordering module is further configured to cause information related to the manner in which the array of pixels are divided into the plurality of groups of pixels to be transmitted from the graphics processing unit to the control logic.
The display system of claim 22, wherein the graphics processing unit further comprises:

a frame buffer, operatively coupled to the graphics pipeline and the pixel data reordering module, configured to store the plurality pieces of pixel data of the frame,

wherein the pixel data reordering module is further configured to control the frame buffer to provide the plurality pieces of pixel data of the frame in the second order.
The display system of claim 28, wherein

the graphics processing unit further comprises a data transmitter interface, operatively coupled to the frame buffer, configured to receive the plurality pieces of pixel data of the frame in the second order from the frame buffer and transmit the plurality pieces of pixel data of the frame in the second order to the control logic； and

the control logic further comprises a data receiver interface configured to receive the plurality pieces of pixel data of the frame in the second order from the data transmitter interface.
The display system of claim 28, wherein

the graphics processing unit further comprises a data compressor, operatively coupled to the frame buffer, configured to receive the plurality pieces of pixel data of the frame in the second order from the frame buffer and encode the plurality pieces of pixel data of the frame based on at least the second order； and

the control logic further comprises a data decompressor configured to decode the encoded plurality pieces of pixel data of the frame based on at least the second order and provide the plurality pieces of pixel data of the frame in the second order.
The display system of claim 22, wherein

the graphics processing unit further comprises a data transmitter interface, operatively coupled to the pixel data reordering module, configured to receive the plurality pieces of pixel data of the frame in the first order, wherein the pixel data reordering module is further configured to control the data transmitter interface to transmit the plurality pieces of pixel data of the frame in the second order to the control logic； and

the control logic further comprises a data receiver interface configured to receive the plurality pieces of pixel data of the frame in the second order from the data transmitter interface.
The display system of claim 22, wherein

the graphics processing unit further comprises a data compressor, operatively coupled to the pixel data reordering module, configured to receive the plurality pieces of pixel data of the frame in the first order and encode the plurality pieces of pixel data of the frame, wherein the pixel data reordering module is further configured to control the data compressor to encode the plurality pieces of pixel data of the frame based on at least the second order； and

the control logic further comprises a data decompressor configured to decode the encoded plurality pieces of pixel data of the frame based on at least the second order and provide the plurality pieces of pixel data of the frame in the second order.
A system for virtual reality or augmented reality, comprising:

a display subsystem comprising:

a display panel having an array of pixels divided into a plurality of groups of pixels, a graphics processing unit comprising:

a graphics pipeline configured to generate a plurality pieces of pixel data of a frame, wherein the plurality pieces of pixel data of the frame are associated with a first order in which the plurality pieces of pixel data of the frame are to be provided to the display panel, and each piece of the plurality pieces of pixel data of the frame corresponds to one pixel of the array of pixels, and

a pixel data reordering module configured to cause the plurality pieces of pixel data of the frame to be obtained by the display panel in a second order, wherein the second order is determined based on at least a manner in which the array of pixels are divided into the plurality of groups of pixels, and

control logic, operatively coupled to the graphics processing unit and the display panel, configured to provide the plurality pieces of pixel data of the frame in the second order to the display panel； and

a tracking subsystem, operatively coupled to the display subsystem, and configured to track motion of a user of the system.
The system of claim 33, wherein the tracking subsystem comprises at least one of an inertial sensor, a camera, and a global positioning system (GPS) .
A method of providing pixel data, comprising:

generating a plurality pieces of pixel data of a frame, wherein

the plurality pieces of pixel data of the frame are associated with a first order in which the plurality pieces of pixel data of the frame are to be provided to a display panel having an array of pixels,

each piece of the plurality pieces of pixel data of the frame corresponds to one pixel of the array of pixels, and

the array of pixels are divided into a plurality of groups of pixels； and

determining a second order based on at least a manner in which the array of pixels are divided into the plurality of groups of pixels； and

causing the plurality pieces of pixel data of the frame to be obtained by the display panel in the second order.
The method of claim 35, wherein each group of the plurality of groups of pixels comprises one or more rows of pixels.
The method of claim 35, wherein each group of the plurality of groups of pixels comprises one or more columns of pixels.
The method of claim 35, wherein each group of the plurality of groups of pixels comprises one or more blocks of pixels.
The method of claim 35, wherein causing the plurality pieces of pixel data of the frame to be obtained by the display panel in the second order comprises:

storing, by a frame buffer, the plurality pieces of pixel data of the frame； and

controlling the frame buffer to provide the plurality pieces of pixel data of the frame in the second order.
The method of claim 39, wherein causing the plurality pieces of pixel data of the frame to be obtained by the display panel in the second order further comprises:

receiving the plurality pieces of pixel data of the frame in the second order from the frame buffer； and

encoding the plurality pieces of pixel data of the frame based on at least the second order.
The method of claim 35, wherein causing the plurality pieces of pixel data of the frame to be obtained by the display panel in the second order comprises:

receiving, by a data transmitter interface, the plurality pieces of pixel data of the frame in the first order, and

controlling the data transmitter interface to transmit the plurality pieces of pixel data of the frame in the second order.
The method of claim 35, wherein causing the plurality pieces of pixel data of the frame to be obtained by the display panel in the second order comprises:

receiving, by a data compressor, the plurality pieces of pixel data of the frame in the first order； and

controlling the data compressor to encode the plurality pieces of pixel data of the frame based on at least the second order.