WO2017106040A1 - Ultrasound t/r isolation diode with fast recovery time on soi - Google Patents

Ultrasound t/r isolation diode with fast recovery time on soi Download PDF

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Publication number
WO2017106040A1
WO2017106040A1 PCT/US2016/065872 US2016065872W WO2017106040A1 WO 2017106040 A1 WO2017106040 A1 WO 2017106040A1 US 2016065872 W US2016065872 W US 2016065872W WO 2017106040 A1 WO2017106040 A1 WO 2017106040A1
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Prior art keywords
type well
approximately
semiconductor device
type
microns
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French (fr)
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Hua Yang
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Microchip Technology Inc
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Microchip Technology Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/114—PN junction isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/128—Anode regions of diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Definitions

  • the present disclosure relates generally to a disolator that may increase the forward current conducted by the device, while reducing capacitance and improving recovery time.
  • Ultrasound transmission/receiver circuits often include diodes, bipolar junction transistors (BJTs), or silicon controlled rectifiers (SCRs) in order to pass large current and isolate the signal from noise within the circuit.
  • Diode and BJT arrays employ multiple p-type and n-type electrodes.
  • SCRs are solid-state current controlling devices that have four layers of alternating p-type and n-type semiconductor material (PNPN).
  • PNPN alternating p-type and n-type semiconductor material
  • diodes, BJTs, and SCRs typically use lightly doped n-type and p-type semiconductor materials, which limits the amount of forward current.
  • the n-type and p-type wells must be made larger, which is disadvantageous for many
  • the increased size causes the negative effect of increasing the capacitance.
  • an integrated disolator device that may achieve an increased forward current, maintain a fast reverse recovery time, but without increasing the size or capacitance of the device.
  • the device may include a silicon- on-insulator (SOI) substrate, a body layer disposed on the SOI substrate, a first p-type well disposed on the body layer, a first n-type well disposed on the first p-type well to form a first p-n junction, and a second p-type well that is spaced a predetermined distance from at least one of the first p-type well and the first n-type well.
  • SOI silicon- on-insulator
  • the p-type well may be circular in shape and may surround the first p-type well and the first n-type well.
  • the first p-type well and the first n-type well may be circular in shape.
  • the diameter of the first p-type well may be less than the diameter of the first n-type well.
  • the diameter of the first p-type well may be approximately 3 microns, and the diameter of the first n-type well may be approximately 7 microns.
  • the first p-type well may have a vertical depth of approximately 0.5 microns, and the first n-type well may have a vertical depth of approximately 0.25 microns.
  • the second p-type well may be more heavily doped than the first p-type well.
  • the second p-type well may have a doping concentration of approximately 2xl0 19 /cm 3
  • the first p-type well may have a doping concentration of approximately 5xl0 18 /cm 3 .
  • the first n-type well may be more heavily doped than the first p-type well.
  • the first n-type well may have a doping concentration of approximately 2xl0 19 /cm 3
  • the first p-type well may have a doping concentration of approximately 5xl0 18 /cm 3 .
  • the doping concentration of the first p-type well may be approximately 2.5 times greater than a doping concentration of the body layer.
  • the first p-type well and the second p-type well may be spaced apart by approximately 3.5 microns. The distance from the first n-type well to the second p-type well may be approximately two microns.
  • the device according to one or more exemplary embodiments may also include a third p-type well disposed on the body layer and outside of the second p-type well and a second n-type well disposed on the third p-type well to form a second p-n junction. The second n-type well may be disposed outside of the second p-type well.
  • the second n-type well may be spaced approximately 7 microns from the first n-type well.
  • the center point of the first n-type well may be spaced approximately 17 microns from the center point of the second n-type well.
  • Fig. 1 is a cross-sectional view of a disolator device according to an exemplary embodiment.
  • FIG. 2 is a top view of a disolator device according to an exemplary embodiment.
  • a device may include a silicon-on-insulator (SOI) substrate 100, which may be made of an oxide, or other material such as sapphire.
  • SOI silicon-on-insulator
  • a p-type body layer 105 may be disposed on the SOI, and may include one or more p-type wells.
  • the device includes three p-type wells 110, 111, and 112. The p-type wells 110, 111, and 112 may be more heavily doped than p-type body layer 105.
  • the three p-type wells 110, 111, and 112 may have a doping concentration of approximately 5xl0 18 /cm 3
  • the p-type body layer 105 may have a doping concentration of approximately 2xl0 18 /cm 3 , however other doping concentrations and relative doping concentrations may be used.
  • the device according to the exemplary embodiment of Fig. 1 may also include one or more n-type wells disposed on the p-type wells so as to form a P-N junction.
  • the device may include three n-type wells 115, 116, and 117 that form P-N junctions with p-type wells 110, 111, and 112, respectively.
  • Each of the n-type wells 115, 116, and 117 may have a higher doping concentration than p- type wells 110, 111, and 112.
  • the three p-type wells 110, 111, and 112 may have a doping concentration of approximately 5xl0 18 /cm 3
  • the three n-type wells 115, 116, and 117 may have a doping concentration of approximately 2xl0 19 /cm 3 .
  • the n-type wells 115, 116, and 117 may also have a greater cross-sectional length than the p-type wells 110, 111, and 112.
  • the n-type wells 115, 116, and 117 may be circular in shape.
  • the three p-type wells 110, 111, and 112 may also be circular in shape.
  • the circular n-type wells 115, 116, and 117 may each have a diameter of approximately 7 ⁇ and a vertical depth of approximately 0.25 ⁇ , though other dimensions may be used as well.
  • the circular p-type wells 110, 111, and 112 may have a diameter of approximately 3 ⁇ , and a vertical depth of approximately 0.5 ⁇ , though other dimensions may also be used.
  • the device according to the exemplary embodiment of Fig. 1 may also include one or more heavily doped p-type wells that are alternatingly disposed between the P-N junctions formed by the p-type wells 110, 111, and 112, and the n-type wells 115, 116, and 117.
  • the device may include three heavily doped p-type wells 120, 121, and 122.
  • the heavily doped p-type wells 120, 121, and 122 may also be circular in shape.
  • the heavily doped p-type wells may have a doping
  • the heavily doped p-type wells 120, 121, and 122 may have a shorter cross- sectional length than the p-type wells 110, 111, and 112, and/or the n-type wells 115, 116, and 117.
  • the heavily doped p-type wells 120, 121, and 122 may have a vertical depth of approximately 0.25 ⁇ .
  • Each of the n-type wells 115, 116, and 117 may be spaced from the next adjacent n-type well by a predetermined distance.
  • the two closest edges of two adjacent n-type wells may be spaced approximately 7 ⁇ , however the exemplary embodiment is not limited to this spacing.
  • the closest edge of an n-type well may be spaced a predetermined distance from the adjacent heavily doped p-type well.
  • n-type well 115 and heavily doped p- type well 120 may be spaced so that the edge of the n-type well 115 closest to the heavily doped p-type well 120 is approximately 3.5 ⁇ from the center of heavily doped p-type well 120.
  • the edge of the n-type well 115 may be spaced approximately 2 ⁇ from the closest edge of the heavily doped p-type well 120.
  • a top surface of the n-type well 115 may be spaced less than 3 ⁇ from a top surface of the SOI substrate 100, however the exemplary embodiment is not limited to this spacing.
  • the top surface of n-type wells 116 and 117 may also be spaced less than 3 ⁇ from the top surface of the SOI substrate 100.
  • an anode may be formed at the heavily doped p-type well 122, and a cathode may be formed at the n-type well 115.
  • the device becomes forward biased and conducts current from the anode to the cathode. Due to the P-N junctions created by the n-type wells and p-type wells, the current flowing from the heavily doped p-type wells to the n-type wells is generally near the surface of the device.
  • the device according to one or more exemplary embodiments of the present disclosure may achieve increased forward current as compared to silicon controlled rectifiers due to the arrangement of the n-type wells and the heavily doped p-type wells, and the exemplary doping
  • the doping concentrations and layout of the n-type wells and heavily doped p-type wells allow for increased forward current without increasing capacitance or the size of the device.
  • the reverse recovery time may also be reduced in one or more exemplary embodiments.
  • Beta radiation is used to reduce the reverse recovery time, however this process is expensive and adds to overall production costs.
  • the device according to one or more of the exemplary embodiments may reduce the reverse recovery time due to defects from the SOI substrate, defects near the surface of the device, and the doping concentrations. Imperfections in the SOI layer and the surface of the device, and the large amount of current flowing near the surface of the device, cause recombination between carriers, and thus reduces the carrier life time. As the carrier life decreases, the reverse recovery time also decreases.

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  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A semiconductor device is provided. The device includes a silicon-on- insulator (SOI) substrate, a body layer disposed on the SOI substrate, a first p-type well disposed on the body layer, a first n-type well disposed on the first p-type well to form a first p-n junction, and a second p-type well that is spaced a predetermined distance from at least one of the first p-type well and first n-type well.

Description

ULTRASOUND T/R ISOLATION DIODE WITH FAST RECOVERY TIME ON SOI
CROSS REFERENCE TO RELATED APPLICATION
[0001] This application claims the benefit of U.S. Provisional Patent Application No. 62/269,506, filed on December 18, 2015, which is incorporated herein by reference in its entirety.
TECHNICAL FIELD
[0002] The present disclosure relates generally to a disolator that may increase the forward current conducted by the device, while reducing capacitance and improving recovery time. Ultrasound transmission/receiver circuits often include diodes, bipolar junction transistors (BJTs), or silicon controlled rectifiers (SCRs) in order to pass large current and isolate the signal from noise within the circuit. Diode and BJT arrays employ multiple p-type and n-type electrodes. SCRs are solid-state current controlling devices that have four layers of alternating p-type and n-type semiconductor material (PNPN). However, diodes, BJTs, and SCRs typically use lightly doped n-type and p-type semiconductor materials, which limits the amount of forward current. In order to increase the amount of forward current, the n-type and p-type wells must be made larger, which is disadvantageous for many
applications. In addition, the increased size causes the negative effect of increasing the capacitance.
[0003] Accordingly, it is desirable to find a solution that allows for increased forward current without increasing the size or the capacitance of the device, and that is fast and can be integrated in chip.
SUMMARY
[0004] According to an aspect of one or more exemplary embodiments, there is provided an integrated disolator device that may achieve an increased forward current, maintain a fast reverse recovery time, but without increasing the size or capacitance of the device. The device according to one or more exemplary embodiments may include a silicon- on-insulator (SOI) substrate, a body layer disposed on the SOI substrate, a first p-type well disposed on the body layer, a first n-type well disposed on the first p-type well to form a first p-n junction, and a second p-type well that is spaced a predetermined distance from at least one of the first p-type well and the first n-type well.
[0005] The p-type well may be circular in shape and may surround the first p-type well and the first n-type well.
[0006] The first p-type well and the first n-type well may be circular in shape. The diameter of the first p-type well may be less than the diameter of the first n-type well. The diameter of the first p-type well may be approximately 3 microns, and the diameter of the first n-type well may be approximately 7 microns.
[0007] The first p-type well may have a vertical depth of approximately 0.5 microns, and the first n-type well may have a vertical depth of approximately 0.25 microns.
[0008] The second p-type well may be more heavily doped than the first p-type well. The second p-type well may have a doping concentration of approximately 2xl019/cm3, and the first p-type well may have a doping concentration of approximately 5xl018/cm3.
[0009] The first n-type well may be more heavily doped than the first p-type well. The first n-type well may have a doping concentration of approximately 2xl019/cm3, and the first p-type well may have a doping concentration of approximately 5xl018/cm3.
[0010] The doping concentration of the first p-type well may be approximately 2.5 times greater than a doping concentration of the body layer.
[0011] The first p-type well and the second p-type well may be spaced apart by approximately 3.5 microns. The distance from the first n-type well to the second p-type well may be approximately two microns. [0012] The device according to one or more exemplary embodiments may also include a third p-type well disposed on the body layer and outside of the second p-type well and a second n-type well disposed on the third p-type well to form a second p-n junction. The second n-type well may be disposed outside of the second p-type well.
[0013] The second n-type well may be spaced approximately 7 microns from the first n-type well. The center point of the first n-type well may be spaced approximately 17 microns from the center point of the second n-type well.
BRIEF DESCRIPTION OF DRAWINGS
[0014] Fig. 1 is a cross-sectional view of a disolator device according to an exemplary embodiment.
[0015] Fig. 2 is a top view of a disolator device according to an exemplary embodiment.
DETAILED DESCRIPTION OF EXEMPLARY EMB ODEVIENT S
[0016] Reference will now be made in detail to the following exemplary
embodiments, which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. The exemplary embodiments may be embodied in various forms without being limited to the exemplary embodiments set forth herein.
Descriptions of well-known parts are omitted for clarity.
[0017] Although the components of Figs. 1 and 2 discussed below are shown for explanatory purposes, the relative sizes of the components are not drawn to scale. Referring to Fig. 1, a device according to an exemplary embodiment may include a silicon-on-insulator (SOI) substrate 100, which may be made of an oxide, or other material such as sapphire. A p-type body layer 105 may be disposed on the SOI, and may include one or more p-type wells. In the exemplary embodiment of Fig. 1, the device includes three p-type wells 110, 111, and 112. The p-type wells 110, 111, and 112 may be more heavily doped than p-type body layer 105. For example, and without limitation, the three p-type wells 110, 111, and 112 may have a doping concentration of approximately 5xl018/cm3, and the p-type body layer 105 may have a doping concentration of approximately 2xl018/cm3, however other doping concentrations and relative doping concentrations may be used.
[0018] The device according to the exemplary embodiment of Fig. 1 may also include one or more n-type wells disposed on the p-type wells so as to form a P-N junction.
According to the exemplary embodiment of Fig. 1, the device may include three n-type wells 115, 116, and 117 that form P-N junctions with p-type wells 110, 111, and 112, respectively. Each of the n-type wells 115, 116, and 117 may have a higher doping concentration than p- type wells 110, 111, and 112. For example, and without limitation, the three p-type wells 110, 111, and 112 may have a doping concentration of approximately 5xl018/cm3, and the three n-type wells 115, 116, and 117 may have a doping concentration of approximately 2xl019/cm3. The n-type wells 115, 116, and 117 may also have a greater cross-sectional length than the p-type wells 110, 111, and 112. According to the exemplary embodiment, the n-type wells 115, 116, and 117 may be circular in shape. The three p-type wells 110, 111, and 112 may also be circular in shape. The circular n-type wells 115, 116, and 117 may each have a diameter of approximately 7 μιη and a vertical depth of approximately 0.25 μιτι, though other dimensions may be used as well. The circular p-type wells 110, 111, and 112 may have a diameter of approximately 3 μιτι, and a vertical depth of approximately 0.5 μιτι, though other dimensions may also be used.
[0019] The device according to the exemplary embodiment of Fig. 1 may also include one or more heavily doped p-type wells that are alternatingly disposed between the P-N junctions formed by the p-type wells 110, 111, and 112, and the n-type wells 115, 116, and 117. According to the exemplary embodiment of Fig. 1, the device may include three heavily doped p-type wells 120, 121, and 122. The heavily doped p-type wells 120, 121, and 122 may also be circular in shape. The heavily doped p-type wells may have a doping
concentration of approximately 2xl019/cm3; however other doping concentrations may also be used. The heavily doped p-type wells 120, 121, and 122 may have a shorter cross- sectional length than the p-type wells 110, 111, and 112, and/or the n-type wells 115, 116, and 117. The heavily doped p-type wells 120, 121, and 122 may have a vertical depth of approximately 0.25 μιη.
[0020] Each of the n-type wells 115, 116, and 117 may be spaced from the next adjacent n-type well by a predetermined distance. According to an exemplary embodiment, the two closest edges of two adjacent n-type wells may be spaced approximately 7 μηι, however the exemplary embodiment is not limited to this spacing. According to an exemplary embodiment, there may be a spacing of approximately 17 μιη from the center of one n-type well and the center of an adjacent n-type well. According to an exemplary embodiment, the closest edge of an n-type well may be spaced a predetermined distance from the adjacent heavily doped p-type well. For example, n-type well 115 and heavily doped p- type well 120 may be spaced so that the edge of the n-type well 115 closest to the heavily doped p-type well 120 is approximately 3.5 μιη from the center of heavily doped p-type well 120. According to one or more exemplary embodiments, the edge of the n-type well 115 may be spaced approximately 2 μιη from the closest edge of the heavily doped p-type well 120. In addition, a top surface of the n-type well 115 may be spaced less than 3 μιη from a top surface of the SOI substrate 100, however the exemplary embodiment is not limited to this spacing. The top surface of n-type wells 116 and 117 may also be spaced less than 3 μιη from the top surface of the SOI substrate 100.
[0021] In the device according to the exemplary embodiment of Fig. 1, an anode may be formed at the heavily doped p-type well 122, and a cathode may be formed at the n-type well 115. When a sufficient voltage is applied to the anode, the device becomes forward biased and conducts current from the anode to the cathode. Due to the P-N junctions created by the n-type wells and p-type wells, the current flowing from the heavily doped p-type wells to the n-type wells is generally near the surface of the device. In addition, the device according to one or more exemplary embodiments of the present disclosure may achieve increased forward current as compared to silicon controlled rectifiers due to the arrangement of the n-type wells and the heavily doped p-type wells, and the exemplary doping
concentrations. Moreover, the doping concentrations and layout of the n-type wells and heavily doped p-type wells allow for increased forward current without increasing capacitance or the size of the device.
[0022] In addition, the reverse recovery time, or the time required to transition from the conducting state to the quiescent state, may also be reduced in one or more exemplary embodiments. In the related art, Beta radiation is used to reduce the reverse recovery time, however this process is expensive and adds to overall production costs. The device according to one or more of the exemplary embodiments may reduce the reverse recovery time due to defects from the SOI substrate, defects near the surface of the device, and the doping concentrations. Imperfections in the SOI layer and the surface of the device, and the large amount of current flowing near the surface of the device, cause recombination between carriers, and thus reduces the carrier life time. As the carrier life decreases, the reverse recovery time also decreases.
[0023] Although the inventive concepts of the present disclosure have been described and illustrated with respect to exemplary embodiments thereof, it is not limited to the exemplary embodiments disclosed herein and modifications may be made therein without departing from the scope of the inventive concepts.

Claims

What is claimed is:
1. A semiconductor device comprising:
a silicon-on-insulator (SOI) substrate;
a body layer disposed on the SOI substrate;
a first p-type well disposed on the body layer;
a first n-type well disposed on the first p-type well to form a first p-n junction; and
a second p-type well that is spaced a predetermined distance from at least one of the first p-type well and first n-type well.
2. The semiconductor device of claim 1, wherein the second p-type well is circular in shape and surrounds the first p-type well and the first n-type well.
3. The semiconductor device of claim 2, wherein the first p-type well and the first n-type well are circular in shape.
4. The semiconductor device of claim 3, wherein a diameter of the first p-type well is less than a diameter of the first n-type well.
5. The semiconductor device of claim 4, wherein the diameter of the first p-type well is approximately 3 microns, and the diameter of the first n-type well is approximately 7 microns.
6. The semiconductor device of claim 5, wherein the first p-type well has a vertical depth of approximately 0.5 microns, and the first n-type well has a vertical depth of approximately 0.25 microns.
7. The semiconductor device of claim 1, wherein the second p-type well is more heavily doped than the first p-type well.
8. The semiconductor device of claim 7, wherein the second p-type well has a doping concentration of approximately 2xl019/cm3, and the first p-type well has a doping concentration of approximately 5xl018/cm3.
9. The semiconductor device of claim 1, wherein the first n-type well is more heavily doped than the first p-type well.
10. The semiconductor device of claim 9, wherein the first n-type well has a doping concentration of approximately 2xl019/cm3, and the first p-type well has a doping concentration of approximately 5xl018/cm3.
11. The semiconductor device of claim 1 wherein a doping concentration of the first p-type well is approximately 2.5 times greater than a doping concentration of the body layer.
12. The semiconductor device of claim 1, wherein the first p-type well and the second p-type well are spaced apart by approximately 3.5 microns.
13. The semiconductor device of claim 1, wherein the distance from the first n- type well to the second p-type well is approximately two microns.
14. The semiconductor device of claim 1, further comprising:
a third p-type well disposed on the body layer and outside of the second p-type well;
a second n-type well disposed on the third p-type well to form a second p-n junction;
wherein the second n-type well is disposed outside of the second p-type well.
15. The semiconductor device of claim 14, wherein the second n-type well is spaced approximately 7 microns from the first n-type well.
16. The semiconductor device of claim 14, wherein a center point of the first n- type well is spaced approximately 17 microns from a center point of the second n-type well.
17. The semiconductor device of claim 1, wherein a top surface of the first n-type well is disposed less than 3 microns from a top surface of the SOI substrate.
PCT/US2016/065872 2015-12-18 2016-12-09 Ultrasound t/r isolation diode with fast recovery time on soi Ceased WO2017106040A1 (en)

Applications Claiming Priority (4)

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US201562269506P 2015-12-18 2015-12-18
US62/269,506 2015-12-18
US15/369,955 US20170179226A1 (en) 2015-12-18 2016-12-06 Ultrasound t/r isoltation disolator with fast recovery time on soi
US15/369,955 2016-12-06

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