WO2017091197A1 - Cache manager-controlled memory array - Google Patents

Cache manager-controlled memory array Download PDF

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Publication number
WO2017091197A1
WO2017091197A1 PCT/US2015/062119 US2015062119W WO2017091197A1 WO 2017091197 A1 WO2017091197 A1 WO 2017091197A1 US 2015062119 W US2015062119 W US 2015062119W WO 2017091197 A1 WO2017091197 A1 WO 2017091197A1
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WO
WIPO (PCT)
Prior art keywords
volatile memory
memory
cache manager
performance
data
Prior art date
Application number
PCT/US2015/062119
Other languages
French (fr)
Inventor
Qiong Cai
Paolo Faraboschi
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Hewlett Packard Enterprise Development Lp
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Priority to PCT/US2015/062119 priority Critical patent/WO2017091197A1/en
Publication of WO2017091197A1 publication Critical patent/WO2017091197A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0873—Mapping of cache memory to specific storage devices or parts thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/21—Employing a record carrier using a specific recording technology
    • G06F2212/214—Solid state disk

Definitions

  • Computing devices employ both storage and memory to save data.
  • storage may be used long-term to hold programs and data until they are purposefully changed or deleted by the user. The programs and data remain in storage even when the storage is powered down.
  • memory may be used as a short-term workspace for retrieving programs and processing data. When the memory is powered down, the programs and data held therein may be lost.
  • Memory and storage work together with a computing device's processor to provide programs with access to data.
  • the processor may transfer data relating to the program from the storage to the memory.
  • the processor then accesses the data from the memory while running the program.
  • the processor may transfer the data, which may have been altered by the program, from the memory back to the storage.
  • FIG. 1 is a block diagram of an example system of the present disclosure
  • FIG. 2 illustrates an example cache organization scheme of the persistent memory array 106 of FIG. 1 ;
  • FIG. 3 illustrates a flowchart of an example method for performing a memory operation in the persistent memory array of FIG. 1 ;
  • FIG. 4 illustrates a flowchart of an example method for performing a memory read in the persistent memory array of FIG. 1 ;
  • FIG. 5 illustrates a flowchart of an example method for performing a memory write in the persistent memory array of FIG. 1 ;
  • FIG. 6 illustrates a flowchart of an example method for performing a cache eviction in the persistent memory array of FIG. 1 ;
  • FIG. 7 depicts a high-level block diagram of an example computer that can be transformed into a machine capable of performing the functions described herein.
  • the present disclosure broadly describes an apparatus, method, and non-transitory computer-readable medium for providing a cache manager- controlled memory array.
  • computing devices employ both storage and memory to save data.
  • Many modern computing programs demand increased bandwidth, increased capacity, and reduced latency from storage; however, to date, no single memory technology is capable of meeting all of these demands.
  • Examples of the present disclosure provide a cache manager- controlled memory array.
  • examples of the present disclosure provide a persistent memory array that combines multiple memory technologies that individually provide high capacity and fast read/write performance.
  • the persistent memory array includes a volatile memory and at least two non-volatile memories.
  • the persistent memory array may include a dynamic random access memory (DRAM), a high-performance non-volatile memory (HP-NVM), and a high-capacity non-volatile memory (HC-NVM).
  • DRAM dynamic random access memory
  • HP-NVM high-performance non-volatile memory
  • HC-NVM high-capacity non-volatile memory
  • the DRAM provides fast read performance
  • the HP-NVM provides fast persistent write performance
  • the HC-NVM provides large memory capacity.
  • FIG. 1 is a block diagram of an example system 100 of the present disclosure.
  • the system 100 generally includes a system-on-chip (SoC) 102, a temporary memory 104 that is directly accessible by the SoC 102, and a persistent memory array 106 that is also directly accessible by the SoC 102.
  • SoC system-on-chip
  • the SoC 102 may comprise an integrated circuit (IC) that integrates various components of a computer or other electronic system, such as a processor, a memory, a timing source, a peripheral, an external interface, and/or other components, onto a single chip substrate.
  • IC integrated circuit
  • the SoC 102 may include digital, analog, mixed-signal, and other functions.
  • the temporary memory 104 comprises a short-term workspace for retrieving programs and processing data used by the SoC 102.
  • the temporary memory 104 is a high-bandwidth memory, such as a hybrid memory cube (HMC) or wide input/output (I/O) memory.
  • the temporary memory 104 may provide read/write latency in a range of approximately fifty to one hundred nanoseconds and may achieve bandwidth in a range of approximately 128 to 512 gigabytes per second.
  • the capacity of the temporary memory 104 may be relatively limited, e.g., in a range of approximately tens of gigabytes
  • the persistent memory array 106 comprises long-term storage for holding programs and data used by the SoC 102.
  • the persistent memory array 106 may store these programs and data until they are purposefully changed or deleted by the user of the SoC 102.
  • the persistent memory array 106 combines multiple, e.g., at least three, memory technologies that individually provide high capacity and fast read/write performance.
  • the persistent memory array 106 includes a volatile memory 108, a first non-volatile memory 1 10, and a second non-volatile memory 1 12.
  • the volatile memory 108 comprises a dynamic random access memory (DRAM).
  • the volatile memory 108 may provide fast read latency, e.g., in a range of fifty to one hundred nanoseconds.
  • the latency of the volatile memory 108 may be similar to that of the temporary memory 104.
  • the temporary memory 104 which may be a volatile memory providing relatively high bandwidth but relatively limited capacity
  • the volatile memory 108 may provide relatively moderate bandwidth, e.g., in a range of approximately eighty-five to 128 gigabytes per second, and relatively moderate capacity, e.g., in a range of hundreds of gigabytes to a few terabytes.
  • the first non-volatile memory 1 10 comprises a high- performance non-volatile memory (HP-NVM), such as a spin-transfer torque magnetic random access memory (STT-RAM), resistive random access memory (RRAM), a memristor, a non-volatile phase change memory (PCM), a programmable metallization cell (PMC), or other non-volatile memory technology capable of providing fast persistent write latency, e.g., in a range of approximately fifty to three hundred nanoseconds.
  • HP-NVM high- performance non-volatile memory
  • STT-RAM spin-transfer torque magnetic random access memory
  • RRAM resistive random access memory
  • PCM non-volatile phase change memory
  • PMC programmable metallization cell
  • the second non-volatile memory 1 12 comprises a high- capacity non-volatile memory (HC-NVM), such as a NAND flash memory.
  • H-NVM high- capacity non-volatile memory
  • the second non-volatile memory 1 12 may provide a relatively large memory capacity, e.g., ten or more times the capacity of the volatile memory 108 or first non-volatile memory 1 10.
  • the second non-volatile memory 1 12 may have a capacity of tens of terabytes or more.
  • the persistent memory array 106 further includes a cache manager 1 14 that provides an interface between the volatile and non-volatile memory of the persistent memory array 106 and the SoC 102.
  • the SoC 102 accesses the volatile memory 108, the first non-volatile memory 1 10, and the second nonvolatile memory 1 12 via the cache manager 1 14.
  • the cache manager 1 14 may store tags for identifying stored data.
  • tags are stored in the volatile memory 108 and/or the first non-volatile memory 1 10.
  • the cache manager 1 14 may be implemented in a computer or hardware processor, as discussed in connection with FIG. 6.
  • the cache manager 1 14 is in direct communication with the volatile memory 108, the first non-volatile memory 1 10, and the second non-volatile memory 1 12. In one example, none of the volatile memory 108, the first nonvolatile memory 1 10, and the second non-volatile memory 1 12 is in direct communication with each other. Thus, in this example all communications to and from the volatile memory 108, the first non-volatile memory 1 10, and the second non-volatile memory 1 12 go through the cache manager 1 14.
  • the cache manager 1 14 may access a different portion of the persistent memory array 106.
  • the cache manager 1 14 will try to serve as many read requests as possible from the volatile memory 108, while completing as many write requests as possible in the first non-volatile memory 1 10.
  • the volatile memory 108 and first non-volatile memory 1 10 may be implemented as hardware- managed cache; in this case, only the second non-volatile memory 1 12 would be visible to a user of the SoC 102.
  • the persistent memory array 106 leverages the strengths of multiple different memory technologies to provide low-latency, persistent, high-capacity storage in a single memory system.
  • FIG. 2 illustrates an example cache organization of the persistent memory array 106 of FIG. 1 .
  • the cache 200 generally comprises a plurality of blocks 202, only one of which is indicated in FIG. 2 for the sake of simplicity.
  • Each block 202 contains N sub-blocks 204, only one of which is indicated in FIG. 2 for the sake of simplicity.
  • each sub-block 204 has the same size as a central processing unit (CPU) cache line, e.g., sixty-four bytes.
  • the total size of the cache 200 is in the range of approximately 256 to 512 gigabytes per SoC 102.
  • the blocks 202 are organized into an array comprising a plurality of rows, or "sets," and a plurality of columns, or “ways.”
  • the cache 200 is divided into a plurality of partitions. For instance, in FIG. 2, the cache 200 is divided into a first partition 206i and a second partition 206 2 , hereinafter collectively referred to as "partitions 206.”
  • each partition 206 includes one or more sets.
  • Each partition 206 is allocated to a different memory technology of the persistent memory array 106.
  • the first partition 206i may be allocated to the volatile memory 108, while the second partition 206 2 may be allocated to the first non-volatile memory 1 10.
  • the first partition 206i and the second partition 206 2 are illustrated as being equal in size, e.g., two sets to each partition, this is not always the case.
  • the cache 200 may be divided so that the sizes of the partitions 206 are proportional to the capacities of the respective memory technologies to which the partitions 206 are allocated.
  • the access granularity between the SoC 102 and the volatile memory 108 or between the SoC 102 and the first non-volatile memory 1 10 is at the sub-block level.
  • the access granularity between the second non-volatile memory 1 12 and the volatile memory 108 or between the second non-volatile memory 1 12 and the first non-volatile memory 1 10 is at the block level.
  • Tag information may be stored at the block level, while dirty bits may be stored at the sub-block level.
  • FIG. 3 illustrates a flowchart of an example method 300 for performing a memory operation in the persistent memory array 106 of FIG. 1 .
  • the method 300 may be performed, for example, by the cache manager 1 14 illustrated in FIG. 1 . It will be appreciated, however, that the method 300 is not limited to implementation with the system illustrated in FIG. 1 .
  • the method 300 begins in block 302.
  • a request for a memory operation is received, e.g., by the cache manager 1 14 of the persistent memory array 106.
  • the memory operation may comprise, for example, a read operation, a write operation, or a cache eviction.
  • At least one memory technology in the persistent memory array 106 is identified, e.g., by the cache manager, for carrying out the memory operation.
  • the at least one memory technology may comprise the volatile memory 108.
  • the at least one memory technology may comprise the first non-volatile memory 1 10.
  • the at least one memory technology may comprise the second non-volatile memory 1 12.
  • more than one memory technology may be identified to carry out the memory operation. For instance, in accordance with the memory operation, data may be moved from a first memory technology to a second memory technology.
  • the appropriate memory technology or technologies to carry out the memory operation are identified by the cache manager 1 14.
  • the memory operation is carried out by the at least one memory technology.
  • the at least one memory technology operates in conjunction with or under the direction of the cache manager 1 14.
  • the method 300 ends in block 310.
  • FIG. 4 illustrates a flowchart of an example method 400 for performing a memory read in the persistent memory array 106 of FIG. 1 .
  • the method 400 is a more specific example of the method 300 illustrated in FIG. 3.
  • the method 400 may be performed, for example, by the cache manager 1 14 illustrated in FIG. 1 . It will be appreciated, however, that the method 400 is not limited to implementation with the system illustrated in FIG. 1 .
  • the method 400 begins in block 402.
  • a request for a memory read is received, e.g., by the cache manager 1 14.
  • the request seeks, for example, to load requested data from the persistent memory array 106 into a processor of the SoC 102.
  • the cache manager 1 14 determines whether there is a hit in the volatile memory 108, i.e., whether the requested data currently resides in the volatile memory 108.
  • the cache manager 1 14 retrieves the requested data from the volatile memory 108 in block 418.
  • blocks 406 and 408 are performed in parallel to reduce the perceived latency of the method 400. Parallel performance of blocks 406 and 408 may be especially useful where data tags are stored in the volatile memory 108 and/or first non-volatile memory 1 10.
  • the cache manager 1 14 retrieves the requested data from the first non-volatile memory 1 10 in block 410.
  • the cache manager 1 14 determines whether there is no hit in the first non-volatile memory 1 10 or not. If, on the other hand, the cache manager 1 14 concludes in block 408 that there is no hit in the first non-volatile memory 1 10, then the cache manager 1 14 moves the requested data from the second non-volatile memory 1 12 to the volatile memory 108 in block 416. The method 400 then proceeds to block 418 and retrieves the requested data from the volatile memory 108.
  • the method 400 proceeds to block 412.
  • the cache manager 1 14 returns the requested data, e.g., to the processor of the SoC 102.
  • the method 400 seeks to serve read requests from the volatile memory 108 as often as possible.
  • the requested data can reside either in the volatile memory 108 or in the first non-volatile memory 1 10, but not in both.
  • two copies of the requested data are stored: one copy in the volatile memory 108 and one copy in the first non-volatile memory 1 10.
  • FIG. 5 illustrates a flowchart of an example method 500 for performing a memory write in the persistent memory array 106 of FIG. 1 .
  • the method 500 is a more specific example of the method 300 illustrated in FIG. 3.
  • the method 500 may be performed, for example, by the cache manager 1 14 illustrated in FIG. 1 . It will be appreciated, however, that the method 500 is not limited to implementation with the system illustrated in FIG. 1 .
  • the method 500 begins in block 502.
  • a request for a memory write is received, e.g., by the cache manager 1 14.
  • the request seeks, for example, to load requested data from a processor of the SoC 102 back into the persistent memory array 106.
  • the cache manager 1 14 determines whether there is a hit in the first non-volatile memory 1 10, i.e., whether the requested data currently resides in the first non-volatile memory 1 10 and can be written back with any updates.
  • the cache manager 1 14 concludes in block 506 that there is a hit in the first non-volatile memory 1 10, then the cache manager 1 14 writes the requested data to the first non-volatile memory 1 10 in block 516.
  • the cache manager 1 14 If, on the other hand, the cache manager 1 14 concludes in block 506 that there is no hit in the first non-volatile memory 1 10, then the cache manager 1 14 allocates a block in the first non-volatile memory 1 10 for the requested data in block 508.
  • the cache manager 1 14 determines whether there is a hit in the volatile memory 108. If the cache manager 1 14 concludes in block 510 that there is a hit in the volatile memory 108, then the cache manager 1 14 moves the requested data from the volatile memory 108 to the allocated block in the first non-volatile memory 1 10 in block 520.
  • the cache manager 1 14 retrieves the requested data from the second non-volatile memory 1 12 in block 512.
  • the cache manager 1 14 moves the requested data from the second non-volatile memory 1 12 to the allocated block in the first non-volatile memory 1 10.
  • the method 400 proceeds to block 516.
  • the cache manager 1 14 writes the requested data to the first non-volatile memory 1 10.
  • the cache manager also sets an indicator to indicate that the data in the first non-volatile memory 1 10 has been updated.
  • setting the indicator involves setting a dirty bit associated with the set, way, and sub-block of the allocated block to which the requested data is written.
  • the method 500 ends in block 518.
  • the method 500 seeks to complete write requests in the first nonvolatile memory 1 10 as often as possible.
  • data residing in the volatile memory 108 or the first non-volatile memory 1 10 may be evicted. The eviction makes room in a full cache for the data to be written.
  • the method 400 includes a block in which requested data is moved from the first non-volatile memory 1 10 to the volatile memory 108. If the volatile memory 108 is full, however, it may be necessary to evict data from the volatile memory 108 before the requested data can be moved from the first non-volatile memory 1 10.
  • FIG. 6 illustrates a flowchart of an example method 600 for performing a cache eviction in the persistent memory array 106 of FIG. 1 .
  • the method 600 is a more specific example of the method 300 illustrated in FIG. 3.
  • the method 600 may be performed, for example, by the cache manager 1 14 illustrated in FIG. 1 . It will be appreciated, however, that the method 600 is not limited to implementation with the system illustrated in FIG. 1 .
  • the method 600 begins in block 602.
  • a full condition is detected in cache, e.g., by the cache manager 1 14.
  • the full condition indicates that at least one of the volatile memory 108 or first non-volatile memory 1 10 is full, i.e., cannot store any more data.
  • the method 600 may proceed in one of three ways, depending on which portions of the persistent memory array 106 are full. That is, the subsequent operation of the method 600 may vary depending on whether the volatile memory 108 is full, the first non-volatile memory 1 10 is full, or both of the volatile memory 108 and the first non-volatile memory 1 10 are full.
  • the cache manager 1 14 may determine that the volatile memory 108 is full, but the first non-volatile memory 1 10 is not full.
  • the cache manager 1 14 allocates a block in the first non-volatile memory 1 10 for the data to be evicted from the volatile memory 108.
  • the cache manager 1 14 moves the data to be evicted from the volatile memory 108 to the allocated block in the first non-volatile memory 1 10.
  • the cache manager 1 14 may instead determine in block 612 that the first non-volatile memory 1 10 is full, but the volatile memory 108 is not full.
  • the cache manager 1 14 allocates a block in the second non-volatile memory 1 12 for the data to be evicted from the first nonvolatile memory 1 10.
  • the cache manager 1 14 moves the data to be evicted from the first non-volatile memory 1 10 to the allocated block in the second non-volatile memory 1 12. In one example, only the dirty, i.e., modified, blocks are moved from the first non-volatile memory 1 10 to the allocated block in the second nonvolatile memory 1 12.
  • the cache manager 1 14 may instead determine in block 618 that the volatile memory 108 and the first non-volatile memory 1 10 are both full.
  • the cache manager 1 14 allocates a block in the second non-volatile memory for the data to be evicted from the first nonvolatile memory 1 10.
  • the cache manager 1 14 moves the data to be evicted from the first non-volatile memory 1 10 to the allocated block in the second non-volatile memory 1 12. In one example, only the dirty, i.e., modified, blocks are moved from the first non-volatile memory 1 10 to the allocated block in the second nonvolatile memory 1 12.
  • the cache manager 1 14 allocates a block in the (no longer full) first non-volatile memory 1 10 for the data to be evicted from the volatile memory 108.
  • the cache manager 141 moves the data to be evicted from the volatile memory 108 to the allocated block in the first non-volatile memory 1 10.
  • the method 600 ends in block 628.
  • blocks, functions, or operations of the methods 300, 400, 500, and 600 described above may include storing, displaying and/or outputting for a particular application.
  • any data, records, fields, and/or intermediate results discussed in the methods can be stored, displayed, and/or outputted to another device depending on the particular application.
  • blocks, functions, or operations in FIGs. 3-6 that recite a determining operation, or involve a decision do not imply that both branches of the determining operation are practiced. In other words, one of the branches of the determining operation may not be performed, depending on the results of the determining operation.
  • FIG. 7 depicts a high-level block diagram of an example computer that can be transformed into a machine capable of performing the functions described herein. Notably, no computer or machine currently exists that performs the functions as described herein. As a result, the examples of the present disclosure modify the operation and functioning of the general-purpose computer to provide a cache manager-controlled memory array, as disclosed herein.
  • the computer 700 comprises a hardware processor element 702, e.g., a central processing unit (CPU), a microprocessor, or a multi-core processor, a memory 704, e.g., a temporary memory such as random access memory (RAM) and/or read only memory (ROM), a cache management module 705 for controlling a persistent memory array, and various input/output devices 706, e.g., storage devices, including but not limited to, a persistent memory array as disclosed in FIG.
  • a hardware processor element 702 e.g., a central processing unit (CPU), a microprocessor, or a multi-core processor
  • a memory 704 e.g., a temporary memory such as random access memory (RAM) and/or read only memory (ROM)
  • RAM random access memory
  • ROM read only memory
  • the cache management module 705 may include different memory modules, including volatile memory modules, high-performance non-volatile memory modules, and high-capacity non-volatile memory modules.
  • the general-purpose computer may employ a plurality of processor elements.
  • one general-purpose computer is shown in the figure, if the method(s) as discussed above is implemented in a distributed or parallel manner for a particular illustrative example, i.e., the blocks of the above method(s) or the entire method(s) are implemented across multiple or parallel general- purpose computers, then the general-purpose computer of this figure is intended to represent each of those multiple general-purpose computers.
  • a hardware processor can be utilized in supporting a virtualized or shared computing environment.
  • the virtualized computing environment may support a virtual machine representing computers, servers, or other computing devices.
  • hardware components such as hardware processors and computer-readable storage devices may be virtualized or logically represented.
  • the present disclosure can be implemented by machine readable instructions and/or in a combination of machine readable instructions and hardware, e.g., using application specific integrated circuits (ASIC), a programmable logic array (PLA), including a field-programmable gate array (FPGA), or a state machine deployed on a hardware device, a general purpose computer or any other hardware equivalents, e.g., computer readable instructions pertaining to the method(s) discussed above can be used to configure a hardware processor to perform the blocks, functions and/or operations of the above disclosed methods.
  • ASIC application specific integrated circuits
  • PDA programmable logic array
  • FPGA field-programmable gate array
  • instructions and data for the present module or process 705 for controlling a persistent memory array can be loaded into memory 704 and executed by hardware processor element 702 to implement the blocks, functions or operations as discussed above in connection with the methods 300, 400, 500, and 600.
  • the module 705 may include a plurality of programming code components, including a reading component 708, and writing component 710, and/or an eviction component 712.
  • the reading component 708 may be configured to perform memory read operations, for example as discussed in connection with FIG. 4.
  • the writing component 610 may be configured to perform memory write operations, for example as discussed in connection with FIG.5.
  • the eviction component 712 may be configured for perform cache evictions, for example as discussed in connection with FIG. 6.
  • a hardware processor executes instructions to perform "operations"
  • the processor executing the machine readable instructions relating to the above described method(s) can be perceived as a programmed processor or a specialized processor.
  • the present module 705 for controlling a persistent memory array, including associated data structures, of the present disclosure can be stored on a tangible or physical (broadly non-transitory) computer-readable storage device or medium, e.g., volatile memory, non-volatile memory, ROM memory, RAM memory, magnetic or optical drive, device or diskette and the like.
  • the computer-readable storage device may comprise any physical devices that provide the ability to store information such as data and/or instructions to be accessed by a processor or a computing device such as a computer or an application server.

Abstract

In an example, an apparatus is described that includes a memory array. The memory array includes a volatile memory, a first non-volatile memory, and a second non-volatile memory. The memory array further includes a cache manager that controls access by a computer system to the memory array. For instance, the cache manager may carry out memory operations, including read operations, write operations, and cache evictions, in conjunction with at least one of the volatile memory, the first non-volatile memory, or the second non-volatile memory.

Description

CACHE MANAGER-CONTROLLED MEMORY ARRAY
BACKGROUND
[0001] Computing devices employ both storage and memory to save data. For instance, storage may be used long-term to hold programs and data until they are purposefully changed or deleted by the user. The programs and data remain in storage even when the storage is powered down. On the other hand, memory may be used as a short-term workspace for retrieving programs and processing data. When the memory is powered down, the programs and data held therein may be lost.
[0002] Memory and storage work together with a computing device's processor to provide programs with access to data. As an example, when the computing device launches a program, the processor may transfer data relating to the program from the storage to the memory. The processor then accesses the data from the memory while running the program. Before closing the program, the processor may transfer the data, which may have been altered by the program, from the memory back to the storage.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] FIG. 1 is a block diagram of an example system of the present disclosure;
[0004] FIG. 2 illustrates an example cache organization scheme of the persistent memory array 106 of FIG. 1 ;
[0005] FIG. 3 illustrates a flowchart of an example method for performing a memory operation in the persistent memory array of FIG. 1 ;
[0006] FIG. 4 illustrates a flowchart of an example method for performing a memory read in the persistent memory array of FIG. 1 ;
[0007] FIG. 5 illustrates a flowchart of an example method for performing a memory write in the persistent memory array of FIG. 1 ;
[0008] FIG. 6 illustrates a flowchart of an example method for performing a cache eviction in the persistent memory array of FIG. 1 ; and
[0009] FIG. 7 depicts a high-level block diagram of an example computer that can be transformed into a machine capable of performing the functions described herein.
DETAILED DESCRIPTION
[0010] The present disclosure broadly describes an apparatus, method, and non-transitory computer-readable medium for providing a cache manager- controlled memory array. As discussed above, computing devices employ both storage and memory to save data. Many modern computing programs demand increased bandwidth, increased capacity, and reduced latency from storage; however, to date, no single memory technology is capable of meeting all of these demands.
[0011 ] Examples of the present disclosure provide a cache manager- controlled memory array. For instance, examples of the present disclosure provide a persistent memory array that combines multiple memory technologies that individually provide high capacity and fast read/write performance. In one example, the persistent memory array includes a volatile memory and at least two non-volatile memories. For instance, the persistent memory array may include a dynamic random access memory (DRAM), a high-performance non-volatile memory (HP-NVM), and a high-capacity non-volatile memory (HC-NVM). In this case, the DRAM provides fast read performance; the HP-NVM provides fast persistent write performance; and the HC-NVM provides large memory capacity. A cache manager provides an interface between the memory technologies of the persistent memory array and a system-on-chip (SoC) and transparently controls access by the SoC to the DRAM, HP-NVM, and HC-NVM. [0012] FIG. 1 is a block diagram of an example system 100 of the present disclosure. In one example, the system 100 generally includes a system-on-chip (SoC) 102, a temporary memory 104 that is directly accessible by the SoC 102, and a persistent memory array 106 that is also directly accessible by the SoC 102.
[0013] The SoC 102 may comprise an integrated circuit (IC) that integrates various components of a computer or other electronic system, such as a processor, a memory, a timing source, a peripheral, an external interface, and/or other components, onto a single chip substrate. Thus, the SoC 102 may include digital, analog, mixed-signal, and other functions.
[0014] The temporary memory 104 comprises a short-term workspace for retrieving programs and processing data used by the SoC 102. In one example, the temporary memory 104 is a high-bandwidth memory, such as a hybrid memory cube (HMC) or wide input/output (I/O) memory. The temporary memory 104 may provide read/write latency in a range of approximately fifty to one hundred nanoseconds and may achieve bandwidth in a range of approximately 128 to 512 gigabytes per second. However, the capacity of the temporary memory 104 may be relatively limited, e.g., in a range of approximately tens of gigabytes
[0015] The persistent memory array 106 comprises long-term storage for holding programs and data used by the SoC 102. The persistent memory array 106 may store these programs and data until they are purposefully changed or deleted by the user of the SoC 102. The persistent memory array 106 combines multiple, e.g., at least three, memory technologies that individually provide high capacity and fast read/write performance. In one example, the persistent memory array 106 includes a volatile memory 108, a first non-volatile memory 1 10, and a second non-volatile memory 1 12.
[0016] In one example, the volatile memory 108 comprises a dynamic random access memory (DRAM). The volatile memory 108 may provide fast read latency, e.g., in a range of fifty to one hundred nanoseconds. Thus, the latency of the volatile memory 108 may be similar to that of the temporary memory 104. However, in contrast to the temporary memory 104, which may be a volatile memory providing relatively high bandwidth but relatively limited capacity, the volatile memory 108 may provide relatively moderate bandwidth, e.g., in a range of approximately eighty-five to 128 gigabytes per second, and relatively moderate capacity, e.g., in a range of hundreds of gigabytes to a few terabytes.
[0017] In one example, the first non-volatile memory 1 10 comprises a high- performance non-volatile memory (HP-NVM), such as a spin-transfer torque magnetic random access memory (STT-RAM), resistive random access memory (RRAM), a memristor, a non-volatile phase change memory (PCM), a programmable metallization cell (PMC), or other non-volatile memory technology capable of providing fast persistent write latency, e.g., in a range of approximately fifty to three hundred nanoseconds.
[0018] In one example, the second non-volatile memory 1 12 comprises a high- capacity non-volatile memory (HC-NVM), such as a NAND flash memory. The second non-volatile memory 1 12 may provide a relatively large memory capacity, e.g., ten or more times the capacity of the volatile memory 108 or first non-volatile memory 1 10. For instance, the second non-volatile memory 1 12 may have a capacity of tens of terabytes or more.
[0019] The persistent memory array 106 further includes a cache manager 1 14 that provides an interface between the volatile and non-volatile memory of the persistent memory array 106 and the SoC 102. Thus, the SoC 102 accesses the volatile memory 108, the first non-volatile memory 1 10, and the second nonvolatile memory 1 12 via the cache manager 1 14. In a further example, the cache manager 1 14 may store tags for identifying stored data. However, in other examples, tags are stored in the volatile memory 108 and/or the first non-volatile memory 1 10. To this end, the cache manager 1 14 may be implemented in a computer or hardware processor, as discussed in connection with FIG. 6.
[0020] The cache manager 1 14 is in direct communication with the volatile memory 108, the first non-volatile memory 1 10, and the second non-volatile memory 1 12. In one example, none of the volatile memory 108, the first nonvolatile memory 1 10, and the second non-volatile memory 1 12 is in direct communication with each other. Thus, in this example all communications to and from the volatile memory 108, the first non-volatile memory 1 10, and the second non-volatile memory 1 12 go through the cache manager 1 14.
[0021] Depending on the memory operation, e.g., read, write, or eviction, the cache manager 1 14 may access a different portion of the persistent memory array 106. In general, the cache manager 1 14 will try to serve as many read requests as possible from the volatile memory 108, while completing as many write requests as possible in the first non-volatile memory 1 10. The volatile memory 108 and first non-volatile memory 1 10 may be implemented as hardware- managed cache; in this case, only the second non-volatile memory 1 12 would be visible to a user of the SoC 102. Thus, the persistent memory array 106 leverages the strengths of multiple different memory technologies to provide low-latency, persistent, high-capacity storage in a single memory system.
[0022] FIG. 2 illustrates an example cache organization of the persistent memory array 106 of FIG. 1 . In one example, the cache 200 generally comprises a plurality of blocks 202, only one of which is indicated in FIG. 2 for the sake of simplicity. Each block 202 contains N sub-blocks 204, only one of which is indicated in FIG. 2 for the sake of simplicity. In one example, each sub-block 204 has the same size as a central processing unit (CPU) cache line, e.g., sixty-four bytes. In one example, the total size of the cache 200 is in the range of approximately 256 to 512 gigabytes per SoC 102.
[0023] The blocks 202 are organized into an array comprising a plurality of rows, or "sets," and a plurality of columns, or "ways." In one example, the cache 200 is divided into a plurality of partitions. For instance, in FIG. 2, the cache 200 is divided into a first partition 206i and a second partition 2062, hereinafter collectively referred to as "partitions 206." In one example, each partition 206 includes one or more sets.
[0024] Each partition 206 is allocated to a different memory technology of the persistent memory array 106. For instance, the first partition 206i may be allocated to the volatile memory 108, while the second partition 2062 may be allocated to the first non-volatile memory 1 10. Although the first partition 206i and the second partition 2062 are illustrated as being equal in size, e.g., two sets to each partition, this is not always the case. In other examples, the cache 200 may be divided so that the sizes of the partitions 206 are proportional to the capacities of the respective memory technologies to which the partitions 206 are allocated.
[0025] In one example, the access granularity between the SoC 102 and the volatile memory 108 or between the SoC 102 and the first non-volatile memory 1 10 is at the sub-block level. In a further example, the access granularity between the second non-volatile memory 1 12 and the volatile memory 108 or between the second non-volatile memory 1 12 and the first non-volatile memory 1 10 is at the block level. Tag information may be stored at the block level, while dirty bits may be stored at the sub-block level.
[0026] FIG. 3 illustrates a flowchart of an example method 300 for performing a memory operation in the persistent memory array 106 of FIG. 1 . The method 300 may be performed, for example, by the cache manager 1 14 illustrated in FIG. 1 . It will be appreciated, however, that the method 300 is not limited to implementation with the system illustrated in FIG. 1 .
[0027] The method 300 begins in block 302. In block 304, a request for a memory operation is received, e.g., by the cache manager 1 14 of the persistent memory array 106. The memory operation may comprise, for example, a read operation, a write operation, or a cache eviction.
[0028] In block 306, at least one memory technology in the persistent memory array 106 is identified, e.g., by the cache manager, for carrying out the memory operation. For instance, when the memory operation is a read operation, the at least one memory technology may comprise the volatile memory 108. When the memory operation is a write operation, the at least one memory technology may comprise the first non-volatile memory 1 10. When the memory operation is a cache eviction, the at least one memory technology may comprise the second non-volatile memory 1 12. In one example, more than one memory technology may be identified to carry out the memory operation. For instance, in accordance with the memory operation, data may be moved from a first memory technology to a second memory technology. In one example, the appropriate memory technology or technologies to carry out the memory operation are identified by the cache manager 1 14.
[0029] In block 308, the memory operation is carried out by the at least one memory technology. In one example, the at least one memory technology operates in conjunction with or under the direction of the cache manager 1 14.
[0030] The method 300 ends in block 310.
[0031] FIG. 4 illustrates a flowchart of an example method 400 for performing a memory read in the persistent memory array 106 of FIG. 1 . Thus, the method 400 is a more specific example of the method 300 illustrated in FIG. 3. The method 400 may be performed, for example, by the cache manager 1 14 illustrated in FIG. 1 . It will be appreciated, however, that the method 400 is not limited to implementation with the system illustrated in FIG. 1 .
[0032] The method 400 begins in block 402. In block 404, a request for a memory read is received, e.g., by the cache manager 1 14. The request seeks, for example, to load requested data from the persistent memory array 106 into a processor of the SoC 102.
[0033] In block 406, the cache manager 1 14 determines whether there is a hit in the volatile memory 108, i.e., whether the requested data currently resides in the volatile memory 108.
[0034] If the cache manager 1 14 concludes in block 406 that there is a hit in the volatile memory 108, then the cache manager 1 14 retrieves the requested data from the volatile memory 108 in block 418.
[0035] If, on the other hand, the cache manager 1 14 concludes in block 406 that there is no hit in the volatile memory 108, then the cache manager 1 14 determines whether there is a hit in the first non-volatile memory 1 10 in block 408. In one example, blocks 406 and 408 are performed in parallel to reduce the perceived latency of the method 400. Parallel performance of blocks 406 and 408 may be especially useful where data tags are stored in the volatile memory 108 and/or first non-volatile memory 1 10.
[0036] If the cache manager 1 14 concludes in block 408 that there is a hit in the first non- volatile memory 1 10, then the cache manager 1 14 retrieves the requested data from the first non-volatile memory 1 10 in block 410.
[0037] If, on the other hand, the cache manager 1 14 concludes in block 408 that there is no hit in the first non-volatile memory 1 10, then the cache manager 1 14 moves the requested data from the second non-volatile memory 1 12 to the volatile memory 108 in block 416. The method 400 then proceeds to block 418 and retrieves the requested data from the volatile memory 108.
[0038] Once the requested data has been retrieved, e.g., from the volatile memory 108, from the first non-volatile memory 1 10, or from the volatile memory
108 by way of the second non-volatile memory 1 12, the method 400 proceeds to block 412. In block 412, the cache manager 1 14 returns the requested data, e.g., to the processor of the SoC 102.
[0039] The method 400 ends in block 414
[0040] Thus, the method 400 seeks to serve read requests from the volatile memory 108 as often as possible. In one example, for a cache hit, the requested data can reside either in the volatile memory 108 or in the first non-volatile memory 1 10, but not in both. In another example, two copies of the requested data are stored: one copy in the volatile memory 108 and one copy in the first non-volatile memory 1 10.
[0041] FIG. 5 illustrates a flowchart of an example method 500 for performing a memory write in the persistent memory array 106 of FIG. 1 . Thus, the method 500 is a more specific example of the method 300 illustrated in FIG. 3. The method 500 may be performed, for example, by the cache manager 1 14 illustrated in FIG. 1 . It will be appreciated, however, that the method 500 is not limited to implementation with the system illustrated in FIG. 1 .
[0042] The method 500 begins in block 502. In block 504, a request for a memory write is received, e.g., by the cache manager 1 14. The request seeks, for example, to load requested data from a processor of the SoC 102 back into the persistent memory array 106.
[0043] In block 506, the cache manager 1 14 determines whether there is a hit in the first non-volatile memory 1 10, i.e., whether the requested data currently resides in the first non-volatile memory 1 10 and can be written back with any updates.
[0044] If the cache manager 1 14 concludes in block 506 that there is a hit in the first non-volatile memory 1 10, then the cache manager 1 14 writes the requested data to the first non-volatile memory 1 10 in block 516.
[0045] If, on the other hand, the cache manager 1 14 concludes in block 506 that there is no hit in the first non-volatile memory 1 10, then the cache manager 1 14 allocates a block in the first non-volatile memory 1 10 for the requested data in block 508.
[0046] In block 510, the cache manager 1 14 determines whether there is a hit in the volatile memory 108. If the cache manager 1 14 concludes in block 510 that there is a hit in the volatile memory 108, then the cache manager 1 14 moves the requested data from the volatile memory 108 to the allocated block in the first non-volatile memory 1 10 in block 520.
[0047] If, on the other hand, the cache manager 1 14 concludes in block 510 that there is no hit in the volatile memory 108, then the cache manager 1 14 retrieves the requested data from the second non-volatile memory 1 12 in block 512.
[0048] In block 514, the cache manager 1 14 moves the requested data from the second non-volatile memory 1 12 to the allocated block in the first non-volatile memory 1 10.
[0049] Once the requested data has been located, e.g., in the first non-volatile memory 1 10, the volatile memory 108, or the second non-volatile memory 1 12, and once a block has been allocated in the first non-volatile memory, the method 400 proceeds to block 516. In block 516, the cache manager 1 14 writes the requested data to the first non-volatile memory 1 10. In one example, the cache manager also sets an indicator to indicate that the data in the first non-volatile memory 1 10 has been updated. In one example, setting the indicator involves setting a dirty bit associated with the set, way, and sub-block of the allocated block to which the requested data is written.
[0050] The method 500 ends in block 518.
[0051] Thus, the method 500 seeks to complete write requests in the first nonvolatile memory 1 10 as often as possible. In some cases, e.g., where a cache miss occurs during the process of writing the requested data back to storage, data residing in the volatile memory 108 or the first non-volatile memory 1 10 may be evicted. The eviction makes room in a full cache for the data to be written.
[0052] It may also be necessary to evict data from the cache in order to satisfy a read request. For instance, the method 400 includes a block in which requested data is moved from the first non-volatile memory 1 10 to the volatile memory 108. If the volatile memory 108 is full, however, it may be necessary to evict data from the volatile memory 108 before the requested data can be moved from the first non-volatile memory 1 10.
[0053] FIG. 6 illustrates a flowchart of an example method 600 for performing a cache eviction in the persistent memory array 106 of FIG. 1 . Thus, the method 600 is a more specific example of the method 300 illustrated in FIG. 3. The method 600 may be performed, for example, by the cache manager 1 14 illustrated in FIG. 1 . It will be appreciated, however, that the method 600 is not limited to implementation with the system illustrated in FIG. 1 .
[0054] The method 600 begins in block 602. In block 604, a full condition is detected in cache, e.g., by the cache manager 1 14. The full condition indicates that at least one of the volatile memory 108 or first non-volatile memory 1 10 is full, i.e., cannot store any more data.
[0055] In one example, from block 604, the method 600 may proceed in one of three ways, depending on which portions of the persistent memory array 106 are full. That is, the subsequent operation of the method 600 may vary depending on whether the volatile memory 108 is full, the first non-volatile memory 1 10 is full, or both of the volatile memory 108 and the first non-volatile memory 1 10 are full.
[0056] For instance, in block 606, the cache manager 1 14 may determine that the volatile memory 108 is full, but the first non-volatile memory 1 10 is not full.
[0057] In this case, in block 608, the cache manager 1 14 allocates a block in the first non-volatile memory 1 10 for the data to be evicted from the volatile memory 108.
[0058] In block 610, the cache manager 1 14 moves the data to be evicted from the volatile memory 108 to the allocated block in the first non-volatile memory 1 10.
[0059] In a different example, the cache manager 1 14 may instead determine in block 612 that the first non-volatile memory 1 10 is full, but the volatile memory 108 is not full.
[0060] In this case, in block 614, the cache manager 1 14 allocates a block in the second non-volatile memory 1 12 for the data to be evicted from the first nonvolatile memory 1 10.
[0061] In block 616, the cache manager 1 14 moves the data to be evicted from the first non-volatile memory 1 10 to the allocated block in the second non-volatile memory 1 12. In one example, only the dirty, i.e., modified, blocks are moved from the first non-volatile memory 1 10 to the allocated block in the second nonvolatile memory 1 12.
[0062] In a different example, the cache manager 1 14 may instead determine in block 618 that the volatile memory 108 and the first non-volatile memory 1 10 are both full.
[0063] In this case, in block 620, the cache manager 1 14 allocates a block in the second non-volatile memory for the data to be evicted from the first nonvolatile memory 1 10.
[0064] In block 622, the cache manager 1 14 moves the data to be evicted from the first non-volatile memory 1 10 to the allocated block in the second non-volatile memory 1 12. In one example, only the dirty, i.e., modified, blocks are moved from the first non-volatile memory 1 10 to the allocated block in the second nonvolatile memory 1 12.
[0065] In block 624, the cache manager 1 14 allocates a block in the (no longer full) first non-volatile memory 1 10 for the data to be evicted from the volatile memory 108.
[0066] In block 626, the cache manager 141 moves the data to be evicted from the volatile memory 108 to the allocated block in the first non-volatile memory 1 10.
[0067] Once the data to be evicted is moved from the volatile memory 108 to the first non-volatile memory 1 10, from the first non-volatile memory 1 10 to the second non-volatile memory 1 12, or from both the first non-volatile memory 1 10 and the volatile memory 108 to the second non-volatile memory 1 12 and the first non-volatile memory 1 10, respectively, the method 600 ends in block 628.
[0068] It should be noted that although not explicitly specified, some of the blocks, functions, or operations of the methods 300, 400, 500, and 600 described above may include storing, displaying and/or outputting for a particular application. In other words, any data, records, fields, and/or intermediate results discussed in the methods can be stored, displayed, and/or outputted to another device depending on the particular application. Furthermore, blocks, functions, or operations in FIGs. 3-6 that recite a determining operation, or involve a decision, do not imply that both branches of the determining operation are practiced. In other words, one of the branches of the determining operation may not be performed, depending on the results of the determining operation.
[0069] FIG. 7 depicts a high-level block diagram of an example computer that can be transformed into a machine capable of performing the functions described herein. Notably, no computer or machine currently exists that performs the functions as described herein. As a result, the examples of the present disclosure modify the operation and functioning of the general-purpose computer to provide a cache manager-controlled memory array, as disclosed herein.
[0070] As depicted in FIG. 7, the computer 700 comprises a hardware processor element 702, e.g., a central processing unit (CPU), a microprocessor, or a multi-core processor, a memory 704, e.g., a temporary memory such as random access memory (RAM) and/or read only memory (ROM), a cache management module 705 for controlling a persistent memory array, and various input/output devices 706, e.g., storage devices, including but not limited to, a persistent memory array as disclosed in FIG. 1 , a tape drive, a floppy drive, a hard disk drive or a compact disk drive, a receiver, a transmitter, a speaker, a display, a speech synthesizer, an output port, an input port and a user input device, such as a keyboard, a keypad, a mouse, a microphone, and the like. Furthermore, the cache management module 705 may include different memory modules, including volatile memory modules, high-performance non-volatile memory modules, and high-capacity non-volatile memory modules.
[0071] Although one processor element is shown, it should be noted that the general-purpose computer may employ a plurality of processor elements. Furthermore, although one general-purpose computer is shown in the figure, if the method(s) as discussed above is implemented in a distributed or parallel manner for a particular illustrative example, i.e., the blocks of the above method(s) or the entire method(s) are implemented across multiple or parallel general- purpose computers, then the general-purpose computer of this figure is intended to represent each of those multiple general-purpose computers. Furthermore, a hardware processor can be utilized in supporting a virtualized or shared computing environment. The virtualized computing environment may support a virtual machine representing computers, servers, or other computing devices. In such virtualized virtual machines, hardware components such as hardware processors and computer-readable storage devices may be virtualized or logically represented.
[0072] It should be noted that the present disclosure can be implemented by machine readable instructions and/or in a combination of machine readable instructions and hardware, e.g., using application specific integrated circuits (ASIC), a programmable logic array (PLA), including a field-programmable gate array (FPGA), or a state machine deployed on a hardware device, a general purpose computer or any other hardware equivalents, e.g., computer readable instructions pertaining to the method(s) discussed above can be used to configure a hardware processor to perform the blocks, functions and/or operations of the above disclosed methods.
[0073] In one example, instructions and data for the present module or process 705 for controlling a persistent memory array, e.g., machine readable instructions can be loaded into memory 704 and executed by hardware processor element 702 to implement the blocks, functions or operations as discussed above in connection with the methods 300, 400, 500, and 600. For instance, the module 705 may include a plurality of programming code components, including a reading component 708, and writing component 710, and/or an eviction component 712.
[0074] The reading component 708 may be configured to perform memory read operations, for example as discussed in connection with FIG. 4. The writing component 610 may be configured to perform memory write operations, for example as discussed in connection with FIG.5. The eviction component 712 may be configured for perform cache evictions, for example as discussed in connection with FIG. 6.
[0075] Furthermore, when a hardware processor executes instructions to perform "operations", this could include the hardware processor performing the operations directly and/or facilitating, directing, or cooperating with another hardware device or component, e.g., a co-processor and the like, to perform the operations.
[0076] The processor executing the machine readable instructions relating to the above described method(s) can be perceived as a programmed processor or a specialized processor. As such, the present module 705 for controlling a persistent memory array, including associated data structures, of the present disclosure can be stored on a tangible or physical (broadly non-transitory) computer-readable storage device or medium, e.g., volatile memory, non-volatile memory, ROM memory, RAM memory, magnetic or optical drive, device or diskette and the like. More specifically, the computer-readable storage device may comprise any physical devices that provide the ability to store information such as data and/or instructions to be accessed by a processor or a computing device such as a computer or an application server.
[0077] It will be appreciated that variants of the above-disclosed and other features and functions, or alternatives thereof, may be combined into many other different systems or applications. Various presently unforeseen or unanticipated alternatives, modifications, or variations therein may be subsequently made which are also intended to be encompassed by the following claims.

Claims

What is claimed is:
1 . An apparatus, comprising:
a memory array comprising:
a volatile memory;
a first non-volatile memory;
a second non-volatile memory; and
a cache manager controlling access by a computer system to the memory array.
2. The apparatus of claim 1 , wherein the volatile memory is a dynamic random access memory.
3. The apparatus of claim 1 , wherein the first non-volatile memory is a high- performance non-volatile memory, and the second non-volatile memory is a high- capacity non-volatile memory.
4. The apparatus of claim 1 , wherein the apparatus is arranged so that all communications to and from the volatile memory, to and from the first non-volatile memory, and to and from the second non-volatile memory go through the cache manager.
5. The apparatus of claim 1 , wherein a cache of the apparatus is divided into a plurality of partitions, and each partition of the plurality of partitions comprises at least one set of cache blocks.
6. The apparatus of claim 5, wherein a first partition of the plurality of partitions is allocated to the volatile memory, and a second partition of the plurality of partitions is allocated to the first non-volatile memory.
7. A method, comprising:
receiving a request for a memory operation by a cache manager of a persistent memory array;
identifying, by the cache manager, at least one memory technology in the persistent memory array for carrying out the memory operation; and
carrying out the memory operation by the cache manager operating in conjunction with the at least one memory technology.
8. The method of claim 7, wherein the persistent memory array comprises: a volatile memory;
a high-performance non-volatile memory; and
a high-capacity non-volatile memory,
wherein the at least one memory technology is at least one of the volatile memory, the high-performance non-volatile memory, or the high-capacity nonvolatile memory.
9. The method of claim 8, wherein the memory operation comprises a read operation, and the carrying out comprises:
retrieving, by the cache manager, data requested by the read operation from the volatile memory, when a hit exists in the volatile memory;
retrieving, by the cache manager, the data requested by the read operation from the high-performance non-volatile memory, when a miss exists in the volatile memory, but a hit exists in the high-performance non-volatile memory; and
moving, by the cache manager, the data requested by the read operation from the high-capacity non-volatile memory to the volatile memory, and then retrieving, by the cache manager, the data requested by the read operation from the volatile memory, when a miss exists in both the volatile memory and the high- performance non-volatile memory.
10. The method of claim 8, wherein the memory operation comprises a write operation, and the carrying out comprises:
writing, by the cache manager, data requested by the write operation to the high-performance non-volatile memory, when a hit exists in the high- performance non-volatile memory;
moving, by the cache manager, the data requested by the write operation from the volatile memory to the high-performance non-volatile memory, and then writing, by the cache manager, the data requested by the write operation to the high-performance non-volatile memory, when a miss exists in the high- performance non-volatile memory, but a hit exists in the volatile memory; and moving, by the cache manager, the data requested by the write operation from the high-capacity non-volatile memory to the high-performance non-volatile memory, and then writing, by the cache manager, the data requested by the write operation to the high-performance non-volatile memory, when a miss exists in the high-performance non-volatile memory and in the volatile memory.
1 1 . The method of claim 8, wherein the memory operation comprises a data eviction, and the carrying out comprises:
allocating, by the cache manager, a block in the high-performance nonvolatile memory for data to be evicted from the volatile memory, when the volatile memory is full; and
moving the data to be evicted from the volatile memory to the block in the high-performance non-volatile memory.
12. The method of claim 8, wherein the memory operation comprises a data eviction, and the carrying out comprises:
allocating, by the cache manager, a block in the high-capacity non-volatile memory for data to be evicted from the high-performance non-volatile memory, when the high-performance non-volatile memory is full; and
moving the data to be evicted from the high-performance non-volatile memory to the block in the high-capacity non-volatile memory.
13. A non-transitory machine-readable storage medium encoded with instructions executable by a processor, the machine-readable storage medium comprising:
instructions to identify at least one memory technology in a persistent memory array for carrying out a requested memory operation, wherein the at least one memory technology is selected from a group comprising: a volatile memory, a high-performance non-volatile memory, and a high-capacity non-volatile memory, and wherein the group is accessed via a cache manager of the persistent memory array; and
instructions to carry out the requested memory operation by the cache manager operating in conjunction with the at least one memory technology.
14. The non-transitory machine-readable storage medium of claim 13, wherein the memory operation comprises a read operation, and the instructions to carry out the requested memory operation comprise:
instructions to retrieve data requested by the read operation from the volatile memory, when a hit exists in the volatile memory;
instructions to retrieve the data requested by the read operation from the high-performance non-volatile memory, when a miss exists in the volatile memory, but a hit exists in the high-performance non-volatile memory; and
instructions to move the data requested by the read operation from the high-capacity non-volatile memory to the volatile memory, and to then retrieve the data requested by the read operation from the volatile memory, when a miss exists in both the volatile memory and the high-performance non-volatile memory.
15. The non-transitory machine-readable storage medium of claim 13, wherein the memory operation comprises a write operation, and the instructions to carry out the requested memory operation comprise:
instructions to write data requested by the write operation to the high- performance non-volatile memory, when a hit exists in the high-performance nonvolatile memory;
instructions to move the data requested by the write operation from the volatile memory to the high-performance non-volatile memory, and to then write the data requested by the write operation to the high-performance non-volatile memory, when a miss exists in the high-performance non-volatile memory, but a hit exists in the volatile memory; and instructions to move the data requested by the write operation from the high-capacity non-volatile memory to the high-performance non-volatile memory, and to then write the data requested by the write operation to the high- performance non-volatile memory, when a miss exists in the high-performance non-volatile memory and in the volatile memory.
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