WO2017076911A1  Key sequence generation for cryptographic operations  Google Patents
Key sequence generation for cryptographic operations Download PDFInfo
 Publication number
 WO2017076911A1 WO2017076911A1 PCT/EP2016/076436 EP2016076436W WO2017076911A1 WO 2017076911 A1 WO2017076911 A1 WO 2017076911A1 EP 2016076436 W EP2016076436 W EP 2016076436W WO 2017076911 A1 WO2017076911 A1 WO 2017076911A1
 Authority
 WO
 WIPO (PCT)
 Prior art keywords
 sub
 sequence
 function
 functions
 keys
 Prior art date
Links
 230000001131 transforming Effects 0.000 claims abstract description 12
 239000002131 composite materials Substances 0.000 claims description 14
 238000004590 computer program Methods 0.000 claims description 3
 230000000875 corresponding Effects 0.000 description 15
 239000000203 mixtures Substances 0.000 description 9
 238000000034 methods Methods 0.000 description 4
 238000010276 construction Methods 0.000 description 3
 239000010950 nickel Substances 0.000 description 3
 280000156839 Program Products companies 0.000 description 2
 238000004422 calculation algorithm Methods 0.000 description 2
 230000001186 cumulative Effects 0.000 description 2
 230000001419 dependent Effects 0.000 description 2
 280000405767 Alphanumeric companies 0.000 description 1
 281000042305 Lecture Notes in Computer Science companies 0.000 description 1
 281000149338 Springer Science+Business Media companies 0.000 description 1
 241000282485 Vulpes vulpes Species 0.000 description 1
 238000004364 calculation methods Methods 0.000 description 1
 230000000694 effects Effects 0.000 description 1
 239000011159 matrix materials Substances 0.000 description 1
 230000003287 optical Effects 0.000 description 1
 230000002441 reversible Effects 0.000 description 1
 239000007787 solids Substances 0.000 description 1
Classifications

 H—ELECTRICITY
 H04—ELECTRIC COMMUNICATION TECHNIQUE
 H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
 H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
 H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication the encryption apparatus using shift registers or memories for blockwise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
 H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation

 H—ELECTRICITY
 H04—ELECTRIC COMMUNICATION TECHNIQUE
 H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
 H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
 H04L2209/24—Key scheduling, i.e. generating round keys or subkeys for block encryption
Abstract
Description
KEY SEQUENCE GENERATION FOR CRYPTOGRAPHIC OPERATIONS
The present disclosure relates to the generation from a main key of a sequence of sub keys for cryptographic operations. More specifically, although not exclusively, the present disclosure relates to a block cipher having a key schedule in accordance with the sequence and use of the block cipher for encryption and decryption of a message.
BACKGROUND Cryptographic block ciphers, such as DES or AES, whether implemented in hardware or in software, can be the target of physical attacks. In such attacks, an attacker gathers information of various types during the operation of the block cipher. Types of information used in such attacks include:
• sidechannel information that leaks from the execution of the block cipher, such as power consumption, timing information or magnetic radiation;
• information from differential or collision fault analysis;
• both of the above.
This information can be used by the attacker to uncover the secret key used during the execution of the block cipher.
Block ciphers operate on round keys, which are subkeys that are derived from the secret or main key according to a key schedule, by an algorithm typically referred to as the key schedule. In general, sidechannel or fault attacks lead to the recovery of a round key. Due to correlations between the main key and round keys inherent in the key schedule of block ciphers such as AES or DES, it is relatively easy to derive the secret key from a recovered round key.
An attacker can target the execution of the key schedule (in which case the attack is likely to be a template attack that models the signal obtained from the sidechannel and its noise), the application of the block cipher in encryption or decryption, or both the key schedule and block cipher execution. In the current state of the art, the main key can be recovered from either operation using a single side channel attack or other attacks on a single subkey. Examples of possible attacks include side channel analysis (CPA  Correlation Power Analysis, DPA Differential Power Analysis), or DFA  Differential Fault Analysis of the encryption/decryption operation. For the key schedule algorithm, a template sidechannel attack is an example of a feasible attack. In one approach proposed in the literature (P. Junod and S. Vaudenay. FOX: a new family of block ciphers. Selected Areas in Cryptography 2004: Waterloo, Canada, August 910, 2004. Lecture Notes in Computer Science. SpringerVerlag), the key schedule has been designed such that each round key is generated by applying a cryptographic, collision resistant and oneway function to the secret main key. In this way, correlations between round keys and between the round keys and the secret key are reduced or eliminated, so that an attack based on recovering a single round key using sidechannel or fault analysis information is unlikely to succeed. While the use of a oneway function in this way to reduce correlations between keys is a step forward, further improvements in resilience to attacks, specifically sidechannel or other physical attacks would be desirable.
SUMMARY Some aspects of the disclosure are set out in the accompanying independent claims. Some optional features of specific embodiments are set out in the dependent claims dependent thereon.
In some embodiments, a sequence of subkeys for cryptographic operations is generated from a main key, with each subkey being defined by respective bit values. The main key is operated on only once to generate the subkeys of the sequence, with a transformation, for example a sequence of operations comprising one or more oneway functions. The respective bit values of the subkeys of the sequence are set using respective bit values of the one or more oneway functions. For example, in some embodiments, each bit of the output of the one or more oneway functions is used only once to set a corresponding bit value of all the bit values of the subkeys. There is thus a one to one relationship between a bit value of the output of the one or more oneway functions and its corresponding bit value of the subkeys. Advantageously, deriving subkey bits from respective output bits of one or more oneway functions removes or at least reduces correlations between the main key and the sub keys, as well as between subkeys, making it harder or even impossible to recover the main key or other subkeys from a single subkey, for example as found using a side channel attack. At the same time, by using the main key only once (rather than using the main key each time a subkey is generated), the vulnerability of the main key to a side channel attack is reduced, because the opportunities for recovering physical information that could lead to the discovery of the main key are reduced. In the context of cryptographic operations, a oneway function will be understood to be a function that is easy to compute to generate an output from an input (for example in the sense that the computational complexity is polynomial in time and space, or more practically, within a certain number of machine operations or time units seconds or milliseconds) and which is practically noninvertible meaning that is not realistic to find or reconstruct the input from the output (in the sense that the computational complexity might involve super polynomial effort, exceeding accessible resources). This is often referred to as preimage resistance. Also, in this context, the output bits of a oneway function will be independent of each other in the sense that there is no information in the state of one bit regarding the state of other bits of the output.
It is further typically preferable, but not mandatory, that a oneway function in this context also has the properties of second preimage resistance and collision resistance.
In particular, one or more of the following oneway functions (combinations of oneway functions) may be used in accordance with various embodiments. This includes, but is not limited to:
• Cryptographic hashes, such as SHA1 , SHA256, RIPEMD160, SHA3, etc.;
• Specialpurpose oneway functions with larger outputs, for example the Rabin function χ^{Λ}2 mod N with N being the product of two large prime numbers, or higher order versions of this function;
• Lightweight pseudo hash functions to decrease computational resource
requirements, such as xxhash or SipHash;
• a DavisMeyer construction based on a, preferably lightweight, permutation (a lightweight permutation are capable of being run on devices with very low computing power;
• a product with a noninvertible matrix;
• use of discrete Logarithm problem: a^{x} mod p, with p a prime, a a generator of Zp^{*}, and x the input of the oneway function
In embodiments where more than one oneway computation is required, the respective oneway functions used may be the same, or may be different from each other. In some embodiments, the respective bit values of at least two of the subkeys are set in accordance with respective bit values of one oneway function, according to a predefined relationship. In this way, two or more subkeys can be generated by computation of a single oneway function. In one particular case, the respective bit values of all the sub keys of the sequence are set in accordance with respective bit values of one oneway function. In this case, all subkeys are generated by a single oneway function, requiring only a single use of the main key and ensuring that the main key is protected by the one way characteristics of the oneway function and that subkey bits and hence subkeys are independent of each other due to the independence of the output bits of the oneway function.
In some embodiments, operating on the main key generates a plurality of intermediate outputs using respective subfunctions. A oneway function applied to each intermediate output then generates a respective oneway output and one or more of the subkeys are generated from each oneway output. By generating a plurality of intermediate outputs using the main key only once, and then using respective oneway functions to generate the subkeys, oneway functions that produce fewer bits than are needed to generate all subkeys can be used to generate the subkeys while still only using the main key once.
In some embodiments, the intermediate outputs are generated by first applying a first sub function to the main key to generate a first intermediate output followed by repeatedly applying a next subfunction to the previous intermediate output to generate a next intermediate output. Respective oneway functions are applied to each intermediate output to generate corresponding one or more of the subkeys of the sequence. In this way the subkeys of the sequence can be generated. The processing from subfunction to the corresponding one or more subkeys may be done synchronously (computing a sub function and the corresponding subkey(s), then computing the next subfunction and corresponding subkey(s), and so on). Alternatively, all subfunctions may first be processed, storing the outputs (of the subfunction and/or the oneway function), and the subkeys may subsequently be generated from the stored values.
Instead of passing the intermediate outputs through respective oneway functions, in some embodiments all intermediate outputs are passed through a single oneway function (or even a single instance of the same oneway function), that is the first and the next oneway functions are the same function. Independently, the subfunctions may be mutually different or may all be the same, for example a bit operator such as a shift or rotation operator. Since each application of the subfunctions is cumulative in the sequence, the inputs to the oneway function(s) will vary with the sequence of repeated applications of the same function and hence produce a sequence of varying subkeys. Since the intermediate outputs are passed through a oneway function to generate the subkeys of the sequence, even for simple and possibly even repeating operations to generate the intermediate outputs, it will be at least as difficult to infer the main key or other subkeys from one recovered subkey as it is difficult to invert the oneway function(s). At the same time, since the main key is only used once to generate the first intermediate output, it is less prone to be discovered in a sidechannel attack or other physical attack. In addition, in some embodiments, the main key can further be dissociated from the generated sub keys by passing it through a oneway function and passing the result to the first sub function, thereby increasing the difficulty of recovering the main key from a cryptanalysis starting from a subkey uncovered using sidechannel information.
In some embodiments, where the subfunctions are cumulative in the sense that the corresponding chain of operations can be captured in a single composite function and are also invertible, this can be exploited to generate a reverse sequence of subkeys. For example the reverse sequence may be used as a decryption sequence of subkeys that is the reverse of an encryption sequence of subkeys, to decrypt a message encrypted with a block cipher having a key schedule generating the encryption sequence of subkeys. For the avoidance of doubt an unencrypted message string is referred to here as a plaintext or plaintext message without any implication as to the content of the message being text but "text" rather referring to any string of symbols, alphanumeric or otherwise. Likewise, the term ciphertext or ciphertext message is to be understood accordingly as an encrypted version of the message.
In some embodiments for generating a reverse sequence of a sequence of subkeys generated using a sequence of subfunctions that are invertible and have a composite function providing as an output the last intermediate output in the generation of the forward sequence of subfunctions, the same process as above is followed with the first subfunction being the composite function and the next subfunctions being the respective inverse functions of the next subfunctions of the forward sequence, in reverse order. While the forward sequence has been described above as an encryption sequence and the reverse sequence as a decryption sequence, it will be appreciated that the roles can be swapped and that the efficient generation of corresponding forward and reverse sequences of subkeys may find wider application.
In some embodiments subfunctions used in the generation of subkeys are not executed in a chained sequence as described above, each subsequent subfunction taking the output of the previous subfunction as an input, but rather the subfunctions are executed independently, for example asynchronously or in parallel. This means that each sub function needs to be supplied with its input independently. In order to avoid using the main key more than once in these embodiments, the main key is passed once through a further oneway function, for example a oneway function as discussed above, and the result is then supplied to each of the subfunctions, thus avoiding multiple reads of the main key. The subkeys are then generated from the output of the subfunctions via respective oneway functions or a shared oneway function, as described above.
One or more of the following subfunctions (combinations of sub functions) may be used in accordance with various embodiments, including but not limited to:
· affine functions (by definition invertible)
• invertible Boolean functions
• invertible Bit or Byte operators, such as XOR/ADD with constant, Shift/rotation, XOR/ADD of different bits of the state, bit permutations.
• an invertible table lookup function
· an invertible exponentiation function
• a Feistel construction
• a combination of the above
The subfunctions may comprise one or more of the above classes of functions.
Specifically, the subfunctions may comprise functions of the same one of the above classes or the same function varying in its parameters. As described above, the sub functions may be the identical and/or a single subfunction used repeatedly, in some embodiments. Any one of the above subfunctions may be combined with any one of the above oneway functions in accordance with various embodiments. In some
embodiments, the subfunction(s) are invertible tablelookup functions and the oneway function(s) are DavisMeyer constructions based on a lightweight permutation. While it is desirable for the subfunctions to be invertible to enable certain of the above embodiments that require the subfunctions to be inverted, this is not necessary in all embodiments. As mentioned above, the oneway functions may be the same or some or all of the oneway functions may be mutually different. The same oneway function may be
implemented, for example in hardware, in a single instance and may take inputs from the subfunctions in sequence to produce the corresponding sequence of subkeys.
Therefore, it will be understood that reference to oneway function in the plural includes the singular in that all oneway functions may be the same single oneway function and may be implemented as a single logical or physical instance of that single oneway function.
Aspects of the disclosure include a block cipher with a key schedule defined by a sequence of subkeys (a sequence of generating subkeys) as described above, and the use of such a block cipher for encryption and decryption of messages.
Further aspects of the disclosure include systems having means for implementing processing steps to generate sequences of subkeys and/or process (encrypt/decrypt) messages as described above; computer program products and signals encoding in physical form coded instructions that, when executed on a processor, implement processing steps as described above; and one or more tangible recordable media or memory devices, for example optical or magnetic discs or solid state devices, storing coded instructions that, when executed on a processor implement processing steps as described above. Further, these aspects extend to the combination of such computer program products and signals, tangible recordable media and memory devices in combination with a processor for executing the instructions, for example in a general purpose computer. Yet further aspects of the disclosure include a device comprising a memory for storing the main key and at least one subkey; and a processor configured to implement processing steps as described above to generate sequences of subkeys and/or process
(encrypt/decrypt) messages as described above. Embodiments of such a device comprise Application Specific Integrated Circuits, Field Programmable Gate Arrays, System On Chip and Integrated Circuit devices, or combinations thereof. It will be understood that in aspects in which processing comprises both encryption and decryption, encryption and decryption may be done in the same device or each may be done in a separate device with messages passed between the separate devices. BRIEF DESCRIPTION OF THE DRAWINGS
Specific embodiments will now be described, by way of example, to illustrate aspects of the disclosure and with reference to the accompanying drawings, in which:
Figures 1 to 4 illustrate different modes of a block cipher with a round key generator;
Figure 5 illustrates an implementation of a round key generator enabling parallel execution of subfunctions to generate round keys; Figure 6 illustrates a recursive version of the implementation of Figure 5;
Figure 7 illustrates an implementation of a round key generator with sequential execution of subfunctions;
Figure 8 illustrates an implementation of a round key generator with sequential execution of subfunctions to generate a reverse sequence of round keys;
Figure 9 illustrates a recursive version of the implementations of Figures 7 and 8; and
Figure 10 illustrates an implementation of a round key generator generating a sequence of round keys using a single oneway function.
DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS
With reference to Figures 1 to 4, a block cipher 10 comprises a round key generator 200 taking as input a main key K stored in a register 100. The round key generator 200 generates a sequence 120 of round keys K_{0}, K_{2},..., K_{N1}. An encryption module 300 takes as input the sequence of round keys 120 and a plaintext from a register 400. The encryption module 300 encrypt the plaintext 400 with the first key in the sequence, then encrypts the result with the second key in the sequence, and so on for all keys in the sequence, and outputs a cipher text to a register 500 as a result. With reference to Figure 2, in a decryption mode of the block cipher 10, the encryption module 300 is replaced with a decryption module 302 taking as an input a cipher text from the register 500 and a decryption sequence 142 that is the reverse of the encryption sequence 140 of round keys 142. The decryption module 302 decrypts the cipher text 500 by applying the first key of the sequence 140 (the last key of the sequence 120) to the cipher text 500, then the second key 142 in the sequence 140 to the result of that operation, and so forth, until the last key in the sequence 140 is used to produce the plaintext 400. It will be understood that, according to the embodiment, encryption and decryption modules of the block cipher 10 are implemented in the same device or circuit (in some embodiments sharing computational modules) or in different devices and circuits.
In some embodiments, as illustrated schematically in Figures 1 and 2, the round keys are generated independently, that is each round key is stored separately to store the entire sequence 120, 140 of round keys, enabling the round keys of the sequence to be generated in any order or in parallel (and the decryption sequence to be generated by reading the encryption sequence in reverse order without further computation). In other embodiments, as schematically illustrated in Figures 3 and 4, the round keys are generated in sequence one at a time. While this is advantageous in requiring less memory to store the round keys and exposing only one round key at a time, it requires that the reverse sequence of round keys is computed again, while in embodiments as depicted in Figures 1 and 2, the stored round keys can simply be traversed in the reverse order. With reference to Figure 5, a specific embodiment of the round key generator 200 is now described. The main key K is passed through a oneway function 220, also referred to as x, and the result is then passed through a set 240 of subfunctions 242, also referred to as Fo_{,} Fi , F_{2},..., F_{N1}. The result of each subfunction 242 is then passed through a sub function 262, also referred to as H. The result of each subfunction 242 may be fed to a common oneway function 262 common to all subfunctions, or each subfunction 242 may have a corresponding oneway function 262 to form a set of instances of oneway functions 260, which may all implement the same oneway function H, or different oneway functions, for example a different oneway function 262 for each subfunction 242. These operations result in a set of round keys 122 as the output of the one or more one way functions 262, in a sequence 120 of subkeys 122, also referred to as K_{0}, K_{1 :} K_{2}, .. . ,
Taking the sequence 120 as an encryption sequence, the decryption sequence can be obtained simply by reading the sequence 120 in reverse order in embodiments where the round keys 122 are all stored. In other embodiments, the decryption sequence can be obtained by generating the reverse sequence of round keys by running the subfunctions 242 in reverse order to the sequence 240, for example where only one round key is stored and generated on the fly. In some embodiments, irrespective of whether the round keys 122 are computed in one go or on the fly, the following functions are used for x, F and H, where p, q, p^{*}, q^{*}, pi and qi are large prime numbers:
• x := K^{2} mod N^{*}, with N^{*}=p^{*}q^{*}
• Fi(x) := x^{2} mod Ni, with Ni=piqi
· H(y) := y^{8} mod N, with N=pq; y:=Fi(x)
The prime numbers for p^{*} and q^{*}, , are chosen such that it is in practice not possible to compute the square root. For example, in some embodiments log_{2}(N^{*}) is at least 2048 bits. The others primes pi and qi are chosen similarly, for example such that log_{2}(Ni) is half the number of bits of the output of x (half of log_{2}(N^{*})) and p and q are chosen such that log_{2}(N) is greater or equal the number of bits required in the round keys 122. To protect the main key K from sidechannel analysis, a random multiple of N^{*} can be added to K on read out, or K can be stored with such a constant added, as, in embodiments using a mod N* operation as a first stage, this will not affect the output of x.
With reference to Figure 6, some embodiments in which only a single round key Ki is stored in a register 640 and generated on the fly to generate the sequence 120 is now described. Such embodiments are particularly suitable for implementation in dedicated circuits in which execution can be done quickly in hardware and storage capacity may be limited. A register 100 holding a value for the main key K is read by a module 220 implementing x. The module 220 calculates x(K) and stores it in internal register. A sub function module 610 configured to compute a subfunction F, for each iteration of key generation communicates with a register 620 holding a sequence of parameters, each defining a specific instance of F, for each iteration: F_{0,} Fi , ... F_{N2,} F_{N1}. The subfunction module 610 passes its output to a oneway module 630 implementing the oneway function H to generate an output K, and store it in a register 640. The subfunction module 610 is configured such that it sends a trigger on a trigger connection 652 to module 220 to receive the value of x(K) again (alternatively this value may be stored in a register in sub function module 610 or elsewhere). On receiving the value of x(K), the next parameter to define F_{i+1} is read from the register 620 and a value for K_{i+1} is calculated via oneway module 630.
Embodiments described so far protect the main key by passing it through a first oneway function x and calculate the round keys 122 from this value as independent inputs to respective subfunctions 242. Alternative embodiments are now described with reference to Figures 7 to 9, in which a first subfunction 242 of the sequence of subfunctions 240 takes the main key K as an input and subsequent subfunctions F_{2}, ... , F_{N1} 244 to 248 (F_{r} F_{2},... , F_{N1}) each take the output of the previous subfunction as an input, for example the subfunction 244 takes as input the output of the subfunction 242, and the sub function 246 takes as input the output of the subfunction 244, and so on. The output of each subfunction 242 to 248 in the sequence 240 is again passed through a oneway function 262, as discussed above with reference to Figure 5 to produce in turn as an output a sequence 120 of round keys 122 to 128, again as described above with reference to Figure 5.
In some specific embodiments, F, is chosen from the classes of functions described above specifically in some embodiments F,: is a table look up function, and the oneway function H(y) is chosen from the classes of functions described above, specifically in some embodiments, H (y) is a DavisMeyer construction based on a lightweight permutation. In some embodiments, the oneway function H may be chosen as above, that is H(y) := y mod N. In some embodiments, a first oneway function x, as described above, may be interposed between K and the first subfunction 242 (F_{0}) of the sequence 240. Taking the sequence of round keys 120 as the encryption sequence, the decryption sequence can be derived simply by reading the sequence 120 in reverse, in embodiments in which the individual round keys 122 to 128 remain stored. Where the round keys 122 to 128 are not available, they can of course be computed by the sequence of subfunctions 240, as described above, with results read in reverse order once computed. However, it may be desirable to begin the computation of the decryption sequence with the first round key of the decryption sequence, which is the last round key of the encryption sequence. This means that the first key to be used is available first, and enables embodiments in which round keys are computed on the fly and not stored. Some embodiments enabling the reversal of the sequence of round keys to derive a decryption sequence 130 of round keys 122 to 128 are now described with reference to Figure 8. These embodiments are suitable for computing the reverse or decryption sequence 134 of a forward or decryption sequence 120 derived using subfunctions 242 to 248, which are invertible and from which a composite function that directly computes the result of the sequence of subfunctions 240 can be constructed as a composite function of the subfunctions 242 to 248 as follows:
F{O_{→}NI} := F_{0} ° Fi ° F_{N2} ° F_{N1}
With reference to Figure 8, a first subfunction 252 of the reverse sequence 250 computes the composite function F_{{0→N}i} of the subfunctions of the forward sequence 240 and the output is passed through a oneway function 262 to generate a first round key 128 in the reverse round key sequence 130, corresponding to the last round key 128 of the forward sequence 120, that is K_{N1}. The output of the subfunction 252 is also passed to the next subfunction 254 of the reverse sequence 250, which corresponds to the inverse function of the last function 248 of the forward sequence 240, F_{N1} ^{"1}. The output of the subfunction 254 is again passed through a oneway function 262 to generate the next round key in the reverse sequence 130, K_{N2}, the penultimate round key in the forward sequence 120. The next subfunction 256 in the reverse sequence 250 corresponds to the inverse of the penultimate subfunction in the forward sequence 240, F_{N2} ^{"1} , and is used to generate the next round key in the inverse sequence 130, and so forth, until the last subfunction in the reverse sequence 250 which corresponds to the inverse of the second subfunction in the forward sequence 240 is used to generate the last round key 122 in the reverse sequence 130, which is the first round key in the forward sequence 120.
As mentioned above, in these embodiments, the subfunctions are required to be invertible and composable into a composite function. In some embodiments, the sub functions are invertible table lookup functions or shift or rotation bit operators. As long as the subfunctions are invertible and composable, the subfunctions of the sequence 240 may be all the same, single subfunction, used repeatedly, or may each be different, or a combination of the two.
With reference to Figure 9, some embodiments in which only a single round key K, is stored in a register 640 and round keys are generated on the fly to generate the sequence 120 using a sequence of subfunctions 240 is now described. It will be understood that these embodiments are equally suitable for producing the sequence 130 described above using the corresponding sequence 250 of subfunctions. Again, such embodiments are particularly suitable for implementation in dedicated circuits in which execution can be done quickly in hardware and storage capacity may be limited.
A register 100 holding a value for the main key K is read by a subfunction module 610. As described above, the subfunction module 610 also reads one or more parameters to define the function F, for the relevant iteration and evaluates Fi, supplying the result as an output to a oneway module 630 which calculates a oneway function of its input and stores the result as the round key K, in register 640. The module 610 also supplies its own output again to its input over a line 660 trigger the calculation of the next subfunction F_{i+1} and hence K_{i+1} via the oneway function module 630.
All of the above embodiments have been described in terms of generating a single round key K from a corresponding subfunction F,. In these embodiments, the number of bits in the output of the oneway function(s) H must be equal to or greater than the number of bits of the round K,. It will, of course, be understood that in some embodiments the output of the oneway functions may have less bits than required for the subkeys. In such embodiments, for example where the number of output bits of the oneway function is ½ the number of bits required, or 1/m more generally, the processes above can be run twice or m times to generate the required bits. Likewise, in some embodiments, the output of two (m) oneway functions run one after the other can be combined to generate the sub keys in sequence, in effect grouping adjacent round keys (as illustrated in the figures) together to form a round key of sufficient bits. On the other hand, in some embodiments, the number of bits in the output of H is at least mfold that of a single round key K, and m round keys are generated from the output of the oneway function H applied to a corresponding subfunction F,. In other words, in these embodiments, m round keys Ki._{m+j}, j = 1 , 2, ... , m, are generated from each subfunction F,. For example, if the output of H has 2048 bits, 16 128 bit round keys K, can be generated from the output of that function.
In some embodiments, the output bits of H are mapped to the bits of the K, by a predetermined relationship. For example, if the number of bits of K, is n, the first n bits of the output of H are used to set the bits of K_{0}, the next n bits of the output of H are used to set the bits of Ki , and so forth. Other relationships are of course equally possible, for example using the first m bits of the output of H to set the first bits of all K,, using the second m bits of the output of H to set the second bits of K,, and so forth, or any other predetermined mapping.
In some embodiments, now described with reference to Figure 10, a single oneway function 280 produces an output with a sufficient number of bits to generate the required number of round keys K, in the sequence 120, that is there are m round keys in the sequence in terms of the above discussion. Since all round keys are generated from the output of a single oneway function, no subfunctions F, are required or, alternatively, the oneway function 280 can be seen as the combination of a single subfunction F, and a oneway function H. As illustrated in Figure 10 and described above, in some
embodiments the bits of contiguous blocks of the output of the oneway function 280 are used to define corresponding K, round keys, although other schemes of assigning oneway function output bits to round key bits are equally possible, as described above.
While the preceding specific description made reference to some specific functions to implement x, H and F,, many other suitable functions are possible subject to the constraints explained above, where applicable, in the various embodiments, and will readily occur to a person skilled in the art. Specifically, some suitable functions have been discussed above and may be used in combination with the described specific
embodiments. The following embodiments are also disclosed: 1. A device for generating from a main key a sequence of subkeys for cryptographic operations, wherein each subkey is defined by respective bit values, the device comprising a memory for storing the main and at least one subkey and a processor configured to:
operate on the main key with a transformation, wherein the transformation comprises one or more oneway functions and the main key is operated on only once to generate the subkeys of the sequence; and
set the respective bit values of the subkeys of the sequence using respective bit values of the one or more oneway functions.
2. A device according to item 1 , wherein setting the respective bit values comprises setting the respective bit values of at least two of the subkeys in accordance with respective bit values of one of the one or more oneway functions according to a predefined relationship.
3. A device according to item 1 , wherein setting the respective bit values comprises setting the respective bit values of all the subkeys of the sequence in accordance with respective bit values of the one of the one or more oneway function according to a predefined relationship.
4. A device according to item 1 or 2, wherein operating on the main key comprises generating a plurality of intermediate outputs and applying a oneway function to each intermediate output to generate a respective oneway output, and wherein the processor is configured to generate one or more of the subkeys from each oneway output.
5. A device according to item 1 , 2 or 4, wherein the processor is configured to
apply a first subfunction to the main key to generate a first intermediate output; apply a first oneway function to the first intermediate output; and
generate a first one or more of the subkeys of the sequence from an output of the first oneway function, and
repeatedly:
apply a next subfunction to the previous intermediate output to generate a next intermediate output;
apply a next oneway function to the next intermediate output; and generate a next one or more of the subkeys of the sequence from an output of the next oneway function. 6. A device according to item 1 , 2 or 4, wherein the processor is configured to:
apply an input oneway function to the main key to generate a working key;
apply a plurality of subfunctions to the working key to generate respective intermediate outputs;
apply an output oneway function to each intermediate output to generate a respective transformation output; and
generate the subkeys of the sequence from the transformation outputs.
7. A device according to any one of items 1 to 6, wherein the processor is configured to implement a block cipher with a key schedule defined by the sequence and to use the subkeys of the sequence as round keys in the block cipher.
8. A device for generating from a main key related forward and reverse sequences of subkeys for use in cryptographic operations, the device comprising a memory for storing the main key and at least one subkey and a processor configured according to item 5 to generate subkeys of the forward sequence,
wherein the next subfunctions are applied in a forward next subfunction sequence and
wherein the first subfunction followed by the subfunctions of the forward next subfunction sequence define a forward subfunction sequence;
and wherein the processor is configured according to item 5 to generate from the main key a reverse sequence of subkeys,
wherein the first subfunction is the composite function of the subfunctions of the forward subfunction sequence and
wherein the next subfunctions are applied in a reverse next subfunction sequence and the subfunctions of the reverse next subfunction sequence correspond to the respective inverse functions of the subfunctions of the forward next subfunctions sequence in reverse order. 9. A device for decrypting a message encrypted with a block cipher, the block cipher having a key schedule comprising round keys applied in an encryption sequence, the encryption sequence of round keys being obtainable from a main key by a processor configured in accordance with item 5, wherein the next subfunctions are applied in an encryption next subfunction sequence and the first subfunction followed by the sub functions of the encryption next subfunction sequence define an encryption subfunction sequence, the device comprising a memory for storing a main key and at least one sub key and a processor configured in accordance with item 5 to generate from the main key a decryption sequence of subkeys,
wherein the first subfunction is the composite function of the subfunctions of the encryption subfunction sequence and
wherein the next subfunctions are applied in a decryption next sub function sequence and the subfunctions of the decryption next subfunction sequence correspond to the respective inverse functions of the subfunctions of the encryption next subfunctions sequence in reverse order; and
configured to apply the subkeys in the order of the decryption sequence to decrypt the message.
10. A device for processing a message with a block cipher having a key schedule, the device comprising a memory for storing a main key and at least one subkey and a processor configured to:
encrypt a plaintext of the message with the block cipher to generate a cipher text, wherein the processor is configured in accordance with item 5 to generate round keys of the key schedule in an encryption sequence from a main key, wherein the next sub functions are applied in an encryption next subfunction sequence and the first sub function followed by the subfunctions of the encryption next subfunction sequence define an encryption subfunction sequence and wherein the processor is configured to
encrypt the plaintext with a first one of the round keys in the encryption sequence to generate a first round text; and
for the remaining round keys in the encryption sequence, encrypt a previous round text with a next round key in the encryption sequence to generate a next round text, wherein the last round text is the cipher text; and wherein the processor is further configured to
decrypt the cipher text to generate the plaintext, wherein the processor is configured in accordance with item 5 to generate from the main key a decryption sequence of subkeys, wherein the first subfunction is the composite function of the sub functions of the encryption subfunction sequence, and wherein the next subfunctions are applied in a decryption next subfunction sequence and the subfunctions of the decryption next subfunction sequence correspond to the respective inverse functions of the subfunctions of the encryption next subfunctions sequence in reverse order; and wherein the processor is configured to
decrypt the cipher text with a first one of the round keys in the decryption sequence to generate a first round text; and for the remaining round keys in the decryption sequence, decrypt a previous round text with a next round key in the decryption sequence to generate a next round text, wherein the last round text is the plaintext. While the above specific description of some embodiments has been made in terms of a block cipher with a key schedule and defined by certain round key generators, it will be appreciated that the described embodiments of generating sequences of cryptographic keys may find wider application then in the context of a block cipher and round keys. The present disclosure is therefore not limited to the context of a block cipher but
encompasses other uses of subkey sequences generated from a main key in accordance with the disclosed embodiments of round key generators which can thus more generally be described as subkey generators.
More generally, the above description of specific embodiments has been made by way of example to illustrate aspects of the disclosure in is not to be read as limiting on the subject matter claimed in the claims that follow.
Claims
Priority Applications (2)
Application Number  Priority Date  Filing Date  Title 

GBGB1519612.4A GB201519612D0 (en)  20151106  20151106  Key sequence generation for cryptographic operations 
GB1519612.4  20151106 
Applications Claiming Priority (7)
Application Number  Priority Date  Filing Date  Title 

CN201680077921.5A CN108476132A (en)  20151106  20161102  Key for an encrypting operation sequence generates 
US15/772,933 US10742394B2 (en)  20151106  20161102  Key sequence generation for cryptographic operations 
MX2018005700A MX2018005700A (en)  20151106  20161102  Key sequence generation for cryptographic operations. 
KR1020187016055A KR20180081559A (en)  20151106  20161102  Generate key sequence for encryption operation 
BR112018009137A BR112018009137A8 (en)  20151106  20161102  method of generating a master key from a subkey sequence for cryptographic operations, method of generating a master key from related direct and reverse sequence of subkeys for use in cryptographic operations, method of decrypting a message encrypted with a block cipher, method of processing a block cipher message having a key programming, device for generating a master key from a subkey sequence for cryptographic operations, device for processing a message with a block cipher having a key programming, computer program product, and one or more computer readable media 
SG11201803741PA SG11201803741PA (en)  20151106  20161102  Key sequence generation for cryptographic operations 
EP16788725.6A EP3371928A1 (en)  20151106  20161102  Key sequence generation for cryptographic operations 
Publications (1)
Publication Number  Publication Date 

WO2017076911A1 true WO2017076911A1 (en)  20170511 
Family
ID=55132394
Family Applications (1)
Application Number  Title  Priority Date  Filing Date 

PCT/EP2016/076436 WO2017076911A1 (en)  20151106  20161102  Key sequence generation for cryptographic operations 
Country Status (9)
Country  Link 

US (1)  US10742394B2 (en) 
EP (1)  EP3371928A1 (en) 
KR (1)  KR20180081559A (en) 
CN (1)  CN108476132A (en) 
BR (1)  BR112018009137A8 (en) 
GB (1)  GB201519612D0 (en) 
MX (1)  MX2018005700A (en) 
SG (1)  SG11201803741PA (en) 
WO (1)  WO2017076911A1 (en) 
Cited By (1)
Publication number  Priority date  Publication date  Assignee  Title 

CN109067528A (en) *  20180831  20181221  阿里巴巴集团控股有限公司  Cryptooperation, method, cryptographic service platform and the equipment for creating working key 
Citations (5)
Publication number  Priority date  Publication date  Assignee  Title 

WO1998031122A1 (en) *  19970108  19980716  Bell Communications Research, Inc.  A method and apparatus for generating secure hash functions 
US6185679B1 (en) *  19980223  20010206  International Business Machines Corporation  Method and apparatus for a symmetric block cipher using multiple stages with type1 and type3 feistel networks 
US20080304664A1 (en) *  20070607  20081211  Shanmugathasan Suthaharan  System and a method for securing information 
US20090245510A1 (en) *  20080325  20091001  Mathieu Ciet  Block cipher with security intrinsic aspects 
EP2197144A1 (en) *  20081215  20100616  Thomson Licensing  Methods and devices for a chained encryption mode 
Family Cites Families (2)
Publication number  Priority date  Publication date  Assignee  Title 

CN101401348B (en) *  20060310  20110831  耶德托公司  Method and system for cipher function vagueness 
US8130946B2 (en) *  20070320  20120306  Michael De Mare  Iterative symmetric key ciphers with keyed Sboxes using modular exponentiation 

2015
 20151106 GB GBGB1519612.4A patent/GB201519612D0/en not_active Ceased

2016
 20161102 US US15/772,933 patent/US10742394B2/en active Active
 20161102 MX MX2018005700A patent/MX2018005700A/en unknown
 20161102 KR KR1020187016055A patent/KR20180081559A/en unknown
 20161102 CN CN201680077921.5A patent/CN108476132A/en active Search and Examination
 20161102 BR BR112018009137A patent/BR112018009137A8/en unknown
 20161102 EP EP16788725.6A patent/EP3371928A1/en active Pending
 20161102 SG SG11201803741PA patent/SG11201803741PA/en unknown
 20161102 WO PCT/EP2016/076436 patent/WO2017076911A1/en active Application Filing
Patent Citations (5)
Publication number  Priority date  Publication date  Assignee  Title 

WO1998031122A1 (en) *  19970108  19980716  Bell Communications Research, Inc.  A method and apparatus for generating secure hash functions 
US6185679B1 (en) *  19980223  20010206  International Business Machines Corporation  Method and apparatus for a symmetric block cipher using multiple stages with type1 and type3 feistel networks 
US20080304664A1 (en) *  20070607  20081211  Shanmugathasan Suthaharan  System and a method for securing information 
US20090245510A1 (en) *  20080325  20091001  Mathieu Ciet  Block cipher with security intrinsic aspects 
EP2197144A1 (en) *  20081215  20100616  Thomson Licensing  Methods and devices for a chained encryption mode 
NonPatent Citations (3)
Title 

JUNOD PASCAL ET AL: "FOX : A New Family of Block Ciphers", 9 August 2004, NETWORK AND PARALLEL COMPUTING; [LECTURE NOTES IN COMPUTER SCIENCE; LECT.NOTES COMPUTER], SPRINGER INTERNATIONAL PUBLISHING, CHAM, PAGE(S) 114  129, ISBN: 9783642279966, ISSN: 03029743, XP047373883 * 
P. JUNOD; S. VAUDENAY: "Selected Areas in Cryptography", 9 August 2004, SPRINGERVERLAG, article "FOX: a new family of block ciphers" 
RIJMEN VINCENT ET AL: "The cipher SHARK", 21 February 1996, NETWORK AND PARALLEL COMPUTING; [LECTURE NOTES IN COMPUTER SCIENCE; LECT.NOTES COMPUTER], SPRINGER INTERNATIONAL PUBLISHING, CHAM, PAGE(S) 99  111, ISBN: 9783642234460, ISSN: 03029743, XP047294329 * 
Cited By (2)
Publication number  Priority date  Publication date  Assignee  Title 

CN109067528A (en) *  20180831  20181221  阿里巴巴集团控股有限公司  Cryptooperation, method, cryptographic service platform and the equipment for creating working key 
CN109067528B (en) *  20180831  20200512  阿里巴巴集团控股有限公司  Password operation method, work key creation method, password service platform and equipment 
Also Published As
Publication number  Publication date 

MX2018005700A (en)  20181211 
EP3371928A1 (en)  20180912 
US10742394B2 (en)  20200811 
SG11201803741PA (en)  20180628 
KR20180081559A (en)  20180716 
US20180316490A1 (en)  20181101 
GB201519612D0 (en)  20151223 
CN108476132A (en)  20180831 
BR112018009137A2 (en)  20181106 
BR112018009137A8 (en)  20190226 
Similar Documents
Publication  Publication Date  Title 

US8983063B1 (en)  Method and system for high throughput blockwise independent encryption/decryption  
Coron  Higher order masking of lookup tables  
Mahajan et al.  A study of encryption algorithms AES, DES and RSA for security  
Bhanot et al.  A review and comparative analysis of various encryption algorithms  
Bogdanov et al.  ALE: AESbased lightweight authenticated encryption  
JP5822970B2 (en)  Encryption device for pseudorandom generation, data encryption, and message encryption hashing  
Karri et al.  Paritybased concurrent error detection of substitutionpermutation network block ciphers  
CA2723319C (en)  A closed galois field cryptographic system  
JP4828068B2 (en)  Computer efficient linear feedback shift register  
US7295671B2 (en)  Advanced encryption standard (AES) hardware cryptographic engine  
US7403620B2 (en)  Cyphering/decyphering performed by an integrated circuit  
US7200232B2 (en)  Method and apparatus for symmetrickey decryption  
US7899190B2 (en)  Security countermeasures for power analysis attacks  
AU2008201156B2 (en)  Precalculated Encryption Key  
US7715553B2 (en)  Encrypting a plaintext message with authentication  
US7251326B2 (en)  Method and apparatus for data encryption  
US8416947B2 (en)  Block cipher using multiplication over a finite field of even characteristic  
US7945049B2 (en)  Stream cipher using multiplication over a finite field of even characteristic  
US7092525B2 (en)  Cryptographic system with enhanced encryption function and cipher key for data encryption standard  
JP5402632B2 (en)  Common key block encryption apparatus, common key block encryption method, and program  
US7907725B2 (en)  Simple universal hash for plaintext aware encryption  
CN101350714B (en)  Efficient advanced encryption standard (AES) data path using hybrid RIJNDAEL SBOX  
US7978851B2 (en)  Keystream encryption device, method, and program  
US9143325B2 (en)  Masking with shared random bits  
US7779272B2 (en)  Hardware cryptographic engine and encryption method 
Legal Events
Date  Code  Title  Description 

121  Ep: the epo has been informed by wipo that ep was designated in this application 
Ref document number: 16788725 Country of ref document: EP Kind code of ref document: A1 

WWE  Wipo information: entry into national phase 
Ref document number: 15772933 Country of ref document: US 

WWE  Wipo information: entry into national phase 
Ref document number: 11201803741P Country of ref document: SG 

WWE  Wipo information: entry into national phase 
Ref document number: MX/A/2018/005700 Country of ref document: MX 

NENP  Nonentry into the national phase 
Ref country code: DE 

REG  Reference to national code 
Ref country code: BR Ref legal event code: B01A Ref document number: 112018009137 Country of ref document: BR 

WWE  Wipo information: entry into national phase 
Ref document number: 1020187016055 Country of ref document: KR 

ENP  Entry into the national phase 
Ref document number: 20187016055 Country of ref document: KR Kind code of ref document: A 

WWE  Wipo information: entry into national phase 
Ref document number: 2016788725 Country of ref document: EP 

ENP  Entry into the national phase 
Ref document number: 112018009137 Country of ref document: BR Kind code of ref document: A2 Effective date: 20180504 