WO2017075448A1

WO2017075448A1 - Power inverter control

Info

Publication number: WO2017075448A1
Application number: PCT/US2016/059460
Authority: WO
Inventors: Nicola O'byrne; Brendan Aengus MURRAY
Original assignee: Analog Devices Global
Priority date: 2015-10-28
Filing date: 2016-10-28
Publication date: 2017-05-04

Abstract

Techniques for a configurable, hardware-implemented, inverter controller are provided. In an example, a power inverter control circuit can include a configurable, hardware-implemented control loop circuit, an application interface and a configuration register. The hardware-implemented nature of the inverter controller can allow for more interface flexibility, more tightly coupled feedback, and high bandwidth while allowing ancillary processors to extract status and diagnostic information without burdening the inverter switch timing control or the acquisition of raw feedback information.

Description

POWER INVERTER CONTROL PRIORITY AND RELATED APPLICATIONS

[0001] This application claims the benefit of priority to O'Byrne et ai., U.S. Provisional Patent Application Serial Number 62/247,552, titled "POWER INVERTER CONTROL", filed on October 28, 2015, which is hereby incorporated by reference herein in its entirety.

TECHNICAL FIELD

[ΘΘ02] This document pertains generally, but not by way of limitation, to inverters, and more particularly to techniques for a hardware-implemented inverter controller.

BACKGROUND

[ΘΘ03] Alternating current (AC) power inverters convert a direct current (DC) voltage input to one or more AC voltage outputs such as for a variety of applications including, but not limited to, motor control, solar power inverters, or uninterruptable power supplies. Conventional control of the power inverter is typically combined with the processing of the application to which the power inverter is associated. Such mingling of the application and inverter control can limit the flexibility of the power inverter. SUMMARY

[ΘΘ04] Techniques for a configurable, hardware-implemented, inverter controller are provided. In an example, a power inverter control circuit can include a configurable, hardware-implemented control loop circuit, an application interface and a configui'ation register. The hardware-implemented nature of the inverter controller can allow for more interface flexibility, more tightly coupled feedback, and high bandwidth while allowing ancillary processors to extract status and diagnostic information without burdening the inverter switch timing control or the acquisition of raw feedback information. [0005] In an example, the configurable, hardware-implemented control loop circuit can include a pulse width modulation (PWM) circuit configured to provide gate drive signals to an off-chip power inverter stage, a digital filter circuit configured to provide feedback information of the inverter, and a sequencer circuit configured to receive an external synchronization signal and to provide first timing signals to the PWM and second timing signals to sample feedback data for generating the feedback information. The application interface can be configured to recei ve command instructions and to provide a set point of the control loop circuit based on the command instructions. The configuration register ca be coupled to the PWM, the digital filter circuit and the sequence circuit, and a value of the configuration register configures operation of the configurable, hardware-implemented control loop circuit. In certain examples, the configurable, hardware-implemented control loop circuit, the application interface and the configuration register are collocated within a single integrated circuit packager within a single integrated circuit die.

[0006] This summar ' is intended to provide an overview of subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the present subject matter. The detailed description is included to provide further information about the present patent application.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. I illustrates generally an example of a power inverter.

[0008] FIG. 2 illustrates generally an alternative example architecture for a power inverter system.

[0009] FIGS. 3A-3C illustrate generally an example current sensing circuit and methods for inverter feedback control.

[0010] FIG. 4 illustrates generally an example inverter system for a motor.

[0011] FIG. 5 illustrates generally an example inverter system for a motor.

[0012] FIG. 6 illustrates generally a detailed breakout of a system including an example configurable, hardware-implemented, inverter control circuit according to the present subject matter. DETAILED DESCRIPTION

[0013] An approach to a motor drive AC inverter system is shown in FIG, 1 below. The system can include a power inverter stage 101, a control stage 102, a motor 107, a motor feedback device 108, such as a tachometer, resoiver, or encoder, and an optional motor feedback interface such as a position interface 109, The power inverter stage 101 can include inverter transistors 110, a gate driver circuit 103 to drive the inverter transistors 110, and an inverter feedback circuit 104, The inverter transistors 110 can receive DC power from a DC supply bus and can provide AC - type power to the motor 107. The inverter feedback circuit 104 can receive inverter information from one or more sensors such as to provide feedback to an inverter control circuit 111. Some examples of sensors that can provide information to the inverter feedback circuit 104 can include one or more current or temperature sensors coupled to the inverter transistors 110,

[0014] The inverter control 111 can include one or several functional circuits to manage power flow from the inverter stage 101 to the motor 107. In certain examples, power flow can be achieved by precision control of motor shaft torque, motor shaft velocity, or motor shaft position, shaft torque, speed, or position according to the user command. Examples of precision control can include controlling timing of one or more gate driver signals, such as based on inverter feedback information or motor feedback position. The application control 112 can include one or more high-level motion command functions or simply managing start up sequencing or fault handling.

[0015] In certain systems, an inverter control 1 1 1 can use mixed signals and ASIC circuits for signal and network interfaces and standard data processing for motor and application control functions. The combined system hardware can include a mixed-signal, application-specific-signal-processor (ASSP), a standalone ADC combined with an ASIC/FPGA, a processor circuit, or any combination thereof.

[0016] Certain approaches to high performance motor drive systems 100 can employ an inverter or power stage 101 and a separate control stage 102 such as shown in FIG. 1. The power inverter stage can be 'driven and sensed' such that the gate dri ve control synchronization signals or PWM originates on the control stage 102, while sensed signals such as current and voltage are fed back to the control stage 102 either as analog signals from isolated sensors or as digital signals from an ADC on the power stage 101 and sent to the control stage 102 as digital samples. Such a configuration can necessitate a gate driver 103 and feedback signal interface 104 between the control stage 102 and power inverter stage 101. The control stage 102, in this approach, handles both the in v erter control processing in addition to the system and application level processing. Such a control scheme can depend on highly integrated roadmaps from the control stage processor vendor. As sensing needs increase and become more complex, the integrated roadmaps may not encompass a variety of application needs such as scalability and modularization. In addition, the location of the safer}' isolation barrier 106 in the example of FIG. 1 can require the use of multiple high voltage isolation circuits between the power inverter stage and the inverter control circuits.

[ΘΘ17] FIG. 2 illustrates generally an alternative example architecture for a power inverter system 200 such as can include a division of inverter control functions from the application control functions that can allow for a more convenient interface 205 across a newly defined safety isolation barrier 206. In certain examples, the power inverter system 200 can include a power inverter stage 201, an application control stage 202, a motor 207, optional motor feedback device 208, and an optional motor feedback interface 209. In certain examples, a configurable, hardware-implemented inverter loop circuit 211 of the power inverter stage, or inverter control circuits, can be partitioned with more 'intelligence' on the power inverter stage 20 ! . In certain examples, the additional hardware-based intelligence on the power inverter stage 201 can include inverter synchronization and inverter feedback data pre-processing circuits or functions. In some examples, the additional intelligence can include control function to close a control loop between the inverter stage 201 and the motor 207 based on application information, such as target information, received from the application control stage 202.

[0018] In the example of FIG. 2, compared to conventional architectures, the application control circuits 212 can be relieved of some of the inverter control functions and can focus more processing power on the application processing. The isolation barrier 206 is now located between the inverter control 211 and application control circuits 212 and can limit the number of voltage isolation circuits to, for example, one isolated communication interface 205. Such reduction of isolation circuits can reduce production, integration and

maintenance costs via reduced interface complexity and can allow for a more robust system.

[0019] In certain motor control applications, the simplified interface 205 can eliminate the motor control ASSP to interface to the power inverter stage 201 , which can allow greater flexibility in the choice of control processor. The result is a more scalable intelligent power stage, where the cyclical measurement processes are decoupled from the application level processing on the control stage. This is an important requirement for industrial drive manufacturers who scale drive system functionality according to end application needs.

[0020] The typical switching frequency of the power inverters used in motor drives and other DC-to-AC applications is relatively high when compared to the roll off frequency of the electrical circuit. Frequency selection can look to balance higher dynamic performance with minimal switching losses. A consequence of this balancing can result in substantial residual ripple in the inverter output currents. Such ripples can compromise accurate current sensing. In certain examples, separating some of the inverter control processing to the power inverter stage can better accommodate synchronizing the inverter current sampling with the mid-point of the inverter PWM waveform. Such alignment can provide better average current sampling without requiring complex circuitry to reject the residual ripple.

[0021] FIGS. 3A-3C illustrate generally an example current sensing circuit 320 and methods for inverter feedback control. In FIG. 3 A, the current sensing circuit 320 can include a current sensor 321, an input filter 322, and analog-to- digital converter 323 and one or more optional output filters 324. Current sampling systems for inverter feedback control can include an input filter 322 in front of the analog-to-digital converter (ADC) 323 to prevent aliasing. The output filters 324 can be used on the output of the ADC 323 to provide further signal conditioning. In certain examples of the present subject matter, the sample rate information (t_s) of the ADC 323 ca match the PWM switching frequency. In such examples, filtering ahead of the feedback control algorithm need not be used since the sample reflects the average current value over the PWM cycle. In some examples, an oversampling converter can be combined with an output filter to provide inverter feedback information including, for example, average current information.

[0022] Depending on the specifi c type of ADC architecture used, the sampling instance can vary. For example, in the case of a Successive

Approximation Register (SAR) ADC (FIG. 3B), the signal sampling is desired at the midpoint 325 of the PWM cycle, while in the case of a sigma-delta ADC (FIG. 3C), where the output is a combination of multiple samples 327, the digital filter read signal can align the 'center pin' of the filter response 326 with the midpoint 325 of the PWM cycle. There are inverter circuit configurations in which the current or voltage sensor placement (in the phases vs. legs, for example) can use different sample timing such as between inverter phase switching edges rather than at the midpoint of the PWM signal.

[0023] In certain examples, multiple output filters with different response characteristics 326 can extract different feedback information depending on the end use. In some examples, overload protection can use a high bandwidth current signal at a relatively low resolution while control feedback can use a signal having high resolution with a lower bandwidth. For example, overload protection should be relatively fast in detecting an actual or potential overload condition such that the system can take action to prevent damage due to the overload. Overload indication can be a simple flag in certain examples, thus low resolution. On the other hand, control feedback can easily effect process quality, For example, in motion control or web systems, precise control of acceleration, velocity, position or combinations thereof can impact quality of an end product. As these are mechanical systems, bandwidth is relatively low, however, resolution of each of the above factors can have a profound impact on process quality as well as system flexibility and robustness. In certain examples, web systems can refer to a more specific motion control system and can include, but is not limited to, paper machines, diaper machines, roll steel mills, and other manufacturing processes that once started use a continuous flow of materials. Such systems use synchronized acceleration and velocity profiles to draw material through the system. High resolution velocity and position feedback ca assist the overall control scheme for such systems. System examples that support feedback controller self-tuning or optimization can use current rate of change information. Filters can also detect waveform signatures that provide diagnostic information of the machine or load.

[0024] FIG. 4 illustrates generally an inverter system 400 for a motor 407 such as in which there is tight coupling, such as multiple interconnecting signals, between PWM timers 420, ADC 421 , sample timer circuit 422, and filters 423 such as to enable accurate synchronization of signal sampling and filtering with inverter PWM signals. The sample tinier circuit 422 can generate multiple timing signals for each element based on a single system timing synchronization signal (sync). The sample timer circuit 422 can also make use of PWM edge timing information to avoid noise generated by the inverter switching. The sequencer and interface unit 425 can manage the data flow between the converter 421, the filters 423, and the data port 426. An optional processor circuit, such as CPU 427, can be available to implement some of the more complex filter functions and can support local control loop implementations. A single port interface 426 or communication interface can simplify the interface to the control stage 402 that can implement higher level control algorithms including synchronizing the inverter control 411 , or smart front end, timing with the execution of the control algorithm.

[0025] The smart system architecture partition as illustrated in FIGS. 2, 4 and 6 can facilitate greater pre-processing on the power stage, thus enabling the adoption of faster and more fl exible sampling front ends and can allow increased sampling of more sensor nodes. Offloading such tasks can allow inverter control enhancement of existing functions or can allow the addition of diagnostic or prognostic functions for example, making use of oversampling, faster conversion times, higher channel bandwidths/ multiplexing capabilities. In certain examples, local pre-processing can enable new algorithms or improvements on existing functions by virtue of local processing and feedback loops. This can include improved feedback performance and optional extraction of other motor parameters such as winding inductance or motor back EMF.

[0026] In certain examples, the configurable, hardware-implemented inverter loop circuit 211 can include a configuration register to provide control flexibility. In certain examples, the configuration register can be used to select various combinations of control functionality. On one end of the control sophistication, the configuration can employ a select few of the hardware implemented functions such that the application controller can be burdened with closing the synchronization between the PWM and the feedback information. In such a configuration, with the exception of synchronizing the sampling of feedback information with the output switching of the PWM, nearly all the benefits of the hardware-implemented inverter control loop circuit would remain unused. Inputs to the configurable, hardware-implemented inverter loop circuit 211 can include timing command signals for the PWM and the feedback information can include current information of, for example, the motor.

[ΘΘ27] On the other end of the spectrum of control, as an example, the configuration register can be configured to allow the configurable, hardware- implemented inverter loop circuit 211 to provide current or torque control of a motor or other device. Under a current/torque loop control selection, the configurable, hardware-implemented inverter loop circuit 211 can receive a torque or current command from the application controller and the configurable, hardware-implemented inverter loop circuit 211 can maintain that current or torque at the device supplied by the inverter by using one or more hardware- implemented control loops. In certain examples, the hardware-implemented control loops can receive feedback information about the device or motor using one or more analog to digital converters. The location and type of feedback information provided to the analog-to-digital converters (ADCs) is discussed below. In certain examples, the ADCs can be collocated in an integrated circuit package with the hardware-implemented inverter loop circuit 211. In some examples, the ADCs can be collocated on the same integrated circuit die as the hardware-implemented inverter loop circuit 211.

[0028] In certain examples, the hardware-implemented inverter loop circuit 211 can include hardware-implemented proportional-integral regulators to provide an error signal indicative of a difference between the command current/torque and the current or torque detected via the feedback information provided using the ADCs. In certain examples, hardware-implemented digital filters can process the feedback information to provide an indication of the current or torque at the device. In certain examples, the digital filters can provide multiple measurements of the device current or torque. Such measurements can include raw measurements, average measurements, peak measurements, etc. [0029] In certain examples, the configuration register can be set such that the hardware-implemented inverter loop circuit 21 ! performs other control schemes including, but not limited to, field or vector control, state vector control, phase voltage control, or combination thereof. In certain examples, the combination of the application controller and the hardware-implemented inverter loop circuit 211 can be configured to provide velocity control, position control, master-slave control, etc using any one of the control schemes discussed above with respect to the hardware-implemented inverter loop circuit 21 1. In some examples, the sampling and PWM switching can be synchronized or slaved to a

synchronization signal provided, for example, by the application controller or another external source.

[0030] In certain examples, sample timers of the hardware-implemented inverter loop circuit 21 1 can synchronize feedback sampling with switching cycles of the PWM to capture a proper feedback measurement. In some examples, the feedback can be oversampled or sampled multiple times each during each pulse of the PWM to provide, for example, more precise measurements. In such an example, one or more digital filter can decimate the samples to provide the desired feedback measurement at the nominal sampling rate or the hardware-implemented inverter loop circuit 211.

[0031] Currents and voltages can be sensed in an inverter system in a variety of locations. In certain examples, average DC link current can be used for control purposes, and motor winding current can be used as a primary feedback variable in more advanced motor drive applications. Direct in-phase winding current measurement can be valuable in high performance systems. However, the winding current can be measured indirectly using a shunt in each of the lower inverter legs or with a single shunt in the DC link. Shunt signals can be referenced to the power common which can be advantageous compared to extraction of winding current from the DC link. Winding current of the DC link can require sampling to be synchronized with the PWM switching. Direct in- phase winding current measurements can be taken with any of the above current sensing techniques but the shunt resistor signals typically work better when isolated. A high common mode amplifier can provide functional isolation, however, an isolated amplifier or isolated modulator can provide additional safety isolation. While only one of the sensing options discussed above may be used for control feedback, the DC link current signal can be used as an additional backup signal for protection.

[0032] If winding current of the motor is considered as the feedback information, the digital output from an isolated modulator 604 can be connected directly to the digital filters in the smart front end I.C. as shown in FIG. 5. In such a case as this, the embedded SAR ADC can be used for housekeeping measurements. Furthermore, if the isolated modulator and gate driver functions are both safety isolated then the smart front end also provides advantages in the circuit architecture. Comparing FIG. 4 and FIG. 5, there can be a common processor even with different isolation architectures. A digital filter configured to accept data inputs from an isolating ADC such as an isolating sigma-deita modulator supports both types of architectures offering scalability across platform designs addressing a variety of power ranges. A smart front end according to the present subject matter can be used with each of the sensing options discussed above.

[0033] FIG. 6 illustrates generally a more detailed breakout of hardware implemented functions of a system 600 including a configurable hardware- implemented inverter control circuit 611 according to the present subject matter. In certain examples, the system 600 can include an application controller 612, an inverter 610, or inverter switch array, and a device for receiving power from the inverter, such as a motor 607. FIG. 6 illustrates generally the configurability of the hardware-implemented inverter control circuit 611. In certain examples, the hardware-implemented inverter control circuit 611 can include master timer or sequencer 625, one or more sampling timers 622, one or more

proportional/integral regulators 630, various transform and filter circuits 631- 636, a pulse-width modulator 620 and one or more analog-to-digital controllers 621. Although FIG. 6 illustrates a 3-phase motor 607 as the control device, other devices can be controlled with an inverter without departing from the scope of the present subject matter.

[0034] The one or more ADCs 621 can provide feedback information about the operation of the motor 607. In certain examples, certain voltage and current information about the motor 607 and the inverter 610 can provide feedback information about the operation of the motor 607. The one or more ADCs 621 and the filters or buffers 634 can provide digital 3-phase current information about motor operation. A hardware implemented transform operation, such as a Clarke transform or a αβθ transform circuit 635 can receive the 3-phase current information (i_u. i_v, iw) and provide 2-phase stationary, current information (i_a, ip). A hardware-implemented rotational coordinate transform circuit 636 can receive the 2-phase, stationary, current information (i_G, is) and provide rotational coordinate current information (id, iq) indicative of actual motor operation.

[0035] The one or more PI regulators 630 can receive the rotational coordinate current information (id, iq) and compare it to target current/torque information provided from the application controller 612. In certain examples, the one or more PI regulators 630 can provide rotation voltage values (Vd, Vq) indicative of the error between the target current/torque information and the actual rotational coordinate current information (id, iq) using the comparison of the receive the rotational coordinate current information (id, iq) and the target current/torque information. A hardware-implemented fixed transform circuit 631 can receive the rotation voltage values (Vd, Vq) and provide stationary 2- phase voltage values (v_a, vp). A hardware-implemented 2-phase to 3-phase transform circuit 632 can receive the stationary 2-phase voltage values (va, vp) and provide 3-phase voltage information (V_a, Vt>, V_c). A hardware-implemented space-vector PWM transformation circuit 633 can receive the 3-phase voltage information and can provide modulation information (T_a, Tt>, TV) for the PWM circuit 620.

[ΘΘ36] In certain examples, the configurable hardware-implemented inverter control circuit oi l can include a configuration register 640 or circuit. The configuration register 640 can allow the configurable hardware-implemented inverter control circuit 61 1 to be configured for various application controllers. In certain examples, the configuration register 640 can allow certain hardware- implemented control functions to be enabled, disabled or by-passed. For example, the configurable hardware-implemented inverter control circuit 611 can be configured to operate in a current or torque mode 650 by enabling each of the hardware-implemented functions 630-636 discussed above.

[0037] In some examples, the configuration register 640 can be programmed, for example via a communication interface 626, to by-pass, disable or reconfigure the PI regulators 630 to provide a vector control interface such as a d-q vector control interface 651 in which the application controller 612 provides complex staior voltage space vector information (Vci, Vq) and receives feedback information in the form of complex current space vector information (id, iq). in certain examples, the configuration register 640 can be programmed to by-pass or disable the hardware-implemented fixed and rotation transforms (631, 636) to provide a α-β vector control interface 652 in which the application controller 640 can provide rotating complex stator voltage space vector information (va, vp) and receives feedback information in the form of rotating complex current space vector information (i_a, ip). In some examples, the configuration register 640 can be programmed to by-pass or disable the hardware implemented α-β transforms 632, 635, sometimes referred as Clarke transforms, to provide a 3 -phase space vector control interface 653 in which the application controller 640 provides a three-phase voltage space vector information (Va, Vt>, Vc) and receives feedback information in the form of 3-phase current information (i_a, ib. ic). In some examples, the configuration register 640 can be programmed to by-pass or disable most of the hardware implemented control functions 630-636 and provide a raw data interface 654 in which the application controller 640 provides PWM command information (T₃, Tt>, T_c) for the PWM circuit 620 and receives raw current information from the s stem ADCs 621.

[0038] In certain examples, the configurable hardware-implemented inverter control circuit 611 can receive voltage information, current information, or both voltage and current information, related to the operation of the inverter, or inverter switches 610, from one or more analog-to-digital converters 621. In some examples, the configurable hardware-implemented inverter control circuit 611 can include the ADCs 621. In certain examples, the configurable hardware- implemented inverter control circuit 611 can optionally include a hardware- implemented a decimation filter such as a cardinal sine (sine) decimation filter 655, to decimate information received from, for example, a delta-sigma ADC. As discussed above, other types of ADCs can be used to provide the feedback information to the configurable hardware-implemented inverter control circuit 611.

[0039] In certain examples, the configurable hardware-implemented inverter control circuit 611 can include an optional encoder interface 656. In certain examples, the encoder interface 656 can provide position information (Θ) indicative of, for example, the position of the rotor of the motor 607. The position information can be passed to the application controller, for example, to close a position loop that includes the motor. In some examples, the

configurable hardware-implemented inverter control circuit 611 can use the position information to assist with field control of the motor 607. In certain examples, the encoder interface 656 can receive raw position information from an external encoder 608 coupled to the motor 607. In some examples, the encoder interface 656 can receive over sampled phase current information from the ADCs 621 and can provide the position information based on for example, phase current slopes during null phases associated with the operation of the inverter switches 610 and the motor 607.

[0040] In any of the aforementioned use cases, pre-processed ADC data, in the form of information, will avoid bandwidth consumption by a large volume of unprocessed raw data samples. A suite of integrated circuit (IC) solutions with increasing levels of digital intelligence can naturally align with the interface considerations between the power stage and control stage. Furthermore, preprocessing of information closer to the power stage facilitates the overall industry need for extracting more information (e.g. prognostic) from more sensor nodes as part of the Industry 4.0 desire to communicate more information upstream directly to the application controller such at a programmable logic control (PLC) level, or indeed cloud level. An intelligent inverter stage according to the present subject matter also supports a need for modularization within distributed systems. In certain examples, there may also be potential for greater functional safet ' realization.

Additional Motes

[0041] In Example 1, a power inverter system, such as used in motor drives, in which the PWM circuit generating the gate drive control signals for the power inverter stage and the inverter sampling and feedback signals can be

synchronized and can be local to that inverter stage. The resulting inverter samples can be pre-processed locally and the output data or processed signal information, can be transmitted to a control stage such as via an interface that may or may not be isolated.

[0042] In Example 2, the apparatus of Example 1 and optionally a full motor control algorithm can be executed on the controi stage. [0043] In Example 3, the apparatus of Example 1 and optionally a part of the motor control algorithm can be executed on the power stage while the remainder can be executed on the control stage.

[0044] In Example 4, any one or more of Examples 1-3, and optionally analog inverter signals can come from multiple sources and can be

simultaneously sampled or multiplexed.

[004S] In Example 5, any one or more of Examples 1-4 and optionally, if the inverter samples can be pre-processed on the power stage, the frequency of an ADC sample rate can be much higher than that of the resulting communications link/ interface to the control stage to communicate those pre-processed results. 10046] In Example 6, any one or more of Examples 1-5 and optionally inverter sample data and/or pre-processed information can be transmitted across the interface to the control stage in the same system for different destinations such as the PLC or cloud.

[0047] In Example 7, any one or more of Examples 1-6 and optionally local fast loops can be closed directly on the power stage without passing through the control stage based on processed signal information, for example threshold indicators.

[0048] In Example 8, any one or more of Examples 1-7 and optionally the apparatus can be constructed using discrete elements on the power stage, or any combination of those elements can be integrated in a single device.

[0049] In Example 9, the apparatus of any one or more of Examples 1-8 and optionally relatively fast ADC sampling rates in an integrated solution can enable motor control algorithm enhancement or new algorithms related to diagnostics and/or prognostics for example. This facilitates extracting more information (e.g. prognostic) from more sensor nodes such as to communicate more information upstream directly to the PLC level, or indeed cloud level.

[0050] In Example 10, a smart front end architecture or I.C. product according any one of apparatus examples 1-9 can also be used in the case of leg- shunt sampling.

[0051] In Example 1 1, a smart front end architecture or I.C. product according any one of apparatus examples 1-10 also be used in the case of a multi-axis power stage. [0052] In Example 12, a smart front end architecture or I.C. product according any one of apparatus examples 1 -1 1 can control other ac inverter applications such as PV inverters, UPS and other ac line interfaces. In UPS systems that need higher sample rates, there are more benefits in offloading functions from the main processor.

[0053] In Example 13, a smart front end architecture or I.C. product according any one of apparatus examples 1-12 can improve upon traditional solutions in the context of architectural improvements, increased robustness, more flexible vendor choice, reduced BOM cost, scalability of designs, supporting modularization and potentially reducing development costs in the following ways:

[0054] In Example 14, a smart front end architecture or I.C. product according any one of apparatus examples 1-13 can optionally include PWM generation with synchronized inverter measurements and associated pre- processing can be offloaded from the processor(s) on the control stage.

[ΘΘ55] In Example 15, a smart front end architecture or I.C. product according any one of apparatus examples 1-14 can optionally eliminate a motor or inverter control ASSP to interface to the power inverter, which can allow greater flexibility in the choice of system processor. This can provide a more scalable intelligent power stage, where the cyclical measurement processes are decoupled from the application level processing on the control stage. This can be hepful for industrial drive manufacturers that scale drive system functionality according to end application needs.

[0056] In Example 6, a smart front end architecture or I.C. product according any one of apparatus examples 1-15 can optionally include flexibility of processor vendor choice that can result in less dependence on integrated processor vendor roadmaps.

[ΘΘ57] In Examples 17, a smart front end architecture or I.C. product according any one of apparatus examples 1-16 can optionally enable a reduction to one simple interface such as standard serial, parallel , or LVDS. Ethernet or Ethernet according to an industrial protocol can also be used.

[0058] In Examples 18, a smart front end architecture or I.C. product according any one of apparatus examples 1-17 can optionally include a simpler interface to allow for safely isolation requirements to be condensed to this singular point,

[0059] In Examples 19, a smart front end architecture or I.C. product according any one of apparatus examples 1-18 can optionally include pre- processing on the power board to provide less bandwidth restrictions on the interface to the control board.

[0060] In Examples 20, a smart front end architecture or I.C. product according any one of apparatus examples 1-19 can optionally include a simpler interface with fewer lines and less activity (less traffic) to enable a more robust interface to be developed.

[0061] In Examples 21, a smart front end architecture or I.C. product according any one of apparatus examples 1-20 can optionally include PWM generation with synchronized inverter measurements and associated preprocessing on the power stage to allow for fast loops to be closed locally such as alarms, threshold trips etc.

[ΘΘ62] In Example 22, a smart front end architecture or I.C. product according any one of apparatus examples 1-21 can optionally include a more intelligent power stage to enhance scalability and support modularization in platform designs.

[0063] In Example 23, the smart architecture can also be applied to a multi- axis power stage.

[0064] In Example 24, a smart front end architecture or I.C. product according any one of apparatus examples 1 -23 can optionally include the ability to oversample and pre-process measurement data can allow for additional performance improvements through primary (e.g. motor control) algorithm enhancement including improved feedback performance and possible extraction of motor parameters such as winding inductance or motor back EMF.

[0065] In Examples 25, a smart front end architecture or I.C. product according any one of apparatus examples 1-24 optionally includes The ability to oversample and pre-process measurement data can allow for additional system information such as diagnostic and prognostics functions, (e.g. machine vibration, bearing wear) potentially leading to increased end service value. This facilitates the overall industry trend towards extracting more information (e.g. prognostic) from more sensor nodes such as to communicate more information upstream directly to the PLC level, or indeed cloud level.

[0066] Example 26 can include, or can optionally be combined with any portion or combination of any portions of any one or more of Examples 1 through 25 to include, subject matter that can include means for performing any one or more of the functions of Examples 1 through 25, or a machine-readable medium including instructions that, when performed by a machine, cause the machine to perform any one or more of the functions of Examples 1 through 25.

[0067] Each of these non-limiting examples can stand on its own, or can be combined in various permutations or combinations with one or more of the other examples.

[0068] The above detailed description includes references to the

accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as "examples." Such examples can include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein. The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as "examples." Such examples can include elements in addition to those shown or described.

However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shows or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein. [0069] In the event of inconsistent usages between this document and any documents so incorporated by reference, the usage in this document controls.

[0070] In this document, the terms "a" or "an" are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of "at least one" or "one or more." In this document, the term "or" is used to refer to a nonexclusive or, such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise indicated. In this document, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein." Also, in the following claims, the terms "including" and "comprising" are open-ended, that is, a system, device, article, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

[0071] Method examples described herein may be machine or computer- implemented at least in part. Some examples may include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods may include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code may include computer readable instructions for performing various methods. The code may form portions of computer program products. Further, in an example, the code may be tangibly stored on one or more volatile, non- transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.

[0072] The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. § 1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than ail features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description as examples or embodiments, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments can be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

What is claimed is: 1. A power inverter control circuit comprising:

a configurable, hardware-implemented control loop circuit, the configurable, hardware-implemented control loop circuit including:

a pulse width modulation (PWM) circuit configured to provide gate drive signals to an off-chip power inverter stage; a digital filter circuit configured to provide feedback information of the inverter; and

a sequencer circuit configured to receive an external synchronization signal and to provide first timing signals to the PWM and second timing signals to sample feedback data for generating the feedback information;

an application interface configured to receive command instructions and to provide a setpoint of the control loop circuit based on the comman d instructions;

a configuration register coupled to the PWM, the digital filter circuit and the sequence circuit, wherein a value of the configuration register configures operation of the configurable, hard ware-impl emented control loop circuit control loop circuit; and

wherein the configurable, hardware-implemented control loop circuit, the application interface and the configuration register are collocated within a single integrated circuit package.

2, The power inverter control circuit of claim 1, wherein the second timing signal s are configured to sample the feedback data at a higher rate than the first timing signals to provide over-sampled feedback information.

3. The power inverter control circuit of claim 1 , wherein the digital filter is configured to decimate the oversampied feedback information to provide the feedback information.

4. The power inverter control circuit of claim 1, wherein the configurable, hardware-implemented control loop circuit, the application interface and the configuration register are collocated on a single integrated circuit die.

5. The power inverter control circuit of claim 1, including an analog-to- digital converter (ADC) configured to receive analog feedback data and provide the feedback data; and wherein the ADC is collocated within the single integrated circuit package.

6. The power inverter control circuit of claim 5, wherein the ADC includes a Successive Approximation Register ADC configured to sample the feedback at a midpoint of a PWM.

7. The power inverter control circuit of claim 5, wherein the ADC includes a delta-sigma ADC.

8. The power inverter control circuit of claim 5, wherein the configurable, hardware-implemented control loop circuit, the application interface, the configuration register and the ADC are collocated on a single integrated circuit die.

9. The power inverter control circuit of claim 1, wherein the application interface is configured to provide at least one of the feedback data, the feedback information or the over-sampled feedback information.

10. The power inverter control circuit of claim 9, wherein the command information includes current set point information,

11. The power inverter control circuit of claim 9, wherein the command information includes vector control set point information.

12. The power inverter control circuit of claim 9, wherein the command information includes space-vector control set point information.

13. The power inverter control circuit of claim 9, wherein the command information includes voltage set point information.

14. The power inverter control circuit of claim 9, wherein the command information includes PWM set point information.

15. The power inverter control circuit of claim 1, including a position decoder configured to receive encoder signals and provide position information related to a device controlled by the power inverter control circuit.

16. The inverter control of claim 15, wherein the position decoder is collocated within the single integrated circuit package.

17. The inverter control of claim 15, wherein the configurable, hardware- implemented control loop circuit, the application interface, the configuration register and the position decoder are collocated on a single integrated circuit die.

18. The inverter control of claim 15, wherein the position decoder includes a quadrature encoder pulse detector.

19. The inverter control of claim 15, wherein the position decoder includes a absolute encoder pulse detector.

20. A system comprising:

a DC supply:

a multiple phase device;

an inverter configured to receive the DC supply and to provide power to the multiple phase motor; and

wherein the inverter includes :

a switch array coupled between the DC supply and the multiple phase device and configured to receive gate drive signals and to convert the DC supply to multiple phase power for the multiple phase device based on the gate drive signals; a power inverter control circuit, the power inverter control circuit icluding:

a pulse width modulation (PWM) circuit configured to provide gate drive signals to an off- chip power inverter stage;

a digital filter circuit configured to provide feedback information of the inverter; and

a sequencer circuit configured to receive an external synchronization signal and to provide first timing signals to the PWM and second timing signals to sample digital feedback data for generating the feedback information;

an application interface configured to receive command instructions and to provide a setpoint of the control loop circuit based on the command instructions;

a configuration register coupled to the PWM, the digital filter circuit and the sequence circuit, wherein a value of the configuration register configures operation of the configurable, hardware-implemented control loop circuit; and

wherein the configurable, hardware-implemented control loop circuit, the application interface and the configuration register are collocated within a single integrated circuit package; and

n analog-to-digital converter (ADC) to receive analog feedback data of :h array and to provide the digital feedback data;.