WO2017074593A1 - Esd protection circuit with two discharge time periods - Google Patents

Abstract

An electrostatic discharge protection circuit may include discharge path circuitry to discharge charge on a supply line in response to detection of an ESD event. The charge on the supply fine may be discharged through the discharge path circuitry from when a first timing window opens until a second timing window closes. The first timing window may also be used to detect ESD events. The two timing windows may allow an initial period of the ESD voltage on the supply line to be suppressed before the second timing window opens, and may further allow a remaining period of the ESD event following the initial period to be suppressed after the first timing window closes.

Description

ESD PROTECTION CIRCUITS WITH TWO DISCHARGE TIME PERIODS

BACKGROUND

fiMM IJ Electrostatic discharge (ESD) eve ts may involve a sodden. How of electricity between two electrically char ed objects earned by contact, m electrics! short, or a dielectric b ckdown. When an ESD event occurs, art accumulation of charge from the s-ndden flow of electricity niay generate an BSD voltage that may peak at a relatively high level., which may cause damage to ekctonie eireints. Electronic devi s may include BSD protection drc-uilry to protect against the harmful effects of ESD events,

|ΐΜΜί2| Some ESD protection circuits may protect against ESD e ents by disc-harging charge generated during m ESD event is order to suppress She ESD vo!lage to sale levels, in addition, some ESD protection circuits ros ut lise a timing window to initially detect an ESD e vent., The timing wi ndow may e relatively s-ho t so that the BSD pr tecti n circuit can differentiate an. ESD event fwm other transient events that do not change as ra dl and thai should not he suppressed. A tinting window may also be used to determine how long the ESD protection circuitry is to disc^'harge charge if an ESD event is detected. The timing wi d w used for detection a be too small to set the duration of discharge. At the same rime, using additional eb¾n!try to set a sec nd timing indow tor discharge ay requite a delay between detection md dischar e, which in t rn may cause an initial portion of the ESD voltage to be inadequately suppressed since ESD events happen so quickly. BSD protection eirettitry that adequately suppresses ESD voltage as early as possible sad o er as long of a doretkin of the BSD e ent as possible may foe desirable.

BRIEF DESCRIPTION OF TiM DRA I GS

|WwSJ The accompanying drawings, which are incorporated in and constitute a part of this specification tll»sttate various aspect of the invention and together with the description. serve to explain sis principles. W erever conven e t, the- same reference mtm ers will he us d throug ut the dra ings to refer to he same or like elements.

[00041 Figure I. is a block diagram of art example electrostatic discharge protection circuit coupled to a supply line.

[0005] Figure 2 is a csrcalt schematic of m example circuit eo lgoration of the electrostatic dischar e protection circuit of Figure 1 ,

[00061 Fi ure 3 is a .flow chart of an exam le method ofm electrostatic discharge pmtectkw* dra. t suppressing a oltage generated on a suppl line in response to a«

electrostatic dtseiiarp e ent

[0O07| Figure 4 is a block diagram of another example electrostatic discharge rotecti n circuit coupled to a supply line.

[0008| Figure 5 is a circtfit sche atic of tm e am le circuit coafigeratka* of the dectrostatie discharge protection^" circuit of Figure 4,

|iMW9| Figure 6 is a flow chart of another example method of an electrostatic discha ge ro ection ci cuit suppressing a voltage generated en a supply line in r spon e to an electrostatic discbarge event,

DETAILED BESCMPTIO OF THE PRESENTLY PREFERRED EMBODIMENTS

[00191 Overview

[001 ij By ay of introduct on, the below embodiments relate to electrostatic discharge (ESD) protection circuits thai uses too time periods or timing windows to discharge charge when mi ESP event occurs. In a first ex mple e bodiment, an electrostatic discharge (BSD) protect on circ it tmy include discharge pa circuitry coupled to a supply line mid a ground ^•reierence, a detection circuit. m4 activation circuitry,. The d tecti n circuit maybe configured, to detect an ESD event oceumBg ou th s pl line, aud generate a detection voltage above a detection level for a fet time period in response to detection of the ESD event The aetivatiors circuitry, hen aetiva.e4_> ^3my be e niigu to easse the discharge path circuitry to discharge c arge he supply line to the gro sRd r icmice,. w ere he activation circuitry s configured to he activa ed for she fmi tims period and a secoad ime period that ends after the first thne period e»ds,

[0012.J In sosse example embodiments., the discharge path circuitry ma include a first discharge path circuit and a seeottd discharge path circuit. The activation dn»ti4r mmy i»cJ«de a first aetivaiioti circuit a«d a seeoad activatioe circuit. When the detection circuit detects the ESI) e ent the firs acts v k droit ma be configured to enerat an activation volt ge at activation level to cause the first discharge- path circuit to discharge charge and to activate the second activation circw.it for the firs:!; ime period, Ja add an, when the second activatioa circuit is activated, the se ond ac-tlvaikm circuit ma be configured to ca se the secon discharge pad* circuit to discharge charge for the second time period.

IM13J In some exam le embodsteents, the first discharge path circuit ma mdade a fi st transistor and the second aciivstuits drcuit may include a secoad transistor. The aefivation veitage at the activation le el ma turn on each of the first transistor to cause the first discharge path to discharge charge a d the s cond traa&istor io activate the second, activation circuit

(0O14| its sotae sssnrple embodi ents, the second aetrvMtem circuit may further iaekde a node connected to the second trans stor, The first activation eiresii rrsay further he configured to generate the activai oa voltage below the activation level w en the first time eriod expires. The first and secoad transistors ma he configured to turn off in respoase to the activation- voltage beiag generated beio-w rite activation level, and whew the second transistor tu ns off, a voltage generated at the -node may cause the second dfeciiarp path to discharge charge for the second time period- fWISf fa some exam le embodiments, fe voltage generated at the node may c use foe second dischar e pafo to be deactivated u on expirarJo« of e seooiki mm period,

Θ ί.61 In some example mlw&nseists,. the first activation, circuit may be configured to begin oaussiag the first discharge path cir uit to discharge charge before the secoad activation mtm k configured to begin causing the second discharge path to discharge charge.

|^'θβ17| la some example bod tm, the activate* circuitry may include a first activation circuit,, a sec d acttvatio« eiradi, and a third activation circuit When the dete tion circuit generates the detection voltage above the detection, level, the third activation eireifo stay be corstlg»red to cause the discha ge path circuitry to discharge charge for the first time period, the firs? activation circuit may be configured i& activate the second activatioa circuit, and the second activate* circ i , aspon being activated, wa be configured to cause the discharge path cicuitry to discharge charge for foe second tee period.

|§0IS| la some example esifosilteents, the third activation circuit, upon behig activated, ma be c nfigu ed to pneraie an activation vol age at an activate* level «a a n de to cause foe diseaarge path circuitry to diseharge charge. In addition, foe second activation circuit, upon being activated, amy be configured to enerate the activatioa voltag at the activatioa level oa the node to cause the discharge path circuitry to discharge the charge.

(0019! ^ soaae example embo iment^ the second activation circuit may be configured to maint in the acti ation voltage on the node at the activation ieve! undl the second ime period ends when the first time period ends and the third activatioa circuit is no longer configured to generate foe activation voltage at the activatioa level_*

[ΘΟ20) fa some example embodiments, the third activation circuit may include a fi st transistor to pull up foe activation vol tags oa foe node, fa addition, foe second activation circoi may Inclu e a sec nd traas¾t«r configured to turn, off when foe detection circuit generates t e defection voltage above foe detection level, When turned o.f¾ the second transistor may prevent a third

second activation circuit front pulling down the activation voltage ©n the node,

[0021J in soa¾e example

the n de a fmt node, and Hie detect on circuit ma be configured to generate the detection voltage between a second node and the supply line. The first transistor and She second transistor may each have a terminal eonplsd to the second node,

[ 0221 Jn a second example embo iments* m electrostatic discharge (BSD) protection circuit may include a first discharge path and a second d scharge path, each configured to, hen activated, ischarge charge ccumulate on a sup l line to a ground reference, The BSD protection circuit ma further inchide a detection ei«¾it configured to generate a detection olta e above a detection le el in .response to detection of an BSD event on the sup l line. The BSD protection dretiit may also include activation circuitry comprising a fmt activation ci cu t and a .secon activation circuit. The first activation drettit may be configured to be activated when the detecti n circuit generates the detection voltage above the detection level When activated,, the first a tivation c rcu ty may be configured to generate a .first activation voltage at. a first activation level to activate each, of the .first discharge path sod the sec n activation circuit. In addition, the second activation circuit, ^•upon being activated, may be configured to generate a second aetivatioft voltage at a second activation level to activate the second discharge path.

[0023_.1 in some example embod ments,, the first activation circuit may be configured to generate the first activation voltage at the first activation level during a timing win o . [Θ024Ί In some example embodiments, the detection circuit trmy include a resistor and a capacitor. A duration of the timing incEo may be based on a resistance of the resistor and a capacitance of the capacitor. fWiSl Jn some example e¾sh ^ ents, fee detection circnii may he configured to generate he detection voltage to deactivate the t½t actuation circntt wk¾ the timing window cioses. Tie first activation c rcnsi, u on being deactivated, may e configured to generate he first activation vol Sags at a deactivation level sad ro ide the first activation ol age at the deactivation level to each of - e ilrst discbarge path and the second activation drettit, A o, lie fet discharge .path ma be configured to be eacti ated lit response to receipt of the .first activation ltage at the deactivation level,. Farthe , the second aetivatton eiretiit ma be configured to emote activated to acti ate the second d scharge path for a time ^•period m spm to receipt of the second activation voltage at the deactivation ievel

|ΘΘ26| In some exam l embodiments,, the second activation circuit may include a resistor coanecte in parallel mih a capacitor. A deration of the time period thai the second activation circuit is coeflgwed to re ain ac ivated may depend on a t st x of the resistor a»d a cagmdtance of the capacitor.

§tt27J la some &mpte bodkx , me Srst dischar e path tmy kdnde a first transistor having a first gate width and the second discharge path may include a second transistor havin a second gate width. A ratio of the second width to a sum of the first gate width and the second gate width may correspond to a p rcentage in a range of between 70*· 80%.

(002$) in a third exam le embodiment,, a raet&od of responding to an eieetrostetk discharge ( SO) event may be performed. The method may include: generating, with a first activate* circuit, a first acti vation voltage to cause discharge path circuitry to discharge cha ge on a supply line in order to sup r ss m ESD voltage for a first t me period:

generating, with a second activation circnit,. a second act vation voltage to cause the

discharge path ci cuitry to discharge charge the sup ly line in order to suppress the BSD voltage for a second time period: and in res nse to generatin the first and second, activation. voltages discharging, with the disc arge path circuitry, charge or* the supply fine from a beginning of the f t t me period, to m end of the second im period

In s me example mt*> ¾ieot¾. the method may include; a l ing, with- the first aclivation circuit, the first activation voltage to a first discharge path of the discharge path eiresJtry to eawse- the .first discharge path to discharge charge tor the first time period; and applying, with the second activation circuit, the sec nd activation voltage to a seco&d discharge path of the discharge path circuitry t cause the second discharge path to d scharge charge for the secoad time period,

(@0 | to s me example embodiments, the discharge path eirenitry may include a single discharge path., where generating the second a ivate voltage may nclude generating, with tie second activate, circuit, the sec nd activate voltage on a same node on which the first activation voltage is generated The met o ma further include mainte ng, with lit© seeontl activation circuit app&ation of the seeortd activation voltage ? the node after the t^'mt lime period expires nntil the cad of the second time period

[$031 J Other embodi ents are possible, and each of the embodiments can be ased alone or together in combination. Accordingly, various mbodiment will now be described with .reference to the attached drawings.

[0032J scBgj jg _:¾ dljjg|¾

|§033| The present description describes electrostatic discharge (BSD) protection circuits and related methods for suppressing an BSD voltage generated on a snpply line as a result of an iSD event. The supply line ma be configured to supply a supply voltage fr m a supply voltage source device to a supply voltage deputation de ice. The sup ly voltage tnay be used to power electronic com nents of the supply destination device.

|MM| In general, an ESF> event may be a sadden flow of electricity between two electrically charged objects aused by contact, n electrics! short, or a dielectric breakdown, When m ESD event occurs on the supply lias, m aceumakti n of charge from the sudden f ow of electricity may generate an BSD voltage on the supply line hat may pe k a » relatively high level_* such as a voltage in the ov lt <fcV) range. S¾ch a high voltage level may cause damage to the su ply voltage host sod or destamiioti devices.

|M35J The ESD proteedaa circuit may be coupled, u the supply line in order to protect the supply voltage source at¾ /©t destination devices front the high, level of the ESD voitege. The ESD ro esters, circuit wa do so by supp*em«g the ESD voltage to a a¾j¾deMly low level durmg the ESD event so that the ESD voltage does not e¾me damage to the supply voltage source m m destituti n device, la particular, the ESD protection circuit may discharge charge aecamukted during the BSD event to groustd in order to tower the level of the ESD voltage.

The ESD voltage tmy be a transient voltage m that its voltage level changes daring die BSD event However, the ESD voltage may not be the only t ansient voltage genera ed on the supply line. The supply voltage may also he a twiskot voitage, at least daring m initial po etvnp time period daring he» he level of the s«pply voltage transitions from an initial level (e.g.,, 0 V) to its final or steady-state supply level. While it may be desirable for the ESD protection circuit to suppress the ESD voltage on the supply line, it ^■tmy not he desirabl e for the BSD protection circuit to su ress trait-dent voltages that are desired to be generated m the supply line, soeh as the supply volta e during wer up. [<M ?J The ESD protection circuit may .include detection circuitry that is configured to detect as ES event and differentiate ESD events ίϊ¾» other transient events for which voltage suppression is not des i red, stsch as power u - If the detection circaitxy detects m ESD event oceumng on he sapply line, discharge eiteuitry of the ESD protection circuit may he activated m order to discharge charge on the supply line to suppress the ESD voltage_* Altenistivdy, if the detection circuitry does not detect an ESD event or detects that a

S trans ent event oeeumrag on the supply tine is not or does not exhibit the characteristics of an

ESD event, the discharge cireniiry roay r o ir} deactivated s ch that voltage sup ressi n on the suppl line does sot occur.

[00381 ESD oltages may dififer from other transient voltages on the supply line, mch m the supply volta e darin po r up, in that ts voltage level ma cha g or transition faster. Otherwise staled, tie ESD voltage ma ha e a higher ftsqaettcy d*an the other transient voltages thai are .not dotted to be sup ressed The detection ekeuttry .may be coniigured to differentiate ESD ev nts from other transient events b detecting a mie or how last a voltage level of a transient voltage on the supply Mae fa changing. If -the d tection d itiy detects thai lie vol age level of the tt&asfeal voltage Is cteg g fast eoo gh to qaatify m art ISO ltage, then Ihe discharge ekea.ft.ry ma be activated is aider to disc arg charge o» the supply line. Alternatively, if the detection circuitry detects that the voltage level o the trarssient voltage Is ©haaging to slowly to aalify as an BSD volt e thea the discharge dretitry may tmm deactivated such that voltage suj ession on the supply Urn does not occur,

(003$! ^'The detection circuitry ma use a timing window or time period io differentiate between ESD events and other «s»stent events. Transient events falling or occurring within the tiinitig window ma be identified as ESD e ents to be su r ssed, and transient eveiits raiting or occurring outside of the timing window may be identified as non-ESD transi n events that are not to he suppressed- Accordingly, the timing window ma be set long enough SO' that a» Initial, spike or rise in m ESP voltage fells or oecors wimin the timing window, fetit short enough so that the initial power-up transition of the snpply voltage falls or occurs ootside th timing window.

[0040^'! .Even thou h an Initial spike or rise in the ESD voltage m y occur within the throng window, the ESD event may still be occurring hen the timing window closes,. Sonse example BSD r tection circuits may use a second timing window during which, to discharge charge OR he supply ti < That is, these exam le BSD protection circuits w&y include » first- stage detection circuit that «tUi¾es a first timing indow to detect BSD events, an a second- stage ischarging circuit that ntilixes a second timing windo that deiena es how long the BSD protection circait discharges charge on the s¾ippi line. ^'However.,, in these example ESQ rotecti n circuits, some delay ma eiist from tte time that the detection circuitry detects ESD event to the time hat the second stags? begins diseteging charge on the supply line, .Daring ftis period of delay, the BSD voltage may rise to a potentially damagin lev©}, and t e ESD protection circuits may not be capable of t ptessisg it.

100411 The ptesewt description describes ESD protection eiretats that utilize t o erne periods to discharge charge th ough one or more discharge paths on the supply line la response to detection, of an BSD event. A first of the two ttraing windows may also be used to detect ESD events. The second timing window ma be of a swffseient duration so that it is open after the first t ming window closes. Use of the two timing windows ma allow an initial period of the ESD lt ge on the supply lime to be sup resse before the second timing w ndow opens, and may farther allow a rem ining period of the ESD event following the initial period to he sup ressed after the first timing window closes. This may allow the ESD ^•protection cireait to begin o ressin an ESD volta e as quickly as possible and for an overall longer damtion compar d to other ESD protection ciraiit c nfigurati ns thai online only a single rime period for ESD sup ressi n,

[00 21 i , I sho s a block diagram of an example ESP protection circuit ISO couple to a s p l line 102 that fa configured to supply a supply voltage front a supply voltage source device 104 to a snppiy voltag destination device 106, Example supply voltage sonree and destination de vices H , 106 may be respectively a host, system and a iK>n-volatile f»ei»ory system, where, m addition to the host and non-vo le memory system eomnswracafmg host commands and res onses related to data, sierage in the sou-volatile memo y s stem, the feast is configured to po er the nonv lat le memo s stem fey supplying the supply voltage m the supply tine 102. Other example su ply voltage sotwe md destination dev ces 104, 106 ma be p ssibl , Tftte ESD protection circuit ΊΟ0 may include ESD detection circuitry 1 ⁽M, .first activation circuitry 110, a first ischar e pail* ! 12, second activation circuitry 114, ami a second discharge th 116, As shown in Fig, 1 , each of the ESD detection circuitr 108, the first a second actuati n cits »i fry 110, 1 1 , md the fee md second discharge paths 1.12, 1 16 may be erupted to the supply rn .102 and to a grouad r ereftce G^' D,

(0043 Tlie ESD detection dratkry 168 may be eotdigursd to detec wtettet a teansicM voltage on the suppl IBC 102 occurs ttau* a Hirst iimasg window or time period, if a t ansient voltage within the l¾t ttmiitg window does occur, th n t e trnmie-nt voltage may be indicative of s ESD vt tage gen rated as a result of ESD ewat fes res oasse, the ESD detection circuitry ί 08 ma generate a voltage at a node Λ w th respect to ground that ields a detection voltage between, the supply line .192 and node A that is above a detection level The detection voltage being above the detection level ma activate the first activation eireailry ί 10, Prior to the defection, a level of the detection voltage may be below the de ectio level s«ch that the first activation circuitr 110 is deactivated

|0044J In some example e atlgyrstsom, fee ESD etection circuitry 1 QU may ^'be configured as a low ass filter or exhibit, low pass filter characteristics. If the f equenc of the imasiesl voltage is high eaough to be indicative of ESD volt ge_s. th n the low pass filter char-»terisiies of the ESD detection circuitry 108 tmy^*t«jeet" the irsasiesi voltage and generate a relatively lo voltage a node A saeh that the v ltage difference between the supply line 102 d node A is a o e: the detection level to activate the first acti ati n circuitry 1 10, Alternatively_* if the fre uenc of the traustest voltage is too slow to be indicative of an ESD voltage, then the low p ss filter characteristics of ttte ESD defe¾ts«« circuitry 108 may "pass" the frankest voltage at d generate a relatively high voltage at nod A such tha the wltag© difference between the supply tine 103 aad node A ¾ below the detection level.

|ft045J In response to being activated, the first activation circuitry ί 10 may generate a first activation voltage (relative to the groiand ref rence OND) at a node , As sho n in Fig. 1 , t e first activation voltage generated at node B may fee provided to the first dis barge path 112 ant! als to the second activation circuitry ! 14. Whe s the first activation circuitry .1 10 is activa ed In ^'res onse to the detection v lta e being generated above the detection level, the first acti ation vol tage may generate the first aetivation vol ta at a level that activates tbe first discharge path 1.2 and the second activation circuitry 4,

|oD46J Tbe first discharge path 1 2 may be config re to transshkm between an activated state and a deactivated stale. When activated (or configured in the activated state}., the fmt discharge path 1.1 may effectively operate as a short circuit and. couple tbe sup ly hoe 1 2 to the gro n referenc OND, As a result, charge ccumulate on the supply lin 102 may discharge to tbe ground reference O D via the first discharge path 112. The discharge of the charge through the first discharge path 1.12 may suppress the level of the BSD voltage on the supply line 102. Alternatively, when deactivated (or configured in the deacti vated state), the first discharge path 112 may effectively operate as an open eiresii between the supply line 1.02 and the gmimd reference GND. When configured in the deactivated state, charge acensraulated on the swpply line 1 2 ma Hot discharge to Use ground reference OND via the first discharge path l !2.

|0t⁾47f fra add ti n, wh n t e second activation circu ry 1.14 k activated, the second activation circuitry 114 may enerate » second activation voltage (relative to the g ound reference OND) at a n de C, As shown in Fig. !, the second acti ation: voltage enerated at

n node C may be provided to the second discharge palfc Similar to the first discharge path J 12, the second discharge path ! 6 may be configured to trans tion b ee ars activated, state and a deactiva ed state. When, activated (or configured in the activated state), the secon discharge path 1 16 may effectively operate as a short cir uit and couple the supply Ike i02 to the gj fid reference- 0 ^'D... As a rsm charge acewmaflated. en the supply line J 02 may discharge to the gro nd reference G^'ND via the s cond dise-h¾t¾e path 1 6, Use discharge of tlte charge through the second discharge path 116 may sup ress the level of the ESP voltage m. the supply line 102, Alternatively, when deactivated (or configured in the deactivated state), the see-ond discharge ath 1 ί 6 m y effectively operate as as open, circuit between the suppl H«e 102- and the ground referetiee GNO, When configured in the deactivated state, charge accumulated the supply line 102 may mi discharge to the grouad reference -GND vi a the sec nd discharge path. U6.

\Wmi As previousl described, the ESD detection circuitry ! 08 ma detect a ESD voltage by detecting a transient voltage o the mpply lh¾e 02 that emits within a first timing window or t me period. When sweh a ttaosimt voltage does oeenr within the first timing window, the SD detection circuitry Ϊ S may generate the detection voltage between the supp y line 102 asd node A above the detection level during the first imin window. When the first- timing window closes (i.e., the first time period expires), the detections voltage may o longer be generated above the detection level As sack, tie first activation circuitry 1.10 may be activated daring the first timing window and may then be deactivated when the fct timing window closes, in turn* the tmi discharge pa ! 1.2 may be acti vated daring the first timing window to discharge charge on the sup l line 102 to the ground reference GND, and then may be deactivated when the firs timing window closes,

|M f The secofiii activation csrenitry I ί4 may be activated daring a sec nd timing window or for a second time pe iod. In torn, during the secon tim ng window, the second discharge paih 11 6 may be activated to discharge charg e on the sup ly line 102 to the ground reference GND_> and then may be deactivated when the second timing wimdow closes, is general_* the first timing indo may be in: heibre the second iimk indow beg ns s«ch thai lite first discharge _.path. I 12 is activated arid begins ischarg ng charge on the supply line 102 to the ground refereoee 0N^'D before the second discharge path 1 16 ss activated and egins d sc a g ng charge, to addition, the seeoad iimmg window ma etasi after the first timing window ids, ch thai when the first t ding window doses an tie first dischar e path .112 stops discharging charge, the second timing in ow has not yei closed and time may still, be available during which (he second discharge path 1 16 ma discharge charge. Use of a first tinting window that opens shortly but quickly fc r BSD detection to activate the first discharge path 11.2 and a seeoad timing wiradow that stays open after the first timing window closes to activate the second discharge at i 16 ma allow the BSD otection r k ϊΰϋ to begin stspprsssmg m BSD voltage of aa ESD event s niel as possible attd to suppress the BSD voltage for m overall iooger duration compared to other ESD protec i etretnt configurations ih uiilfee only a single discharge path and/or a single time period tor ESD suppression.

[OOSOj Fig. 2 shows a circuit schematic of an exam le circuit: configuration of the ESD ^•protection eitenit 108 shown in Fig. 1. The ESD detection circuitry 108 ma include a series connection of a fi s t resistor M &ηά a first capacitor CL The first resistor 1.1 and the first capacitor CI may each, have a first end connected together at .node A. In addition, the first resistor .1 may have a second end connected to the supply Mae 1.02, and the first capacitor C^'l ma have a sseeoad end connected to the ^onad reference GND,

[ 0511 The first activation circuitry 1 10 may comprise first, inverter errantry -hat includes a first p-typa »^ί8ΐ'0χ 1^^ΐΒΚ0ϊ^ΐίβΐ0ΓΓ Μ0 ^','^') transistor PI end a first n-iype metal- oxsde-sem eoadndar ("NMO-T) transistor Nl . The first PMOS transistor PI nay include a. source- lenmaai connected to the supply lias; i )2 a d a draiti Vsrmimi eorinecisd to n de B. The first NMOS trass? stor 1 msy include a s rce terrains! connected to the ground reference OND sod a drsia terminal als c aaecte to aode B. Gate erminals ofee-cit of to© first PMOS transistor P i and the first NMOS trarssistor l ma be connected to node A. The first PMOS transistor Pi and the firs NMOS transistor ^'l ma form an Irrverter ciroiit i that w a level of the voltage at .node A corresponds to a log c low value, he first PMOS transistor PI taay be t tted m md the first NMOS tmrtsistor I may be turned off to pull νφ the voltage geae ated a oodc B to a level cortespoodiog to a gic high, value. .Alternativel , hen the level of the voltage at riode A corresponds to a logic high value, the fi st PMOS traosistor P i may be turned, off and the first NMOS itass or ^' .l may be tamed on to pull ii m the voltage nerated ai node 0 to a level eorresoosdiiag to a logic low v l e.

|W52J The first d schar e path 1 2 may include a second NMOS transistor N2 having a drain ietmmal connected to the up ly line 102 sad a source terminal connected to the giotmd reference CND. lo addition., a gate ten»iass! of the second NMOS !xsosisior N2 may be eoooected to node 8, The second NMOS taasklor M2 may be referred to as a clamp transistor since it may operate to clamp a level of voltage generated on the supply ttm 11)2 to an identi fied safe voltage level that is wot likely to cause damage to the supply voltage som¾e mdfot estmatioa devices 1 4. 1 6. lit sortie xamples, the identified safe voltage level tm be below atjd/ r correspond to a breakdown voltage level, A vol Sag above the breakdown voltage level may bum and/or cause a short in the transistor,, such as between two terminals of the irsnsiistor aad/or between a temvinaS aad the substrate,

|Θ053| The first activation v ltage generated at node B may be applied to the gate terminal of the second NMOS transistor N2. A level of the first activations voltage may etemtme whether the secood MOS transistor N2 is either turned on or turned d < Whets the second NMOS transistor N2 b taraed oa, the first disc arge path 1 12 ma he eots!lgwed

IS m the activated state- md charge the supply line 102 may flow through the second NMOS transist r N2 io the ornx! ference ONP. Alternatively, whm the sec nd NMOS transistor 2 is turned oft the first discharge path ! 12 may he emftgured in the deac i ated state md charge n the suppl I e 102 may be revented from flowing throagh the seeond NMOS transistor N2 to the ground reference GMD.

M54| The second act vation circuit I ! 4 may Mad a parallel connect!©® of a second resistor R2 and a second e¾p»dt r€2, First ends of each of the second resistor R2 and th second capacitor C2 may be connected to the supply line 102, and c nd esscJs of eac h of the secend resistor R2 arid the second eaparitor C2 may he c nnected together at a node P. («551 T¾e second activation circuit 114 m y als Inektde a third NMOS transistor N3 that has a drain terminal connected to node D and a sowce terminal connected to the ground reference GND, in addition, a gate tetm iwtt of the third NMOS iratmistor N3 may be connected to the g te terminal of the second NMOS tra sist r N2 a id the drain temhnak of the first PMOS and NMOS tanslstors PI, M node B.

(<K»56| The second activation circuit f 1 ma further include mv-erier circuitry thai ineiades a second .PMOS teansistor P2 and a fourth NMOS transistor N4. The second PMOS transistor P2 may include a sou ce terminal connected to the supply line 102 and a drain terminal connected to node C. The foarth NMOS trsnsistor N4 may include a s urce terminal connected to the ground reference GMD and a drain terminal also co nected to n de B, Gate terminals of each of the first FMOS transistor PI and the first NMOS transistor Nl may he con ec ed to de A_*

|fW57J The second discharge path 116 may include a fifth NMOS transistor N5 having a drain, terminal connected t the supply line 102 and a s urce terminal connected to the rou d reference O NP. fe addition, a gate tert ilta of the fifth NMOS transistor N5 may be connected to node C Like the second HMDS transistor 2 of the fim discharge path 1.12, the fifth MMDS transistor N5 may be referred to as a damp transistor since it may operate to clamp a level of voltage generated, on the supply Ike 102 to m. de tified safe voltage level e a breakdown, voltage level thai fa not likely to cmm damage to the supply voltage source ano¾ r destination devices 104, 106,

|ftOS¾ The second activation voltage generated at node C may be a plied to the gate te«Himi of the fifth NMOS tm tmW. A level of the second activation voltage may deiermsae whether the fifth NMOS transistor N5 k eit er lamed on or turned off When t e fifth NMOS tmnsisier S is tamed on, the second discharge path 1 16 may he configured its tits activated sta e and charge on the supply !iee 102 may Sow thmugh the fifth NMOS trassistor MS to the ground reference GND. Alternatively, when toe fifth OS terisistor N5 is tamed off, the second discharge path 1 16 may fee eonligttred m the deactivated state and charge on the supply line 102 may be pr ent d fr m flowing through the fifth NMOS transistor N5 to lie ground reference GND,

\m-S9 Prior to ESP event, a level of the detections voltage generated between the supply hoe 102 and node A (or a voltage drop across the first esisto R 1 ) may be relatively small (i,e„ below a threshold voltage of the first PMOS transferor PI) such that he first PMOS transistor Pi is tamed oil De ending on the voltage level at node A, the first NMOS transistor Ml may be either tamed on or oil In either ease., however, the level of the voltage at node B ma be sui¾ie«tly low to cause each of the second and third NMOS transis ors N2,. M3 to be turned off. With the third NMOS transistor M3 turned off the level of the voltage at node D msy be close enough to the level of the voltage on the sti f i line 1 2 such that the second PMOS transistor F2 is tamed off. In tarn, the level of the second activation voltage generated a node C may ^'be saifseiently low to eassse the fifth NMOS transistor 5 to he smed off Aeeotoi gly, prior to m ESD event* both e first &¾d the second discharge paths ! 12, 1 16 may he deacti vated, 1006 1 The series connection of ins first resistor and capacitor ^' l ,€ I m be es ons ve to a speed or fojqueney of olta e transients on the suppl line W2. When a transient vol tage fa generated, the voltage on the s p l 1i.se 02 may experience a change voltage level. However, the oapaciti ve characteristics of the fei capacitor C i may cause the chang m ol ag level of th voltage at node A to lag behind the level change on the supply line 102, which to turn may use an. irserease in the level of the detection oltage generated between the supply tine 2 sod node A, Mathematically,, the detection voltage generated between the supply line 102 and n d A ma correspond to a derivative of the transient voltage. As sock the faster or higher In frequ nc that the transient voltage is. th latte an initial level of the detection voltage is generate when the transient voltage initially occurs. Hereafter, the first capacitor CI ma begi to charge, causing the voltage level of the voltage at node A to increas and the detection, voltage between the sup ly line 102 and node A to decrease. A restores of the first resistor Rl and a capacitance of the first capacitor Ci may detemtme how fast the voltage at node A increases,, sod. m ttttn tow fast the det ction voltage between the supply fine 102 and node A decreases. As described below, the resistance of the first resistor Rl and. the capacitance of the first capacitor Ci may determine a duration of the .first timing window,

( 061 J When a ES^'D event initially occurs, the initial spike or rise in the ^'BSD voltage on the snppiy line 102 ma occur fast enoogb to cause the detection voltage between the supply line 102 and node A to he initially generated at a sufficiently large level (e.g., above a detection level) to caase the first PM€¾S transistor PI to turn on. la e e al_* a transien voltage on the supply line 102 occurring last enough So cause the first PMOS transistor PI to turn n may be synonymous with the transient voltage occurring within the first timing windo . Also, the first PMOS transistor P I initially turn ng on may be synonymou with the first timing window initially opening,

13 |W»2J After the first PMOS transistor PI initially turns fm, the vol Sage at node A ma begin. (*> ri se accor ing to the resistance and capacitance, values of the first, resistor and capacitor III , C !_s respectively. As Use voltage at node A contimies to se, the detection ^•voltage between the suppl line 102 and node A may continually decrease «ntU the detection vol age teaches a sufficiently small level to cause the first PMOS tra sistor Pi to turn ofE The first PMOS tmnststor P i naming of! may be sy on mous with the firs! timing isstow cl sin ,

[8 631 When the first iming window h open and the first PMOS transistor PI is tamed on, the first PMOS a¾nsistor Pi may pull np the first activattttn voltage generated at nods B to a level that turns mi he second NMOS tiiMEstar N2 and the third NMOS trans stor N3L When the second NMOS traaaistor N2 is toned on, the first discharge path 112 activated, and m charge accumulated on th supply line 102 m y be discharged through th second NMOS transistor N2 to the ground r feree OND. When the -first timing window closes, the mt PMOS transistor PI amy turn off, which in tarn tnay cause the level of the first activation voltage to be swflciestly low to tarn off the second NMOS transisto N2. Stoee the turning on and off of the second NMOS transistor H2 is determined by the uniting on and off of the first PMOS ransistor PU then the first discharge path ! 12 is activated during the first linnng window. As siich, not only Is the first timing window used to detect an ESD event, but it is also used to set a. time donation duri g which charge is discharged through the first discharge path 112, Also, any delay between, the initial rise or spike of the ESD voltage and the activation of the .first disc arge path 112 (Le,, (he tsamog on of the second NMOS transistor N2) xmy be relatively short suc that the first discharge path 1 1 may begin su pressing the ESD voltage before it ca reach an iradestrahly high level.

[006 ^'i In addition, when the ESD event initially occurs, m initial rise or spik in the ESD voltage le el may cause an Initial rise in the voltage level at node D via the second resistor

IS R However, f¾« first PMOS trans stor P i may torn on and pull up the level of th first activation voltage at nods B shortly there fter, which ma cause the third MOS tr nsis or N3 to tarn on and pnll do n fee le vel of the voltage at node D down so the grousd reference voltage level {i.e., 0 V). The second, activation circuitry 1 14 may he comidered to he initially activated when the third OS transistor 3 is turned on. Aecirf»giy ihe first activation dfe»ttr 110 may activate o e first discharge path 1 .12 and tie second activation dresttry 114 when the first PMOS transistor Fi palls ιψ the .first tctivatkn voltage to a level that term on both the second NMOS transisto N2 and the third NMOS translato N3.

(0O$5f When the third NMOS transistor 3 is named on and the voltage at node Ό is pulled down to the ound reference voltage level, a voltage difference between the supply line 1.02 and node .0 ma be sufficiently large to turn on the second PMOS transistor P2, When the first timing window closes and the fet PMOS transistor PI tnms off, the s l in level of the first activation voltage n¾ay cause the third NMOS transistor ΪΝ3 to also tor off. Witii the thM NMOS transistor N3 ttraed off, a level of the voltage at node D a begin to rise toward the voltage level oa th supply line .102 v a the parallel connection of the second resistor R2 and. the second eapadior€2. The voltage at node D ma continue to rise until the voltage difference between, the voltage on the supply Hue 102 and the voltage at .node D ss sufficiently sm ll to caase the s cond PMOS transistor P2 to turn off.

( 0ft6j The second PMOS transistor F2 initially taming on may be ynonymous with the second timing window initially opening, and the second PMOS transistor P2 turning off may be synonymous with, the second, tiroing window closing. How fast t e level of the voltage at node 0 rises (and how fast the seeond tuning window closes when the third NMOS transistor N3 s off) may depend on the resistance of the second resistor R2 and the capacitance of the second capac itor€2, As stick, the dura tion of the second timing window may depend at feast in part on the resistance of the secorsd resistor R2 4 the capac tance of the sec nd capacitor C2.

Θ067ί When the second timing iistow open* and the second FMOS transistor P2 is iw d oil, the second FMOS transistor P2 ma pull up (he second activation vol (age generated at node C to a level that turns on the fifth NMOS tmnsistor N5. When the fifth NMOS transistor H5 is t rned _T the second diseh path 1 16 1$ activated, causing ch rge accumulated on (he sispply line 102 to e discharged through the fifth NMOS transistor N5 to the ground reference GND, When she second tinting window closes, the second PMOS transistor P2 may Mm off, which its turn may c use the level of the first aetivatfen voltage to e sufficiently lo to tern off the fifth NMOS transistor NS. Sioee the turning on and oflf f the fifth NMOS transistor N5 is de ermined by the tim ng on and off of the second PMOS transistor P2, then the second discharge ath lie is aotiwted dering the second timing n o .

|IKN»$J The resistance of the second resistor R2 md the capacitance of (fee second capacitor€2 may he set to respective alues that cause the second timing window to be open and the second discharge path 116 to he activated for a sufficient duration after the first timin window closes. In this wa , after the first timing window closes and the first discharge path 112 is deactivated, the BSD protection dredt 100 still has a discharge path activated to sup ress the ESD voltage, should the ESD even still be occurring when the first timing window lo es.

|^§0n i In some examples of the circuit configuration of the ISP protection ctrcail 1 0 shown in Fig, 2, & ratio of a st¾e icg,, a gate width) of the fifth NMOS transistor N5 to a total ize o -he second and fifth transistors N2_t N5 (e.g., a m of the gate widths of the second and fifth NMOS transistors N2» S) may he in » range o about 7G%-8Q%_» although other ratios ma he possible. |W7 1 Figure 3 shows a flow chart of an exam le method.300 of n ESD protection circuit su osing a voltage generated ©o a supply line m .response to m ISO even! At l ck 302, so ESD detection circuit of the ESD protection circwtt may delect the ESP event the s p l line. The BSD detection circuit amy detect the ESD event by detecting m initial rise of a level of the voltage on S e sup ly line occurring within a fxm timi g window. When the Mt rise occurs within the first timing Mo% t e ESD detects as circui may generate a detection voltage between a first node and the supply line at an initial detection, level that is sufficiently large to ac ivate a first aetivatioa c rcuit of e ESD protection eireslt, The ESO detection circuit may inelade a first resistor a d a first capacitor thai re connected o each other at the first n d . Ate the dete tio voltage Is g nerated at the initial level the voltage at the first node may begin to increase and the detection voltage between the su pl line and fet node may begin to cora^spondingly decrease in accordance with a resistance of the first resistor and a capacitance of the first capacitor,

»7.tJ At Mods 304, in res- oos© to being activated, ie first activation drctiit stay generate a first activation voltage at a second node that activates a first discharge path and a s cond activation circuit Activating the first activation circuit may include turning on a first PMOS transistor to pull tip the first activation voltage generated at the second node to a level tha activates the first discharge path and the second activation circuit Activating the it i discharge path may include tenting n a first NMOS transist r of the first discharge path. Activating the second activation circuit may include turning on a second NMOS transistor, which ma arn m a second PMOS transistor of the second activa ion circuit

|Θ072| At block 306, in response to being activated, the first discharge path ma discharge charge on the su ly line to ground, in addition, in response to being activated, the second activation circuit ma generate a second activation voltage at a third node to activate a second discharge path. For example, t e¹ second PMOS transistor of the second activation cirenit may pisll up the second activation vol age to a level that activate the second discharge path, la addi!lcm, turning on the second NMOS transistor ros pull down a feuttii n de- to grwo , whlds tn t ns may cause the second P OS transistor to pull. «p the second activatieu voltage. Also, activating t e second discharge path way e ide turning on a th rd NMOS transistor of the second dischar e pa h.

fiMTOJ At block 308, in response, to being activ ed- ie second discharge path «¾ay discharge harge m. the suppl line to ground. For example, when the f¾st N OS transistor h turned ts, charge on the su ply tine may flow t ough the first NMOS transistor to ground. (6074J At ock 310, the first timing wi dow ma cl se aa the fits! activation mmmt mm be deactivated In mm® exam le methods, the first timing window may dose md the first act vation circuit may be deacti ated when the voitage at the fim. node rises to a level thai c uses he detection voltage enerate be wee the supply !½e and the first node to be sufficiently small to torn off the first PMOS transistor of the first activation circuit.

»75| At block 312, whet* the first timing indo closes and the first, activation circuit s deactivated, fee first activation, circuit may gene ate the first activation, voltage at a level that deacti va es the first discharge path, in addition, the level of the first activation voltage when the first timing window closes may turn off the second NMOS transistor.

(0O7£| At block 314, when die first tiatiag. window closes and the first activation circuit is. deacti vated, the second activat tt circuit may continue to activate the second discharge path. For example, when the first timing window closes, the second NMOS transistor may turn oil and a level of the voltage generated at the fourth node may begin to rise j» accordance with a resistance of a second resistor and a capacitance of a second capacitor that are comneetod in parallel with each other.. Although the level of the voltage at the .fo th node is rising, dlfceoee bet ee® lbs level of the voltage on he su l line and the level of the

B activ ted for a eri d, of tune. As a result, charge may continue to be discharged fr m t e: s pply line to gmun . during this period of time,

[00771 At block 31 , the level of the voltage at the fwrth node may increase to a kvel that c uses the -voltage difference between (he supply line and the fourth node to be sufficiently small to deactivate the second activation drarit and close the second timing windo . At Mock 318, in res ns to the second timing window closing and the $&c d activation circuit being deactivated, the sec ad activation circuit may generate (he second activation voltage at a level that deact ates the second discharge ath. In. resp nse o be deactivated, charge on the suppl ii may m longer be disdtatged to ground via the seco d disc a ge path,

[ft78J Fig, 4 shows, a Mock dia ram of a second. example ESD protection circuit 400 t at may be coupled to the suppl line 102. In c nt ast to the .first ESD protection, circuit 100 of Fig. 1 , the second BSD pro ec i n circuit 400 of Fig. 4 may include a single discharge path rather than two discharge paths. Also,, tsther than use the detectio voltage gejsemted by the ESD defection circuit y to activate (fee first activation circuitry to, in turn, ac i a e the fei of the two discharge paths, the second ESD protection circuit 400 of Fig, 4 may use the detection voltage to activate third activation dredtry to, in tarn, activate the same discharge path that is activated with fee second activation dscoitry. The third circuitry may keep the discharge path act vated, antii a f st lime period closes. Similar to die first ESD protection eirei 100, the first activation circuitry of the second BSD circuit 400 may acti vate the second acttvatton circuitry, which in. turn, n»y activate die dischar¾e a h un il a second time period closes. The first time period may begin before the sseoo»d time period, and the second time period may end after the first time period.. As sack, like the first ESD protection circuit 100, the second. BSD protection circuit 400 ma use two time periods to discharge charge In response to an BSD even However, in contrast to rhe first ESD protection circuit 100, t e seeorid ESD protection eirctat 400 army use a single d schar e path to discharge fee charge,

[99791 In iwthet detail, the BSD pr te tion circuit 400 ma include BSD detection, eircaiiiy 08 that like She ESD detection drouihy 108, w configured to delect whether a transient voltage on toe supply tme 102 occurs within s fet iming window or time period. I it does, then t½ ESD detection circuitry- 408 ma geaemte a olt ge at a node A' with respect to ground that yields a def ctio voltage between the supply liae I 2 sad node A' that h above a detec ion level. The defection voltage being abo ve the detection level may activate fi st activation etatoy 410 and third activation dre^iby 412, Prior to the detection, a level of the detection voltage may be below the detection level $ h that each of the reacti ation eirettiiry 4.1§ and toe ihsrd activation circuitry 412 -may be deactivated

\998ty in some example cortfigta-aiiotis, the BSD detection eireu&ry 08, l te the ESD detection circ t y 108, ma be- c nfigured as a low pass filter or exhi it o pas* filter ehsfaeterisll.es,. if the frequency of the Ira iem voltage is high enough to be indicative of a ESD voltage, then the low pass filter chameieristks of the BSD detection eireuiity 408 may ^ ej cf the transient voltage and generate s relatively low voltage at node A⁴ such that the voltage difference between the supply tine 102 and node A¹ ¾ above the detection level to activate the first c ivation cifcuiliy 410. Alternatively, if the frequency of the it-ansie voltage is too slow to be Indicative of an ESD voltage, then the low pass filter characteristics of the ESD detection circuitry 408 may " ass^** toe transient voltage and generate a rela tively high voltage at node A^! such that the voltage difference between the suppl line 102 sad n de A^s is below the detection level

|(H)81 J As sho n in Fig. 4, the ESD protection circuit 4f ma include a single discharge path 416 that is configured to tr nsiti n between at? activated s a e and a deactivated state. When activated (or coaitguted in the activated state), the discharge path 16 may effectively operate as a short circuit and! couple the se piy line 102 to the ground reference GND, As a result., charge aecHmulated »n tiie sispp y line 102 ma dischar e to the ground reference GND via the disc arge pat 16» The discha ge of he cha ge through ¾he first discharge path 112 fmy suppress the level of the BSD voltage on the supply lias HJ2. Alternatively, when deaetlvaied (or configured in the deactivated state), the discharge path 416 ma effectively operate m en circui between the suppl line 102 and the ground reference GND,. When, coo figured in. the deactivated state, charge ccumul te on. the supply line 102 amy not disoharg e to t e grouad reference GND via the first d scharge ath 112,

(00821 When the detection voltage generated by tie BSD deteettoa circuit 408 at node A' k above the defecti n level the third activation eireuittr 41:2 may be activated and to response, generate a first acftvatioa voltage (relative to the ground reference GND) at a aode C at a fcv that activates the Msarge path 416. Alternatively, he s the ESD deletion eireu ry 408 generates the detection voltage at node A¹ belo the detection level, then th third act vation cimtiity 12. tmy b deactivate , and response generate a first activat n voltage at ods C at a level thai deacti vate the discharge path 416.

(00831 ϊ« addition, hen activated, the first activation circuitry 410 may enera e a second activation voltage (relative to the gronnd reference GND) at a node ΒΛ As shown in Fig, 1 _s the first activation vohage generated at Rode B' ma be provided, to second activation eireiiitry 4 4. When, the first a tivation circaitry 410 is acti v ted in response to the detec tion voltage being generated above tie detection level, the first activation dreaitry 410 raay ge erate the second activation voltage at a leve that activate the second activation citcuihy 41 ..

[00841 When the second activation eircukry 414 is activated, the second activation circuitry 14 may gene a e the felt activation, voltage at node C\ Accordingly, both the secon activation, circuitr 4-14 arid the third activation, eireiiitry 412 may he used io activate the discnarp path 416. That i¾ when both- or only oae of the second and third activation eiretairies 12, 414 ar activated, the §m activate voltage gene ated at node n»y be generated at a level that activates the discharge path 1 , Aitereatjvely, when both the second: aedvaiioa circuitry 414 arid the third activation circuitry 412 are deactivated, then the discharge path 416 may be deactivated,

|^'0085J Whm the BSD detection circuitry 401 detects s ESD event by detecting a transient voltage on the suppl line 102 thai occurs wiilin a fx i tinting indow, the ESD detection eireu&ry 408 ma generate the detection voltage et een the supply line 102 and node A¹ above ths detection level dur ng the first timing window. When he first iimmg lasfe closes (Le,, the fet time period e pi es), the detectat voltag am m ionpr be generated above the detection, level. As such, (be .first activate circuitry 4I and the third activate circuitry 412 may activated fkmng the first timing window aad may then be deactivated when the first timing window closes. l e third activMloa eteuttry 412 being acti vated during the fet timing window ma cause the discharge path 416 to be activated dsrirsg the first timing window to discharge charge ©« the sup l line 102 to (he ground reifere¾ee G D.

(&0 { Similar to the second activation cireaitry 1 14 of Fig, 1, the second aetiv&tian circaiiry 414 of Fig. 4 may be activated during a second timing window of for a secoisd time periods is timi during the second timing window, the disc arge path 416 ma ^'be activated to discharge charge oa the supply line 102 to the ground reference GND. I general the first tjmiag window tmy begin before i ts secoad timing ta o begins such thai die third activation ci uitry 412 may be activated to ca se the discharge path 416 begin discharging ch rge on he supply line 102 before t e secon activation circuitry 434 is activated to cause the discbarge path } 16 begin dise atfisi , In addition* the second timmg window may end after the fat tisaing do ends. As such, when the third activation circuitry 412 steps

17 activating he disciwge path 416 when the fet timing window doses_* sa the discharge path 416 rmy ims to dischar e charge b cause di se«o»d timing wind w has not yet dosed and the second activation ctr^aitry 414 may still he activated Use of the two timin windows to activate a discharge pat — a first window that o ras shortly hist quickly for ESD detection and a second: window that: stays open after the first window closes— -may allow the BSD protection circuit 4» to start ^ ressing the ISO voltage as early possible and also to suppr ss the ESD voltage for an o verall longer dotation of sis ESD event compared to otter ESD p otect on circuit eoaf1 r&iic«¾5 that «ttli¾e only a single time window or period !br ESD sup ression.

jftWS?] Fig, 5 shows a circuit schematic of an e am le circuit cottilgtsrstion of the ESD protection circuit 400 shown m Fig, 4, Lite, the ESD defection dax ixy im of Fig, I, the ESD detection circuitry 408 may incl de a series cormediors. of a first resistor RJ ^'' wad a first capacitor C Γ, ^'The first resistor RT and the first capacitor CI ' ma each ave a first end connected together at node A'. In addition, tie first esistor RF may ha e a second end connected to the snpply line 102, and the first capacitor CV ma have a second end connected to the ground reference GND,

(ΘΘ | In addi i n, like the first activation circuitry ? 10 of Fig, I, the firs act vation clrcaitr 410 may include first nvmet circuitry that includes a fet PMOS tra sisto ΡΓ and a first NMOS transistor NT. The first PMOS trans stor FT may include a source terminal connected to the supply Ike W2 and a drain terminal connected to node B\ The first NMOS transistor W may include a s u ce terminal connected to he ground reference G B and a drain te nal also connected to node B^s, Gate terminals of each of the first PMOS transistor PF nd the first MOS transistor 1 ' may be connected to node Al The first: PMOS transistor F I ' and the first NMOS transistor ^' Γ ma form an inverter circuit- When a level of the voltage at n de A* is at a logic low vstoe, the fei PMOS transistor FT and the first NMOS transistor f may operate to pull s. the voltage generated, at nod B* o a logic high level, and whm the level of the voltage at node A^T is at a log c high value, the first. PMOS imasisior Fl ' and the first NMOS Usnxufor Nl' ma operate to pull do n, the voltage generated at n de B' to s logic low level.

| M½t9J In additi n like the second activation circui 1 1 of Fig, 2, the second activation eiretit 414 may include a parallel connection of a. second resistor R2^T and a second eapcitor. C2\ First en s of each of the sec nd .resistor R2' and {he see-ond capacitor C2' may be connected to the supply line 1.02, and second ends of each o f the second :n¾¾stor R2' and the sectMid capacitor C2' may e connected together at. a oode I

i mi The second activation circuit 414 m y also indtade a second NMOS transistor N2' thai has a drain terminal connected to node D^* and a sourc terminal connected to the ground, refcfiawe GND, lo. addition, a gate temn a! of the second MOS transistor NT may be connected to the drd n terminals of the f st PMOS atid. NMOS tmas ors Ρ , !⁵ at nod© B\ M I| The second activation circuit 14 may further indade inverter dteuitry that ncludes a sec nd PMOS tr nsistor P2' and a third NMOS transistor HT. The s c d FMOS transistor P2' may include a. source torrninal connected, to the supply line 1 2 and a drain terminal: connected, to node C. Tie third NMOS transistor N3* may include a drain erminal also connected to node C in addition, gate terminals of toe: second PMOS transistor Ρ and the third NMOS transistor f¾^s may be connected together at node IF,. The second activation 414 may also include a fourth NMOS transistor N4' connected in series with the third NMOS transistor 3'. in. particular, a drain tetmlnai of the fourth NMOS transistor N4' oiay be connected to a source termi al of the third. NMOS transistor 3'. Also, a source terminal of toe fourth NMOS transistor N4^† may be connected to the ground reisrenee GND.

Addl.tlon.aUy,, a gate term nal of the. fourth NMOS transistor N4^! may be connected to node A^T and configure to receive the detection volt ge. As explained in. farthe detail belo w, the S fourth MOS transistor s 4^s raaycooaected in series with the third NMOS transistor N3^S in order to eliminate contention at node€7 between the t M NMOS fcmwte W d the i rd activation eirouUry 12,

[0092J The discharge path 416 may include a fifth NMOS tra»s½i»r NS' aving a drain terminal connected to the supply line 102 and a source terminal connecte to the groun reference GND. I» addition, a. gate tmmrnl of lite fifth MMOS trarsstsior NS' may be cotmecfed to n de C\ Like the MMOS transistors 2, NS of the first ischa ge paths 112, i 16 of Fig. 2, the fifth MMOS ttwnnftv NS' of th discharge path 416 may he referred a eiarap ttanst&or rns it may op rate to clamp ts level of voltage generated on the supply lire 103 to m Identified safe voltage level below a breakdo n voltage level t at is tmt likely to cause damage to the su p y voltage s iree and/or destioatfoa devices 104, 106,

[Q093J The §m activation voltage generated at rwde C ma be applied to the gate termtesl of the fifth NMOS transistor S^f. A level of the H t ac iv ti n votop may de ermlne whether the fifth NMOS transistor NS⁵ is either tamed on or turned off. i« particular, whea the first activation voltage is above a threshold voltage of the fifth transistor NS' (or at a logic high level), the fifth MMOS transistor NS' ma be fame en, and when the first act vation voltage is below the threshold voltage (or at & logic low level), the fifth NMOS transistor N5^! umy he tattled off^"

|®0 | W en the fifth HMOS transistor N5' is tamed ύ the discharge pat 416 may be configured m the activated state and charge on the supply tine 102 may flow through the fifth NMOS transistor 5^! to the pound reference GND, Alternatively, when the fifth. NMOS transistor 5^': is turned off, the discharge path 416 may be eo« «red in the deactivated state and charge on she supply line 1⁽ 2 may be prevented from flowing through the fifth NMOS transistor NS' to the g ound reference GNP. 51 The third activation eircsutsy 412 may include a third PMOS transistor F3* that inel tides a rn &t terminal connected to the supply line 102, a drain terminal e Miseted to node€*, a»d a gate terminal connected to aode A' md configured to receive t detection wltage. The third acti vation circuitry 412 x y he activated when the detection voltage causes the third PMOS transistor F3 to be turned on, sad may he deactivated when he etection voltage c & the ihM FMOS ttattsistot P3^? to be turned off

|Θ0961 Prior to an. ESO event, a .level of ihe etection voltage generate beiweert ihe supply li 102 and node A' (or a voltage drop across he first resist r R 1 -) ma be relatively m W (i.e., faslow threshold voltages of the first asd third PMOS transistor Pi':, F3^*) such that third PMOS tansistet P3^f is t rned off. Beoes, prior to a« BSD event, the third activation ciret ry 412 h mi activating the discharge pat 416, Also, with the detection v ltage generated hetweetj the supply line 102 and node A' being relatively small, the first PMOS transistor Ρϊ' Is also turned off Depending OH the voltage level at «ode A-₅ the first NMOS transistor Ν md the fourth NMOS tmisist f M4^S may he either toed on or oft in either ease, however, the level of ihe voltage si node W ma e su eiently low to caus the second NMOS transistor N2^< to be aimed oil. With fee second NMOS trausistor N2' turned off, the fevd of the voltage at .node D' may be close enough to the level of the voltage on the sopply Kite 102 such tha the second PMOS transistor P2* is turned off. Since both the second md third PMOS tosistors ΡΓ and P3^S a e tanked off prior to ajil D event, than the level of the first activation voltage generated a node C may be soffiden lo to cause the fifth NMOS transistor M5' to be turned off and general, the dis harge at 16 to be deact ivated. ϊββ 1 Similar to operator* of the ESD detection circuitry ICfS, when, m BSD event initially occurs, an initial spike or rise i» the ESO voltage o¾ the suppl hue 102 a occur fast eoougfe o caus the detection voltage between, the s p ly H e 1 2 and wode A^* to be init ally generated at a sufficientl large level (eg_*, above a detectto level) to cause th 6 t and third PMOS transistors Pi\ Ρ3^Γ i<> tam on- in eneral, a t nsient olta e m the supply Ike 102 ocesmisg fast ei»«gh to caus the first a»d third PMOS transistors Pi. P3^r ¾> turn o« may e synonymous with the transient voltage ocowwSag within the first timing window, Also, the fi st and third PMOS transistors ΡΓ, P3' initially ta ing on may be s ¾OB m us with the first timing window initially opening.

|^'9O0 SI Ate the first and third PMOS twisters W, P3' initially ism on, the voltage at node A ' may be in to rise according to the resistance and capacitance alises of the first resistor d capacitor RJ \ C , espec ively. As the volta e at node A^* continues rise, due detection voltage b en the supp fine 102 a»d node A' may continually decrease mistii the de ection oltage reaches a sufficient small level to cause the fl PMOS transistor to iwm off. The first PMOS transistor PI' tumiag off may be synanymous with the first timing window closing.

|iW9i When the third PMOS transistor P3^! tares OR, the third PMOS traasisfor P3¹ ma puM tip the fitat activation volia at node C to a logic high level to cms® the fifth MOS traasistor 5' to turn ors and begin discbar¾mg charge on the snpply line 102. In this way, the discharge path 1.6 is activated when the first timing window o eras. Subsequentl , when the first timing window closes, the third PMOS transistor ? may tarn. o¾ and k turn, the discharge path 416 may no longer be acti ated based en the third activation circuttty 412. Since the taming sin and off of the third N OS iraa&isior 3^S is determined by the first timing window, then not onl is the first timing window used, to detect an BSD v n, but it is also used to set a time duration daring which the third activation circuitry 12 activates the discha ge pain 416, Also, any delay between the initial rise or spike of die ESD voltage and the activation of the discharge path 4 ί 2 (I.e., the aiming an of the third PMOS transistor P3^* and in turn the fifth MOS t a sistor S^*} may be relatively shor sueb that the discharge path 416 may be in suppressing the BSD voltage ie fore it eart reac h ass «no¼sirably high level

[OOUMlj sedition, ti> circuit mfigum bn of the seco ac&tvation c rcuitr 414 asay operate similarly to that of itie second activation circuitry 1 14 of Fig. 1, When die first tim ng window is o en and the l¾rst FMOS transistor Ft is turned on, the first FMOS transistor Pi ntay pttl.1 up the .second activation voltage generated at node ^* to a level that twm mi the seeoad NMDS transistor M2 When the BSD e en initially ccu s, an initial rise or sp k m the BSD voltage level may cause aa initial me in the vol Sage level, at node O^f via the second resistor R2^!. However, the first FMOS t ansistor Pi ' may m and pall u the le el of the first activation voltage at node W shor l thereafter, wh ch rnay cause the second MOS transistor M2' to urn on a d pttl down (he level of the voltage at node !>' down to the gmuad referen.ee voHage level (te,_? 0 V).

|iMt>l J The second activation circuitry i 14 may be considered to he initially activated wfeea the .second NMDS transistor N2' is turned on. Accwdfogiy- the first aetivsta circuitry 410 may activate (he second activation circuitry 414 w en the first FMOS tr nsistor ΡΓ pails up the second act vat n voltage at node B* to a level that turns on the seea«d MO transistor N.2^*.,

(001821 When the seeoad HMOS tiansktor N2' k tamed on aad the vol tags at nods D^! is puled downs to the gronnd r forenee voltage level, a voltage difference between the su pl line 102 and. node .0* may be sufficiently large to iura on the second PMOS transistor F2', When the first timing window closes and the fet and third FMOS t ans sto s Ρ , P3^! tarn off, the resulting level of the second activation voltage at node W may eause She second NMOS transistor ^'NT to also Sum off. With the second N.M0S transistor N ^* tamed off a level of the vol tage at node D' mm begin to ri se toward the voltage level m the supply line 102 via the parallel connection of the second resistor %.T and the second capacitor C2^!, The voltage at node D' may continue to rise until fee oltage diO¾Fersce between t e voltage on the supply ilrse 102 and fee voltage at node P Is sufficiently small to cause he second PMOS transistor P2^* to Inrn olT,

The second PMOS transistor P2' initially tami g en. may be synon mo s with, the second: timing- indow initially openi g, and the second PMOS transistor ^'P2^* taraing off may be s non mous with the second asnsg window closing, How fast the level of the voltage at node D' rises (and how f st the second tirning window closes hen the second. NMOS transistor H2' tunas oft) .roay depend on the resistance of e second resistor R2* and the capacitance of th second capacit r C2\ As such, the deration of the second, timing wiaidow may depend at lea t to part n lie resistance of the second, resistor 1 2' and the capacitanc of the second capacitor C2".

\Wi M\ Waen the second timing window opens and t!te second PMOS transistor P2' is titmed 08, the second PMOS transistor P2- tmy pull «» the second acti vation voltage generated, at node C to a level that turns on the fifth NMOS transistor 5', However, due to the delay betweea the art of fee ESD event and. when the second PMOS transistor ΡΓ turns on, fee third FMOS ttsrssistor F3\ with its gate being directly c nnected to node A\ may have already turned ors and started activat ng the discharge path 1.6 by the time that the seeotsd PMOS transistor P2' turns on. Yet, like die e eswt configuration of the second aetrvatioa oireai ry 1 .14 of F ig, 2, fee resistance of the second resistor 2' and the capacitance of tie second capacitor C2* may be set to respective values to cause the second timing window to be open for a saiieknt duration ate the first timing window doses. In this way, after the first timing window closes and the third activation circuitry 412 is deacti vated. e ESD protection Cireak 400_» the dischar path 16 is still activated to sisp ess fee ESD voltage, should fee ESP event still he occnrr ng when the first timing window closes. Subsequently, when the s con timing window closes, the second PMOS ansis to P2^f ¾aay turn oft_* Since lite first window may be closed a d the third PMOS transistor P3^f may be turned off when the second timing window closer then h ts the second and third activation esretdtdes 41 , 412 may fee deactivated with the s c nd tiniing window closes.. As such, when the second timing windo closes and fee second PMOS transistor P2' tarns off, me fifth NMOS transistor N5^! may turn off, deactivating the disc a ge path 4 J 6.

j l&S) Om difference bet eea the circuit «%u¾ati n of the second activation, dreultry 414 and that of me second activation cifcaiiry 14 of Fig, I is the indttston of the fourth NMOS trans stor 4^!, As previ usly described, when an BSD event occurs, there ma be & initial rise of spike m the BSD voltage level oeew ng at stodc D' shortly before the second NMOS tnsns ot H2? turn on and starts pulling down the voltage at uod 17, Tie thi d NMOS transistor N3^S. m response to this initial increase in v ltage, ma want to turn on and. star pulling d w the level of the first activation ol age at node C\ However, when the BSD event first ocea *, the third PMOS transistor P3^! is to turn m in order to pail up th le vel of the first activation oltage at node C so thai the .fifth NMOS transistor N5' turns. o« an4 starts discharging (he charge on the supply line 102, Taming on tie third NMOS transistor would nndesimhiy cause contention at node C and hinder he ability erf the third. PMOS transist r F3^* to activate the discharge path 416 right when the BSD detection ekenitry Θ8 detects the BSD event. However, by connecting the gate tet ksai of the fourth NMOS transistor N4⁵ to node A", Ac initial level of the detection v lta e when as BSD event ccurs may tars off the fourth NMOS transistor N4\ which in. turn may prevent the third NMOS transistor 3' from pttUing down the e el of the first activation voltage at node despise the initial spike or rise at node D' when the ESD event starts. As such, the fourth NMOS transistor N4\ by eing tamed off when an BSD event occurs, ma allow the t i d PMOS transistor F3' to torn on to activate the discharge path 41.6 without being affected by c ntention at aode€' due to the third NMOS i atmsto N3^f heisg turned on. \Μ)ΙΜ\ Fig, 6 shows a flow chart of soother exaisp method 600 of an ESD protection circuit mpp diig a voltage ene a ed on a supply line m .response to m ISO eveat. At bloc k 602, m ESD de eetioa circuit of the ESD protection circuit may detect the ESD event on me s p l line. The BSD detection circuit a y detect the ESD event by detecting m initial rise of a level of the voltage on t e supply line occurring within a fxm timi g window. When the MtM rise c s within the first timing w » the ESD detection circuit .may generate a detection voltage bet en a first twite and the supply line at an initial detection level that is sufficiently large to activate a fet activation xt i and a third activatkm circuit of the- ESD protection circuit The ESD detection eirctdt ma include a first resistor aid a first capacitor that are eoni*ecte to each other at the fi s node. Ate the detection voltage is generated at the initial level, the voltage at the first node may begin to increase nd the detection voltage between the su ply line a»d first n de may begin to coi espoodmgly decrease 1s accordance with a resistance of the Ftist resistor and a capacitance of the first capacitor,

\MW7\ At block 604 in es ons to being activate the third activation cirenit may generate a first activation voltage at a second node thai activates a discharge path, causing charge on the supply line to be discharged to ground Activating the third activation circuit ^■tmy include tottin a first FMOS ransistor o pull up the fi st ac ation voltage generated at the second node to a level that ac va es the discharge path, Activating the discharge path may include turning on a first NMOS transistor of the discharge path.. In addition, in response to- being activated, the fci activation circuit may generate a second activation voltage at a third node thai activates a second activation circui Activating the first activation eirenh may include taming on a second FMOS transistor to pail n the second activation voltage gen rat d at the third node to a level that ac ivates the second activation dist l Activating the second activation circuit may include turning on a s cond NMOS transistor, which ma tors on a sec nd PMOS o^s sto of the eeoB activat on circuit

[00188] At block 606, ia .res onse to being activated, Ifee second activation circuit amy contribute to generating the first activation voltage, along wit the third activation circuitry, at the third node to acti vate the disc arge path. In addition, Saammg on the second NMOS transistor may pnH down a fourth .node to g ound, which its turn m»y ca se the second PMOS transistor to generate the fir activation voltage to activate the discharge path.

\MIW] At block-.608, the first iming window ma close and the first and third activation etfceits may be deactivated, it* mm exa ple eth ds, the first timing window t y close an the first and hird activation, cfeiits may he deactivated when the voltage at me first node rises to a level that causes the etecti n voltage generated between the supply line and the first node be sufficiently small to mm off the PMOS transistors of the first and third activation circuits,

|W119J At block 610, when the first ti mg window closes and the first and third activation ci cuit are deactivate!, the second activation eireasit may eonmnte to activate the discharge path. For example, when the first timing window closes, the second NMOS transis o may turn off and a level of the voltage generated at the fourth node may begin to rise in accordance with a esistance of a second resistor and a capac tance of a second capacitor that are connected in parallel with each other. Although the level of the voltage a the fourth node Is rising. & difference between the level of the voltage on the supply line and the level of the voltage at the fourt node may remain swi tly large to keep the d scha ge path activated for a period of time. As a result, charge may continue to he discharged from the supply line to ground during this period of time.

[00.1111 At block 612, the level of the voltage at the towtfc node ma increa e to a level, that ca ses the voltage dtfleieace between the su pl ine and the fourth node to be sufficientl small to deactivate the second activation circuit a d close the sec nd timing window. At black 614, in. res onse to the sec nd, t ieg window closing and the sec nd activation circuit bemg deactivated, ihe second activstio circuit nsay generate the first activation wltage at a level thai deactivates he discharge path, la response to fee deactivated, charge on the supply lias may longer be discharged to ground via the discharge path. \milZ\ It is intended that the foregoing de ailed description be u derfeed as m

llustrati n of selected fxm tfeat the invention can lake and not as a definition afthe if v¾!ttsoi>. It is «ai.ly the fo!lwing claims, including all equivalents,, that ate Intende to dei¾e the scope of the claimed invention. Finally, it should e noted that any aspect of any of he preferred, «ttibodkne«t$ described herein caa be used alone or .in combination with one amsther.

Claims

We cla m

I .. An electrostatic discbarge (ESP) protection circuit comprisin :

discharge path circuitry coupled to a supply fine and a ground reference;

a detection circuit configured to:

¾etet an ESB event omt o« the supply line;

generate a detection vol tags? above a detection level for a first time period m res po se to iteteciion of the ESP event; and

activation circuitry ihat, when act vated, is conf gure to cause the disctage path circuitry to discharge charge on the supply rn to the ground reference, wherein tiie activation circuitry is configured to be activated for the fmi time period and s second time period that ends after the .first time period e ds,

2, Tie ESD profeetioo i cuit of claim I , wherein he discharge path e rea iry comprises a fet discharge path circuit and a se ond discharge pa h circuit, wherein the activation circuitry c mprises a first activation circuit and a second activates circuit,

wherein when the detection cirenft de ects the ESD event, the first activation circuit is conf gured to generate art activation volta e at an activation, level to cause the first ischarge ^•path circuit to discharge charge and to activate the second activation eit¾uit for the first time p i d_^ and

wherein jfee second activation circuit_* when activated, is configured to canse the second discharge ath circuit to discharge c arge for the secon time period.

3, The ESD protection errc-utt of claim 2, wherein the first discharge path circuit comprises a first transistor and the second activation c rcuit comprises a second transistor, whereto the activation voltage at the activation level ferns on each of the fi rst transistor to

33 cause the first discharge path to discharge charge arid, the sec nd transistor to activate ihe secoHd activation circuit

4, The ESD protection circuit of claim 3, wherein the second activation circuit further compr ses a node connected to the second transistor, herein the first activation circuit k ftnther configured to generate the activation volta e: below the activation level when he fci time period expires, toeta he first and secend transistors e e configured to turn off is. response to the activation voltage being generated below he activation level, and wherein when the second transistor turns off, a vol Sage generated s the node causes the second discharge path to discharge charge for the second ime period.

5, Tie ESD protection circuit of claim 4, wherein the voltage gesemted at the node causes the second discharge path to be deactivated noon expiration of the sec nd time period.,

6, The ESD protection circuit of claim 2, wherein the first activation eirerrh is configu ed to begin causing the first discharge path circuit to discharge charge before the sec nd activation circuit is configured to begin ca li g the second discharge pith to discharge charge.,

1, The BSD protection circuit of claim 1, wherein the activation circuitry comprises a first activation circuit., a second activation circuit, and a third activation circuit,

wherein when the detection circuit enerates the detection voltage above the detection level;

the third activation circuit is configured to cause the discharge path circuitry to discharge charge for the first time period;

the first activation circnit is configured to activate the second activation circuit; and the second activation circuit, wpon being activated_* is configured to cause the discharge path eiremtry to discharge charge for the second time period. 8, The BSD rotection circuit of claim 7_f h rein the third activation cirettit, upoa feeing activated, is

voltage at aa activation evel on a node t.o cause fee discharge path circuitry to d scha e charge, arid

wherein lite seco d activation circuit_* upon bei g acti ated, ts configured to geaerate the acnvarioa voltage at fee activation level OK fee n i s to cause fee discharge path circuitry to dischar e the charge.

9, The BSD protection ci cu t of claim 8, erein, the second activaiioa circuit is coafigured to roa tain She activation voltage o the ttede at the activation level txl the seeend time perio ends when the first time period ends ami the third activate* circuit is m longer configured to generate (he activate* voltage at he activation level

lit The ESD protee oa c rcuit of claim 8„ wherein fee third activation circuit comprises a first transistor to pail up the activs&bn voltage oa the node, h re n the sec nd activation eiratit eompdses a second transistor eooilgwed to tern off when the detection circuit

«eraies the detect on voltage above the detection level and whe ein the second transistor, when turned f, prevents a third transistor of the second activate* circuit from pollin down, the activation voltage, on the node,

11. The ESD protection circuit of claim 10, wherein the node comprises a first node, and wherein the d tection circuit is configured io generate the de ection voK&ge between a second node and the su l fine, and wherein the first transistor and the second transisto each have a terminal coupled to the second node.

1 , An electrostatic discharge (ESP) protection cirenh eon^ri mg;

a first discharge path and a second discharge path, each eonfignred to, when activated, discharge charge accumul te en a sa pty line to a ground reference;

a detection eirewit configured o generate a detection voltage shove a detection levelm ^" tf sponse to detection of an ESP event on the snppJy l i ne; activation d^'fcihtr comprising a firs* act vation ckcmt and. a second act ation circuit,. wherein the fet activation circuit Is configured to be activated, w ea the detection circatl generates the detecfiort voltage above the detscfiort level, and hen a ti ate generate a first activation voltage at a first activation level to activate each of the first discharge path and the second activation circuit, and

wherein the second activation etrenit- upon being activated, is eordlpsresd to generate a second activation voltage at a sec nd activation level to activate the second discharge path,

13, The BSD protection drcu.it of claim 12, wherein the fet activation circuit s configu ed to generate the first activation voltage at the first activations level artin a timin window.

14, Tim ESD protection circuit of claim 13, wherein the detection etecmt comprises a resistor aad a capacitor, and wherdrt a duratio of the timing window is based on a resistance of the resistor and a capacita ce of the capacitor,

15, The BSD proi«ctio« ircuit of claim 1.3, wherein the d tect on eiretat is configured to gene ate the deject n ltage to deactivate the first activation eh nit when ie timing w ndow closes,

wherein the first activation circuit, upon being deactivated, ½ configured to generate tite first activation voltage at a deactivation level and provide She first activation voltage at the deactivation levd to each of the first discharge path and the second activation eirein¾ wherein the fet discharge path is confi ured to be deactivated in response to rece t of the first activation voltage at the deactivation level and

wherein the second activation eireait is configured to remain activated to activate the second discharge path for a time period in response to r ceipt of ihe second activatio voltage at the deactivation level 1 tx The ESD prftteetion ohxjuit of claim 15, wherein the second ac s vatioft eiretnl composes a resistor esrsrieeted in parallel with a capa itor, and wherein 8 ifeatioD of the time er o that she second activation circuit is configured, to remain activated depends on a resistaace of the resistor and a capacitance of the capacitor,

17. The ESD protection circuit of claim 12, wherein the first discharge path comprises a fet transistor havleg a first gate width and the second dischar e path comprises a second transisto having a second gate width, and wherein, a rati o of the second width to a mm of he first gate width and he second gate width corresponds to a percentage in a range of between 70-80%.

18 , A method, of respondi ng to m electrostatic discharge (BSD) e vent, the method c mprising;

ener ting, with a fi st activation circuit, a first activation voltage to c use discharge path circuitry to dischar e charge on a supply line ¾ order to su press an ESD voltage for a first time period;

generating, with a second activation circuit, a seeo aciiva oa voltage to cause the discharge path circuitry to discharge charge on the supply line in order to suppress the ESD voltage for a second lime period; and

iii response to generating the first and second activation oltages, discharging., with the discharge path circuitry_* charge on the supply line fr m a begbning of the first time period to art end of the second time period.

19. The method of claim ί 8, further comprising:

applying, with the first activation circuit, the first activation voltage to a first discharge path of the discharge path circuitry its cause the first discharge path to discharge charge for the first time juried; and applying, with the secsiid activation circuit,. ihe second activation voltage io a second discba!f ? p th of the discharge path circuitry to e» e the second discharge at to discharge charge ibr the secoisd time period.

20, The method of claim 18_» wherein the discharge path clrctatry coinprsses a siagle discharge path, wherein j meraimg the second acdvaftsn voltage com rises generating, with the second activate circtwt, t e seeoisd activate* voltage on a same aode csa which t e- first activate voltage is generated, and whereto the method further comprises:

iimtot& atog,. with the second activs&ton- c rcuit, app Ikation of the second activation voltage m he node after the first time period esplnjs »otll the end of the secetsd time period