WO2017074592A1

WO2017074592A1 - Loop delay optimization for multi-voltage self-synchronous systems

Info

Publication number: WO2017074592A1
Application number: PCT/US2016/051840
Authority: WO
Inventors: Shiv Harit MATHUR
Original assignee: SanDisk Technologies LLC
Current assignee: SanDisk Technologies LLC
Priority date: 2015-10-30
Filing date: 2016-09-15
Publication date: 2017-05-04
Anticipated expiration: 2018-04-30
Also published as: US10348276B2; US9859874B2; US20170126213A1; US20180123570A1

Abstract

A clock-receiving system may receive a host clock signal on a communications bus from a clock-sending system. Circuitry of a critical path of the clock-receiving system may communicate the clock signal to a multiplexer configured directly behind output driver circuitry. Core logic circuitry and data path circuitry may communicate pairs of phase-shifted data signals to the multiplexer. The multiplexer may use the clock signal and the pairs of phase-shifted data signals to generate an output pair of data signals, and send the output pair of data signals to the output driver circuitry. In turn, the output driver circuitry may generate an output data signal for communication on the communicator bus. The clock-receiving system may enable the critical path and use the multiplexer to generate the output data signal when in a low operating voltage mode.

Description

LOOP DELAY OPTIMIZATION FOR. MULTI-VOLTAGE

SELF-SYNCHRONOUS SYSTEMS

BACKGROUND

jOOOt} in sdf-s>¾chroooiss systems, there may be a critical timing de½>\ referred to as clock-to-data loop delay (or sim l loop delay), for exam le from the time a clock signal is launched ton s host to a device to She time that data equested by the host may he mads available by the de vice. When the host has .re u sted data from the device, the host may launch the dock signal and thesi expect the requested data within a certain timing windo . The clock signal may ravel on a dock lin to the device, the device siay then process the req ested data, based on the clock signal, aad finally the device ma make the re sted data available to the host by seedin the requested data as a data line bask to the host ff the data m made available within the txmmg, window, thsa the read o er t on may he performed sitccessfulty. Ho ever, If the data is riot made available within he imin window, then the host may determine a timeout event and/or thai the device is usable to send the requested dat back to the h s

|ftO02| The timing window may be measured m terms of unit intervals fUI), For lower operat g |Ve »ericiex (eg,, aro nd 100 Megahertz MHz , the timing ind w ma he one unit interval. ( I Ui) in duration_* For higher o er tion, frequ ncies (e,g_i; 208 MMz the timin window may be two ¾m¾ mtemds (2UI) in duration. For Zl.li t m ng window coiifigw&u ons, the hos may perform a timing sequence within the 2ΌΪ timing indo to detettBtae the availability of the requested d ta, and t align its lock state using delay locked loop (DLL) circuit ,

|W§SJ The host a«d device may c mmunicate data, clock, and command signals with each mher accordi g to an operating voltage. In mtsltt- oltage etivhwMseot , the operating voltage ma be at a first, higher level or at second, lower level. Example operating voltages may fee 3.3 Volts (V) and 1 J V. The transistors configured in a critical pat of due devk-e- that are used to receive the clock signal frora the h st and generate the data signal for sending io ¾e host m&y ha e a certain gate tl»ck»ess that o imi es area sod reliability_* Ho eve , the delay caused by the rartslsSom when p ocessin the signals may differ for the different operatin voltage levels due to large loading. In particular, heo the- transistors are operating at the lower voltage level, the dela may b& si ifiearitiy higher, such as ato ad four times greater for example, compared to when, the taaslstors are oper ting at the higher voltage level As a result while t¾e- transistors may provide an adequately small amount of delay hen operating at the higher voltage level (i.e. a delay that ea ises data to he available- witMst the specified timing window), the may provide too large of a delay when operating at the lower voltage level fie., a delay that causes data to be available only afte-r the timing window as lapsed). So hat uested data ma be available within the specified timing window, de ices configured with reduced loop dela nay he desirable.

BRIEF ESCEir i OF THE EA IMiS

[0004} The accompanying drawings, which are incorporated in and constitute a part of this s cification iikstrats various aspects of the in ent on and together with the description, serve to explain its principles. Wherever con enient_* the sam reference nsmbers will be used throughout the drawings to refer to the same or like elements.

[0005_.1 Figure 1 is a block diagram of an example self-synchronous system,

[00061 Figure 2 is a block diagram of com onents of a clock-receiving sytem. of the self- s nch o us system of Figure 1 that may be included in a first critical path and a second critical path of the nou- olatile me r system.

[0007J Figure is a circuit schematic diagram of reference generation circuitry

confi ur d io generate a reference vo age. [000&1 Fig e 4 is a timing diagram of si nals generated by the eompoweists. s orn* Figure 2 when the ciock-i«ceiv!»g system k operatin in a high voltage mode f petati n_*

[00891 Figure 5 is a timing diagram of sign ls generated by the osro oaeats skwn m Figwe 2 wfeen the eloek-receiviag system k operating m & low voltage mode of operation. fftOl 0| Figwre 6 is a csrealt schematic of as example circuit configuration, of a second multiplexer of Figure 2.

(00111 Fi ure ? Is a eirciit sc emaic of an e ample circuit co lgisratioa of hybrid otttpat Wve citeuitt of Fiue 2,

(0012J Figure U is clrctit schemaic of m example circuit coafiguratloa of seeoud re^tfiver dreuitry of Figwe 2,

[08 | Figure 9 s s a flow ehart of an example metho of a clock-meei tog system generating a data signal for coftammfcation m a data line to a eiock-sedtng system.

|#01 | Figwte 10 sh s a How chart of another xample aietliod of a ctac&reoeivtng s stem generating a data signal for comtatinicstoft m a data ilm to a clock-sending system, (00151 Figure 11 shows a How chart of aaother example method of a clock-receiving system, generating a data signal for cornmiinfcatkss en a data ti to a clock-sending system, (016 F igare 12 shows a flow chart of another example ethod of a eck-receiving system ene tin a data signa for Ottramuuc iott Oii a data line to a dock-sending system. (0017| Figare 13 is a bl ock diagram of a se1.f-synck¾»ou& memory system that may implement the circuit com onents of Figures 2-8 and/or perform the methods described with reference to Figures 9-12. DETAILED DESCRIPTION OF PR S L Y PREFERRED EMBODIMENTS i i Overvfe

[00I9J The folfowmg eaAodaneat describe clock_^reeeivin s st ms of self-synoferosons syst ms that include a critical path confi ured to communicate a host clock signal to a mult plexer configured direetiy behind output driver dreuitry to reduce op delay for getseraiion of a data signal ore a dam Mm, In xm e ample etnbodstneats, tte doek-reeetviog system am utilize the critical path and the multiplexer for a low operating voltage mode ut uot for Ingtt operatiag vol a e m d . The output driver circuitry may include two circuit portions, one that generates the date sigstal m lite high operating voltage mode aad another that geaer ie tte data, si nal in he tew erating voltage taode.

gu#2§J la one examp e emhodimeat, a docfc-recdviag system ma include outpBt driver circuitry, critical patb csrc-uitry, aad a multiplexer circuit. The output driver circuitry may be c nfigured to gen ra e au ou u dais si n for conwuaieation oa a data Mae of a commti»icati.om bm. The critical pails circuitry ma be configured to generate a clock signal based o-n a host cbek signal received OR a clock line of the ews unkations us. The .multiplexer circuit may be configured to: receive a plurality of multiplexer in ut data signals, receive the ock signal from the critical path drcaitry, gen rate a pair of multiplexer output data s gnals based on the clock signal and the plurality of multiplexer iapat data signals, aad osit ifi tie pair of multiplexer oatpnt data signals to the output driver circuitry for generation of the output, data si nal,

[Will In another embodiment, a me hod of generating an ottlput data signal ma be performed. The method may include ontputtmg, with core lode circuitry, a pair of phase shifted core output data signals; generating, with data path circuitry, a. plurality of data path, output data signals bas d on the pair of phase shi fted core output data signals; generating, with critical path drctdtry, a clock, si nal based on host dock signs! received OK a dock line; generating, with a multiplexer csrc-ut , a pair of multiplexer output d ta sig als in es onse to recei.v¾g the pluralit of data path output sigaais from the data path circuitry and the clock si nal from the critical path droiitry; and generating, with out ut driver circuitr , ^•the data signal in response to receiving the pair of amltiptexer output data s gnals from the ^•multiplexer circuit.

M22| 1st some example mbs^toen s,, cote logic circuitry maybe ce&figwed to enable md disabl the .tlrsi critical path circuitry. Also, second critical path circuitry may be configured to genera e a iseeond clock signal based on the host clock signal, md data path eiresitty may he osnigursd to, whea the first critical path is disabled, generate a pair of data path output data signal s based on the second clod* stgstal sad output the pair of data path output data s gnals to t e output driver dretairy. The output dri er dneu try may be further configured to generate m output data signal in response to receipt of the pair of data path outpta data sign ls when the first critical pth is disabled.

M13| 1st some example mibedtoents,, data path dfeuitry may be configured to generate the plurality of multiplexer input data signals, T¾e piitraliiy of multiplexer nput data signals .may include a first, pair of multiplexer input data signals md a second pair of multiplexer input data signals,, where the f t md second pairs are phase shifted 1.80 degrees relative to each other with reference to the dock signal.

(0024) In some example emhodiraenfe, the Multiplexer dreuit may .include a plurality of ass gate circuits. Es&h of he pass gate circuits may he configured to receive the clock s ignal an one of the multiplexer in ut dat signals of the ?m\ md second pai rs of multiplexer input data signals.

[ 02 1 f» some example embodiments, the clock signal may include a pair of complem nt r clock signals, [0026J Ja some exam le embod ments, a rate of the clock signal is twice a rate of th plurality o mult plexer input data signals.

[00271 lit anot er example u^dlment a cloc H^ee ng s s em may include output driver circuitry and a multiplexer circuit The output driver circuitry may be co»figured to generate an output data si nal for communication n a daia line of a communications bus- Ira a itio , the output driver ctantry ma include » first circuit orta* eoafigured to generate the output data signal m high o era in vol ge mode, md a second eiraM portiott coallgured to generate the output data signal in a low operating voltage mode. The multiplexer circuit may fee configured to output and mmXs a first set of voltages at a first set of levels to deactivate the s c nd circuit portion in tie high operating voltage mode: md output md maktaia a s«ennd set of oltages at a second se of levels to deactivate the first circuit portion m the lo operating votege mode.

[ 28J In some example embodsrBents, cots logic dreul ry may be cot !gttred to coatroi whether the m lti exer circuit is configured to output the first set of voltages in he hi h operating voltage mode or the second set of voltages m the low operating voltage m de. (002&1 1» some example embo iment^ the core logic circuitry ma be config red to, in the high operating voltage mode, output a core output data s nal to the multi lexer for generation of the output data signal, and hi She low operating ve!i&ge mode, output a pair of phase shifted c«re output data signals to the multiplexer fo ge eratio of the output data signal.

[00301 I» some example mbodiments_* the multiplexer ma he configured to, its the high operating voltage mode, output_* to first data path circuitry, a first pair of multiplexer output data signals for gen r tion of the output data signal in resp nse to receipt of the core output data signal, and. m the low opera ing voltage mode, output, to second^' data path circuitry, a secon pair of multiplexer output data signals and a third pair of multiplexer output da a signals. The second pair may be associated with a first data sigual of the pair of phase shifted core output date signals md the third pair ma be associated w¾h a second data signal of (fee air of phase shsf ed cote output data signals.

[003! 1 In s me exam le embo iments, in. the high operating voltage mode,, the first data ^•path circuitry may b configured to generate a first pair of data path output data signals based o.n. the first pair of multiplexer out pal d ta sign&k, and output e {list pair of data path output data si nals to the first circuit portion of the output driwr circuity for generation of the data signal. Also, in the .high opera ing voltage mode, the s cond data path circuitry may be configured to eneate a third set of voltages a? a thi rd i of levels to the seeond circui t portion of the output driver citcuitry for deactivation of the second dtmlt portal. In the low o mm g voltage mode, the second data path. dt¾uiity may be configured to generate a second pair of data path output data si als based on the s ond and third pairs of tnaUip!exer out ut tte signals, and output the second jalr f ata path utpu signals to the seso dreuit a te of the output driver elrei try for gersenstio of the data, signal Also, in the low operating voltage mode, the first data path circuitry may be configured to generate a fourth set of voltages at a fourth set of voltage levels to the first circuit portion, of the output driver circuitry for deactivatiou of the first circuit portion.

(§0321 ¾ some essruple embedm nts, the second data path circuitry uay include a pre- driver circuit that ktdwfes an output node, and first, second, and third t ansistor circuitries. The .first transistor circuitry may be connected to the output node and configured to be supplied with- an input/output (I/O) voltage sad pull up a voltage as she output node to a level of the I/O voltage. The second transistor circuitry may be connected to the output node and configured to pull down the voltage at the output node to ground_* The third transistor circuitry may be ongeste to an internal node of the second transistor circuitry and configured to be supplied with a reference voltage, where a level of .foe reference voltage may be o e than a level of the I/O voltage m the Mgh operating voltage mode,

[00331 In wms example enibo iin:sent¾. he se ond data path circuitry may further include level shifter drcuitry configured to generate first and second pairs of level shifter output data signals based on the second and third pairs of multiplexer output data signals. Each of .foe first circuitry, the second circuitry, and the third dreuttry of the p¾»driver circtdtry may include a data signal, input connect to a « o¾¾> t of the level shifter rctiitry.

[@0 | in som estample embodiments, e m thod may further Include: en blin , with t e core log c dratkry, the critical at in response to fcte«« ng that a host interface operating in a low operating voltage mode ,

[0035J Its some example emtsodiments_t the multi le e circuit may .indude a first multiplex r dreuit, and the pair of. multiplexer output data signals tnay include a .first p ir of atdtiplejter output data sig als, and the data path circuitry m y Include a fet data pth dreuitfy. The me hod may f rther haclude: b a sec nd tr tiplexer, ouf utting second and third pairs of multiplexer output data signals in .response to receiving the pair of phase shifted core output data signals from the core logic circuitry to the first data path drcuitry, while outputting a first pair of voltages at constant levels to seeoiid data path dreuitry: and oatpnttmg, with the second pails circuitry,, a s&eoad pair of voltages at constant levels based on the first pair of voltages- For these example em odiment , generating the plurality of data path output data signals with the first date path circuitry may be- based on the second and thi d pairs of mul i lexer output data sigaa-ls, and generating die output data signal may include generating, with a fi rst circuit portion of the output driver circuitry, the output data signal in response t receiving the first pair of multiplexer output data signals while a second circuit portion of the output driver c rcui ry is deacti ated m response to recei ing the second pair of voltages_* s |W l Other embo iments are possible, am each of the embo iments cm be used alone or together hi s Mmti _* Accordingly,, various embodi ents will BOW he described with reference to the attached dr wings,

[0037J V^m^f Emb mm s

| 3$| As mentioned hi the hacfcgroiaxi section, transistors i» a critical, path of a device o mt rg m a sdf~syad>ro«o»$ system may provide tots k¾«g of a cIock o-data loop delay (or simply lo p delay) wh t the devic is operating according to a lowe operating voltage such that the device is ursable to t ka requ sted d t available to a host system ithta a timing windo that is reeogrstad sad monitored by the host s s em. The following embodiments show as example d vice that rednees the loop delay for host clock signals generates! at a lower of two o erating voltages for which the de ic is designed. I» p&rtkttkr, the device ioclades two critical paths associated with two different ope atie voltage levels. Each critical path includes eteukry configured to receive a host clock s gnal on a clock Urn from a os and, based on the received host clock signal, ge er te a clock signal that Is used to generate a data signal for connnnni cation a data line back to the host. The critical path associated with the lower of the two operating voltage levels may provide shorter loop May for the host clock signal at the lower voltage level compared to the loop delay provided by the critical path associated with the high voltage level for that gains test clack si nal The device .may be configured to delect the operating voltage level, and based on the detection, enable one of the critical paths while disabling the other,

[00391 Figwe 1 shows a Mock diagram of an example self' -syttchroitous system 100 that includes a clock-sending system 102 and a clock-receiving system 104. In the

self-synchronous s s em 100, the eloek-seading system 102 may send a clock signal to the clock- receiving system 10 , and the clock-receiving systero 1 4 ma be configured t operate and ammwrocate with the ctack-seitdirig system. 1 2 mm the clock signal, |O04#J Ja some exam les,, the clock- sessdiag system 102 may be a ost or a master device or system, and the clwk-recdvmg system 10 a fee a slave device or system, In addition oraliomalively, the c!o k-rceci m s stem 102 ma hav or store Wormatioa or data that ^•the dock-sending device 102 wants. The clock %tgml mat by the eloek-seadiug. syste 102 ^•may be used in order to r sfer the desired mlbmsaton or data from the- cioc -receivisig s sem 104 to the eloek-seiKt ig ystem 102. As used herein, the clock signal, .seat by the doek-sendiag system 102 may be referred to as .a host dock sigaak

|I¾ :I.| At a given p int m time or period of operation, the eloek-sendmg system 1.02 ma be configured to se d the host clock si nal at one of a pluralit of different operating voltge le els. Which level the clock sigtml is setii stay depeod on the eoa «ratio« of the clock-sending s stem 102, a protocol isader which the clock-sending and/or ctod^reeeivteg s ste s 02, 104 are confi ed to peate, mdior m operation, mde at which the eloefccitdmg s stem 102 an or the dock-receiving system 104 ae operating, As described m further detail below, the cloek»fceeiving system ! 04 may Indttde two critical paths for commuttkttAtan »fthe hos clock signal m order to send the reveted data back to the clock-sending system 102, Which path the clock-receiving s stem 104 enables and which path, the dock-receiving system 104 disables may depend the level of the opeisdag oltage.

|O042j The clock-receiving s tem 104 ma include core logic dre ltry .106 that ma perform functions specific to the clock-receiving system 14, Generally, the core logic eiretihy 106· may have or obtain the data or o«»ation that the cloek-seadisg 102 has requested. The clock-receiving system.104 may also include a host interface 108 to communicate with the cfock-sendiag system 102, The host imet&ce I OS -may lie coupled to a communicati ns ha i 10 on which the host interface 108 sends and recei ves signals to and from the olock-sesdmg s stem 102, As described in further detail below, te os interface i0 108 ma include driver circuitry configured to generate the signals, such as by pvlUng p to a high level and pi ting do n to a low level voltages m the Hues of the commmieaions b¾s 110.

[0031 The coiamonacaiitTO bm 110 tnay include a host clock line 112 on which the ei ek-seadmg system 102 ma send a host dock signal CLKf_$g_$r t» the clock- recevin s sem 104; an N-mtm er of data lines I 14[N^»1:0] on which ite dock-sending syste 10 and the dock-i^er ing system 104 tmy e«m a ic&te data si nals DATN-1; | with each otter; and a command line 1.16 cm which the deck-send g. s stem 102 am! the

etaek-reeeivmg s st m 104 may commu icate e mm i slgtmis C D and res nses RES with me eher. Th dm signals DAT[NM:0] may include dais that ine ciock-sesidkg system 102 wants to receive fwm the clock-receiving system 1.04, Comman signals CMD sent fr m the doek~se»dmg sy tem 1Θ2 may instruct or : qaes that the clock-receiving system 104 perform some ae a, sMclt as perform m operation, tansi!s it into a certan state, or respond with tem ese dam or in formation, as example. The response signals RES sent from lite dock~*eee.iving s stem 104 may acknowledge receipt of the comm nd signals CMD, indicate that the instmetedactiou is performed, or include the requested infommti n, as examples. As described in further detail below, the host clock, sigitai CLKH ST saa set the fre uency at which data, and/or coimitassds CMD are communic te on the e«tn«unkatioas bus 110 andbr control the dat flow by providing the times aridor rates at w ich the host efoek signal CiJC^sr and data signals DAT| -I;0] may be sampled by the clock-receiving s stem 104,

[Θ04^'| The clock-sending system 1.02 and the d ck-reeetviag syst m 104, using the host interlace 108, may e configured to generate and communic te- the cioek, data, and comm ndrspond sig ais CiK« sr_> DAT£N ;0]₍ CMD/RES in a»d/or corresponding to a leas ne of 8 plurality of operating voltage d mains . The plurality of perating voltage

1.1 domains may i clu e at least two operating voltage domains: a high operating voltage domain and a tow o e a ing voltage domain_* For a example e nJSgum ns, mo e than two operating vol age doniaias may be ossi le

g#045J Each of the operating voltage omains may have an associated .high voltage le vel and an associated low voltage level Additionally, each of the operating voltage domains ma have an associated high voltage range within which the associated high voltage level, l es and an associated low voltage mrtge wUhm which the associated low v ltage level lies. The high voltage level associated with the high operating voltage domain m be higher t an the high voltage level associat d with the low oper&tktg wtep doetai A signal ge erated In a particular operating voltage domain ma tmrtsitten between a high level i!¾at is within the associated high voltage range and a low level thai is within the as ociated low veliage range. W46 The eloek^ending system 2 and the clock-receiving system 1.04 us ng the h st ioter!aee 108 may be configured to gene a arid e nmainkats the clock, data, and eomtna signals CLKKST, DAT[ ^«1 :0], CMD/R1S in lie high opemtfng voltage donaain,, the tew operating voltage domain, or both.. As used herein for simplicity, and unless otherwise specified., a signal being generated and/or communicated in the high operating voltage domain or the low operating voltage domain may be syno mous and/ear used

interchangeably with a signal being generated nd or eonnttunicated at and/or according to a high operating voltage level or a low operating voltage level, respectively, where the high operating voltage level refers to the high voltage level associated, with the high operating vol tage domain and the low operating voltage le vel refers to the high voltage level associated with the low operating voltage domain- In other words, as used herein, a signal generated and/or communicated a* arid or according to the high operating voltage level m y mean that the high level of the signal, is at the associated high voltage level and½r w ao the associated high voltage ange of the hig operating voltage domain_* Likewise, a signal generated and/or

n comnswracafed at sa or according to the tow operating voltage level may mean thai ihe high level of the signal is a the associated high voltage level aiid of ithin the associated high voltage range of the lo opemttng volta e dom in. Similarly, as used herein, a voltage enerated, supplied to„ and/or recei ed by a circuit co poaettt (e.g., a traasistor) at trad or according to the high operatiag voliage domain and or the ^'high operating voltage level may mean that the level of the voltage Is at the assoc ated high voltage level and/or within the associated high voltage range of the igh opersfeg voltage domain. Likewise, a voltage generated in/at, su l d to. and/or received by a circuit com nent at an /or accordin to the tow operating voltage domafe and/or the lo operating v tage level t y mean ttet the level of me voltage is at the associated high voltage level and/or within the associated high voltage range of the low voltage domain,

[<KM7J In one ex mple configuration, the high perating voltage domain may be a 3.3 V o rstlstg voltage domain, and e to operating voltage domahi may be a 1.8 V operating voltage domain, A sig al enerated its the 3 J V operatiag voltage domain and/or according to the 33 V o erating voltage level may ir ns oa between a .high level e r Ks J ndin to 33 V (i.e,,. at 3.3 V and/or within a voltage range associated with 3.3 V) and a low level corresponding to 0 V (i.e., at 0 V and/or within a voltage range associated with 0 V).

Similarly_* a signal ge erated ia the iJ V operating voltage doraaia asd or according to the IJ V operating voltage level may ts&nsrtion between a high level corresponding to 1.8 V (i.e., at IJ V and/or within a voltage range associated with 1,8 V) and a low level con¾spo*wfi»g to 0 V. Likewise, a voltage generated at and/or according to lite 33 V operating voltage may have a level that is at 33 V and/or that is within a voltage range associated with 33 V, and a voltage gener ted at and/or according to the 1.8 V operating voltage may ha e level that Is at I M V and/or that w within s voltage range associated with 1.8 V. Hgh aud low levels lor the operaihjg veltage domains other than or i ddition to 3.3 V and I V tmy be. possible.

it? sddsti a, as s own m Fig, I , ibe cloefc-send g s stem 02 ma supply a su pl ^•voltage VCC an a suppl line 118 to ΐ-he clock-receiving system 1 4· to power c m nents of the clock-receiving system ! 0. Vol ges supplied to circuit components of E e

clo k-receivtog s stem 104 may be generaed based on the supply voltage VCC, For e am le, althugh not sh s ts Kg.1 , the host irnedace 1,08 may include a .r gulator that recei s the supply voltage VCC. Based on receipt of the supply voltage VCC, the regulator ma be configured to getrat-e a voltage at the high operating voltage le el or die low operatmg voltage level, and provide the voltage to otter circuit components of the ost interface .108 ,

[ 049J The host interface 108 ma be configured to o erate in both a high operating wltage mode and a low operating voltage mode. When the host, interlace 1 8 is com t treati g with the doek^endmg syst m 102 via the eo tmmikatioM bus 1 i O m the high operating voltage domain, then. the host interface 108 may be perat i n the high operati voltage mode, d vice versa.. Conversely, whe the host interface H>8 is eo mnnie&ting with the .host sysfcera 102 via the communicati ns bus 1 ϊ in. the low operating voltage domain, h a the host interface 108 may be operating the low operating, voltage mode, and vice versa,

[00S&I When the clock-sending system 102 requests that the clock-receiving system.104 send it data, the core logic c cuUr 106 ma provide the data to the tost interface I CIS, which m turn may ser*d the data as data signals DAT[ -1 :0] to (he ciock-sendsug s stem 102 on the -nomber of data Ikes Ϊ 1S|N-1: |.

[0051^'J Tlie clock-receiving system 104 v ? ms, the host clock signal CLKnosT received oa the dock ii I 12 to generate tie data sign l OATN :Q] that are scot back to the eioefc-sending system 102, in particular, eettain circuit components of the tost inter&ee l&$ and/or tfee cor logic cinantry 10» at y receive the ost dock s gnal CLKHO-ST* or at least a bta¾red wrsion of the host dock si nal CLK ST* and _.pal! «p and down the levels of the data signals 0AT N^»i:0j according to the rats- of the host dock signal (is,, according to the rising and/or falling edge occurrences of the host dock signal).

j 52) The cloek^endln system 102 may be configured to monitor ami/or keep track of a timing window when requesting data from the elock-rewiving s stem 104, The clock-sending system 102 ma identify an initial or starting time of the timing window,, walsh tray correspond to an initial time that the host system 102 sends the host dock signal CL H»T and/or a dock pulse of the host clock s gnal C K st that the dock-sending system 1 2 sends for die teque&ied data to be sent hack to the host system 102 on the data lines I !4[NVI :0], Ϊ» s me example eonfigunatsons, the timing window may correspond to a number of anil intervals (lil), here each IJ! eorrespoads to a sing e time period or cycle of the host clock signal CLKH ST- ^ *^e cf«cfe-se« in system. 102 has not received at least some of the requested data on the data lines .1 14[N~1 :ø] upon exp- miioa of the timing window, the dock-sending system 1 2 may identify a timeout event and/or determine that the eloek-teedving system 104 is unable or unavailable to send the requeste data to the clock-sending s stem 102. As a result, the reques for the data may not be completed.

(0053) A critical path of the clock-sending system 104 may be a path along which the ^'host dock signal CL½st propagates within the dock-sending system 104 to generate the data signals DAT N-! ;0], Whether the data signals BATf ~ i ;Q] are able to be generated and sent otn on the date lines 1 14|[N~^'i:0^') within the timing window may depend on the critical ^•path and die delay provided by the critical path to commu cate the host clack signal

CU tnwr aod generate the data^, si nals DATf - 1 :0j using the host clock signal CiXnomr_* The delay provided by he critical, path may be referred to as a cioefc-to-data loop delay (or

1.5 simply loop delay). The shorter the loo dela , fee faster the host raterraee 108 of the clock- receiving s stem

on the data l nes 1 f 4[ -0] for seadteg back to the clock-sending system 102.

[0O5 J The clock-receiving system 104 ma iaefade two critical paths to c jftmunieaie the host clock signal CL _¾«_f and generate a data signal wittt tie host clock signal CLK_HOS_T to' eoiTOTOsieatkra on a data !iae back to the c ek-se io s stem 102, lie two critical paths may mclade a first critical path io c m mMieate the hosi clock signal CL¾¾¾r a¾d generate a data signal mmg the host clock signal CLKHOST hen: the host ieterfaee 108 is operating in the h gh operating voltage .mode, an a second critical path to coamnt&teate the host clock signal CL¾o?ii a«d generate the data signal mifig the host dock signal CL¾ t when the host interface .1 8 opemtiag in the to perating voltage mo te,

|W55J Fig. 2 stows a block diagram of disait compon s of the clock-receiving system 104 that may be included in the first and second critical paths, For sorac example coailgtirations, »ther than the core logic da ritry 106, the circuit c«»po«ents shown in Fig. 2 may be pa t of the host interface 108 shown in Fig. 1, although in other example

confi urations,, me or more of the cire-ait com onents may he separate from the host interface l t. The first critical path and the second critical path, may each be configured to generate a clock signal based the host clock signal CL _HOST then use that clock signal to generate a data signal, which turn may be converted into a data signal DAT that is communicated on a jih data line .114 ] of the N -number of data lines 1 14|M^«! :0] back to the clock-sending system 102, When the host interface 108 is operating the high operating voltage mode, the data signal DAT may be generated based on the data si al generated with the first critical path. Alternatively, when the hast interface 108 is operating the low opemting voltage mode, the data signal OAT may be g ner e based on the data signal enerate with the second critical path. The seeoffil critical path may provide shorter loop delay to generate the data si n l DAT compared to the first critical path.

In further detail, the firs critical path associated with the high operating voltage level may include a first Schroiit trigger 202» clock level shifter eira»tiy 204, first clock driver eireitiiry 206, and data generati n circuitry 2 ί 6 located in the core logic circuitry 1½ The circu t co onents of the fet critical path may be coaft ired to receive tie ost cfock si nal CL uosT on the host clock line .112 and generate a first clock signal CLK l 2 based the b st clock signal. CIJ¾<» Th« seeottd critical path associated ida the low op rating voltage level may include a seco d Sehmitt trigger 208, second clock driver circuitry 214, a clock uff r 210, n a s cond trmhiplexer {^'MUX) 212. The drcoii eatapeneals of Use seeead critical path may be configured to receive the host clock sigaai CL HOST on the host clock l ne 1 12 and generate a second clock signal CLKl 8 based o» the bost clock, signal. M57J Wfees¾ the mi interface 108 is operating in the high operating voltage m de, a data sig»a! 12 may be generated by the core logic Cifeaiiry 106 with or nsmg the fet clock signal CL 12, As described in farther detail below, the data signal 12 may then be converted, using additional circuitry, into the data signal DAT that is comtiinnicated on the jth data line 1 140}. However, alter the data signal 12 is generated, farther or additional clock signals ma rsot e us d to convert the data signs! 12 to the data signal DAT.. Alternatively, when the host- interface 108 is operating in the low operating voltage mode, a data signal gate 18_» which a Inchide a pair of directly aligned data signals ngate l S and pgatel 8_* ma be generated by the second multiplexer 12 with or using She second clock signal CLK! 8, As de cribed in farther detail below, the data signal gateiS ma then be converted., usi g additional eirettiny. Into the data signal OAT, However, after the dala. signal gate! 8 is generate , further or additional clock signal ma not be used. t» convert the data signal gate 18 to the data signal PAT.

[0Θ58! The core logic circuitry 106 ma be omiiguted 1» detemriae hether the host interface 108 is operating in the high operating voltage mode or the low operating voltage" ^•mode. Based on the determination, the core logic circuitry 1 $6 ma ^'be configured to generate a path enable signal LV thai enables or dis b es the sec« critical path. That is, when the c re logic cireuMry .106 determ nes that the host interface 108 s operating m ihe low operation voltage mode, the core logic circuitry 108 .may generate toe path eaafcle signal LV to ea&ble he second critical path, and hoa the core logic circuitry 106 teisfjoiries that the host in er ace 10S is operating the high o e atin voltage ode, the core logic circyitry 108 may geaemte fee path enable signal LV to disable the second critical path, W en the second critical path is enabled, the- second clock si nal CL .18 may be osed to generate a data slgsaf for sammuntcatkut on the jth data Hoc 11 [j j. Alternatively, w en the second critical path is disabled, the f i clock sijpal CL I2 m y be osed to generate a data si nal for communication on the jth. data line 1 140 ]-

In farther detail as sh ws* so Fig, 2, each of the first S bmStt trigger 202, the second Sebiaitt trigger 208, and the second dock d ive circuitry 214 may be configured to receive the path enable signal LV.. In addition, each of the first Sehroitt trigger 202 and the second Schmitt trigger 208 may be configu e to receive the host clock signal CL¾og:₅ on the dock line 212,

[ i When the core logic circuitry 1 6 eteimines that the host interface 108 is operating in the high operating voltage mode, the core logic circuitry 106 rosy generate the path enable signal LV such iha. the first Schmitt trigger 202 is enabled while the second Scfefsitt trigger 8 and the se«o»d clock driver circuitry 14 are disabled m res onse to the path enable sign l. LV. Alternatively_* when the cor logic circuitry 106 0¾ensi es tha the

IS host interface 108 is operating in th& low operating voltage mode-, ihe cots? logic circuitry 106 may generat the at enable signal. LV suc tteat the fi st Sehmitt trigg r 202 h disabled while the second Sehraitt logger 208 and the second clock driver circuitry 214 are ena led in response to the path ena le signal LV.

|ftWl J Irs the high operating voltage mode, with the first^" S hmitt trigger 202 activated md t e sec nd Sehfnitt trigger 208 d^ciivated, the first Setaitt t gger 202 may poeraie a ciock signal GLK33 ased m the h st clock signal CLKaosr a»d ut ut the clock signal C.L 33 to the clock level shifter eiremiry 268 and the seceod clock driver elrcttMry 214, As described in farther detail below, the clock level shifter eireiiitry 208 aad the first cloefc driver circuitry 206 of lie first critical path ma tiers convert the clock signal CL 33 Into the first host clock signal CLK12 and send t e first host ciock signal to the core logic eiroa fery 106, Using the first clock signal CLIQ2, the cote logic circuitry 106 may enerate the data signal 12, which m turn am be converted to the data signal DAT without se of far her clocking. Also, since the second clock driver circuitry 214 h deactivated the high oper t g voltage mode, the ec nd clock signal CLJQ8 .may m be generate ith the second critical path in rder to generate the data signal DAT,

(00621 Alternatively, in the low operating voltage mode, with the first Schmilt trigger 202 deactivated and the second Schmttt trigger 208 activated. She sec nd Sehmitt trigger 208, rather than the first Sehrrait trigger 202, may gene ate the clock signal CU 3 based oft the host clock signal. CO¾OST »» oatpnt the clock signal CLK to the clock level shifter circuitry 288 and the sec nd clock dri e circuitry 214. As described in farther detail below, t ough in the low operating voltage mode, the clock level shifter circuitry 204 and the first clock dri er Circuitry 206 may still generate the first clock signal CLK 12 for use by the - ere logic circuitry 1 6, However, the s cond clock driver circuitry 214, being activated, ma generate the- second clock signal CL il.₍ and the second multiplexer 212 may generate the data signal gatel 8 for generation of the- da a s gnal PAT based m the second clock, si nal CLJU8.- [00631 the high ope atin voltage mo e, the second critical pat may be considered disabled since it not nsed to generate the data signal DAT, .1» the low erating voltage ^•m 4e_> the second critical path may be conside ed enabled since it is used to genemte- the data signal DAT, Enabling and disabling the second critical path Is described m ftarfe detail below,

[0064^'f The circuit components shown in Fig. 2.may each receive aad be po ered by one or mote of a plurality of voltages, hseinding an 10 voltage VDDO, a core voltage VDD, and a refeeit.ee voltage REF. The ΪΟ voltage VDPO is generated at the high operating voltage le vel when the host interface 112 b operating n¾ the .high operating voltage mode, and is generated at the low operating voltage level when the host taterfe-ce i 12 is operating at the low opetattag veltags mode. The 10 voltage VDDO ma be generated «stag -regulator dreiitry or other voltage generati n dreuitry of the clock»reeeiving s stem 104 based on the sup l voltage VCC, Se&ing the ID voltage Vl 00 to be at the high op rating voltage level or the low operating voltage level is outside the scope of the present description,

[0065| Its addition, the level of the core voltage VDD may be the level at which, the core logic circuitry 106 operates, In general the level of the core voltage VDD may be lower than the low operating voltage level In oise example con%uK_tion_* the level of the core voltage VDD may he 12 V, while the low operating voltage le vel is 1 , 8 V and the high opera ting voltage level is 33 V.

[0066^'i The reference voltage REF may he gewetated at the low ope-rat tg voltage level, and may be generated at that, level both when die host interface 108 is operating -in the high operating voltage mode and. in the low operating ltag mode. As described in further detail belo , the .refiareace -voltage REF may he used m ener te the second clock, signal CLE, I I and the complimenta y clock s gnals QU .l8ji» CLK^'l 8Jb provided to the second nmidplexer 12,. Additionally, when the t interface 108 s opetstra is the high po e -mode, reference voltage R F may be used to protect cert in circaii <%s*npane«J$ (e,.g, , troasfctare) ^•that are used for generatiori of the data signals m the low operating -v ltage mode,

|IM½7| As sho n in Fig. 2, refe e ce generation circuitry 2 6 ay foe included to generate he reference voltage REF, The reference generation eireuhry 316 ma receive he 10 voltage VDOO. Additionally, the ref rence generation ctr ritr 21.6 may . eceive t e path enable signal LV k order to ene ate the reference voltage REF at lis; low operating voltage lev l whes the 10 voltage V^'DOO is either at tbe low oper tin voltage level or the high operating voltage level

|iM &8| Fig, 3 shows a eirenft sehernat e diagram of an. exam le circu conS u s&m for the re&rence geaetsto circrdiry 216, The exa ple circuit conf mtion ma mehjde a first p-chsmrtel nieid-axid -scfBteowd ietof -field-efffect transistor <P OS tssraister) M i. having a source termtas) configured to ecei e the 10 voltage VDOG, a drain temimai connected to ¾ first end of a first resistor R.I , and a gate terminal configured to .receive the pal enable signal LV. In the ckcnit configuration show** in. Fig, 3, the pa enable signal. LV may be generated at a logic low level (e. ., ϋ V) when the host inte&ee 1 1.2 s k the high, oper&ttrag voltage ^■mode and &t a logic high level when the host interface 1 12 is in the low epera ag voltage mod . The logic high level may he the high operating voltage level

(•Wg A first n-channel n¾ial-o»ide-&emiconducior field-effect transistor ( MOS transistor) :2 may include a draw ieramn l connected to a first end of a second resistor E.2, a source teftrtinal connected to a ground reference voltage O i and a gate terminal connected to an inverse path enable signal LVJ>_* (Inverter clrenitry to invert the path enable signal LV in order to generate the invert path enable signal LV J? is not shown fo simplicity}_* The level of the inverse path enable signal. LVJ may be the inverse of the level of the path enable signal LVJ% Accordingly, when the host interface 1 Ϊ 2 Is in the high opcratsag voltage mad , t e path enable signal LV may e at its logic la level (e.g., 0 V) and the inverse path enable signal LVJ may be at a iogk high- level, which may be the high o erating voltage level Further, hea the host interface 1 12 k in the low operating voltage s¾cscte, the path enable signal LV may ^'be at its logic high level

the low perating voltage level), and the nwetse path, enable signal LV b may he at a logic low level (e.g., 0V)„

(80701 Additionall , second ends of the first and second restate R _s 12 may be connected together at a node A. A second NMOS tra s stor M3 xmy have a drain terminal connected to node A, a. s u ce teranaal connected to fee ground reference voltage O^'NI⁾,. and a pte terminal configured to receive the path enable signal LV, A transistor M4 may ha e a drain terminal configured to receive the 10 voltage V^'DDO, a gate lermlaal connected to node A, and a source terminal connected to a source torrninal of a second PMOS tr nsisto MS at a nude B, The second PMOS transistor M5 may have a gate terminal co figu ed to receive the path, enable signal LV, and a drain terminal connected to a re erence node at whkh the reference voltage EEF is ge e a ed, A third PMOS transistor M6 may have a source terminal configured to receive the IO voltage V^'DDO, a gate terminal configured to .receive the inverse path enable signal LYJb, and a drain terminal connected to the refere ce node at whic the reference voltage REP is generated.

(00711 F r some example configuratio s_* the transistor M4 ma be a native V* (NVT) transistor that operates as a sonree follower. In particular, the threshold voltage V t of the transistor M4 may be at or near 0 V such that the voltage generated at node 8 follows^; the voltage generated at node A, Using a ^"NYT transistor for the transistor M4, the reference voltage EF may he equal to the voltage at node A when the second PMOS transistor MS is t rned n. In other example coirfigamiioris, a NMOS trans stor with a. threshold voltage greater than 0 V may be used tor the transistor M4, For these other example conltgoratjons, the voltage generate, at node Λ may be increased by the threshold oltage of the NMOS transistor in order o gene a e » desire efee taj voltage REF,

[00721 in the fejgt* ope atin voltage mode* the first FMOS transistor Mi may be turned on, the first NMOS transistor M:2 may ^'be turned on, and the second NMOS transistor M3 ma be imed ol As a resul a voltage Ngate jref may ^'be generated at node A at a level thai tm o» the third NMOS tnuts&tor 4. Also, the voltage at node- B may be eq al to the voltage Ngste _ref less the threshold, voltage Yth of the transistor M4 (where- the transistor M4 h configu e its a NVT traosisi , the voltage Ygate_ref may also be gerterate a node B sto.ee the threshold voltage Vti ma be zero). With the path enable signal LV at the logic low lev l, the second PMOS transistor MS may be maied on, and the third PMOS t a si tor Μδ may be turned oft^". With the t ansistors Ml -M6 to their re& eeuve on and oil slates, the le vel of the voltage generated at node .8 may he about the low p ra ing volt g level and/or, in s me coral! yr tions, may be about 55% of the high operat ng voltage level With he second PMOS transistor MS turned on- the level of the refer nce voltage REF may be about the sam as the level of the voltage generated at node B,

[0073J In the low operating voltage mode, the first PMOS transistor Ml ma be turned off, the first ^'NMOS transistor M2 may be turned oiT_s and the second NMOS transistor M3 ma fee turned on. As & result, the voltage Ngate j¾# ay be pulled down to gronad such that the transistor M4 is turned oil The sec n FMOS tensktor MS may also be lurried il, am! the third FMOS transistor M& may be turned on. With, the transistors M 1 -M6 in their es ecti e OR and ίί ^'states, the level of the te&resce voltage REF may be about the level of the 10 voltage VDDO, which m the low operating voltage mode k the low operating voltage level. Accordingly, the level of the reference voltage REF is shout the same regardless of whether operation k m the high or the low operat ng voltage mode. [80741 .Referring back to Fsg, 2,. generation of the date, signal DAT when the host interface I 12 is in the high operating voltage mode Is now described. Reference m also roade to Fsg, 4, which sho s a timing diagram of data si nals and clock s nals hai are generated with the chxmi components shown in Fig. 2 when the host Interface .! 12 is m the high operathjg voltage mode. For sunplteUy,, ra accurate depiction o -relative delay etw n .rise times and fall times amo g the si nals i Fig, 2 is omitted,

\W?5 As previously described, in t e high operating voltage mode, the path, enable sign l LV ma enable the first Sehmitt trigger 202 and disable the second Sehmitt trig er 208, i response, the fct Schmlit trigger 202 may geaetaie the clock signal CL 33 sad ooipnt tfei c ck signal CL 3 to the clock le el shifter circuitry 204. As s wn la Fig, 2, the clock level shifter circuitry 204 may receive the 10 voltage VD O and the core voteg VDD. The clock level shifter circus try 204 ma be hig o-low level shifter i*t that the d ck level shifter circuitry 204 m y convert the clock signal COG3 in the high operating voltage d main: to a level-shifted clock signal CL 1 _ pre in the core voltage omain, The le vel-sbifled clock signal CLK.12_j>re may he output to the clock driver ci cuitry 206, In response, the dock driver cirenkry 2 6 ma generate and output the first clock signal QUO 2 to the core logic circuitry 106,

(007 ! As pre iousl described, the core logic ciiCiatry 106 ma be eonilgored to generate the data signs! Ϊ2 using lie first clock signal CL&J2, The data signal 12 may mciade dste that the clock-receiving system 1.04 wants to send to the clock-sending system 02 and¾r data that the oioc-k-setiding s stem 102 wants to receive from the clock-receiving system 104. The data may hjchide data that the core logic circuitry 106 has internally generated, stored, -retrieved from another component of the clock-fseeeivmg system 104, .from a component external the clock-receiving system 104, or sonic combination thereof Using the first clock signal CL ^'12 to generate the data signal 12 may «iea?t that the core logic

74 c:trctik:t 106 pespn s to the transitions (rising edge and or Ming edge transitions) of the first clock signs! CL !2 t© generate the data, si s! I2₅ %wh as by itch g or operating in response to trsnsUioiws of the first clock *i.g»a!€LK!2 and/or ¾»»s ioaj.sg th© data signal. 12 between high and low levels m res onse traasitions of the first clock signal CL I .

|ftft77J Alter Che data signal 12 k gen rated by the cor logic circuitry KM, the core logic cfeitry 1 6 may ou put the data, si nal 12 to a fmt data path associated with the h gh operating voltage mode, Circuit components, of th first data path ma con ves the data signal. 12 to the dam signal DAT, The firsi dam path may dmk a first multiplexer (MUX) 218, first le vel shifter ci c itry 220, tat pro-driver elrewttry 222, and a hybrid e«tp»t driver eireaMry 224, The hybrid output driver dteuitty 224 ma he the circuitry that g nera es the d ta signal DAT sad outputs the data si ns! DAT on the jth data line I !4¾], whether the hos interface 1 8 h m. the high operating voltage mode or the low operating voltage mode.

|§0?S| In further detail, to es onse to receipt of the data signal 12 from the core logic cfeitry 106, the fits? multiplexer (MUX) 218 ma gener data, signals <taJ2, dpJ2 based o the mm signal 12. As sh wn la Fig, 4, the data si nals da J2, dp J2 may be directly ali ed with each other, as well as directly aligned, with the data signal 12, As used herein, two signals arc directly aligned with each other when they transition high together and transition low together, not accounting for delay between the signals. Ftnt&er.. as used herein, signals are inversely aligned if when one signal transi tions high, the other transitions low, not accounting for delay between the two signals.

\W1% In addition, as s o n is Fig, 2, she first multiplexe 218 ma receive and be powered by the core voltage VDD. Accordingly, the data signals dnj2» dpJ2 outpnt by the first multiplexer 21 $ may he ener ted in ie core voltage domai , as shown in. Fig, 4.. The first multiplexer 21$ may send the pair of data signals. dnj¾ %J2 to the firs level sMfier OHPcatfcy 22©, As shown in. Fig. 2, the first level shifter circuitry 22(1 may receive and be powered by the core voltage YDD and the 10 voltage VDOO. The t¼t level shifter eireaiir 220 mm be a !o -to-hifh. level shifter that converts the da a signals d»J2, dp_.j2 in the co?e voltage domain t» data signa s d«33, dp33 In he high operating ol ge domain. As sho n in Ftg. 4, the data signals dts_3.3, dpJB n? directly aligned with each other, as well directly ali ned with t e: data signals dn J2, dpji2 and the data signal 12.

\Wmi The first le e shite etoiit 220 may se the da a slgn&k d»33. dp33 to f t re-driver dreniiry 222, which in asm may generate data si nals ngate33, pgate33 and ut the data signals »gate33, pgate33 to the hybrid ow m driver circuitry 224. As shown in Fig. 4, the data signals ngaie33, page33 ar directly aligned with eac otter inversely aligned with the data si nals dp33, to es nse to rec«i\½g the data signal «gats33, pga¾33, the .hybrid, ontput driver cireoMry 224 may be eoalgBrod to generate the data signal DAT in the high operating wlt&ge domain md send the data signal DAT on the jt¾ data line 1. i S[j J to the host s stem 102, As sho n Fig. 4, the data signal DAT is Inversel aligned with the data signals «§ate33, pgate33,

|Θ08.1| In general, the first level shlfkr rcuitty 220 ma be nnaMe to directly drive the capaeittve load of the input of the hybrid ouiput driver eireiMry 224 with the data signals dn33, dp33. As such, the first pre-driver circu t 222 ma be positioned in. between the first level shifter drcaitry 220 and the hybrid output driver circuitry 224. Hi first pre-driver eireaitry 22§ may have m input eanaeid ve load tha the first level cincsdtry 220 is able to drive, and the first ore-driver circtatry .222 may g nerate nou h curren at its output such that it is capable of driving the input ca eitive load of the hybrid output dri e r ciretritry 224. |Θ082| In addition to a fitsl data path, the host interface 11.2 may also .include a second data path nsed to ge erate the data signal DAT on the data line i I4 ] hen the hos interface 1 12 is in the low operating voltage mod . The seeond data ih ay include the first multiplexer 2.18, second level shii¾r circnilry 226, second pre-driver circuitry 22$, the second multiplexer 212_? and he hybrid oniput driver «r«iitry 224. Generation of the ata s nal PAT with the second data pat and the secon critical path hen t e host interface 11 m the tow operating voltage mode daring perier atice of a read operation is sa described. Reference is also made to Fig, 5, which shows a tim ng diagram of die data signals and clock signals thai are generated with the tm components of Fig, 2 hen the host interface- 1 2 is In lie tow operating voltage mode.

\md Wh the h st interface 112 is s the low operating voltage mode, the a* enable si nal LV may enable the second Setaiti trigger 208 and disable die first Setamtt trigger 2:02, in response, tte second Sc msti trigger 2W tmy generate the clock signal CLIO 3 n output the cl ck si nal CI.JB3 to the dock le el shifter circuitry -04 and the second clock driver eircaiiry 2.! 4. I¾e second clock driver errantry 214. which also may be enabled, may generate the second clock signal C.LK18 in the low o erating voltage domain and send the second clock signal CLK!S to the dock buffer 210.

MS41 As described in fnrte detail Mow, the second twtr ptexer 212 »y be configured to wse the second clock signal CLJQS as its selection signal In one- example configuration, however, the second .ra«ltiplex.e 2I2 may use the second clock signal CtXIS as a pair of complementary signals in order to operate. Accordingly, based on the clock signal CL 18. the clock naffer 210 ma generate a pair of compleme tar clock signals CL lS ji, CL 18 The clock signal CL lS a may directly aligned with the clock signal CLKi 8, while the other clock signal CL I gjj ma be inversely aligned with the clock signal CLKI T¾e clock buffer 210 m be configured to .sni imbe skew between Use complementary clock signals CLK! S ji. CLKI 8 J>. The second multiplexer 12 may receive the complem nta y clock signals CL&i S CL 18 J? and use them as selection signals to generate the directly aligned d ta si m!s ngaf lS, telS, which may he sent to the hybrid οαίρίίί driver etrenitry 224 to generate the data si nal OAT^", as described in farther detail belo ,

1 0851 Kn reference to I e second data path, when he host iinerfsee ! 12 Is » the low operatin voltage- mode, a pair of data signal 10, 1! may be generated! b the co logic eiresJiry 1 6 and tstpttt to the second data path for gener tion of the data signal DAT by the hybrid o¾ pu:i < vet circuitry 224, The data signals Ϊ0, 0 may be phsse-s fted versi ns of each o her. As shown in Fig, 5, the data, signals 10, 11 may be phase-shifted 90 degress relat v to each other. Also, he dam signals .10, U amy be phase-s fkd 180- !egrees relative to each other with reicnsnee to the second dock signal CL 1 As sh&m in Fig. 5, the data signals ¾, II may perform risi g transitions dnr!ng ifferent halves of a cycle of the second clock signal CLI IS, For exam le, inc. data i nal II. .may perfotra its .rising transition during a first half of a clock cycle of fe second clock signal CLK.I 8 (e.g., while the second clack signal CL 18 Is high), an the data signal 10 may then p i m its rising transi ion during a second half of the cycle of the .second clock signal CLKIS {e.g., while the second clock signal CL 18 is low). Similarly, the da a signals 1 , 11 may perform falling hmsliions during different halves of a cycle of the second clock signal CL 1S. For example, the data signal II may perform its falling transition during 3 first half of a clock cycle of the second clock signal CLKIS and the data signal IB may then jperf««m lis falling transition during a second .half of the cycle of the second dock s nal CLK 1 . lit this sense, the data signals id, 11 may be considered 1 Bfr-degree phase shifted signals .relative to each other with reference to the second clock signal CL 11. Also, Fig, 5 shows dais signal 10 leading data, signal 11 _* although in other configurations, date signal 11 may lead data signal 10,

|8086f Also, ssnn r to the dam signal 12, the data signals Id, .11 may be generated by the core logic circnitry 10 and may include data that the core logic? circuitry 106 has inten¾sily generated, stored, retrieved from another om onent of the clock-receiving system 10 ;, from

23 a component external the clock-i¾¾etving s stem 50 ,. or some combination thereof. Also, the dais signals 10, I I ma be generated mitig p:revi.»y$ c cles of the fte clock signal CL I 2 thai is seat its t e cote logic eireoiKy 6, However, t e daa sign l DAT that is nhhnae-ly generated based OR the data signals ϊθ, II is generated using the second clock signal CLKI 8. To do so, the data si nals 10, H m y be generated and o tpwt by the- core logi circuitry 106 so ;)·¾·

(#087} As sh n i« Fig.2, the data signals Ϊ0, 0 may be sent to the first .rmtbiplexer 218, and IB response, the first multiplexer 218 may generate a pair of data signals 4»_i0, p JO based »n the data signal 10 n a pair of data signals dej 1, dp-J I ased on the data si ! 11 in the core voltage doi»aia. As shows is Fig, 5, the pairs of data si nals dnJ0, dpJ0 may he directly aligned with each other a d mt the aa s nal ¾, and the data si n ls d.« J.L #J.I ma be directly aligned wth each other md with he data signal 1 L Also, the phase shift may be maintai ed sach that and the two alm of date signals d« JO, dp J) and dnjl _s dp J ί may be phase-shifted 9 ~de fees relative to eac other ami I BC Iegrecs relative to each other with refeence to the second dock signal. CL I 8..

jft088j The seeo-nd level shifter circuitry 226 ma .receive the two pairs of data signals do JO,, dp JO and dnJL dp J I and. based on these signals, generate two pairs of data signals d»l8J0, dp 18 O md dnlS L dp IB J! is the low operating voltage domain. As shown in Fig.5, the data signals d l 8 JO, dp 18 JO ay be directly aligned with each other and also with data signals dn J0, dp JO, Likewise, the data signals d«1.8 JI, dpi 8JI may he directly allotted with each other and also with data signals d i 3 , dp JJ , In addition, as sho s in Fig, 5, the phase shift may be maintai ed, and the two pairs of data signas dn 1 J0, dp I S J> and dn l 8 J.1 dpi $ jl. may be phase-shifted 0~degrees relative to each other and ISO-degrees relative to each other with reerence in the second clack, signal CLKI.8.· Fnrther, the sec nd level shifter circuitry 226 may recei ve the eons voltage V P and the reference voltage RBF,

2i and be c nfigured to convert t e two airs of data signals d« JO, dp JO aad dnjt, dpjl iet the core voltage dom in - the two airs of data signals tin IS 10, dp 18_. JO and. dn.FB_.Ji» d IS 11 in the low opei¾ting voltage doa*a«i.

|#0S9J The second pre-drivsr cifcutry 228 may receive the two pairs of data signals dnt$J6, dp 18 JO and dnlSji-. dpi $ J! fern the sec nd level shifter circuitry 226_» wdm response, t¾arate corresponding pairs of dam signals ugatel 8J0, pgaiel 8_. JO aad n telS jl, pgatelS JL As shown in Fig, , the pair of data signals agai lSJO, p teiSJO may fee directly ali ned with each otter, and inversely aligned with data signals dnlSJO, dp { 8J0. l¾ addition, the pair of date signal* rsgate 18 J 1 , pgale 1 I may be dire ly a llped with each eh r, a**d inversel aligned with the data signals d«18 Ji, dpl& jl , Also, die phs.se shift, may fee smtotaked, and ihe two pahs of data signals ngatefSJO, pgaiel 8 JO and rtgats 18 I , pgatel 8 _j 1 ma bo pi*ase~abiited 9G~degfees relative to each other and 180- degrees with efere ce to the seeo clock signal CL 18.

|@Q90J In ditio ., as show ta Fig, 2, he second pre-driver circuitry 228 ma ecei e tlte refe*e«ce volt ge REF and the 10 voltage VDDO, s explai ed so further detail below, the date signals pg&t i S JC pga.ts-.18 J1 may fee use to turn on and -off a PMOS transistor of the hybrid output driver circuitry 224_s and the data signals agate 18J0, »gatel8Jl may be used to turn on and off an MMGS transistor of ihs hybrid output driver drcaitry 224. The PMOS transistor may be turned off by applyi ng a gate ltage at the level of the 10 voltage VDDO, Since the .reference volta e .REF is at the low operating voltage level regardless of the operating m de, the feence voltage REF ma not he a high enough level to u off the PMOS transistor whets the host interface is in the high operating -voltage mode. As such, the TO Tallae VDDO may be supplied to the second pre-driver circuitry 228 in order to set pgatol $ JO sod pgatetSJJ to the level of the 10 voltage VDDO so thai the PM^'OS transistor may tans oft iten the best interface 112 is n the high operat g voltage mod _* |W IJ However, as described further detail belo _* the tesisistofs of the second pre-driycr circuitry 228 ma be opiimiged for delay for the la operating voltage mode, which may ause toa high of dratrMo-souree voltage stress OSJ the transistors if proper precaution m the i mk&m configuration is not taken. One way to lake roper precaution may be to avoid ap l ng the high o erating voltage to the transis ors where possi le. -Since CI V f ther thm the high ope ating voltage may be used to mm off the ^' MOS transistor of the hybrid oittfsui d ver circuitry 224 in the high, ope ating voltage roode, the reference voltage REF m&y be used to generate t*ga$el8 J0 and npte! 8J i . Accordingly, as shown in Fig, 5, ths data signals pgats! JO aid pptei 8 J 1 tmy immitk between tie kvel of the lO voltage VD^'PO a d 0 V, whereas the data n&h n§ate! .8 JO a ngntel 8 JJ may t ansition between, the level of the r f rence voltage REF aad 0 V, in Ihe .low operating voltage mode however, the levels of the 10 voltstge VDDO ami ihe rderence voltage .REF may be t e same. Further description of transistor opttmt¾sti»n for the low oper img voltage mode sm use of both the IQ voltage VDOO ataJ the .reference vol ta REF for the seeond pre<friver circoitry 228 is provided, in farther deta l he low..

(Θ092| The seecsnd multiplexer 212 may receive the pairs of data signals ngateiS JO, gafeiS JO arsd ngaieiSJI _s pgaiel 8J I item the second pre-driver circuitry 228. Based on. these signsls. the sec nd Multiplexer 212 may enerate a pair of date signals iigateiS, pgateiS, which are .sent to the hyb id o«tpot driver cirertilry 224 for en rators of the data, signal DAT. As shown hx Fig. 5, the data signals ngatel.8, pgatel.8 are directly aligned with each other.

[Θ0$3^'{ The second^' multiplexer 212 ma also receive the c m lem ntar clock signals CLK½_wn» CLKlSHb and use ihera as selection signals to select whether to set he levels of the date signals rtg&te! 8_t pgatelS being out ut by the s con multiplexer 212 to the levels of the data signals ngat lS iO, pgs elS JO com'spo-txii.og to the data signal 10 (Le,, ss, the data signals «gal«lS J0_f pgateiS J0 t the output terraiaak of the second t tiplexer 211 or to set the levels of ths? dais signals ogatelS, pgafei 8 to the levels of fee data signals nga el 8 J L pptoi 8 J! ¾t espoi¾dl¾g to the data signal II , Is ot er ords, the second twhtplexer easy use the comptorateatey clock ste ls CU iSjj, CL i l_b as selection signals m order to select either t pass the data signals s gateiS JO, pgate^'18 JiG eo-responding to the d ts signal 0 or to pass fee dat s pals data s%aate ngatelS JL pgateiS Jl oarfespomil«g to Sis? date, signal 0 to the output tatinals of ¾c second mdtiplexef 212.

\W94| In Ά particular example c afigorsto as sh n in the timing diagram of Fig. 5, whet* the seeaad clock signal CLKlft (aad the clock sigaal CLK!Sj¾) is Μ , t e second *»uMpfexef 2.12 is confi ured to set the le els of the data signals ogatolS, pgate!B to the levels of (he data si nals agate 1.8_i0, pgatoiS Ji) eo8«§poadi8g to dala signal W, and whe the seesmd clock, signal CLK!.8 (aad he clock signal CLi .i8_a) is tow, set the levels of the data signals ng&telS, pgstol 8 to the levels of the data sigaa!s nptel 8 J { , pgate!SJ ί eorrs¾spo«dt«g to lie data signal 11„ To ensure stability under this particular eo»ttgur»tioa, the mtes md relative phases of the data aad clock signals iapwt to the second multiplexer 312 .may be such that within, a clock cycle of the dock signal CL J 8_..a, du in a first half cycle or time that the clock, signal CLKJ 8 jj. is high, the data signals ngatelSjO,

corresponding to the data signal i§ ataiataift constant levels (Le,_? they are mt ttaasttioiuag. from high to tow or vice versa), and during a second half cycle or time that the clock signal CL I8 n is low, the data signals agate 18 l, pgaiel&Ji corresponding to the data signal il s»ai»iato constant levels ί i,e<., they are a»t traasttionisg from high to low or. vice versa). Also, during the first half cycle that the. clock signal CL ^'ISji is .high, the data sigaak agate 18 J ϊ , pgatet S Jl corfcs oitdi g to the data signal il may .imshtoa, and their transittom *»ay not affect the levels of the data signal ngat lS, pga el B at the oatpta of the second m ltiplexer 212,. Similarl * dorisg the second half eye to that the clock signal CL I 8 « s low, the data signals ^'a ate 18 J% pgateiS J0 c<¾xesp©nding to the data signal f(> may transition, sad their transitions may not affect the levels of the data signjtl agate IS, pgate S at the output of the second mnltiplexer 212,

[CW95J A s shown in Fig, 5, the rate of the ock signals (i.e., CLK.18, CL 18 jrs.

LKiSJs) ma be twice ttte rate of the data signals, fa th s se se* the second ^'mult lexe 212 is operating in a double data rale (DDR) fashion, sinee it is operating to pass he levels ofts apnts data signals to its out ut termi als on both the rising edge sad the falling edge of the clock, s gnals CLKja, CLJ _h. However, because the input data signals n iel8J0, ptei Sj i and ngats !SJ L pgatslS J l are as^-sh!fts iW de rees with reference to the second clock si nal CL I 8, then over a clock cycle, the associated 10 data sign ls <ie,_t data, signals rsgate J , pgate JO) for one half of the clock cycle ma be at the mm& level as the associated II data signals (i.e., datts signals nptejl„ pgatej l) for the other .half of the clock cycle. For example, in Fig. S, suppose dwlng a first half of the clock cycle, the clock signal CLKji is low, and daring a second half of the clock cycle, the clock signal CLK_» is high, D ae to the 1 SO -degree phase shi ft between th e associated 11 and i f data signals, .if the O data si nals are low during the first, half of the clock cycle, then the 10 data signals are low during the second half of the dock cycle. Similarly, if the 11 data si nals are high during the first half of the deck cycle, then the W data signals ate g during the second half of the clock cycle, S ce the second multiplexer 212 operates to output the 0 data signals when the clock signal CLK ji is low and to output the 10 data signals when the clock signal CLK n is high, then the rate of the output data signals ngstelB, opiei $ may be the same as the rate of the othe r data signals (half the rate of the clock signals), despite the despite the DDR operation of die second multiplexer 212.

|M f Fig. 6 shows a circuit schematic diagram of as example circuit configuration of the second multiplexer 212. The example circuit c nfiguration ma include four pass gates 602_f 604, 604 6 . Each of the- pass gates 602-608 may include a NMOS transistor and a PMOS transistor, m input configured to receive one of the data signsis ngate!S J _S pptol 8 JO, B st iSJ I, pgateiBJl and an out ut connected to one of two out t terminals of die sec nd multiplexer 2:12, iaelnd g a first output tentorial 610 and a second outpai lenramat 612. For eac of the pass gates 602-808, source terrainsis of each, of the NMOS and ^'PMOS transistors raay be connected to the htpt of the pssss ate, md dram temsinak of each of the NMOS am FMOS tntnsistors wa be a-sna eted to the ou&pnt of the ass ie. The gate terminal of the NMOS transistor ma configured to receive one- of the clock signal CL ja and the tewrse clock signs! CUK.J), sad toe gate terminal of the FMOS transistor ma be co figured to recei ve toe other of the clock signal CLK « aod the inverse clock signal CLK .

!^'ø0§ ?| In addition, it* the extanple cifceit configuration of Fig, two of the four pass gates 202-208 may ^'have utputs connected the first output terminal 6^' 1 _S nd the other two pass g tes may have outputs connected to toe second output tem toal 612, Ooe of the two pass gates may be configured t receive an 10 data signal and the other of the two ss ates .may be configured to receive an 11 data, signal For example, as showrt in Fig 6, the first pass gate 602 configured to receive the data signal pgatel.BJ.0 and the second pass gate 604 configured, to receive the data signal pgate I SJ 1 ma have their respective outputs connected to the firs* output terminal 610, and the third ass a e 60 configured to receive the data signal ngateiS JO and the fourth pass gate 608 configured to receive the date signal agate IS Jl. may have their respective out uts connected to the second output terminal 612,. |SW SI Addition, for the two pass gates having their utputs connected together, one of toe pass gates ma have its NMOS transistor configured to receive the clock signal CL l Sjn and its FMOS transistor configured to receive toe inverse clock, signs! CLKJJ, wh le the other pass gate may have its NMOS transistor configured to recei ve the kverse clock signal CL^'K Jj arad its PMOS tnsajsistor config red to receive the clock signal CLKjo. For example,. m 8¾e ewtsple ctrcnit conit ratioii of Fig. 6_S the firs? pass tc 602 ros iadude a NMOS iranstsiar M37 having a gate tmautal c R%ui¾d to .receive the eloefc sigas CLK jt sad a PMOS transistor M38 having a gate terminal configured to receive ilie invoke dock signal GLKJ»_> and the s cond ass gate 60 may include a NMOS irtmsisior M39 c<>n%ured to receive the i erse clock si nal CLK b aasl a PMOS Inamistor M4 having » gate terminal eoafigutsd to receive the dock signal CLK In addition, Ihe third _.pass gate 606 may tnoiede a NMOS tHmststorM49 liv g a gate terminal configured to eceiv the dock si al CL _a and a PMOS transist r M50 having a ga e teroinai co«figi«¾d to ecei e the inverse clock signal CLK , n the fontth p ss gate 60S m include a NMOS ixmofcbx MSI configured to receive Ihe hrvetse dock sign l CLKJb and a PMOS imnssstor M52 having a gate terminal configured to receive the deck signal CLKjt

|§W9| 1st opcmt of . when t e clock si ns! CLK n is high nd the invoree dock signal CLK b ¾ low, the data signal pga el 8 10 ma be passed to the first ©utpwt teraw*al 610 and. tlte data signal ngatot 8 JS ma be passed to the s cond outpni terminal 612, Thai is, whe , the dock signal CLK. n JS high and the mverse dock signal CL J> is low, fee level of the data signal pgatel 8 genetsted at the first out ut temiinal 610 ma be set to the tovei of the data signal pgs el S JO and the level of the data signal iigais i S enerated at the second output terminal 612 ma be set to the level of the date, signal ngatel8 JO, In addition, when the clock signal CLK jt is low and the inverse clock signal CLK. Js is high, the data, signal pgstelSJl .rosy be _.passed o the first output tent»isa! 6i0 and. Ihe data signal oga e!S Jl may be passed to the second output temtiaal 612, That is, whets the clock signal CLKJR is low and the in erse clock signal CLK J? is high, the level of the data signal pgaiel 8 generated at the fet. output tertnina! 610 ma be set to the level of the da a signal pgatel 8 J 1. and. the level.

3S of the data signal ngatei 8 generated at the second o tpet terminal 612 ma be set to th le vel of the data si nal np.fe!8J l .

[OOi Ml] Refe ag back so Fig, 2, as previously desc ibed, generating the data signal DAT ^•using the second critical path and the second clock sigssal CLK 18 may rovide a shorter loop delay compared to generating the data signal DAT using Use first critical path and the first dock sigaat CLK 1 , This may be achie ed became the second multiplexer 212 is configured directly behind the hybrid output driver circuitry 224 (le,, the utput of the multiplexer 212 is connected directly to the input of the hybrid output c irc ry 224), When the second multiplexer 212 generates the data si nal gate! 8 using the clock signals CLKi Bja,

CL I8 , the data s gnal gate! 8 may he output directly to the hybrid outpttt driver dmatry 224 for generation of the data signal .OAT. .In other words, when the data signal gate 18 k generated by the second multiplexer 212, the circuit c m onen s of t e second da a path (including he first m lti lexe 218, the second level shifter efoeuifry 226, and the second p e- driver ctnst&ry .228} a e not thereafter tssed in atdet for the data signal DAT to be generated with the hybrid outpttt driver circuitry 224, In contrast, when the core logic circuitry I 06 generates the data signal 12 with the first dock signal CLK 12, die circuit components of the first data path {including the first multiplexer 218, the first level shifter circuitry 220, and the first pFe-driver drcdiry 222) sre thereafter used to convert the data signal 12 to data signals «gate33, pgate33 in order for the data signal DAT to he generated with the hybrid outpai driver circuitry 224,

|§01tll J In order to take advantage o f the shortened loop delay provided b the second critical path, the initial cycles of the data signals agate 18 JO, pga el S J6 (which lead the data signals agate 18 JJ_t pgatelS Ji ) may be sseceived by the secon .urultip-lexer 212 (i.e,_s. the date si nals 10, 1 ! may he nssde available to the second multiplexer 212) at least ne half cycle of the sec nd clock signal CLK! 8 before the initial cycles of the clock signals€L 18 a, CLKJb arrive at She second raiiltsplexer 21 2. In order for iris to h p en, S e core- logic circnitry 106 ma alread have she data for sending back to the cloek^ndi g system W2 bei&re the clock-iweiviug s stem 104 recei ves the h st clock signal CLKHOST (<W at least the port on of ihe host dock signal Ci¾;¾sr iha is to be nsed to communicate die data back to the dock-sending system 102). la addition., even if the second critical path is enabled and ased to generate rn data signai DAT, the first clock signal CLK12 is still generated and seat to the core logic circuitry 106 for generation of the dais signals 10, Π . This is s own in Fig. 2, whh t e second Schrai t trigger 208 being configure to output the clock signal CLK33 to both the second clock driver dras ry 214 of the second critics! -path and. the clock level sMfier eireyitry 204 of the first critical path. The core logic circuitry 106 ma se the first clock signal CIJK.12 to generate the data signal s 10, !L and may do so a su ficient amount of time In advance of the emmatio of the dat signal OAT such that the initial cycles, of the data signals ngate &Jft, pgatel SjO (which lead the data signals RgatelS JI , r*gatel8jl) si¾ received by the second rn itifsiexer 212 at least ose half cycle before the initial cycles of the dock si nals CXK 18_..n, CLK18J> (or at least initial, cycles of those portions of the clock signals CLK.18 js, CI.K b used to communicate she data hack, to the clock-sending s stem 102) a e received by the second multiplexer. 212.

(0O1@2| The hybrid iput driver circuitry 22 may referred to .as a " ybrid" i that: it ittdades two circuit ortions, a first circuit portion that gene ates the data signal DAT on the data line 11 Sfj] when the host interface 1.12 is operating in the high operating voltage m de and a secoad circui portion that generate the dais signal DAT on the data line 118 ] when the host interface 112 is operating m the low operating vol tage mode. I» the high operating voltage m de, the first circuit portion may be enabled or acti vated to generate the data signal. DAT, white the second circuit ortion may foe disabled or deactivated. OH the other hand, in the low operating voltage mod®, the second circuit portion m y be ena led or activated to generate the data signal DAT, while the fct circuit portion, m be disabled or deactivated

[001031 Pig- 7 sho s a c r uit schematic d agram of an example circuit co lgutatien for the hybrid output driver circuitry 224. In the example circuit co» urs*k»s shown is Fig. 7, each of the first and second eh i portions may be ceciftgufed in pnli-up pnii-do n eonilg uradoas whet* activated. That s, whet* each, are activated, in. order to generate the data, signal DAT, the first a»d second circuit portion ma pull tip the level of the data signal DAT to the ievd of the 0 voltage and all down the level of the data s na DAT o a lo level, such as ground.

[0010*1 The fi st dtsuit portio may include a first PMOS transistor M61 and a first NMOS transistor M62, The first PMOS translator M61. may have a source terminal configured to recei the 10 voltage V.DDO, a gate trantaal. configured to recei ve the data signal pgate33, sad a drain tertmaaf co pled to a node C a*m¾eeted to the data hoe ! 14fj ] w ere the data signal DAT ge«etated. The fmt MOS transistor M62 taay ha a o rce terminal eoune ad to the ground reference voltage OND, a gate terminal mfigured to receive the data signal ngaie33, and. a drain tenohi l coupled, to .node C. As previously described, data signals pgate33, ngate33 tnay be directly aligned with each other, When the data sijpals r¾ste33_s pgate33 are at their high levels, the first: PMOS transistor M61 is tanssd off aad the first HMOS transistor M62 m y be turned on pulllttg dow» the voltage level of the data signal DAT to ground ND, Alternatively, when the data signals ngale33_;t pgate.33 are at their low l vels, the first PMOS traaststor M61 may he turned on and the fi st NMOS transistor M62 may he turned off, pulling tsp the voltage level of She data signal DAT to the level of the 10 voltage VDDO.

[00.1051 Similarly, the second circui portion, may ssehtde a .second PMOS jsusistor 63 and a second NMOS transistor M64, The second P OS tr¾«sislor M63 may have a sou ce terminal configured to receive the 10 voltage VDDO, a gate terminal connected to receive the data signal pgatel md a drab tomunsl. eonpled to node C> The sec nd NMOS transistor M63 may have s so rce tertninal coanec-ted So ^{fee ground nrfetesee voltage GND, a gate terminal configured to receive the data signal agate 18, and a drain terminal coupled to node C, As previously esc ibe _* data signals pgatel 8, ngatel S ma be directly aligned with eachi her. When, the data sig als ogateiS, pgatel 8 are at the r high l vels, the second PMOS tmnststor M63 msy e turned off and she second NMOS transistor M64 may be turned on, polling down the voltage level of the da a sign l DAT to ground G X Ahemattvdy, when the dat» signals ngtitei 8, pgatslB ate at their low levels, the second PMOS transistor M6S m y be twrned oo and the second NMOS transistor MM tmy be lamed ofC polling «p the voltage level, of ¾e data signal OAT to the level of ie IO voltage VDDO,

WJi6| As previously described, when the first circuit portion k activated the second eire¾lt portion may be deactivated, so vice versa. Accordingly, n the high opera ing o tage mod when the first transistors 6Ί , M62 are pulling up sod down the level on node C to generate the data signal DAT, the lines thai supply the data si nals pgatel 8, ogatel 8 to the gate terminals of the second, transistors 63, MM may he set to voltage levels that turn off she second transistors M63, MM. For xample, data signal pgate i I may be set to the ΪΟ ^•voltage level VDDO to tuns off the second PMOS transistor Mol a id data signal. ngatelS may be se to the roesd reference voltage G D (e.g., V) to to of? the second NMOS transistor M . In this way, wh n the host interface 1 12 s in the high operating voltage mode, only -first transistor* M61, M62 are being used to generate the data signal DAT the data line 1 Ι β^'|. Similarly, in the low operating voltage mode when the second nmsistors

MM aire pull ng up and down the level on node€ to generate the data si na DAT, the Hoes mat supply the data signals pgato33, ngate33 to the gate terminals of the fat trans istors M6I₄ M62 may be set to voltage levels that torn off fhs first transistors ΜόΊ„ M63, For

33 exampl ,, data si nal pgate33 may be sei to the 10 vohage level VDDO to Uir» off the fxm PMOS transisto MM s d data sipal ¾p.te33 may be set to the und lefereitee voltage G (e.g,_? 0 V) to tun? off he imt M OS tr&oststor !vf 62, this way, hets the host interfere IDS is i» the low operating voltage mode, only second transistors M63, M64 are- hs g d to generate the data signal DAT^' m he data Use I 1 0],

|iMH07J Referring back to Pig, 2, when, the host interface.108 is the high operating voltage mode, the -f t .mt tiptexer 218 may he c figured to set and mai &irt appropriate voltage levels for the data sign ls dn Q, dpJO, and dftJJ, dpjl in order to keep the second ^•portion of the brid otttput driver eis'cthtry 224 deactivate white ths host interlac 108 is to the high operating voltage mode, Additionally, the second dock driver circ ir 214, being disabled, may be c nfigured to set md mantain the level of Ihe dock signal CL 18, and in t rn the clock buffer 210 ma he cortilgired to s t and mamt&m the levels f the complimentary dock signals CLKlSjo, C^'L i.8 _b to appropriate levels,, so that upon receipt of the data si nas ngate!E JO, pgatol 8 JO, «g3tel8_.iL pgatelSJI and the complimentary dock si nals CUD 8_..», CL J 8, the second multiplexer 212 sets md .ra&iniains. the data signals ng&telS, pgatel8 at levels that deactivate the second portion of the hybrid output driver circuitry .224,

(001881 Referring back to Pig, 4_S in the high operating volta e m e, the second clock driver oireiiiiry 14 may set and a¾ri»tam the clock signal CLKl 8 at the referenc voltage level REP, and m turn the clock buffer 210 may se and maintai the complimentary clock signals CLKISji, CU b at the reference voltage level RIF mid 0 V (ie,_s the low votap) respectively. Using the exatnpk circttit configuration of the second multiplexer 212 of Fig. 6_» wih the clock signals CL _wn_s CL b se to their respective levels, the level of pgaisj 8 at the fc ut t terminal 610 mi the le vel of the ngateiS at the second a¾tput terminal 612 may he se t to levels of the 10 s nals pgatel8 JO, agaielS J.O. As shown Fig, , so that the voltages of pgatelS at the first ootpet terminal 610 and the oltage f agate at the seennd utput terminal 612 deactivate (L.e„ turn off) th leeortd F OS trsaststo M63 and the seeo»d MOS trsBsisior 64 of the hybrid output driver circuitry 224 (Fig. ?), respectively,, ^•the voltage ofpgaie I S may be set to the 10 voltage V.DDO and the voltage of ngaiel 8 may be set to ϋ ¥.. in orde to have these voltages set accordingly, the first multiplexer 218 may set to and rnrnmm® sk JO am dnj I at the high voltage level in the core voltage omai (ie,, the core voltage VDD) md dp_i0 md dpjl at the ow voltage level in the core voltage donia½ (le,, 0 V). In response, the second level shifter circuitry 226 may set to and maintain dnl8J0 and drri Sji. at the re&retic v»Stage le e RE , arid dp 18 JO and doiSJI at 0 V. As previousl described, the s co d pre* rivex cucftttry 228 ma invert the levels of Ms inputs. Accordingly, the ascend pre-driver drcuitry 228 .may pull down dnJO anddnjl to generate ngatel&JO and gatelSJl, respect ely, and ma pull up dp J and dp J I to generate pgate ! 8J0 mi pgate ! 8 J 1. res ects vgiy, in addition, whew gen rate , pg&te i 8 JO sa pgatel 8J I may be pulled op to the level of the 10 voltage VDDG other that* he level of the reference voltage REF s that second PfviOS trans stor M63 of the hybrid, output driver cincaifey 224 may be turned off m the high operating voltage mode.

ίίϊ a similar manner, when the host interface 112 is in the low operating voltage mods, the first multiplexer 218 may he eoafigared to set a d raaintaiti appropriate voltage levels for the data signals & J2_f dp.J2 in order to keep the first circuit portion of the hybrid outpa* driver circuitry 224 deactivated. As shown in Fig.. 5, the first multiplexer 218 may be configured tcs set and sraaiatsio dnJ2 at the care v l age level VDD saddpj:2 at 0 V,. J» turn_* the first level shifter circuitry 220 may set md maintain d»33 at the level of the I D voltage VDDO (which is here the low operating voltage level), and 33 at V. n res o se, the first pre-driver eiretsl¾y 222 ma be configured to set and m intain ngate33 at 0 V and ppteBS at the level of the 10 voltage level VDDO (which is here the lo o erati g voltage level). With gate-33 at t e 10 voltage- level VDD0 and npte33 al t) V, the fei F OS transistor Μ6Ί and the fet. MOS torasistor M62 of ths hybri o tput driver circuitry 224 (Fig. 7) may each be deactivated (is., turned off)_*

[OOliftJ As shown m Fig, 2_» the core logic circuitry 106 may ou put a data path control signal OE thai co figur s the first multiplexer in eifter a first sta e associated with the high opetsting voltage mode or a second state associa ed with flic low op&ratfeg voltage mode. When the cor® logic eirosHry 106 determines that the ost interface 108 k in the high operating voltage mode, th core logic circuitry 106^' tmy output the data path -control signal OE to the H t multi lexer 218 such that the first multiplexer 218 s configured in the first state ami se s md maintains the app opriate voltage levels for the data sign ls dnJO, dp jil and dn j f, dp_. J I in order to keep the second portion of the hybrid ou t d i er circuitry 224 deactivated Alternatively, whet* the core logic circuitry 106 determiiJtes hat the host int rface 108 is m the tow operating voltage mode, the core logic circuitry Ϊ06 may output the da a path control signal OE to the fxmt multiplexer 218 sneh that the first moMpteer 218 is configured in ths second state am! sets and maintains the appropriate voltage le els for the data si nals da J2, dpJ2 in order to keep the first circuit portion of the hybrid output driver circaitry 224 deactivated,

(001111 he transistors of the fttst arid second data paths m&y be of the same type in that they may have the same sate widths. In one example c figuration, where the high: and law operating volta es are 3.3 ¥ and LS V respectively, the gate width may he 55 Angstroms (A), H wever, due to cspacttive loading, a transist risi a gate length optimized tor t e hi gh operating voltage mode may provide an increased amount of delay when switching in the low operating voltage m ds- That is, a tra istor with a certain gate length may have its source terminal configured to receive fe IO voltage VDP0, When the IO voltage VDD Is at the high operating, voltage evel, the transistor may provide a certain elay when taming on and off to drive an output signal to high and tow levels- However, due to the esparitive loading at the output, hen the 10 voltage VDDO is at di tow operating oltage level the delay provided by the transistor when. t«n«ng on and elf to drive the output signal to the high and low levels rosy increase, such as the order of ½ for some transisiur technologies, fa general, reducing the gate length ma serve to reduce the delay. However,, rise

dtain o»soi*feo bfeaksfown voltage may also be reduced, Depending m the trans or tedirsology nsed and ihe voltage levels for the first nd second operaiiag voltages, reducing toe gate length, to opt mi e fm the lo er peratin voltage level tmy yield a rmtM»-«owee !br at least some of the transistors that Is above the breakdown d aiu-ro-son ^ voltage, causing the transistors to experience too high of stress levels and break down,

{Win] The gates of h¾¾ die fkst PMOS and NMOS transistors MbL M62 of the hybrid, oatptn driver circuitry 224 and the sec nd PMOS and NMOS transistors ¾3, M6 ma all a e the s me gate length, which may be ptimize for t e high operating voltage level The gate length o timised lor the high operating voltage- level may be heaei» referred to as the longer gate length. To optimise for delay, the gates of she transistors of the .first pre-driver circuitry 220 in the first data path .may be configured, with the longer gate length. However, the gates of the transistors of the second pRi-driver eiretritry 258 and the second multiplexer 212 in ihs second data path may have gate lengths imis d for the tow operating voltage level. The gate length optim zed for the low operating voltage level may be herein referred to as th shorter gate length.

[001131 As previously described, in ihs high operatin voltage mode, the second pre-driver circuitry 221 may output pgate I8J.0 and pgatelSJiat the high operating voltage level in order to have the second PMOS M63 of th ^'hybrid ouipnt driver circuitry 224 turned off; As &K at least some of the PMOS transistors of the second pre-driver circuitry 228 n¾ay have source terminals -configured to receive the 10 voltage VDDO in order to genera e pgatei 8 JO md pg&telS Ji t ibe high operating voltage level, fa order to preveat itte transistors of the sec nd pre-driver circuitry 228 havkag the shorter pie lenghs from b &kwg dows, tie reference v ltage REF ma be «§ to reduce the stress_*

[00il4j Fig.8 sbows a circuit schematic iagram ofs» example circuit coa aralio» of the second pre-driver eireuttry 22$. The example circuit c nfi uration: may include four pte-drivet citc«¾ itrctoding a first pre-ddv«r circuit 802, a second pre-driver circuit 804, a thM ri w circuit 806, a»d a fourth jsre-driver circuit 808, The first pre-driw dtcnit 802 ma be coaftgared to recei ve dplBJO ami outpu pgate.l$J0;. the second pre-dsiver ctrceit 804 ma be configured to receive dp!SJ 1 aad tp t pgatei8_S I ; the thtal pre-drrver etreaii 80 may be configured to receive tatftJO aud oaput » te!8J¾ and the fcsarth re -driver drcuit 808 may be confi ued to eceive drvi.8 Jl md ip t agate ί 8 J I ,

[WI 15J The first pre-driver am t WZ may ktctude a first tra«sistor drcaitry iaeiudm first PMOS transistor 27 aad a second PMOS ttaasfeier M3¾ seeoad tramistor circuitry trading a first MMDS d tsistor 28 artd a se ad NMOS traasistet 2 , aud t ird transistor circuitry iudadmg a third PMOS taft&istor 31 , ¾ se »«d re^riw* ci cuit 804 may include, a first FMOS trarasistor M¾ a second PMOS transistor 35, a first NMOS transistor M33, a second NMOS traastetor M^'34, and a third PMOS tratmstor 3&. As Aowft in Fig, 8, he tmjtsistors of the ftt&i md seeoud re^vsr circuits 802, 804 may ave the same circuit configuraton. Aec rdisgly, for simplicity, th transistor eonfigniutiou and operatkm of the first mad xecossd pre-driver circuts S#2._t 804 is made only with .refer nce to the first pre-driver drcui 802 but is equally applicable to the second pie-driver circuit W. |M!M| As previously described, pgate!SJO generated at an output isjTsitiat S 10 may be ^■polled up to the level of the 10 voltage VDDQ raft tha» the level of the refeinenee voltage REF in order to turn off the sec n PMOS ttnauK* Mf>3 (Fig, 7) of the hybrid out u driver circuitry 224, As such* as sh wn: in. Fig, 8, the first mi sec«»d PMOS transistos M27, M30 may eac have their source teortinals configured to receive the JO voltage VDDCK In arfditioR, the first PMOS transistor M2? have Its drain te inal connected to 8» out ut node of the output term.i»a 810 and its gate te minal mec d to an nput 812 of the fi s pre- driver circuit to receive the data signal ΐ 8 JO. The second PMOS transisto M30 may ^'have its drain terminal c nnect to the out ut terminal 81 and its gate iernnna connected to the reference voltage R1F, The first. NMOS trMtslstor M2I tnay have Its drain temnnai connected to the output node of She output terminal 810, its source terminal connected to an internal node of the second transistor circuitry, node D, and its gate terminal connected to the reference voltage RBF. The second PMOS transistor M29 etay have lis drain terminal connected to node D„ its source temnnal connected to ground, and lis gate tertnfaai connected to the input terminal 812, The third PMOS transistor M31 may have its drain terminal connected to the reference voltage REF, lis source term nal connected to node D, and its ga e terralnai ate co n cted to the inpu tenninsl 812 and coftfigwed to receive (lie data signal

\^<mit7\ the tow operating voltage mode, both the level of the lO voltage VDDO and the level of the reference voltage REF may be at the low operating voltage level Also during operation, the date signal dpl8 JCi stay transition between the level of the reference voltage REE (its high tevd) and: 0 V f ts low level). When the data si nal dp 18...10 is high, the first PMOS transistor 27 may be tamed off. The second PMOS transistor 30 may also be off. The second NMOS transistor M29 may be tamed on, pulling the voltage at node O down to g ound. The first NMOS tmmiste M28 may b tamed on sod the third. PMOS transistor M31 may be turned off. As a resnlt the level of the data signal gat lSJO generated at the output level may he palled down to 0 V.

[QQllft] Alternatively, when the dsta signa dpi H ;0 is lo , the first PMOS transistor M 7 may he turned on. pulling u pgate 18 J O at the output terminal 810 to the level of the 10 voltage VDDO. The second PMOS trustor M30 may be off: Additionally, th second NMOS transistor M29 may foe t¾roed oil he first NMOS twlsw M28 ma be toraed oft and tfiay further cause t se voltage at node P to be about lite level of the :re.fereace voltage R EF less a threshold voltage f die first: NMOS fnmaMctor 2& With t e dais signal dp 18 JO ^'being low, fee referenc voltage REF on tie drain of the third PMOS transistor M31 may mum the voltage at node D to inersase to a level above he e the level won Id be If he third PMOS transistor M31 as not part of ihe circui , Alihongh not erideal m the low operadng voltage mode, this increase In voltage at node 0 may redttee tlte dm two-source voltage across the first NMOS ttmsistor M28, which tmy reven breakdown I» the high operating voltage mode as des rv d ne t

[Θ0Π9| In the high operating oltage mode, fee level of the 10 voltage VDDO tmy be at tie high operating voltage level and the level of the reference voltage REF may be at the low operating voltage level. Also dwlng o eration, the dam signal dpi SJ tsay be set sad owtalaiMd at 0 V, The first PMOS t ans st r M27 may be amed an, pulling tip pgatelSJO at ¾e out ut terminal 810 to the level of the 10 voltage VDDO. Depending on the characteristics of the transistors, the second PMOS transistor 30 may be on or off, The second NMOS transistor M2 n¾ay be turned off. As in the low operating voltage mode,, the first NMOS transistor ^'28 ma cause the voltage at -node D to be the level of the reference voltage PEF at ts gate terminal less its threshold voltage. If the difference between the level of the 10 voltage VDDO arid the level of the .reference voltage REF is great enough,, the sonr¾e-io»dra.tn voltage across the fsrs MMOS transistor M2I, having the shorter gate length, tnay be above the breakdown voltage. The reference voltage REF being applied to the drain terminal of the third PMOS transistor M3 ί may ioerease the voltage level at node D in order to reduce the level of the d siu-to-s urce voltage across the first N OS frasststor MM from where it would be if the third PMOS transistor M31 was not part of the circuit. The increase of the voltage at tsode D amy he such that the draii to-soaree l togs? across the first NMOS transistor M28 SLs at a fs level below the breakdo level. As a result, by including the third PMGS transistor 3 ! sad consen ing its drata to the re erence voltage VREF, the first s lri er circuit 802 a y be able to safely operate both when the 10 voltage is at the low op ra in voltage level and the h gh operating voltage level.

\mm\ The third itMM er circuit 806 tmy include a first PMOS ttmsistof 1 , a secoad PMOS fn∞bferM42, a first NMOS tt¾»sistor.M43, and a secon NMOS transistor M44. The fourth prenMver circuit 808 ma include a firs PMOS trus or M45, a second PMOS transistor M45, a fet NMOS transistor M47, am! a seeotid ^'NMOS transistor 48, As sho a in Fig.. 8, the tramlstors of the third aod fourth e-drtvet elretilfe 806, 80? may have the same circuit configuration Acc rdingl ., for simplicity, the transistor confii ratioa md operation of the third aa fourth pre-driver circuits Θ6, 808 is mad only with, reference to the th rd p -driver c rcuit 806 but is equally applicable to the fourth pre-driw circuit 80S, \WUl\ The first PMOS teEslstor M41 tmy include a source temthmi configured to receive the refeterjee voltage ESP, a du texmiml co rec ed to a source rr»in¾l of ihe second PMOS ttausistor M42, and a gate terminal connected to m input terminal 814 of the third pre-driver circuit 806 andcoaiigured id receive the data signal dn.l8j0. fo addition- to having its source tom¾inal eon&eeted to the drain terminal of the- first F ^'OS transistor M41, the second PMOS transistor M42 may have i gale term nal connected to ground an its drain temt ud connected to an output terminal 816 of the third pre-driver circuit 806, where the data signal o ! 8 J n geners d. The first NMOS transistor M43 ma iaeiude a drain temtinal connected to the output terminal 16,. a source terminal cotraeeted to ground, and. a gate teradnai connected to the inpat te minal 81 and configured to receive the data signal do 18 Jit The second OS transistor may include a drain terminal connected to the outp t

4? tertniraai 816, a source terminal connected to gswnd, and a gate lerrn nal also connected to ground.

[001221 Since the ΪΟ voltage V0DO is sot applied to the third pre-driver i uit 8 6, the third pre-dri ve circuit mm operate is the same way m both the hig operating voltage mode snd the low o erating vol tags? mode, although as previously described, the low operating veK&gg mode, the data signal i 8 JO transitions et een the level of the reference voltage REP (sis high level) sad 0 V (its low level), whe eas in the high o erating ltage mode, the data signal do.l8_iO held high at the le vel of the reference voltage - Further, since the lO voltage VOOO not. applied to the third pre-drivet circui 106, the tts»s&te 4I«M44 may he amilgured with the shorter gaie lengths witho t oarjeem for b eakd n,

[001231 When the data signal dnf.8J0 is high, the ilrst PMOS transistor M41 is turned off and the first NMOS transistor M43 is tamed on. The second PMOS t ansistor M42 and the second PMOS tmmisi«M44 are turned, off. As a result, the level of the data sig al agate 18 JO generated at the output terminal 816 is pulled down to groand. Alternatively, when the data signal. dsiUjO is low, the first PMOS transistor M41. is turned on and the first NMOS transistor M43 is turned off. The second PMOS transistor M42 is tamed m and the second NMOS transistor MM tamed off. As a result, the level of the data signal agate in JO is pulled op to the level of the reference voltage REP,

[001241 deferring to all fow of She pre-driver circuits 802-8 4, the gate terminals of the second PMOS transistors 35 and the gate terminals of the first MMOS transistors M28, M33 of the first and second pre~dfiver circuits 802, 804 are sh wn as receiving the reference voltage E^'F. Additionally,, the g te $e«ni»a!s of the second PMOS transistors M42, M4 and the gate term i als of the second NMOS transistors M44, M4S of the fe and fourth pre-driver circuits 806, W are shown, as being c nec ed, in ground. These PMOS and NMOS transistors xmy he included in their respective circuits to tune or adjust the output

4S impedance of their respective pre-driver drcaits 802-80$.. AdjMSi ie f of fee- m put

Impedance o itsk e the scope of the present escription and f simplicity, the gate te««tsaJs of these tr nsistors are sho n as being ardwire! to the reference voltage REF md grotmd accordingly. However, in. other applications where iso «sljne»t of output in pethsice is des rable, rather ten be hardcoded to the reference voltage REF and t»«« the gate terahttals may be connect to co roi voltages that may be set esltraall , such as by the cote logic circuitry 106 (F gs, ! and 2), to high, or low levels in order to turn on md off these transistors o achieve desired output smpedattces.

fthMlSj Fig. 9 shows a flow chart of an example method 900 of a dock-receiving s stem generating a data signal tb.r eorTOuatestkm on a data fits© to a e!oek-sendmg system. At block 902, core logic dtcmixy may eterm ne thai a tost mtsrS¾ce of the clock-receiviisg s ste h erating it) a tew operating voltage mode where m IO voltage VP^'DG is at a l peratin voltage level rather t&ars in a high operating voltage mode where the ΪΟ voltage VDDO is at a high opera i g voltage level in response, the core logic circuitry may enable a seoosd critical pa h for gene ation of {he data signal to s me example methods, the core logic circuitry may do by gener&tisig and outpntt g a path enable signal thai disables a first Sehmitt trigger powered by the 10 voltage sad eaaMsng a secoad Sehmitt trigger and clock driver circuitry powered by a reference vol age, in additi n, at block 9(52, in order to enable the second crit cal path, the core logic circuitry ma also output the path enable signal to eonligyre reference voltage generation dreaitry to generate and ontput the reference voltage a the low operating voltage level with the 10 voltage also being at the low operating voltage level

fWi j At block 904, the second critical paih, being enabled, may receive a. host clock signal on a h st clock line, generate a pair of complementary el ek signals bas d on the host clock signal and out t the pair of oon^Jeraeraai signals to a multiplexer. In some example

43 methods, t is may include the second Schniitt being emibled, receiv ng the host clock s nal on ¾ clock toe fern a el ek^ndmg system. In resp nse* the second Schmto trigger may geneme a firs clock s gnal ased oo the host dock si nal a i output the to clock signal to ^'the clock driver eir diry, M response, the clock driver oiroiairy may generate a second clock signal based on the .first clock driver w m y ami output die second clock sh af to a clock h fks. In response to receipt of the second clock sigaai, the deck buffer may generate the pair of eompkmeni&ty si nals teed on the wrd clock signal and aui jt the compl men ary signals to th multiplexer.

fthiOTj At block 906, the onjliiplcxer may receive the pair of com lementary signals and two p&m of prs-d m signals, includi g a first pair of pre-data signals and a sec nd pat of re-data signals. The term pre-data signal may refer to a data signal thai includes data to he seat to the clock-sending system and that is generate by the cl cfc^cenin system before and order f»r the data signal to be generated and eonwmnk ted on the clock Urn. The first pair of pre-daia si na may be directly ali ned th each other, and the second pair of pre- data signals may be directly aligned with each nthet. in addition, revious described, the first pair and second pair of pre~dat si nals may be phase-shifted relative to each othe by SKHIegrees relative to each other, or 1.80-degrees relat e to each, other with reference to the complementa dock signals. Doe to the phase shift the first pair of pre-data. si nals n« lea the second pair of pre-d&ta signals.

| W .2^ In addition the rate of the complementary clock signals may be twice the rate of complementary clock sign ls ami the Hirst and second pairs of re-data si nals may be sisch tha fo each of plurality of clock cyc les of the clock signals, during a first half of .he clock cycle where a first of the clock sig als Is hi gh sad a second of the cloc k signals is low, the leading first pa o pre-data signals may raaiatain a constaot level while the lagging second ^•pair of pro-dat signals may tramition their levels (ie.., pcrfottn rising transi lions or falling transitions), sad during a seco half of the dock cyde ere the fi rst eiock signal is low a il ihe sec nd is high, he lagging second pair ofpre-data signals rosy maintain s constant level while we leading first pair of pre-data signals may trans or* their levels. At block 906, initial cycles of the leading fei pair of pre-data signals may he received by the imiitipie-xer at feast arse half cyde of the c mple nta y clock signals before initial cycles of the complementar dock si nals are received by he- multiple e ,

[00129] At block 908, the multiplexer may generate a third pair of rodata. si nals based on reedving the c iptamta dock signals and ihe first and second ai s ef nxtet si nals. In some mmpfe methods, generating the third pair ofpre-dste sipials with the multiplexer at block 908 may include: for each cycle of the co plementary clock signals, d r ng a rst half cycle when tite first clock signal is high aed the second clock signal fa low, setting a voltage on tie firs and second outputs -of the nvdtlplexsr to a level that ma ches a voltage level of the first pair o pre-data s nals, and dndng second half cycle when the first clock signal is low and the second dock signal is high, seating the voltage on the first and second outputs of the multiplexer to a level that matches a voltage level of the second pair of pie-data signals. Also, at block 008 _s the multiplexer may output the third pair ofpre-da s si nals directly to output driver circuitry,

(§0 30] At block §10, the output driver circuitry may general the data signal oa fee data line in response to the third pair of pre-data signals. In some example methods, to generate the data sign l, the output driver circuitry may pull p the voltage to the lo operating voltage level In response to the third pair of pre-data signals being at their respective low levels and may pall down th voltage o low level (e.g., ground or QV) in response to the third pair of se-d ta signals being at their respective hig levels.

SI [001311 Fig. 10 shows a flow chart of another example method 1000 of a eloek-reeeiving syste gcweiaiing a data signal for com nicati n on a data lint? to a clock-sending system. At block 1002, core lo ic ciiceitiy of the cl0ok-.receivi»g system ma generate a imt pair of*re~ lata sigaals including or carrying data, Jhat s Is e seat to the c ck sidi system. The care logic ehx;¾ift"y may generate the first pair of re-data signals in a core vol Ca domain associated ife a cote- voltage VDD, In some esampk me ods, the core logic dteaitry may generate the first pair o te-data si nals nsiag a first dock signal generated with drcaft components of a first critical path of the clock-teeervmg system.. In addition, in s me exam le methods, block 1003 stay also include gene ating the first clock signal with the circuit components of the first eritka! path based. oa receipt of a host dock signal on a host clock line. For example, a Schmitt trigger, being _.powered with a reference voHage REF, may receive the os clock sig»al sad in response, ontpat a second clock signal to clock level shifter circuitry, lie reference- voltage REF ma be set to a low operating voltage level ofaa IQ voltage VDOO, The s co d clock siptal ma oscillate between the low operating voltage- level aad a low level (e„g., 0 Vi The clock level shifter circuitry may generate- a {bird clock signal that is & down-shifted version of the second clock signal. For example, the clock level shifter circuitry may generate the third clock signal by down shifting the second clock signal from the low operating voltage domain to the core voltage domain. The clock level shifter eireaitry mfcy utput the third clock sig l to first clock driver cirCnitry, which in iam may generate the .first clock, signal and output the first clock signal to the core logic ckcuitry. |§0i32J The rate of the first clock si nal tnay be two t mes faster than th rate of the first pair of t¾-data signals. In addition,. he f st pair of re-dala signals may be phase-shifted ^•relative to each other by 0-degrees with reference to their rate and 180-degrees th reference to the rate of the first clock signal A fat pre-data signal of the first pair of pre~ data signals osy lead a second pie-data signal of the tksf pair of pre-dats signals_* In

$2 addiitoa,. at lock 1002_» the core logic circuitr may oaj ut the first pair of pre~data si nals to a first da a path,

[001331 At block 1004, the first data path may recei e the first pair of pre-data signals., and m response genera a second pair of pre~data signals associated with the first pm-data signal of the first pair and a third pair ofpre-data signals associated with the second pro-data signal of the firs* pair. The pre-data signals of 8» second pair ma be directly ahgoed with each the , and the pre^»data signals of the third pair may be directly aligned with each other. Also, the secon and third pasts may he phase-shifted rela ive to eac other m the same way that the first and second data signals of h first air are p se shitted elati e to each other, (00 341 ϊ« some e ample m th ds, at block 1004, ¾ first multiplexer t»a.y receive Che fi t pairaad in. response generate a fourth pair of pre-data signals associated with, the first data gnal of the first pair and a fifth pair of pas-data si n ls associated with the second data signal of the first pair, Mot only may (he first nmitplexer be «ssd to convert the first pair of e-dats s als into e fourth and fifth pair, but it also m y be used to toggle between the first data pth and a second data path being activated. The exam le method ΙΘ00 may be used for when the doek-receHiiig sys em is operating m a low operating vol age mode associated with the low operating voltage level of the 10 voltage VDDO, in alternative m thods, when the doek-reeet ving system is o erati g in. s high operating voltage mode associated with the 10 voltage VDDO bein at a gh operating voltage level, the first multiplexer may activate the second data path instead of the .first data path in order to

[00135] The first mul i lexe may output the fourth and fifth pairs of re-daia signals So level shifter ehx-uit , which in torn may up-sbifi the ibwth and .fif h pairs from the core voltage domain in the low operating voltage dom in to ge&erate sixth and seventh pairs of pre-data signals. The sixth pair of ts-data signals ma he associated with the first pts-data signal of the first pair, and the seventh pair of pre- ata signals may be associated with the second pre-date signal of the first pain The level shifter elrenitry ma output the sixt md v ik pairs of pre^lata sigaals to ¾ ciradtry, ich in tars may generate l s seco and third pairs of pre-data signals. Also, at block 1004, the pre-driver circuitry t y ontpnt the second and third pairs of re-data signals to a second multiplexer_*

M!36| At block 1 (M , the second mul ples** ma receive the second and third pairs of re~data signals as well as a pair of complementary eloek si -safe generated with circuit components of a second em c&l path of the ciock-r ceivmg system Like the fi st clock signal used to ene ate the firs pair of pro-data si nals, the- r te of the complimentary signals mm he twice the of she second and third pairs of re-data .signals. In a dition the relative rates mid phase shifts of the pair of complementary clock si nals md the second md third itas ofpre-d&ta signals .rnay be such that for each of a plurality of clock cycles of the cloek. sigrsals, daring a first half of the clock cycle where a first of the eloek signals Is high and. a &ec»rsd of the clock signals is low, the leading second pair of pre-data stgaais may maintain a eaastant level while the lagging third ai of pre-date signals may transition their levels tie,, perform rising transitions or falling transitions), and dar ng a second half of the clock cycle where the first dock signal is low and the second is igh_* the lagging third pair of pre-<!ai signals ma maintain a constant level while the leading secoa pair fpren a signals raay transition their levels,

[0O137| lu addition, the core logic eiremtry may id output the first pair of pre-date signals, and In tam t e circuit com onents of the ί¾¾ί data may enerate and output the second and third pairs of pre-data signals mm that initial cycles of the second md third pairs are received at a first inputs of the second multiplexer at least one half clock cycle of the com lementary clock signals before initial cycles of the coi«pleroentst clock signals an? received at second in uts of the second multiplexer. [Θ013&1 At block 1008,. t e second multiplexer may generate m eighth pair of pre-data s nals has d 0» ceivin the complementary clock si nals and the second anil third pairs of pre-data signals. The pre-dsta signals of the eight pair amy be directly s%oed with each other, hi addition, in some example- methods, generating tb«? eighth pair ofpre-daia signals with the second m«tftple-xer at bl ck 1 $08 may me!ode: for each cycle of the complementary clock signals, daring a fet half cycle when the first clock signal s high and the seco d clock signal is low, settmg a voltage on first and second owtpals of the second muMi lexer to a level that matches a voltage level of the sec n pair of pre^«data si nals, a«d daring a second half cycle when the first clack signal is low and the second clock i is high, settin the voltage an the first a«d second outputs of the second multiplex r to a level that matches a voltage level of the third pair of prenlata si nals,

|W f J At Mock 1.0.10, the second multiplexer ma ou put the eighth pair of pre-data signals directl to an in t of output driver circuitry. At block: 1012, the output driver circt try may generate the data signal n (to data line la response to receiving the eighth pair of pre~data signals. I» some example methods, to gene a e the data signal, the output driver circaitry may pull up the voltage to the low operating voltage le vel in response to the eighth pair of pre-date signals being at their respective low levels and may pall down, the voltage to a b level (e.g.. ground or 0 V) in response to the eighth pair of pre-date signals being at their respective high levels.

(<ΜΜ Θ| Fig. 11. shows a flow chart of another example method 0 of & clock-receiving s stem generating a data signal for coi.nm«nicatso» m a data rn to a ctack-seadrag systesa_* At 1 102, core logic circuitry of the clock-receiving system may determine that a host interface of the cfcscfc-reeei viag system is operating in a low operating voltage mods. Ai block. 1 04, in resp nse to the determination, the core logic circuitry may output, a data path control signal to a first mnl pkxer to cause the first multiplexer to set a second data path used to generate ttse data signal when fee host interlace is operating in a high opesafeig voltage mode in a deaetiystion state, in the deactivation state, the s c nd data, path may deactivate a secon circuit portion of output driver cir utry while a first circuit flatten of the output driver circuitry generates the data signal on fee coram mcation line.

[Ml 4I| At Mock 1 iOd, in response to reserving the data pat control sign l, the first multiplexe may output and maintain a first pair of voltages on the second data path that .keeps the seeoad data path in the deactivation state, In one example, a first voltage of fee voltage pair may be at a core vol ag level VDD and a secon voltage of the voltage pair may be at a low level, such as 0 V,

(001 21 At block ! 108, fee core logic circuitry tmy output, d the tot multiplexer may recei e from the core logic cireaitry, a first pair of pre-data signal . ^'He first pair of pre-data signals may include d la to be sent to the clock-sending system, in addit on, the first pair of pre- ata sign ls may he generated by the core logic circuitry to a core voltage doma n associated wife fee c re voltage level VDD, Als , the p e-daia signals of the first pair may be hase shifted relative to each tter, as previously described.. In. res onse to receiving the first pair of pr -data signals, the first multiplexer may generate a second and third pair of pre- data slgitak, with, the second pair being associated with a first pre-data signal of the first pair and the third pair being assoc ated wife a second pre-data signal of the first pair, In addition,, the second and th ird pairs ma each be generated in the core voltage domain The first multiplexer may output the second and third pairs ofpre-daia signals on the first data path while outputfetg the fim pair of voltages on the seoasd data path to keep the second data path in fee deactivation slate.

[001431 At block 1 1 10, a second -multiplexer may ge erate a fourth pair of pre-daia signals based on the second arid third pai rs, of ore-data signals for generating the data signal with fee first circuit portion of the output driver circuitry. In so e example methods, in order to generate Ihs fourth pair of pre-data signals, lew! shifter c are-utery of the first data path may receive the second an third pas? of pre-daia signals from the first myitiplessf and in res onse, g ne ate and output and sixth pairs of pre-date signals. he fifth pair of pre- data signal may be associated with the first pre-date signal of the f rst pair and the sixth pah^* of re-data signals rosy be associated with the seeorad pre -data signal of the fi rst pair. Tn addi ion the tevel shifter circatiry may gene ie t e fifth and s xth pairs by converting the seoosd and third pre~dara signals in the core voltage domam to a low operati-ng voltage d maia Pre-dsiver circuitry of the first data path may then receive the fifth aud sixth pairs and getwate ssvect h a e ghth pairs of pre~driver signals based on the fifth and skth pairs. The pre-ddver circuitry ma output the seventh and eighth pairs to the secoud multiplexer in o der to gen ra the fourth air of_.pre-data stgaals. The second wl lexet am also r ceive an use a pair of complementary clock signals generated on a secoad critical path to. order to generate the fourth pair of data signals, as previously described

\mi44\ In addition, at block .1 1 10, circuit components of the second date path may generate a second pair of oltages for deactivating the second circuit porti on of the output, driver circuitry- The second pair of voltages ma foe generated in the low operating voltage omain. In some example methods,, its order to generate the second pair of voltages, the first omiiipkxer may output: the first: pair of voltages to level shifter eireuiay of the .second, data path, which in tarn may generate a third pair of voltages in the l w operating voltage domain, with one of the voltages of the third pair being at the low operating voltage level and the o er of the third pair being at a low level suc as 0 V, The level shifter eireaitry of the second date path may output the third pair of voltages^* to pre-driver circuitry of the second path, whic irs turn may generate the second pair of voltages.

IWI.4S] At block 1112, e second multiplexer may output the fourth pair of pie-date signal* to the first elreeit portion of the output driver circuitry while the second data path outputs the second pair of voltages to the second c mh ^'portion of the oatpwt driver circuitry. At block 1. 1.14, the second circ it portion ma be eactivate in response to the second pair of voltages received frost he second, data path while the first circuit portion pails up and down ^•tfce voltage the data line an response to the fourth pair of pre-data signals to generate the date signal.

§0I46] Fig, ! 2 shows a flow chart of another example method. 1200 of a elook^«t«cdvtag system g^ ra ng a data signal for co municat on on a data line to a eiock^ending system At core logic circuitry of the clock-recdvmg sys em m y determine that a host interlace of the clock-reviving s stem is apera m m a high operating voltage m de. At block 1204, in . esponse to the determit ttion, the core logic circuitry may cutout a date, path control signal to a first multiplexer to cause the first multiplexer to set a first date path use to generate the data signal whets the host Interface fes operating in a low operat n voUage mode in a deactivation state. In the deactivation state, the first da path may deactivate: a first circuit arte of utput dr e circuitry while a second circuit portion of the out ut driver circuitry generates the data signal on the commtimcaiion line.

(Θ014^'?| At block. 1206, in response to receiving the data path control signal, the first .multiplexer may ou ut and maintain, firs t and second pairs of volta ges on the i¾sf data path, that keeps the second dat path in the deactivation, state, in one ex m l , a first voltage of each of the first and sec nd voltage pairs may he at a c te voltage level VDD and a second voltage of each of the first and second voltage pairs may be at a low level, such as 0 V.

100148] At block 120S, the core logic circuitry am out ut, and the first multiplexer may receive from the c te logic circuitry, a pre-data signal thai includes data to fee sent to the clock-sending sys em, Jn addition, t e pre-data s gnal may be generated fey the core logic eireta ry in a core voltage domain associated with the core voltage level VDP, in response to receiving the p e-dat signal_* the first multiplexer may nerate a ftrsl pair of e-data signals. The i¾t pair may he generated m the core voltage d main and be directl aligned with each other. The firs multiplexer x y output the first pair of pre-data signals m the s cond data path w ik o«tp«tting the two ai s of oltages an the first date path to kee the first data path m the deactivation state,

[Ml 491 At Mock 121 , c rc uit components of the second d te path may generate a second pair of pro-data si nals tit he high opets mg oltage detrain based on. the first pair of pre- data signals for generating the data signal with the second, c rcuit portion, of e outpttt driver eircntti . in some example methods, in order to enerate the secon pair ofpre-data signals,, kvet s ifter clre»ttry of the second data path may receive the first pah of pre-data signals fr m the first tnuitipSew and in response, gen ate sad. output, third pai of pre-data signals. The level shifter circuitry may generate the third pair by converting the first pair in the core voltage d main to the high operating voltage domain. Pa-dr v r circuitry of the second data a may thes receive the third pair and generate the second pair based on th third pair, \mi \ In addition, at block .1210, circuit components of the first, data, path may generate a third pair of voltages for deactivating the first cir u t portion of the oBtput driver dreuifry based on the first aud second pairs of voltages. One of the voltages of the third pair may be generated at the high operating voltage level and the other voltage of the third pair may he enerated at a low level such as 0 V. In s me, example taefhadft, its order to generate the third pair of vol tages, the first multiplexer may output the first and second _.pairs of voltages to level shifter circuitry of the first data path, which in turn may generate fourth and fifth pairs of voltages. One of the olt ges of each of the fourth sad fifth pairs may he generated at a relereace voltage level, which may be km than She high operating voltage level (e.g., the reference voltage level, may be the low operating voltage level), and the other voltage of each of the fourth and fifth pairs may be gene ted at a low level such m 0 V_* The level shifter circuitry of the first data path, may output the fourth and fifth pai s of voltages to pre-dri ver

53 ciwaatry of the first path, which in turn may generate sixth, and sevent pairs of voltages. One of the voltages of each of the sixth a id seventh airs i y he generated at the high operatiag voltage e el and the other voltage of each of the sixth and sevent airs may be enerated, at a low level such m 0 V.

[Ml Si J In sosse example methods, the pre-driver eireuitry of the f l data path m y include a pair of pre-ddver eirettl!s, mciading a first pte-dr et circuit arid a second ^d ive cfcamt, that generate the voltages of the sixth mid seventh pairs at the high opetatktg voltage level As previously described with respect to Fig. 8₅ each, of the pre-dt er circuits may Ineisde a firs PMOS transistor that is supplied m 10 voltage VDDO generated at the high operahog voto level aad that pails up a voltage generated an otstpti of a. respecti ve p - driver eirenh to the high o e ating volta e level. The vdtages generated at tire low levels (e.g.. 0 V) of the fourth and fifth pairs may be applied to the gate voltages f the rst MOS transistors to turn on the first PMOS traosistors, ea«si«g them to pail up the voltages at the outptits. Also, each of the pre^»driver circaMs may aelude a OS transistor ith a dram temtlrtal connected to tire output of the respective re^«driver circuit, and a second PMOS transistor with a s urce teimiijal connected to a source terminal of the NMOS t ansistor The drain terminate of the secotsd PMOS transistors tu&y he supplied with the rd¾renes voltage RBF mi gate teifttinals of the sec nd PMOS tiarssfetors may receive the low level voltages of the ioarth anil fifth pairs. The secoad PMOS transistors may set a voltage OK the source terminal of the NMOS tramktors that yields a drain-to-source voltage across the NMOS transistors that is safely below their hi¾akdo ti voltage levels while the first PMOS transistors are pulling up the voltages to the high operating voltage levels.

fWISiJ Also, to generate the third pair of voltages a block 1210_» the pre-ddver eircaitry may output the sixth and .seventh pairs to a second maltlpiexer, which may also receive t eighth pair of voltages as selection sigsmk On of the voltages of the eighth pair ma be ai the reference voltage level and the other voltage of ie eighth pair ntay be at V. In response to feeefving he sixth, evenh, and eighth ars of voltages_* the second m ltiplexer may generate st Us output the shard pai r of voltages. T e sec nd rnaisipis er ma lave the pass gate cireim eon. um.k*n previously shown md described with reference to Fig.6 to receive the sixth, sevenh, and eighth pairs of voltages d g nerate the third pair of voltages,

S 153] At lock 1212, the second dala path m output the second pair of pre-data si n ls to the second eke portion of the output driver circuitry for ge erating (he data s nal m, the data hate while the scond multiplexer cN*tpu& the third air of voltages to the first circuit portion of the oirtpat drive ciradtry. At block 1214, the first cir uit portion may be deactivated res nse to the third pair of voltages received froraa the first data path while the second drcuit portion ptdfe up and do «th¾ volage on the date late in resonse to (he second pair ofpre-data sigsiak to generate the data si na,

|#015 J In other example tnethods, less t m ail of the actions- kfentifled in the Oo charts of Figs, 9-12 may be performed to generte a data, signal for eoimmraicatio® on a dam toe. Still other xam le mehods ma combine at leas t some of the actions pefomed in two or .more of the different methods of Figs.9-12 to generate a ditto signal. Various ways of generating a data signal m a date lias using the actions described in the flow charts with ^•rference to Figs, 9-12 may be possible.

(§01 §51 Figure 1.3 shows a block diagram of as example im tefnea i K of the dock- receiving system 102 and the clock-receiving system 104 of Fig, 1 that may se or include the circuit components shown and described with feren e to Figs.2-8 and/or perform the methods described with reference to Figs, 9-12. The clock-receiving s stem 102 may be a host system 1302 and the clock-receiving system 1 4 tn»y he non-volatile memory system 1300.: The s¾n- olatile memor system 1300 that may me½de two critical aths for two operating voltages. In one embodiment* the sraemsry system 1300 may be a card based s stem., s¾cfj as a secure digital O) or a micro secure d gital (micro-SD) card. I s alternate embodiment, the non-volatile meraaw system 1300 ma be part of m embedded n¾ea»ry system. The host s stem 1302 ma be any eiesttonic system or device titat is configured to conrau cate a»d/ r operate with die non-volatile memory s stem 1300. [Ml 50j As shown in Fig. 13, the nonvolatile memory system J 300 may include the core fogle cifcuitrv 106 sail the host nte face 108, which may include the circuit eot«pone«ts and operate as described above with fet¾re«ce to Fig. 1, in addition, the host-system 13 2 and the- nonv l t le memory system 1300 may be oi l ts! to communicate with each other via ths coi»m»«ttc8tio« bus 1 ! 0, which may incl de the eiock line 112, Ac -nomber of data lines 11.4, sad the co mand lin i 1 , Also, to test s s em O 2 tmy supply a supply oltage VCC on a supply line 118 to the non-volatile memory system 1 00 to power components of the non olatile mem ry system 1300,

JW1S7J la addition the core logic circuitry 106 and the host interface 108, t e »ot votode memor system 1300 may include nonvolatile memor 1304, which tm include a pmmltty- of non-volatile memory elements or cells, eac configured to store one or m te bits of data. The nonvolatile memory -demerits or cells may be any suitable aonvokriie memory cells, such as NAKD flash memory cells and r NO flash memory cells hi a two dimensional and/or three dmieasknial configuration. The meatory ceils may take the form of solid-state (e,g,, Basil} memory cells and cm be one-lime programmable, few-time programmable, or man -time programmable,

|^§015 ] In addition to the operations pre iousl described, the core logic- circuitry 106 ma also be coailgwed to perform memory management factions for the storage of data Its the nonvolatile^•memory 104. Example memory management iimciiorss may include, but not limited to, ommu«fcatl»g with the host system 102, including n?c-e.H½g« handling, and ^•responding to host requests or commands_* such as read, write, am®* and status reqyestscomrosiiiiii receved isws the host system 1302; formatting the nois -volatile memory 1 04 to ensure It is operating p operly; ma ping u ad memory cells; alloeatlag s are ceils to be substituted for .fetee failed ceils; and ti5j»sitio»iiJg the noa-wlatile memory s fesH 1300 between different state, operation -mods, andor power eomurnption modes. In operation, whets the host s sem 102 seeds to read data from or write ata to the wn-volatile m mory 104, ft ma eotmrnreicate wife the core lope circuitry 106·,

[ 0159] The non-vo sie memory system 13Θ0 may also include a memor tefaee (IF) 1306 that provides art .interface between the core logic circuitry 106 and the mn~-vo iie memoty .1304. T e c re logic circuitry ϊθ^' tmy be cor? figued so eomm iiieate daa sad eomtnatttfe with the rk>t vekt.ile memory 1 04 s the memory interface 1306 to st e data i¾ aridor read data from the n n olatile memory 1304.

|WJ M\ The nots-voktile memory system 100 ma also is imk saalog circuitry 1308 that provides s pfeaallty oftsgaJatet s p ly vola es to the core logic eireaitjy i06_s including a core strpply voltage VDD. la addition, the analog drctritiy i 0 may provide a. base clock si nal CLK_BAS_E* ««e «sr more presees^ ttage-iemperature (PVT signals, and a core voltage s&biksi iM signal VDDJSOREjQK. dieat¾g whether the core supply voltage is at a stable level The core logic circuitry 106 tmy send one or more control signals o the analog CireaMry 13 §8 to c iriigEite, program, enable, aiidof disable -ari us comp nents of the analog cir¾aih 130fc.

[0016 ί Wien the host system II 02 sends a read request to mqaesi that the rioa-volaole memo s stem 1300 prfom a ad eperatim to read requested data stored k the stort-voktsle meawy 1304, the core logic- circuitry 106 nwy coramoaicate with the non-volatile memory 304 via the em y interface 1306 to retrieve She requested data. When the requested data is retrieved, the core logic eirewiry 106 »»y provide the data o the

m host snterfeee 108_> which in tarts tmy send the daia as data signals DAT[N-l :0] to ffte host system. 102 oss the ^wmbe of dam lines 1 M -Ii ],

[001621 Tfee nonvolatile i»emory system 1300 may use t e host clock signal CL aoei received m the clock^' line 112 to generate the data si nals DATf -i :0] that are s at back to the host system .1 2 to execute the read pe-mtiojj. la oartkolar,. t e eireirit components of the host interface 108 and/or the core logic drcuttry 106 previousl described with reference to Figs. 2-8 may receive die host dock, signal CL HOST, or at least a buffered version of the host clock signal

and pall up and down the levels of the data s gn ls ΒΑΤ[Ν^«1:ίϊ] aseordmg to the rats of the host clock signal (is,_s aceordtag to the mmg and/or idlmg edge CH uraeees of the ^'h st clock signal! m order to transfer to eq ested data back to the bost s stem 1302 for execution of ihe host read re uest

[00163J Similar cmfigu»¾tk>tis may be mplemented and/or similar methods may be performed in slectroak systems, devices, or ap rais s m ltoa seil-sy ebronotis doek-se«di«g md cloefc-reeeiv g systems other Iters rto.tt~ volat le memor sysiems.

[ 01641 ft is intended that tie foregoing detailed description be understood w m illustration of selected forms that the invention can take md not as a definition of the invention. It is only the following claims, inciading all equivalents, that aire iateaded to deftos the scope of the claimed inveatioa. Fiaally. ii should be nosed that my aspec of my of the preferred embodiments described herein can e used ato e or in comb nati n with one another..

Claims

We claim

1 , A iock-i^eivKi system comprising

output driver circutry eon%»?ed to enerate an output data signal for coraramik-ation cm a data ling of a communcatons has ;.

critical pat circuitry co.«.fig»¾«d to generate a clock sipai bsed on a host clock signal recei ed on a dock \im of the eonmuatea& fts ; a«d

a multiplexer circuit c nfigure to:

re ei e a p!ar&lity of multiplexer input data signals;

receive t e dock signal from the etitfcal path circuitry;

generate a pair of multiplexer oetp»t data, si ais based on the dock signal aad the plurality of m ltiplexer Input data signals: and

o utput the pair of multiple s¾r o tpat d a signals to the o ip»i driver circuitry for gsrsorstiors of the otaput dam signal

2, lie clock-receiving s stem of eiairo J , wherein the critical, path circuity comprises first critical ath circoitr , the clock signal comprises a first clock si nl, and wherein the system farther comprises:

core logic circuitry configure to enable d disable the first critical pah circus try; second critical path circuitry configured to generate a secoud clock signal based on the st clock signal; an

data path circuitry eoa ured to: whea the first critical path s disabled, generate a pair of data p th output data s nals based oa the seco d clock si goal and output the pai of data path, o«ps.st daa si nals to the output driver circutr_* bereis? the m pvsi driver e¾n¾-¾fy s further eo«figured to generate the out ut date s ns! In response to receipt: of the pair of data path, output data signals w en the first critical path disabled

3- Trie clock-rseetying system, of cla m 2_f bercia the eore logic circuitry is further coafiguted to;

nable the first critical _.path etKuttjry for gsaeastkm of (be oucpist data a s ! based oa air of ultiplexer otaput data slpals when a host interface is a low eratin voltage mode; and

disable the first cri ical path dr euiuy for enec atiort of the output data sigaal based m (be _.pair ofo¾ta path output data, si nals when fee host interface is in a high operating voltage mode.

4, The c feck-receiving s stem of data ί , further comprising data ptl* circuitry configured to generate the plurality of mult lexer tapat data si nals, whensia the plurality of multiplexer input data s gnals comprises a first pair of multiplexer hiput data signals and a second pair of multiplexer input data si nals, the first and second pairs phase- shifted 180 degrees rd trve to each other with reference to the dock signal.

5.. The clock-receiving s stem of claim 4, wherein the multiplexer circuit comprises a plurality of _.pass ate circuits, each of the plurality of ass gate circuits c nllg red to receive the clock signal sad one of the multiplexer inpat data signals of the f t and second pa rs of multiplexer input data signals. 6, The clock-receiving s stem of dahn 5_» wherein the plurality f pass gate circuity in order to gen ra e the pair of TOd ipfcxer otii ut data signals, s configured to;

durin first portions; of the clock cycles of the clock si sa)., pass the first pair o f inuiupkxer input data signals to outputs of the multiplexer circuit;

during second portions of the clock cycles of She clock signal, pass ihe second pair of multiplexer iapttt data signals to the outputs of the mu ple>w circuit.

7, The clock-receiving system of claim 6, wherein the pluiah^'ty of ass gate circuits comprises:

a firs? pass gate circuit configured to receive a first multiplexer inpat da a signal of the first pair of multiplexer input d a signals;

a second ass gate circuit coafipred to receive a first multiplexer topnt dam signal of the second pair of multiplexer taput data signals-;.

a third pass gate circuit configured to receive a secoud. multiplexe input data sig al of the first pair of multiplexer input data signals; and

a fourth pass gate circuit configured to recei ve a second multiplexer input data signal of the second pair of multiplexer in ut data si nals,

wherein outputs ef the first and seco d ass ate circuits are connected together to form a firs output: of the outputs of the multiplexer circuit, and o t uts of ihe third and fourth pass gate circuits an? connected together to form a second output of the outputs of She multiplexe circuit

8, The clock receiving system of claim 7, wherein the output dri ve circuit comprises a pull-up circuit and a pu¾klaw» circuit, herein the ull-up circuit comprises a first input

6? eoBBeetsii to the first output of the multiplexer x: u s i_s and whereto the pull- wn circuit composes a second iojmt m tsd to the- second output of the aiultiptexer circuit

9, The elock-weiviog system of daira 4, wberei» the eloe-k signal comprises: a alr of eonspteraeutsi dock signals.

Ml Ttte doek-reeeivtog s stem of <Mm 4, heeto a rare of the clock signal is twice a rate of the plurality of multiplexer pto ata signals,

11, A dock-rceiving s stem comprising:

output driver circuitry c nfigured to ssse m output data signal for c mmunication, oa a data Ime of & m oB^k bus, the output driver circuitry ootrsp sirtg:

a first circuit orion configured to generate the output data signal to a higfe o eraing voltage mod ;

a sec nd eircait orton configured to generate the output daa sigaal to a low operating voltage mode; and

a misltipkserdreiiit configured to:

etttput and maititaia a first set of voltages at a first set oilevds to deactivate tie sec nd circuit portion in the high operating voltage mode; aad

otoput and maintain a second set of voltages at a second set of levels to deactivate the fi rst circuit porfioB in the low oper tist voltage mode.

12_s Tlie doek-reeeiving system of clasra 11, forther e<mprbtog:

m core iog¾c ctrciiitry configured to control whether the multiplexer circuit is eerfgured to utput the fat set of volta es in the .high operating voltage mode or the second set o voltages m the low operating voltage mode.

1.3, The clock-reeeiving system of clam 12, wherein the c re logic circuitry s fttrt er coefigured to;

ia the hi h operatin voltage m de, output a c re out ut data si nal to the multi lexer for eneation of t e output data signal.; and

{ft the low operating voltage mode, output a pair of p ase shifted cots- output daia signafe to fee txiultiptexer f generation of the output dais signal.

1.4, Tie clock~re¾etvi»g s stm of claim 13, wherein te multiplexer is corlgured to: in the high operating voltage mode, output, to first data h circuitry, a first pair of multiplexer ouput data signals for gejswaton of the output data signal in respon se to rece t of the core out t data signal; and

in the low operating voltage mode, output, to second data, path circuitry, a second pair of multi lexer output data signals and a third pair of multiplexer output data, signals, wherein we second pair associated wi th $ first data signal of the pm of phase shifted core output data sgnals and the third pair is associated with a second data signal o the pair of phase shifted core ontpat data signals.

1 . The coek-receivmg s stem of claim 14, wherein:

in the high operating voltage mode:

the first data path e esitry is co fig e to generate a first pair of data path output data si nals based o» the fat pair of multiplexer output data signals; and output the mt pair f daa pata output data signals to the -first circuit portoa of t e output driver circuitry for geasrattoa f the data si s!; d

the second data path ciseeitry is configured to geaerate a third set of voltages at a m! set of leels to the secoad eircait portion of the output driver circuitry for deactivation of the seeood circuit -portion; and

io the tow operatrog v tage mode:

the seetand data path circuitry is c nfi ured to gene ls a second pair of data path o tput data signals based mi me seeo d and third pates of multiplexer outpat data signals; and output the second pair of data path output signals to the seeoadi circuit portioi of the oatpat driver circuitry for geaeratioa of the data sipai; and

the first data path dre toy is c nfi ure to generate a fourth set of voltages at a fourth set of voltage levels to the first circuit porton of the output driver eiteu ry for dsaeti^'vatoft of the first circuit portion,

16, The clock-receiving s stem of dta 1 , wheein the second data path circuitry comprises a pre-driver circuit, comprising:

an ou ut node;

first transistor dreuitry eonaeeted t& the output node aad configured to fee supplied with an inputoutput (¥0) voltage and pull up a voltage at the output node to a level of the I/O voltage;

sec nd traasistar ci uitry eo aected to the output node sad configured o pull o a tite voltage at the output node to rou ; and

third transistor circuitry connected to an internal node of the second transistor cireaitry »sd configured to be supplied with a mfeenee voltage, wherein a le vel o the ^■reference voltage ower thaa a level of the I/O oltage Ϊ» the h igh operating voltage ode. 17, The cloek receiving s stem ofe!aira l*i wherein the second data path circuitry farther comprises leve shifter oirouifcry coaftgwed to generate first and second pairs of tevei shitfer utpti data stgpate based mt the second aad third pairs- of multiplexer output dais signals, he in eaeti of the firsi circuitry, the seeoud circuitry,, and the third circuitry f the te-driver cire¾nt$y comp ises a dafei. si nal input wt tod to a same output of the level shifter circuitry,

18, A method of generating an owtput data slgaal, the method comprising:

outputting, w t core logic circuitry, a pair of phas shifted, core output dais signal; gertemtasg,. wiihdaia path circuitry, a plurality of data path output data sigaals based oa the pair of p ase shifted core output data signals;

geueratiiig, with critical path ci cuitry, a clock l ased eu host clock signal received m a dock Mae;

generating, with a multiplexer circuit, a pair of muiu le&er output data signals hi response to rece ving the phsraiiiy of data path output signals from the data path circuitry and the dock signal from the critical path circuitry; and

generating,, with output driver circuitry, he data signal in response to receiving the pai r of multiplexer output data s gn ls from the multiplexer circuit

19, Tic method of claim ί 8, further comp isin :

enabltag» with the ore logic circuitry, the critical path in rcsposse to determining that a host interface Is operating in a low operating voltage m de. 20; The method of claim 18, w ereto the n tiplexer circuit comprises a first mul iplexer circuit, m& the pai of m ltiplexer output date signals composes a first pair of multi lexer further compriss rsg;

with a second multiplexer, oaiputtJag second and third pairs of multiplexer output data signals m response to ece ing the air csf phase shifted core output data si als from the core logic circuitry to the first daia ath circuitry, while outputtmg a first pair of voltages at eoRsteit levels to second data path circuitry; aud

outputting, with the second path circuitry, a sceswsd pair of voltages at cetostaut levels based au the first pair of voltages,

whereia generatiug the plurality of data palls utput data, sigaals with the first data path circuitry Is based on the iseeond and ftdtd airs of rauHipie&er o tpat data sigrsak, and wherel pnerattng the ut ut data f rial comprises generating, with a fmt circuit portion of the output driver circuitry, the ou p t data signal to response to receiving he first pair of multiplexer output data signals while a sec nd circuit porlioa of the out ut driver circuitry is deactivated ia response to receiving the second, pair of voltages.