WO2017073207A1 - Semiconductor pressure sensor - Google Patents

Semiconductor pressure sensor Download PDF

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Publication number
WO2017073207A1
WO2017073207A1 PCT/JP2016/077850 JP2016077850W WO2017073207A1 WO 2017073207 A1 WO2017073207 A1 WO 2017073207A1 JP 2016077850 W JP2016077850 W JP 2016077850W WO 2017073207 A1 WO2017073207 A1 WO 2017073207A1
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WO
WIPO (PCT)
Prior art keywords
piezoresistor
piezoresistors
wiring
pressure sensor
semiconductor pressure
Prior art date
Application number
PCT/JP2016/077850
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French (fr)
Japanese (ja)
Inventor
直樹 高山
Original Assignee
株式会社フジクラ
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Filing date
Publication date
Priority claimed from JP2016122130A external-priority patent/JP6431505B2/en
Application filed by 株式会社フジクラ filed Critical 株式会社フジクラ
Publication of WO2017073207A1 publication Critical patent/WO2017073207A1/en

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01LMEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
    • G01L9/00Measuring steady of quasi-steady pressure of fluid or fluent solid material by electric or magnetic pressure-sensitive elements; Transmitting or indicating the displacement of mechanical pressure-sensitive elements, used to measure the steady or quasi-steady pressure of a fluid or fluent solid material, by electric or magnetic means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/84Types of semiconductor device ; Multistep manufacturing processes therefor controllable by variation of applied mechanical force, e.g. of pressure

Definitions

  • the present invention relates to a semiconductor pressure sensor.
  • This application claims priority based on Japanese Patent Application No. 2015-212005 filed in Japan on October 28, 2015 and Japanese Patent Application No. 2016-122130 filed in Japan on June 20, 2016. , The contents of which are incorporated herein.
  • This semiconductor pressure sensor includes a diaphragm (pressure receiving portion) formed on a silicon substrate and a piezoresistor formed on the diaphragm by diffusion or ion implantation. When the diaphragm is bent under pressure, it is a sensor that measures a pressure by detecting a change in resistivity caused by applying a stress corresponding to the deflection to the piezoresistor.
  • a semiconductor pressure sensor has characteristics of being ultra-small and ultra-light, and thus is used in various devices such as wrist watches, mobile phones, and other portable devices.
  • Patent Document 1 discloses a conventional semiconductor pressure sensor using a piezoresistive effect.
  • a bridge circuit (a circuit configured by a piezoresistor and detecting the change in resistivity described above) is formed so as to cover an upper portion of the piezoresistor via an insulating film.
  • a semiconductor pressure sensor comprising a conductor film connected to the highest potential part is disclosed.
  • the above-described conductor film reduces measurement errors caused by changes in the resistance value of the piezoresistance caused by ions on the sensor surface or charging.
  • the rising characteristics of the semiconductor pressure sensor are deteriorated due to the parasitic capacitance formed between the conductor film and the piezoresistor.
  • a measurement error is caused when an intermittent operation is performed to suppress the power consumption of the semiconductor pressure sensor.
  • the measurement error becomes smaller as the potential difference between the piezoresistor and the conductor film is smaller. This is because the smaller the potential difference between the piezoresistor and the conductor film, the smaller the charge accumulated in the parasitic capacitance and the smaller the change in resistance value of the piezoresistor.
  • the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor pressure sensor capable of reducing measurement errors as compared with the prior art.
  • a semiconductor pressure sensor includes a semiconductor substrate having a diaphragm portion, a plurality of piezoresistors formed on the surface of the diaphragm portion, and the plurality of piezoresistors.
  • At least one of the plurality of conductive regions may be formed on the insulating film so as to cover the piezoresistor in plan view.
  • At least one of the plurality of wirings is a first wiring formed on the insulating film, and at least one of the plurality of wirings is formed on the surface of the diaphragm portion, and is formed on the insulating film.
  • the second wiring may be connected to the first wiring through the formed contact portion.
  • the first wiring is connected to the first end or the second end of the piezoresistor, and the conductive region is formed on the insulating film from the first end or the second end of the piezoresistor. You may form so that it may extend toward wiring.
  • the plurality of piezoresistors include a first piezoresistor and a second piezoresistor, one end of which is connected to each other, and at least one of the plurality of conductive regions is formed corresponding to the first piezoresistor. It may be a first conductive region, and at least one of the plurality of conductive regions may be a second conductive region formed corresponding to the second piezoresistor.
  • the first piezoresistor and the second piezoresistor may be formed side by side so that the longitudinal direction of the first piezoresistor and the longitudinal direction of the second piezoresistor are in the same direction.
  • the plurality of conductive regions may be formed on the insulating film such that a part of the plurality of conductive regions is located outside the diaphragm portion in plan view.
  • the planar view shape of the plurality of conductive regions on the diaphragm portion may be a point-symmetric shape with respect to the central portion of the diaphragm portion.
  • the conductor film (conductive region) is individually provided corresponding to each of the plurality of piezoresistors formed on the surface of the diaphragm portion, and each conductor film is provided with the first end of the corresponding piezoresistor or Since the connection is made to the second end, the potential difference between the piezoresistor and the conductor film can be reduced, and the measurement error can be reduced as compared with the conventional case.
  • the conductor film is provided corresponding to each of the piezoresistors and is not formed so as to cover all the piezoresistors as in the prior art, so the heat between the conductor film and the diaphragm portion is not provided. It is possible to reduce the stress caused by the difference in the expansion coefficient, and to reduce the measurement error.
  • FIG. 1 is a plan perspective view of a semiconductor pressure sensor according to a first embodiment of the present invention.
  • FIG. 2 is an enlarged view of a portion indicated by a symbol X in FIG. 1.
  • FIG. 2 is a sectional view taken along line AA in FIG. 1. It is a figure which shows the bridge circuit comprised by 1st Embodiment of this invention. It is a figure which shows the bridge circuit comprised by 2nd Embodiment of this invention. It is a figure which shows the bridge circuit comprised by 3rd Embodiment of this invention. It is a figure which shows the bridge circuit comprised by 3rd Embodiment of this invention. It is a figure which shows the bridge circuit comprised by 3rd Embodiment of this invention. It is a figure which shows the bridge circuit comprised by 3rd Embodiment of this invention.
  • FIG. 1 is a plan perspective view of the semiconductor pressure sensor according to the first embodiment of the present invention.
  • FIG. 2 is an enlarged view of a portion indicated by a symbol X in FIG.
  • FIG. 3 is a sectional view taken along the line AA in FIG.
  • the semiconductor pressure sensor 1 according to this embodiment includes a semiconductor substrate 10, piezoresistors 11 to 14, diffusion wirings 21 to 24 (second wiring), an insulating film 30, a conductor film 41 to 44 and metal wires 51 to 54 (first wires).
  • at least one of the conductor films 41 to 44 may be referred to as a conductive region.
  • an individual conductive film among the conductive films 41 to 44 may be indicated as a conductive region.
  • the semiconductor substrate 10 is, for example, a silicon substrate having a rectangular shape in plan view.
  • a diaphragm portion 10 a having a rectangular shape in plan view is formed in the central portion of the semiconductor substrate 10.
  • the diaphragm part 10a is a part where the pressure of the measurement target (for example, fluid) acts, and is configured to bend according to the received pressure.
  • the diaphragm portion 10a is formed, for example, by etching the back surface of the semiconductor substrate 10 to a predetermined thickness.
  • the piezoresistors 11 to 14 are elements in which a piezoresistive effect (a phenomenon in which the resistivity changes due to applied stress) occurs, and is provided for measuring the pressure acting on the diaphragm portion 10a.
  • the piezoresistors 11 to 14 are formed on the surface of the diaphragm portion 10a (surface on the + Z side) so as to be close to the four sides SD1 to SD4 of the diaphragm portion 10a in plan view.
  • the piezoresistors 11 to 14 are formed, for example, by diffusing impurities on the surface of the diaphragm portion 10a.
  • Each of the piezoresistors 11 to 14 includes a pair of piezoresistors that are connected in close proximity to each other.
  • the piezoresistor 11 includes a piezoresistor 11a (first piezoresistor) and a piezoresistor 11b (second piezoresistor).
  • the piezoresistor 12 includes a piezoresistor 12a (first piezoresistor) and a piezoresistor 12b (second piezoresistor).
  • the piezoresistor 13 includes a piezoresistor 13a (first piezoresistor) and a piezoresistor 13b (second piezoresistor).
  • the piezoresistor 14 includes a piezoresistor 14a (first piezoresistor) and a piezoresistor 14b (second piezoresistor).
  • the piezoresistors 11a, 11b, 12a, 12b, 13a, 13b, 14a, and 14b are all formed so as to extend in the Y direction (the longitudinal directions are the same).
  • the piezoresistors 11a and 11b are formed side by side in the X direction at a position close to the side SD1 of the diaphragm portion 10a in plan view.
  • the piezo resistors 12a and 12b are formed side by side in the X direction at a position close to the side SD2 of the diaphragm portion 10a in plan view.
  • the piezoresistors 13a and 13b are formed side by side in the X direction at a position close to the side SD3 of the diaphragm portion 10a in plan view.
  • the piezoresistors 14a and 14b are formed side by side in the X direction at a position close to the side SD4 of the diaphragm portion 10a in plan view.
  • the diffusion wirings 21 to 24 are wirings formed on the surface of the diaphragm portion 10a in order to constitute the bridge circuit BR1 (see FIG. 4) of the piezoresistors 11 to 14.
  • the diffusion wirings 21 to 24 are formed, for example, by diffusing impurities on the surface of the diaphragm portion 10a.
  • the diffusion wiring 21 connects the diffusion wiring 21a connected to the other end (second end) of the piezoresistor 11a, one end (first end) of the piezoresistor 11a, and one end (first end) of the piezoresistor 11b.
  • a diffusion wiring 21b and a diffusion wiring 21c connected to the other end (second end) of the piezoresistor 11b are configured.
  • the diffusion wiring 22 connects the diffusion wiring 22a connected to the other end (second end) of the piezoresistor 12a, one end (first end) of the piezoresistor 12a, and one end (first end) of the piezoresistor 12b.
  • the diffusion wiring 22b and the diffusion wiring 22c connected to the other end (second end) of the piezoresistor 12b are configured.
  • the diffusion wiring 23 connects the diffusion wiring 23a connected to the other end (second end) of the piezoresistor 13a, one end (first end) of the piezoresistor 13a, and one end (first end) of the piezoresistor 13b.
  • a diffusion wiring 23b and a diffusion wiring 23c connected to the other end (second end) of the piezoresistor 13b are configured.
  • the diffusion wiring 24 connects the diffusion wiring 24a connected to the other end (second end) of the piezoresistor 14a, one end (first end) of the piezoresistor 14a, and one end (first end) of the piezoresistor 14b.
  • a diffusion wiring 24b and a diffusion wiring 24c connected to the other end (second end) of the piezoresistor 14b are configured.
  • the insulating film 30 is a member that insulates the surface of the semiconductor substrate 10 on which the piezoresistors 11 to 14 and the diffusion wirings 21 to 24 are formed. As shown in FIGS. 1 and 3, the insulating film 30 is formed on the entire surface of the semiconductor substrate 10 including the surfaces of the piezoresistors 11 to 14 and the surfaces of the diffusion wirings 21 to 24 (so as to cover the entire surface). .
  • a material of the insulating film 30 for example, an oxide film (SiO 2 ) or silicon nitride (SiN) can be used, and the thickness of the insulating film 30 is set to about 100 [nm], for example.
  • the conductor films 41 to 44 are individually formed on the insulating film 30 corresponding to each of the piezoresistors 11 to 14, and the resistance values of the piezoresistors 11 to 14 generated by ions on the surface of the semiconductor substrate 10 or charging. It is provided in order to reduce the measurement error due to the change of.
  • the conductor films 41 to 44 are formed so as to cover the corresponding piezoresistors 11 to 14 in plan view.
  • polysilicon can be used as the material of the conductor films 41 to 44, and the thickness of the conductor films 41 to 44 is set to, for example, about 100 to 500 [nm].
  • the conductor films 41 to 44 include a pair of conductor films formed corresponding to the pair of piezoresistors included in the piezoresistors 11 to 14, respectively.
  • the conductor film (conductive region) 41 corresponds to the piezoresistor 11a and is formed so as to cover the piezoresistor 11a in plan view (first conductor film, first conductive region).
  • a conductor film 41b (second conductor film, second conductive region) corresponding to the piezoresistor 11b and formed to cover the piezoresistor 11b in plan view.
  • the conductor film (conductive region) 42 corresponds to the piezoresistor 12a, and a conductor film 42a (first conductor film, first conductive region) formed so as to cover the piezoresistor 12a in plan view, and a piezoresistor. And a conductor film 42b (second conductor film, second conductive region) formed so as to cover the piezoresistor 12b in plan view.
  • the conductor film (conductive region) 43 corresponds to the piezoresistor 13a, and a conductor film 43a (first conductor film, first conductive region) formed so as to cover the piezoresistor 13a in plan view;
  • a conductor film 43b second conductor film, second conductive region formed so as to cover the piezoresistor 13b in plan view is provided.
  • the conductor film (conductive region) 44 corresponds to the piezoresistor 14a, and a conductor film 44a (first conductor film, first conductive region) formed so as to cover the piezoresistor 14a in plan view, and a piezoresistor. 14b, and a conductor film 44b (second conductor film, second conductive region) formed so as to cover the piezoresistor 14b in plan view.
  • the conductor films 41a, 41b, 42a, 42b, 43a, 43b, 44a, 44b are all on the other end (second end) of the corresponding piezoresistors 11a, 11b, 12a, 12b, 13a, 13b, 14a, 14b. Each is connected.
  • the conductor film 41a is connected to the other end (second end) of the corresponding piezoresistor 11a via the metal wiring 51 and the diffusion wiring 21a.
  • the other end (second end) of the corresponding piezoresistor 11b is connected through the metal wiring 52 and the diffusion wiring 21c.
  • the conductor films 41 to 44 (conductor films 41a, 41b, 42a, 42b, 43a, 43b, 44a, 44b) all extend from the inside (inside) to the outside (outside) of the diaphragm portion 10a in plan view. It is formed on the insulating film 30 so as to exist. That is, the conductor films 41 to 44 are formed such that a part of the conductor films 41 to 44 is located outside (outside) the diaphragm portion 10a in plan view. The reason why a part of the conductor films 41 to 44 is formed so as to be located outside the diaphragm portion 10a in plan view is mainly to reduce measurement errors.
  • the metal wirings 51 to 54 are formed outside the diaphragm portion 10a in a plan view, and part of the conductor films 41 to 44 are positioned outside the diaphragm portion 10a in a plan view.
  • the metal wirings 51 to 54 and the conductor films 41 to 44 are connected to each other outside the diaphragm portion 10a (outside in plan view, outside). In this way, the stress due to the deformation of the metal wirings 51 to 54 is prevented from being applied to the diaphragm portion 10a, thereby preventing an error in the measurement pressure.
  • the conductive film formed inside the diaphragm portion 10a in plan view and the metal wiring formed outside the diaphragm portion 10a in plan view are connected by wiring. It is also possible. Specifically, a first contact portion that connects the conductor film and the surface of the diaphragm portion 10a and a second contact portion that connects the metal wiring and the surface of the semiconductor substrate 10 are formed. The first contact portion and the second contact portion are connected by a diffusion wiring formed on the surface of the semiconductor substrate 10 (diaphragm portion 10a).
  • the conductor films (conductive regions) 41 to 44 have at least a plan view shape on the diaphragm portion 10a as shown in FIG. These are arranged in a point-symmetric shape with respect to the central portion Q of the diaphragm portion 10a.
  • the reason why the conductor films 41 to 44 are arranged in a point-symmetrical shape is mainly to prevent an error from occurring in the output of the semiconductor pressure sensor 1.
  • the piezoresistors piezoresistor 11 and piezoresistor 13 or piezoresistor 13 or piezoresistors 13 disposed at positions facing each other with the central portion Q of the diaphragm portion 10 a interposed therebetween. It is desirable that the same stress changes occur in the resistor 12 and the piezoresistor 14). Therefore, as shown in FIG. 1, the piezoresistors 11 to 14 are arranged point-symmetrically with respect to the central portion Q of the diaphragm portion 10a.
  • planar view shapes (plan view shapes on the diaphragm portion 10a) of the conductor films 41 to 44 formed corresponding to the piezoresistors 11 to 14 are asymmetric with respect to the central portion Q of the diaphragm portion 10a. In this case, the stress applied to the piezoresistors 11 to 14 becomes asymmetric, and an error occurs in the output of the semiconductor pressure sensor 1.
  • the shape of the conductor films 41 to 44 in a plan view (a plan view shape on the diaphragm portion 10a) is made point-symmetric with respect to the central portion Q of the diaphragm portion 10a.
  • an error in the output of the semiconductor pressure sensor 1 is prevented.
  • the shape of the conductor films 41 to 44 in plan view on the diaphragm portion 10a but also the overall shape of the conductor films 41 to 44 (including the shape of the portion extending outside the diaphragm portion 10a in plan view).
  • the shape may be point-symmetric with respect to the central portion Q of the diaphragm portion 10a.
  • the metal wires 51 to 54 are wires formed on the insulating film 30 in order to constitute the bridge circuit BR1 (see FIG. 4) of the piezoresistors 11 to 14 together with the diffusion wires 21 to 24.
  • a material of the metal wirings 51 to 54 for example, aluminum (Al) can be used, and the thickness of the metal wirings 51 to 54 is set to, for example, about 1500 [nm].
  • the metal wiring 51 includes a pad portion 51a provided at the upper left corner of the insulating film 30, a wiring portion 51b extending from the pad portion 51a in the ⁇ Y direction, and a wiring portion 51c extending from the pad portion 51a in the + X direction.
  • the metal wiring 52 includes a pad portion 52a provided at the upper right corner of the insulating film 30 in the drawing, a wiring portion 52b extending from the pad portion 52a in the ⁇ X direction, and a wiring portion 52c extending from the pad portion 52a in the ⁇ Y direction.
  • the metal wiring 53 includes a pad portion 53a provided at the lower right corner of the insulating film 30, a wiring portion 53b extending from the pad portion 53a in the + Y direction, and a wiring portion 53c extending from the pad portion 53a in the ⁇ X direction.
  • the metal wiring 54 includes a pad part 54a provided at the lower left corner of the insulating film 30, a wiring part 54b extending from the pad part 54a in the + X direction, and a wiring part 54c extending from the pad part 54a in the + Y direction.
  • the metal wirings 51 to 54 are connected to the diffusion wirings 21 to 24 through contact portions formed on the insulating film 30. Specifically, as shown in FIG. 2, the metal wiring 51 (wiring part 51c) is connected to the diffusion wiring 21 (diffusion wiring 21a) via the contact part CN.
  • the metal wiring 52 (wiring part 52b) is connected to the diffusion wiring 21 (diffusion wiring 21c) via the contact part CN.
  • the metal wiring 52 (wiring part 52c) is connected to the diffusion wiring 22 (diffusion wiring 22a) through a contact part (not shown).
  • the metal wiring 53 (wiring part 53b) is connected to the diffusion wiring 22 (diffusion wiring 22c) through a contact part (not shown).
  • the contact portion is formed, for example, by etching the insulating film 30, and the metal wiring and the diffusion wiring are connected by filling the contact portion with the metal wiring.
  • the metal wiring 53 (wiring portion 53c) is connected to the diffusion wiring 23 (diffusion wiring 23a) through a contact portion (not shown).
  • the metal wiring 54 (wiring portion 54b) is connected to the diffusion wiring 23 (diffusion wiring 23c) through a contact portion (not shown).
  • the metal wiring 54 (wiring part 54c) is connected to the diffusion wiring 24 (diffusion wiring 24a) through a contact part (not shown).
  • the metal wiring 51 (wiring part 51b) is connected to the diffusion wiring 24 (diffusion wiring 24c) through a contact part (not shown).
  • the conductor film (conductive region) 41a is formed to extend from the first end of the piezoresistor 11a toward the metal wiring 51 (wiring portion 51c).
  • the conductor film (conductive region) 41b is formed so as to extend from the first end of the piezoresistor 11b toward the metal wiring 52 (wiring portion 52b).
  • the metal wiring 51 (wiring part 51c) is connected to the second end of the piezoresistor 11a via the contact part CN and the diffusion wiring 21a.
  • the metal wiring 52 (wiring part 52b) is connected to the second end of the piezoresistor 11b via the contact part CN and the diffusion wiring 21c.
  • the conductor film 41a is formed on the insulating film 30 so as to extend from the first end of the piezoresistor 11a toward the metal wiring 51 (wiring part 51c) connected to the second end of the piezoresistor 11a.
  • the conductor film 41b is formed on the insulating film 30 so as to extend from the first end of the piezoresistor 11b toward the metal wiring 52 (wiring part 52b) connected to the second end of the piezoresistor 11b. ing.
  • the conductor film (conductive region) 42a is directed from the first end of the piezoresistor 12a to the metal wiring 52 (wiring portion 52c) connected to the second end of the piezoresistor 12a. It is formed to extend.
  • the conductor film (conductive region) 42b extends from the first end of the piezoresistor 12b toward the metal wiring 53 (wiring portion 53b) connected to the second end of the piezoresistor 12b. Is formed.
  • the conductor film (conductive region) 43a extends on the insulating film 30 from the first end of the piezoresistor 13a toward the metal wiring 53 (wiring portion 53c) connected to the second end of the piezoresistor 13a.
  • the conductor film (conductive region) 43b extends on the insulating film 30 from the first end of the piezoresistor 13b toward the metal wiring 54 (wiring portion 54b) connected to the second end of the piezoresistor 13b. Is formed.
  • the conductor film (conductive region) 44a extends on the insulating film 30 from the first end of the piezoresistor 14a toward the metal wiring 54 (wiring portion 54c) connected to the second end of the piezoresistor 14a. It is formed as follows.
  • the conductor film (conductive region) 44b extends on the insulating film 30 from the first end of the piezoresistor 14b toward the metal wiring 51 (wiring part 51b) connected to the second end of the piezoresistor 14b. Is formed.
  • FIG. 4 is a diagram showing a bridge circuit configured in the first embodiment of the present invention.
  • the bridge circuit BR1 includes a piezoresistor 11 (11a, 11b), a piezoresistor 12 (12a, 12b), a piezoresistor 13 (13a, 13b), and a piezoresistor 14 (14a, 14b). It is a connected circuit.
  • a metal wiring 51 is connected between the piezoresistor 14 and the piezoresistor 11.
  • a metal wiring 52 is connected between the piezoresistor 11 and the piezoresistor 12.
  • a metal wiring 53 is connected between the piezoresistor 12 and the piezoresistor 13.
  • a metal wiring 54 is connected between the piezoresistor 13 and the piezoresistor 14.
  • the metal wiring 51 is connected to the power source, the metal wiring 53 is grounded, and the metal wirings 52 and 54 are connected to the voltage output terminal.
  • the bridge circuit BR1 shown in FIG. 4 corresponds to the piezoresistor 11 (11a, 11b), the piezoresistor 12 (12a, 12b), the piezoresistor 13 (13a, 13b), and the piezoresistor 14 (14a, 14b).
  • the conductor film 41 (41a, 41b), the conductor film 42 (42a, 42b), the conductor film 43 (43a, 43b), and the conductor film 44 (44a, 44b) are provided.
  • the conductor films 41a, 41b, 42a, 42b, 43a, 43b, 44a, 44b are connected to the second ends of the corresponding piezoresistors 11a, 11b, 12a, 12b, 13a, 13b, 14a, 14b, respectively. Yes.
  • the diaphragm portion 10a bends. Then, stress corresponding to the deflection of the diaphragm portion 10a is applied to the piezoresistors 11 (11a, 11b), piezoresistors 12 (12a, 12b), piezoresistors 13 (13a, 13b), and piezoresistors 14 (14a, 14b). Acts and the resistance value changes. When such a change in resistance value occurs, the voltage between the voltage output terminals to which the metal wirings 52 and 54 are connected changes, and the pressure applied to the diaphragm portion 10a is obtained by detecting the voltage change between the voltage output terminals. be able to.
  • the potential difference between the piezoresistor and the conductor film is considered.
  • the power supply voltage is 4 [V] and the resistance values of the piezoresistors 11a, 11b, 12a, 12b, 13a, 13b, 14a, and 14b are all equal.
  • the conductor film is formed so as to cover all the piezoresistors as in the conventional semiconductor pressure sensor, the potential difference between the conductor film and the piezoresistors is a maximum of the power supply voltage (4 [V]). It becomes the same level.
  • the conductor film (conductive region) corresponding to the piezoresistor is individually formed and connected to the second end of the corresponding piezoresistor.
  • the maximum potential difference is approximately the same as the voltage drop of each piezoresistor (1 [V]), and the potential difference can be significantly reduced as compared with the conventional case. Thereby, a measurement error can be reduced as compared with the conventional case.
  • 43b, 44a, and 44b are individually provided on the insulating film 30.
  • the conductor films 41a, 41b, 42a, 42b, 43a, 43b, 44a, 44b are connected to the second ends of the corresponding piezoresistors 11a, 11b, 12a, 12b, 13a, 13b, 14a, 14b. ing.
  • the conductive film is not formed so as to cover all the piezoresistors as in the prior art, but the conductive regions are individually formed so as to cover each of the piezoresistors in plan view. Therefore, the stress generated by the difference in thermal expansion coefficient between the conductor film and the diaphragm portion 10a (or the insulating film 30) can be reduced. This also makes it possible to reduce measurement errors.
  • FIG. 5 is a diagram showing a bridge circuit configured in the second embodiment of the present invention.
  • the same members as those shown in FIG. 4 are denoted by the same reference numerals.
  • the bridge circuit BR2 configured in the present embodiment is similar to the bridge circuit BR1 shown in FIG. 4.
  • the piezoresistor 11 (11a, 11b), the piezoresistor 12 (12a, 12b), and the piezoresistor 13 (13a, 13b) and a piezoresistor 14 (14a, 14b) are connected in a ring shape.
  • a metal wiring 51 is connected between the piezoresistor 14 and the piezoresistor 11.
  • a metal wiring 52 is connected between the piezoresistor 11 and the piezoresistor 12.
  • a metal wiring 53 is connected between the piezoresistor 12 and the piezoresistor 13.
  • a metal wiring 54 is connected between the piezoresistor 13 and the piezoresistor 14.
  • the bridge circuit BR2 configured in this embodiment is different from the bridge circuit BR1 shown in FIG. 4 in that the conductor films (conductive regions) 41a, 41b, 42a, 42b, 43a, 43b, 44a, 44b are supported.
  • the piezoresistors 11a, 11b, 12a, 12b, 13a, 13b, 14a, 14b are respectively connected to the first ends. That is, in the present embodiment, the conductor films 41 to 44 shown in FIG. 1 are not connected to the metal wirings 51 to 52, but are connected to the diffusion wirings 21 to 24, which is different from the first embodiment. Different.
  • the conductor film 41 (41a, 41b) is not connected to the metal wirings 51, 52 (wiring portions 51c, 52b), but is connected to the diffusion wiring 21 (21b).
  • the conductor film 42 (42a, 42b) is not connected to the metal wirings 52, 53 (wiring portions 52c, 53b), but is connected to the diffusion wiring 22 (22b).
  • the conductor film 43 (43a, 43b) is not connected to the metal wirings 53, 54 (wiring portions 53c, 54b), but is connected to the diffusion wiring 23 (23b).
  • the conductor film 44 (44a, 44b) is not connected to the metal wirings 54, 51 (wiring portions 54c, 51b), but is connected to the diffusion wiring 24 (24b).
  • the semiconductor pressure sensor according to the present embodiment has the conductor films 41a, 41b, 42a, 42b, 43a, 43b, 44a, 44b for the piezoresistors 11a, 11b, 12a, 12b, 13a, 13b, 14a, 14b.
  • the basic configuration is the same as that of the semiconductor pressure sensor according to the first embodiment, except that the positions of the connection points are different. For this reason, also in this embodiment, it is possible to reduce a measurement error compared with the past.
  • FIG. 6A to 6C are diagrams showing a bridge circuit configured in the third embodiment of the present invention.
  • 6A to 6C like FIG. 5, the same members as those shown in FIG. 4 are denoted by the same reference numerals.
  • the piezoresistors 11 to 14 each include a pair of piezoresistors arranged in close proximity with one end connected to each other.
  • (Regions) 41 to 44 have a configuration including a pair of conductor films formed corresponding to the pair of piezoresistors included in the piezoresistors 11 to 14, respectively.
  • the semiconductor pressure sensor according to the present embodiment has a configuration in which each of the piezoresistors 11 to 14 is composed of one element, and the conductor films 41 to 44 are provided for the piezoresistors 11 to 14, respectively. Have.
  • a metal wiring 51 is connected between the piezoresistor 14 and the piezoresistor 11.
  • a metal wiring 52 is connected between the piezoresistor 11 and the piezoresistor 12.
  • a metal wiring 53 is connected between the piezoresistor 12 and the piezoresistor 13.
  • a metal wiring 54 is connected between the piezoresistor 13 and the piezoresistor 14.
  • the conductor films 41 to 44 need only be provided corresponding to the piezoresistors 11 to 14, respectively, and the positions of the connection points of the conductor films 41 to 44 to the piezoresistors 11 to 14 are arbitrary.
  • the conductor films 41 to 44 may be connected to the first ends of the piezoresistors 11 to 14.
  • the conductor films 41 to 44 may be connected to the second ends of the piezoresistors 11 to 14.
  • the conductor film 41 and the conductor film 44 are connected to the metal wiring 51 to have the same potential
  • the conductor film 42 and the conductor film 43 are connected to the metal wiring 53 to have the same potential.
  • the conductor film 41 and the conductor film 42 are connected to the metal wiring 52 to have the same potential
  • the conductor film 43 and the conductor film 44 are connected to the metal wiring 54 to have the same potential. become.
  • the conductor film 41 is connected to the first end of the piezoresistor 11, the conductor film 42 is connected to the second end of the piezoresistor 12, and the conductor film 43 is connected to the first end of the piezoresistor 13.
  • the conductor film 44 may be connected to the second end of the piezoresistor 14.
  • the conductor films 41 to 44 are connected to different metal wirings 51 to 54, respectively. That is, the conductor film 41 is connected to the metal wiring 51, the conductor film 42 is connected to the metal wiring 52, the conductor film 43 is connected to the metal wiring 53, and the conductor film 44 is connected to the metal wiring 54. .
  • the semiconductor pressure sensor according to the present embodiment has a configuration in which the piezoresistors 11 to 14 are composed of one element, and the conductor films 41 to 44 are provided corresponding to the piezoresistors 11 to 14, respectively.
  • the semiconductor pressure sensor according to the present embodiment corresponds to each of the piezoresistors although the number of piezoresistors and conductor films is different from the semiconductor pressure sensor according to the first embodiment and the second embodiment.
  • the conductive film is individually formed and is the same as the first and second embodiments in that the conductive film is connected to the first end or the second end of the corresponding piezoresistor. . For this reason, also in this embodiment, it is possible to reduce a measurement error compared with the past.
  • FIG. 7 is a diagram showing a bridge circuit configured in the fourth embodiment of the present invention.
  • the semiconductor pressure sensors according to the first to third embodiments described above has a configuration in which one conductor film is formed corresponding to one piezoresistor.
  • the semiconductor pressure sensor according to the present embodiment has a configuration in which a plurality of conductor films (conductive regions) are formed corresponding to one piezoresistor.
  • the piezoresistor 11 (11a, 11b), the piezoresistor 12 (12a, 12b), the piezoresistor 13 (13a, 13b), and the piezoresistor. 14 (14a, 14b), conductor film 41 (41a, 41b), conductor film 42 (42a, 42b), conductor film 43 (43a, 43b), and conductor film 44 (44a, 44b). ) Were formed.
  • the conductor films 41 to 44 are formed for the piezoresistors 11 to 14, respectively.
  • a conductor film 41 composed of two conductor films (conductive regions) 41a and 41b is formed corresponding to one piezoresistor 11 and correspondingly formed.
  • a conductor film 42 composed of two conductor films 42 a and 42 b is formed corresponding to one piezoresistor 12.
  • a conductor film 43 composed of two conductor films 43 a and 43 b is formed corresponding to one piezoresistor 13, and two conductors corresponding to one piezoresistor 14.
  • a conductor film 44 composed of the films 44a and 44b is formed correspondingly.
  • the piezoresistors 11 to 14 (piezoresistors each having a pair of piezoresistors) constituting the bridge circuit BR1 shown in FIG. This is a configuration that replaces the piezoresistors 11 to 14 formed of one element.
  • the semiconductor pressure sensor according to the present embodiment has a configuration in which the piezoresistors 11 to 14 are composed of one element, and a plurality of conductor films are provided corresponding to the piezoresistors 11 to 14, respectively.
  • the conductor film is individually formed corresponding to each of the piezoresistors, and the first end or the second end of the piezoresistor corresponding to the conductor film. This is the same as the first to third embodiments in that it is connected to. For this reason, also in this embodiment, it is possible to reduce a measurement error compared with the past.
  • FIG. 8 is a diagram showing a bridge circuit configured in the fifth embodiment of the present invention. Also in FIG. 8, the same members as those shown in FIG. 4 are denoted by the same reference numerals as in FIGS.
  • the number of piezoresistors provided in each of the piezoresistors 11 to 14 and the number of conductor films (conductive regions) provided in each of the conductor films 41 to 44 are set as follows. The configuration is increased from that in the embodiment and the second embodiment. Specifically, in the semiconductor pressure sensor according to the present embodiment, each of the piezoresistors 11 to 14 is provided with four piezoresistors, and each of the conductor films 41 to 44 is provided with four conductor films. Yes.
  • the bridge circuit BR5 configured in this embodiment includes a piezoresistor 11 (11a to 11d), a piezoresistor 12 (12a to 12d), a piezoresistor 13 (13a to 13d), and a piezoresistor 14 ( 14a to 14d) are connected in a ring shape.
  • a metal wiring 51 is connected between the piezoresistor 14 and the piezoresistor 11.
  • a metal wiring 52 is connected between the piezoresistor 11 and the piezoresistor 12.
  • a metal wiring 53 is connected between the piezoresistor 12 and the piezoresistor 13.
  • a metal wiring 54 is connected between the piezoresistor 13 and the piezoresistor 14.
  • the first end of the piezoresistor 11a and the first end of the piezoresistor 11b are connected to each other.
  • the first end of the piezoresistor 11c and the first end of the piezoresistor 11d are connected to each other.
  • the second end of the piezoresistor 11b and the second end of the piezoresistor 11c are connected to each other.
  • the first end of the piezoresistor 12a and the first end of the piezoresistor 12b are connected to each other.
  • the first end of the piezoresistor 12c and the first end of the piezoresistor 12d are connected to each other.
  • the second end of the piezoresistor 12b and the second end of the piezoresistor 12c are connected to each other.
  • the first end of the piezoresistor 13a and the first end of the piezoresistor 13b are connected to each other.
  • the first end of the piezoresistor 13c and the first end of the piezoresistor 13d are connected to each other.
  • the second end of the piezoresistor 13b and the second end of the piezoresistor 13c are connected to each other.
  • the first end of the piezoresistor 14a and the first end of the piezoresistor 14b are connected to each other.
  • the first end of the piezoresistor 14c and the first end of the piezoresistor 14d are connected to each other.
  • the second end of the piezoresistor 14b and the second end of the piezoresistor 14c are connected to each other.
  • the conductive film 41 (41a to 41d), the conductive film 42 (42a to 42d), the conductive film 43 (43a to 43d), and the conductive film 44 (44a to 44d) are provided.
  • the conductor films 41a to 41d, 42a to 42d, 43a to 43d, 44a to 44d are connected to the second ends of the corresponding piezoresistors 11a to 11d, 12a to 12d, 13a to 13d, and 14a to 14d, respectively. Yes.
  • FIG. 9 is a plan view showing the main configuration of a semiconductor pressure sensor according to the fifth embodiment of the present invention, which corresponds to FIG. In FIG. 9, the same members as those shown in FIG. As described above, in the semiconductor pressure sensor according to the present embodiment, the number of piezoresistors provided in each of the piezoresistors 11 to 14 and the number of conductor films provided in each of the conductor films 41 to 44 are set as follows. The configuration is twice that of the embodiment. For this reason, the configuration of the part indicated by the symbol X in FIG. 1 is generally a configuration in which two configurations shown in FIG. 2 are arranged in the X direction as shown in FIG.
  • each of the piezoresistors 11a to 11d provided in the piezoresistor 11 is formed so as to extend in the Y direction (the longitudinal direction is the same direction), and the piezoresistors 11a to 11d are X Arranged side by side.
  • the diffusion line 21 includes a diffusion line 21a connected to the second end of the piezoresistor 11a, a diffusion line 21b connecting the first end of the piezoresistor 11a and the first end of the piezoresistor 11b, and the first of the piezoresistor 11b.
  • a diffusion line 21c connected to two ends, a diffusion line 21d connected to the second end of the piezoresistor 11c, a diffusion line 21e connecting the first end of the piezoresistor 11c and the first end of the piezoresistor 11d, and It comprises a diffusion wiring 21f connected to the second end of the piezoresistor 11d.
  • the conductor film 41 corresponds to the piezoresistor 11a, and is formed so as to cover the piezoresistor 11a in plan view, and to correspond to the piezoresistor 11b and to cover the piezoresistor 11b in plan view.
  • the conductive film 41c formed to cover the piezoresistor 11c in plan view, and to correspond to the piezoresistor 11d and to cover the piezoresistor 11d in plan view And a conductor film 41d formed on the substrate.
  • the conductive film 41b and the conductive film 41c are connected at the end on the -Y side.
  • the conductor films 41a to 41d are all connected to the second ends of the corresponding piezoresistors 11a to 11d, respectively. Specifically, the conductor film 41a is connected to the second end of the corresponding piezoresistor 11a via the metal wiring 51 and the diffusion wiring 21a, and the conductor films 41b and 41c are connected to the metal wiring 55 and the diffusion wirings 21c and 21d. Are connected to the second ends of the corresponding piezoresistors 11b and 11c, respectively, and the conductor film 41d is connected to the second end of the corresponding piezoresistors 11d via the metal wiring 52 and the diffusion wiring 21f.
  • the metal wiring 55 is a wiring formed on the insulating film 30 in order to connect the diffusion wiring 21c, the diffusion wiring 21d, and the conductor films 41b and 41c.
  • the semiconductor pressure sensor according to the present embodiment differs only in the number of piezoresistors provided in each of the piezoresistors 11 to 14 and the number of conductor films provided in each of the conductor films 41 to 44.
  • the basic configuration is the same as that of the semiconductor pressure sensor according to the first embodiment. For this reason, also in this embodiment, it is possible to reduce a measurement error compared with the past.
  • the semiconductor pressure sensor 1 in which the planar shape of the diaphragm portion 10a is rectangular has been described as an example, but the planar shape of the diaphragm portion 10a is not limited to the rectangular shape. Any shape (for example, a circular shape) may be used.
  • the insulating film 30 is formed on the entire surface of the semiconductor substrate 10 including the surfaces of the piezoresistors 11 to 14 and the surfaces of the diffusion wirings 21 to 24 (so as to cover the entire surface).
  • the insulating film 30 above the diaphragm portion 10a except for the portion where the piezoresistors 11 to 14, the diffusion wirings 21 to 24, and the conductor films 41 to 44 are formed) may be omitted.

Abstract

Provided is a semiconductor pressure sensor, wherein: the semiconductor pressure sensor is provided with a semiconductor substrate having a diaphragm part, a plurality of piezoresistors formed on the surface of the diaphragm part, a plurality of wirings that connect the plurality of piezoresistors to constitute part of a bridge circuit, an insulation film formed so as to cover the surface of the semiconductor substrate including the surfaces of the plurality of piezoresistors, and an electroconductive film having a plurality of electroconductive regions independently formed on the insulation film correspondingly with respect to the plurality of piezoresistors; at least one of the electroconductive regions being connected to a first end or a second end of one of the piezoresistors.

Description

半導体圧力センサSemiconductor pressure sensor
 本発明は、半導体圧力センサに関する。
 本願は、2015年10月28日に、日本に出願された特願2015-212005号、および2016年6月20日に、日本に出願された特願2016-122130号に基づき優先権を主張し、その内容をここに援用する。
The present invention relates to a semiconductor pressure sensor.
This application claims priority based on Japanese Patent Application No. 2015-212005 filed in Japan on October 28, 2015 and Japanese Patent Application No. 2016-122130 filed in Japan on June 20, 2016. , The contents of which are incorporated herein.
 近年、MEMS(Micro Electro-Mechanical Systems)技術を用いて製造され、ピエゾ抵抗効果(ピエゾ抵抗に加わる応力によって抵抗率が変化する現象)を利用して圧力を測定する半導体圧力センサが開発されている。この半導体圧力センサは、シリコン基板に形成されたダイヤフラム(受圧部)と、ダイヤフラムに上に拡散やイオン打ち込み等によって形成されたピエゾ抵抗とを備えており、ダイヤフラムが圧力を受けて撓んだ際に、撓みに応じた応力がピエゾ抵抗に加わることによって生ずる抵抗率の変化を検出して圧力を測定するセンサである。このような半導体圧力センサは、超小型、超軽量という特徴を有することから、腕時計、携帯電話機、その他の携帯用の機器をはじめとして種々の機器に用いられている。 In recent years, semiconductor pressure sensors that are manufactured using MEMS (Micro Electro-Mechanical Systems) technology and measure pressure using the piezoresistive effect (a phenomenon in which resistivity changes due to stress applied to the piezoresistor) have been developed. . This semiconductor pressure sensor includes a diaphragm (pressure receiving portion) formed on a silicon substrate and a piezoresistor formed on the diaphragm by diffusion or ion implantation. When the diaphragm is bent under pressure In addition, it is a sensor that measures a pressure by detecting a change in resistivity caused by applying a stress corresponding to the deflection to the piezoresistor. Such a semiconductor pressure sensor has characteristics of being ultra-small and ultra-light, and thus is used in various devices such as wrist watches, mobile phones, and other portable devices.
 以下の特許文献1には、ピエゾ抵抗効果を利用した従来の半導体圧力センサが開示されている。具体的に、以下の特許文献1には、絶縁膜を介してピエゾ抵抗の上方を覆うように形成され、ブリッジ回路(ピエゾ抵抗によって構成されて、上述の抵抗率の変化を検出する回路)の最高電位部に接続される導電体膜を備える半導体圧力センサが開示されている。この半導体圧力センサでは、上記の導電体膜によって、センサ表面のイオンや帯電によって生ずるピエゾ抵抗の抵抗値の変化に起因する測定誤差を低減するようにしている。 The following Patent Document 1 discloses a conventional semiconductor pressure sensor using a piezoresistive effect. Specifically, in Patent Document 1 below, a bridge circuit (a circuit configured by a piezoresistor and detecting the change in resistivity described above) is formed so as to cover an upper portion of the piezoresistor via an insulating film. A semiconductor pressure sensor comprising a conductor film connected to the highest potential part is disclosed. In this semiconductor pressure sensor, the above-described conductor film reduces measurement errors caused by changes in the resistance value of the piezoresistance caused by ions on the sensor surface or charging.
日本国特許第5002468号公報Japanese Patent No. 5002468
 ところで、上述した特許文献1に開示された半導体圧力センサでは、全てのピエゾ抵抗がブリッジ回路の最高電位部に接続される導電体膜によって覆われているため、ピエゾ抵抗と導電体膜との間の電位差がピエゾ抵抗の位置に応じて異なる。これにより、シリコン基板表面のキャリアの分布がピエゾ抵抗の位置に応じて変化することから、出力オフセット或いは感度の変化が生じ、測定誤差が生じてしまうという問題がある。 By the way, in the semiconductor pressure sensor disclosed in Patent Document 1 described above, since all the piezoresistors are covered with the conductor film connected to the highest potential portion of the bridge circuit, the piezoresistor and the conductor film are not connected. The potential difference differs depending on the position of the piezoresistor. As a result, the carrier distribution on the surface of the silicon substrate changes according to the position of the piezoresistor, so that there is a problem that an output offset or a change in sensitivity occurs and a measurement error occurs.
 また、上述した特許文献1に開示された半導体圧力センサでは、導電体膜とピエゾ抵抗との間に形成される寄生容量によって、半導体圧力センサの立ち上がり特性が悪化する。
 このような立ち上がり特性の悪化が生ずると、間欠動作をさせて半導体圧力センサの消費電力を抑える場合に、測定誤差が生ずる原因となるという問題がある。尚、測定誤差は、ピエゾ抵抗と導電体膜との間の電位差が小さいほど小さくなる。これは、ピエゾ抵抗と導電体膜との間の電位差が小さいほど、寄生容量に蓄積される電荷が小さくなり、且つピエゾ抵抗の抵抗値変化が小さくなるためである。
Moreover, in the semiconductor pressure sensor disclosed in Patent Document 1 described above, the rising characteristics of the semiconductor pressure sensor are deteriorated due to the parasitic capacitance formed between the conductor film and the piezoresistor.
When such a rise characteristic is deteriorated, there is a problem that a measurement error is caused when an intermittent operation is performed to suppress the power consumption of the semiconductor pressure sensor. The measurement error becomes smaller as the potential difference between the piezoresistor and the conductor film is smaller. This is because the smaller the potential difference between the piezoresistor and the conductor film, the smaller the charge accumulated in the parasitic capacitance and the smaller the change in resistance value of the piezoresistor.
 また、上述した特許文献1に開示された半導体圧力センサでは、導電体膜が全てのピエゾ抵抗を覆うように形成されていることから、導電体膜とダイヤフラム(或いは、絶縁体)との熱膨張係数の差によって生ずる応力が大きくなる。このような応力が大きくなると、ダイヤフラムが圧力を受けた際の撓みの程度が変化するため、測定誤差が生じてしまうという問題がある。 In the semiconductor pressure sensor disclosed in Patent Document 1 described above, since the conductor film is formed so as to cover all the piezoresistors, the thermal expansion between the conductor film and the diaphragm (or the insulator) is performed. The stress caused by the difference in coefficients increases. When such stress increases, there is a problem in that a measurement error occurs because the degree of bending when the diaphragm is subjected to pressure changes.
 本発明は上記事情に鑑みてなされたものであり、従来よりも測定誤差を低減することが可能な半導体圧力センサを提供することを目的とする。 The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor pressure sensor capable of reducing measurement errors as compared with the prior art.
 上記課題を解決するために、本発明の第一態様に係る半導体圧力センサは、ダイヤフラム部を有する半導体基板と、前記ダイヤフラム部の表面に形成された複数のピエゾ抵抗と、前記複数のピエゾ抵抗を接続してブリッジ回路を構成する複数の配線と、前記複数のピエゾ抵抗の表面を含む前記半導体基板の表面を覆うように形成された絶縁膜と、前記複数のピエゾ抵抗に対応して前記絶縁膜上に個別に形成された複数の導電領域を有する導電体膜と、を備え、少なくとも一つの導電領域は、一のピエゾ抵抗の第一端又は第二端に接続されている。
 前記複数の導電領域のうち少なくとも一つは、前記ピエゾ抵抗を平面視で覆うように前記絶縁膜上に形成されていてもよい。
 前記複数の配線のうち少なくとも一つは、前記絶縁膜上に形成された第1配線であり、前記複数の配線のうち少なくとも一つは、前記ダイヤフラム部の前記表面に形成され、前記絶縁膜に形成されたコンタクト部を介して前記第1配線に接続されている第2配線であってもよい。
 前記第1配線は前記ピエゾ抵抗の前記第一端又は前記第二端に接続され、前記導電領域は、前記絶縁膜上において、前記ピエゾ抵抗の前記第一端又は前記第二端から前記第1配線に向かって延びるように形成されていてもよい。
 前記複数のピエゾ抵抗は、一端が互いに接続された第1ピエゾ抵抗と第2ピエゾ抵抗とを備え、前記複数の導電領域のうち少なくとも一つは、前記第1ピエゾ抵抗に対応して形成された第1導電領域であり、前記複数の導電領域のうち少なくとも一つは、前記第2ピエゾ抵抗に対応して形成された第2導電領域であってもよい。
 前記第1ピエゾ抵抗と前記第2ピエゾ抵抗とは、前記第1ピエゾ抵抗の長手方向と前記第2ピエゾ抵抗の長手方向とが同じ方向になるように並べて形成されていてもよい。
 前記複数の導電領域は、前記複数の導電領域の一部が平面視で前記ダイヤフラム部の外側に位置するように前記絶縁膜上に形成されていてもよい。
 前記複数の導電領域の前記ダイヤフラム部上における平面視形状は、前記ダイヤフラム部の中央部に対して点対称形状であってもよい。
In order to solve the above problems, a semiconductor pressure sensor according to a first aspect of the present invention includes a semiconductor substrate having a diaphragm portion, a plurality of piezoresistors formed on the surface of the diaphragm portion, and the plurality of piezoresistors. A plurality of wires connected to form a bridge circuit; an insulating film formed to cover a surface of the semiconductor substrate including a surface of the plurality of piezoresistors; and the insulating film corresponding to the plurality of piezoresistors A conductive film having a plurality of conductive regions individually formed thereon, and at least one conductive region is connected to a first end or a second end of one piezoresistor.
At least one of the plurality of conductive regions may be formed on the insulating film so as to cover the piezoresistor in plan view.
At least one of the plurality of wirings is a first wiring formed on the insulating film, and at least one of the plurality of wirings is formed on the surface of the diaphragm portion, and is formed on the insulating film. The second wiring may be connected to the first wiring through the formed contact portion.
The first wiring is connected to the first end or the second end of the piezoresistor, and the conductive region is formed on the insulating film from the first end or the second end of the piezoresistor. You may form so that it may extend toward wiring.
The plurality of piezoresistors include a first piezoresistor and a second piezoresistor, one end of which is connected to each other, and at least one of the plurality of conductive regions is formed corresponding to the first piezoresistor. It may be a first conductive region, and at least one of the plurality of conductive regions may be a second conductive region formed corresponding to the second piezoresistor.
The first piezoresistor and the second piezoresistor may be formed side by side so that the longitudinal direction of the first piezoresistor and the longitudinal direction of the second piezoresistor are in the same direction.
The plurality of conductive regions may be formed on the insulating film such that a part of the plurality of conductive regions is located outside the diaphragm portion in plan view.
The planar view shape of the plurality of conductive regions on the diaphragm portion may be a point-symmetric shape with respect to the central portion of the diaphragm portion.
 上記態様によれば、ダイヤフラム部表面に形成された複数のピエゾ抵抗の各々に対応して個別に導電体膜(導電領域)を設け、各々の導電体膜を対応するピエゾ抵抗の第一端又は第二端に接続するようにしているため、ピエゾ抵抗と導電体膜との間の電位差を小さくすることができ、従来よりも測定誤差を低減することが可能であるという効果がある。
 また、導電体膜は、ピエゾ抵抗の各々に対応して設けられており、従来のように全てのピエゾ抵抗を覆うように形成されている訳ではないため、導電体膜とダイヤフラム部との熱膨張係数の差によって生ずる応力を小さくすることができ、測定誤差を低減することが可能であるという効果がある。
According to the above aspect, the conductor film (conductive region) is individually provided corresponding to each of the plurality of piezoresistors formed on the surface of the diaphragm portion, and each conductor film is provided with the first end of the corresponding piezoresistor or Since the connection is made to the second end, the potential difference between the piezoresistor and the conductor film can be reduced, and the measurement error can be reduced as compared with the conventional case.
In addition, the conductor film is provided corresponding to each of the piezoresistors and is not formed so as to cover all the piezoresistors as in the prior art, so the heat between the conductor film and the diaphragm portion is not provided. It is possible to reduce the stress caused by the difference in the expansion coefficient, and to reduce the measurement error.
本発明の第1実施形態に係る半導体圧力センサの平面透視図である。1 is a plan perspective view of a semiconductor pressure sensor according to a first embodiment of the present invention. 図1中の符号Xで指し示されている部分の拡大図である。FIG. 2 is an enlarged view of a portion indicated by a symbol X in FIG. 1. 図1中のA-A線に沿う断面矢視図である。FIG. 2 is a sectional view taken along line AA in FIG. 1. 本発明の第1実施形態で構成されるブリッジ回路を示す図である。It is a figure which shows the bridge circuit comprised by 1st Embodiment of this invention. 本発明の第2実施形態で構成されるブリッジ回路を示す図である。It is a figure which shows the bridge circuit comprised by 2nd Embodiment of this invention. 本発明の第3実施形態で構成されるブリッジ回路を示す図である。It is a figure which shows the bridge circuit comprised by 3rd Embodiment of this invention. 本発明の第3実施形態で構成されるブリッジ回路を示す図である。It is a figure which shows the bridge circuit comprised by 3rd Embodiment of this invention. 本発明の第3実施形態で構成されるブリッジ回路を示す図である。It is a figure which shows the bridge circuit comprised by 3rd Embodiment of this invention. 本発明の第4実施形態で構成されるブリッジ回路を示す図である。It is a figure which shows the bridge circuit comprised by 4th Embodiment of this invention. 本発明の第5実施形態で構成されるブリッジ回路を示す図である。It is a figure which shows the bridge circuit comprised by 5th Embodiment of this invention. 本発明の第5実施形態に係る半導体圧力センサの要部構成を示す平面図である。It is a top view which shows the principal part structure of the semiconductor pressure sensor which concerns on 5th Embodiment of this invention.
 以下、図面を参照して本発明の実施形態に係る半導体圧力センサについて詳細に説明する。尚、以下では理解を容易にするために、図中に設定したXYZ直交座標系(原点の位置は適宜変更する)を必要に応じて参照しつつ各部材の位置関係について説明する。また、以下で参照する図面では、理解を容易にするために、必要に応じて各部材の寸法を適宜変えて図示している。 Hereinafter, a semiconductor pressure sensor according to an embodiment of the present invention will be described in detail with reference to the drawings. In the following, for easy understanding, the positional relationship of each member will be described with reference to the XYZ orthogonal coordinate system (the position of the origin is changed as appropriate) set in the drawing as necessary. Further, in the drawings referred to below, the dimensions of each member are appropriately changed as necessary for easy understanding.
〔第1実施形態〕
 図1は、本発明の第1実施形態に係る半導体圧力センサの平面透視図である。図2は、図1中の符号Xで指し示されている部分の拡大図である。図3は、図1中のA-A線に沿う断面矢視図である。図1~図3に示す通り、本実施形態に係る半導体圧力センサ1は、半導体基板10、ピエゾ抵抗11~14、拡散配線21~24(第2配線)、絶縁膜30、導電体膜41~44、及び金属配線51~54(第1配線)を備える。なお、以下において、導電体膜41~44のうち少なくとも1つの導電体膜を導電領域と示すことがある。換言すれば、導電体膜41~44のうち個別の導電体膜を指して、導電領域と示すことがある。
[First Embodiment]
FIG. 1 is a plan perspective view of the semiconductor pressure sensor according to the first embodiment of the present invention. FIG. 2 is an enlarged view of a portion indicated by a symbol X in FIG. FIG. 3 is a sectional view taken along the line AA in FIG. As shown in FIGS. 1 to 3, the semiconductor pressure sensor 1 according to this embodiment includes a semiconductor substrate 10, piezoresistors 11 to 14, diffusion wirings 21 to 24 (second wiring), an insulating film 30, a conductor film 41 to 44 and metal wires 51 to 54 (first wires). Hereinafter, at least one of the conductor films 41 to 44 may be referred to as a conductive region. In other words, an individual conductive film among the conductive films 41 to 44 may be indicated as a conductive region.
 半導体基板10は、例えば平面視形状が矩形形状であるシリコン基板である。半導体基板10の中央部には、平面視形状が矩形形状のダイヤフラム部10aが形成されている。ダイヤフラム部10aは、測定対象(例えば、流体)の圧力が作用する部位であり、受けた圧力に応じた撓みが生ずるように構成されている。ダイヤフラム部10aは、例えば半導体基板10の裏面を予め規定された厚みになるまでエッチングすることによって形成される。 The semiconductor substrate 10 is, for example, a silicon substrate having a rectangular shape in plan view. A diaphragm portion 10 a having a rectangular shape in plan view is formed in the central portion of the semiconductor substrate 10. The diaphragm part 10a is a part where the pressure of the measurement target (for example, fluid) acts, and is configured to bend according to the received pressure. The diaphragm portion 10a is formed, for example, by etching the back surface of the semiconductor substrate 10 to a predetermined thickness.
 ピエゾ抵抗11~14は、ピエゾ抵抗効果(加わる応力によって抵抗率が変化する現象)が生ずる素子であり、ダイヤフラム部10aに作用する圧力を測定するために設けられる。ピエゾ抵抗11~14は、それぞれ平面視でダイヤフラム部10aの4つの辺SD1~SD4に近接するようにダイヤフラム部10aの表面(+Z側の面)に形成されている。尚、ピエゾ抵抗11~14は、例えば不純物をダイヤフラム部10aの表面に拡散させることによって形成される。 The piezoresistors 11 to 14 are elements in which a piezoresistive effect (a phenomenon in which the resistivity changes due to applied stress) occurs, and is provided for measuring the pressure acting on the diaphragm portion 10a. The piezoresistors 11 to 14 are formed on the surface of the diaphragm portion 10a (surface on the + Z side) so as to be close to the four sides SD1 to SD4 of the diaphragm portion 10a in plan view. The piezoresistors 11 to 14 are formed, for example, by diffusing impurities on the surface of the diaphragm portion 10a.
 ピエゾ抵抗11~14は、一端が互いに接続されて近接配置された一対のピエゾ抵抗をそれぞれ備える。具体的に、ピエゾ抵抗11は、ピエゾ抵抗11a(第1ピエゾ抵抗)とピエゾ抵抗11b(第2ピエゾ抵抗)とを備えている。ピエゾ抵抗12は、ピエゾ抵抗12a(第1ピエゾ抵抗)とピエゾ抵抗12b(第2ピエゾ抵抗)とを備えている。また、ピエゾ抵抗13は、ピエゾ抵抗13a(第1ピエゾ抵抗)とピエゾ抵抗13b(第2ピエゾ抵抗)とを備えている。ピエゾ抵抗14は、ピエゾ抵抗14a(第1ピエゾ抵抗)とピエゾ抵抗14b(第2ピエゾ抵抗)とを備えている。 Each of the piezoresistors 11 to 14 includes a pair of piezoresistors that are connected in close proximity to each other. Specifically, the piezoresistor 11 includes a piezoresistor 11a (first piezoresistor) and a piezoresistor 11b (second piezoresistor). The piezoresistor 12 includes a piezoresistor 12a (first piezoresistor) and a piezoresistor 12b (second piezoresistor). The piezoresistor 13 includes a piezoresistor 13a (first piezoresistor) and a piezoresistor 13b (second piezoresistor). The piezoresistor 14 includes a piezoresistor 14a (first piezoresistor) and a piezoresistor 14b (second piezoresistor).
 ピエゾ抵抗11a,11b,12a,12b,13a,13b,14a,14bは何れも、Y方向に延びるように(長手方向が同じ方向になるように)形成されている。ピエゾ抵抗11a,11bは、平面視でダイヤフラム部10aの辺SD1に近接する位置においてX方向に並べて形成されている。ピエゾ抵抗12a,12bは、平面視でダイヤフラム部10aの辺SD2に近接する位置においてX方向に並べて形成されている。また、ピエゾ抵抗13a,13bは、平面視でダイヤフラム部10aの辺SD3に近接する位置においてX方向に並べて形成されている。ピエゾ抵抗14a,14bは、平面視でダイヤフラム部10aの辺SD4に近接する位置においてX方向に並べて形成されている。 The piezoresistors 11a, 11b, 12a, 12b, 13a, 13b, 14a, and 14b are all formed so as to extend in the Y direction (the longitudinal directions are the same). The piezoresistors 11a and 11b are formed side by side in the X direction at a position close to the side SD1 of the diaphragm portion 10a in plan view. The piezo resistors 12a and 12b are formed side by side in the X direction at a position close to the side SD2 of the diaphragm portion 10a in plan view. The piezoresistors 13a and 13b are formed side by side in the X direction at a position close to the side SD3 of the diaphragm portion 10a in plan view. The piezoresistors 14a and 14b are formed side by side in the X direction at a position close to the side SD4 of the diaphragm portion 10a in plan view.
 拡散配線21~24は、ピエゾ抵抗11~14のブリッジ回路BR1(図4参照)を構成するために、ダイヤフラム部10aの表面に形成される配線である。尚、拡散配線21~24は、例えば不純物をダイヤフラム部10aの表面に拡散させることによって形成される。 The diffusion wirings 21 to 24 are wirings formed on the surface of the diaphragm portion 10a in order to constitute the bridge circuit BR1 (see FIG. 4) of the piezoresistors 11 to 14. The diffusion wirings 21 to 24 are formed, for example, by diffusing impurities on the surface of the diaphragm portion 10a.
 拡散配線21は、ピエゾ抵抗11aの他端(第二端)に接続された拡散配線21a、ピエゾ抵抗11aの一端(第一端)とピエゾ抵抗11bの一端(第一端)とを互いに接続する拡散配線21b、及びピエゾ抵抗11bの他端(第二端)に接続された拡散配線21cから構成される。拡散配線22は、ピエゾ抵抗12aの他端(第二端)に接続された拡散配線22a、ピエゾ抵抗12aの一端(第一端)とピエゾ抵抗12bの一端(第一端)とを互いに接続する拡散配線22b、及びピエゾ抵抗12bの他端(第二端)に接続された拡散配線22cから構成される。 The diffusion wiring 21 connects the diffusion wiring 21a connected to the other end (second end) of the piezoresistor 11a, one end (first end) of the piezoresistor 11a, and one end (first end) of the piezoresistor 11b. A diffusion wiring 21b and a diffusion wiring 21c connected to the other end (second end) of the piezoresistor 11b are configured. The diffusion wiring 22 connects the diffusion wiring 22a connected to the other end (second end) of the piezoresistor 12a, one end (first end) of the piezoresistor 12a, and one end (first end) of the piezoresistor 12b. The diffusion wiring 22b and the diffusion wiring 22c connected to the other end (second end) of the piezoresistor 12b are configured.
 拡散配線23は、ピエゾ抵抗13aの他端(第二端)に接続された拡散配線23a、ピエゾ抵抗13aの一端(第一端)とピエゾ抵抗13bの一端(第一端)とを互いに接続する拡散配線23b、及びピエゾ抵抗13bの他端(第二端)に接続された拡散配線23cから構成される。拡散配線24は、ピエゾ抵抗14aの他端(第二端)に接続された拡散配線24a、ピエゾ抵抗14aの一端(第一端)とピエゾ抵抗14bの一端(第一端)とを互いに接続する拡散配線24b、及びピエゾ抵抗14bの他端(第二端)に接続された拡散配線24cから構成される。 The diffusion wiring 23 connects the diffusion wiring 23a connected to the other end (second end) of the piezoresistor 13a, one end (first end) of the piezoresistor 13a, and one end (first end) of the piezoresistor 13b. A diffusion wiring 23b and a diffusion wiring 23c connected to the other end (second end) of the piezoresistor 13b are configured. The diffusion wiring 24 connects the diffusion wiring 24a connected to the other end (second end) of the piezoresistor 14a, one end (first end) of the piezoresistor 14a, and one end (first end) of the piezoresistor 14b. A diffusion wiring 24b and a diffusion wiring 24c connected to the other end (second end) of the piezoresistor 14b are configured.
 絶縁膜30は、ピエゾ抵抗11~14及び拡散配線21~24が形成された半導体基板10の表面を絶縁する部材である。絶縁膜30は、図1,図3に示す通り、ピエゾ抵抗11~14の表面及び拡散配線21~24の表面を含む半導体基板10の表面の全面に(全面を覆うように)形成されている。絶縁膜30の材料としては、例えば酸化膜(SiO)や窒化シリコン(SiN)を用いることができ、絶縁膜30の厚みは、例えば100[nm]程度に設定される。 The insulating film 30 is a member that insulates the surface of the semiconductor substrate 10 on which the piezoresistors 11 to 14 and the diffusion wirings 21 to 24 are formed. As shown in FIGS. 1 and 3, the insulating film 30 is formed on the entire surface of the semiconductor substrate 10 including the surfaces of the piezoresistors 11 to 14 and the surfaces of the diffusion wirings 21 to 24 (so as to cover the entire surface). . As a material of the insulating film 30, for example, an oxide film (SiO 2 ) or silicon nitride (SiN) can be used, and the thickness of the insulating film 30 is set to about 100 [nm], for example.
 導電体膜41~44は、ピエゾ抵抗11~14の各々に対応して絶縁膜30上に個別に形成されており、半導体基板10の表面のイオンや帯電によって生ずるピエゾ抵抗11~14の抵抗値の変化に起因する測定誤差を低減するために設けられる。導電体膜41~44は、対応するピエゾ抵抗11~14を平面視で覆うように形成されている。導電体膜41~44の材料としては、例えばポリシリコンを用いることができ、導電体膜41~44の厚みは、例えば100~500[nm]程度に設定される。 The conductor films 41 to 44 are individually formed on the insulating film 30 corresponding to each of the piezoresistors 11 to 14, and the resistance values of the piezoresistors 11 to 14 generated by ions on the surface of the semiconductor substrate 10 or charging. It is provided in order to reduce the measurement error due to the change of. The conductor films 41 to 44 are formed so as to cover the corresponding piezoresistors 11 to 14 in plan view. For example, polysilicon can be used as the material of the conductor films 41 to 44, and the thickness of the conductor films 41 to 44 is set to, for example, about 100 to 500 [nm].
 導電体膜41~44は、ピエゾ抵抗11~14が備える一対のピエゾ抵抗に対応して形成された一対の導電体膜をそれぞれ備える。具体的に、導電体膜(導電領域)41は、ピエゾ抵抗11aに対応し、ピエゾ抵抗11aを平面視で覆うように形成された導電体膜41a(第1導電体膜、第1導電領域)と、ピエゾ抵抗11bに対応し、ピエゾ抵抗11bを平面視で覆うように形成された導電体膜41b(第2導電体膜、第2導電領域)とを備える。導電体膜(導電領域)42は、ピエゾ抵抗12aに対応し、ピエゾ抵抗12aを平面視で覆うように形成された導電体膜42a(第1導電体膜、第1導電領域)と、ピエゾ抵抗12bに対応し、ピエゾ抵抗12bを平面視で覆うように形成された導電体膜42b(第2導電体膜、第2導電領域)とを備える。 The conductor films 41 to 44 include a pair of conductor films formed corresponding to the pair of piezoresistors included in the piezoresistors 11 to 14, respectively. Specifically, the conductor film (conductive region) 41 corresponds to the piezoresistor 11a and is formed so as to cover the piezoresistor 11a in plan view (first conductor film, first conductive region). And a conductor film 41b (second conductor film, second conductive region) corresponding to the piezoresistor 11b and formed to cover the piezoresistor 11b in plan view. The conductor film (conductive region) 42 corresponds to the piezoresistor 12a, and a conductor film 42a (first conductor film, first conductive region) formed so as to cover the piezoresistor 12a in plan view, and a piezoresistor. And a conductor film 42b (second conductor film, second conductive region) formed so as to cover the piezoresistor 12b in plan view.
 また、導電体膜(導電領域)43は、ピエゾ抵抗13aに対応し、ピエゾ抵抗13aを平面視で覆うように形成された導電体膜43a(第1導電体膜、第1導電領域)と、ピエゾ抵抗13bに対応し、ピエゾ抵抗13bを平面視で覆うように形成された導電体膜43b(第2導電体膜、第2導電領域)とを備える。導電体膜(導電領域)44は、ピエゾ抵抗14aに対応し、ピエゾ抵抗14aを平面視で覆うように形成された導電体膜44a(第1導電体膜、第1導電領域)と、ピエゾ抵抗14bに対応し、ピエゾ抵抗14bを平面視で覆うように形成された導電体膜44b(第2導電体膜、第2導電領域)とを備える。 Further, the conductor film (conductive region) 43 corresponds to the piezoresistor 13a, and a conductor film 43a (first conductor film, first conductive region) formed so as to cover the piezoresistor 13a in plan view; Corresponding to the piezoresistor 13b, a conductor film 43b (second conductor film, second conductive region) formed so as to cover the piezoresistor 13b in plan view is provided. The conductor film (conductive region) 44 corresponds to the piezoresistor 14a, and a conductor film 44a (first conductor film, first conductive region) formed so as to cover the piezoresistor 14a in plan view, and a piezoresistor. 14b, and a conductor film 44b (second conductor film, second conductive region) formed so as to cover the piezoresistor 14b in plan view.
 導電体膜41a,41b,42a,42b,43a,43b,44a,44bは何れも、対応するピエゾ抵抗11a,11b,12a,12b,13a,13b,14a,14bの他端(第二端)にそれぞれ接続される。例えば、図1,図2に示す通り、導電体膜41aは、金属配線51及び拡散配線21aを介して対応するピエゾ抵抗11aの他端(第二端)に接続され、導電体膜41bは、金属配線52及び拡散配線21cを介して対応するピエゾ抵抗11bの他端(第二端)に接続される。このような接続を行うのは、導電体膜41a,41b,42a,42b,43a,43b,44a,44bと、対応するピエゾ抵抗11a,11b,12a,12b,13a,13b,14a,14bとの間の電位差を極力小さくして、測定誤差を低減するためである。 The conductor films 41a, 41b, 42a, 42b, 43a, 43b, 44a, 44b are all on the other end (second end) of the corresponding piezoresistors 11a, 11b, 12a, 12b, 13a, 13b, 14a, 14b. Each is connected. For example, as shown in FIGS. 1 and 2, the conductor film 41a is connected to the other end (second end) of the corresponding piezoresistor 11a via the metal wiring 51 and the diffusion wiring 21a. The other end (second end) of the corresponding piezoresistor 11b is connected through the metal wiring 52 and the diffusion wiring 21c. This connection is made between the conductor films 41a, 41b, 42a, 42b, 43a, 43b, 44a, 44b and the corresponding piezoresistors 11a, 11b, 12a, 12b, 13a, 13b, 14a, 14b. This is to reduce the measurement error by reducing the potential difference between them as much as possible.
 また、導電体膜41~44(導電体膜41a,41b,42a,42b,43a,43b,44a,44b)は何れも、平面視でダイヤフラム部10aの内側(内部)から外側(外部)に延在するように絶縁膜30上に形成されている。即ち、導電体膜41~44は、導電体膜41~44の一部が平面視でダイヤフラム部10aの外側(外部)に位置するように形成されている。導電体膜41~44の一部が平面視でダイヤフラム部10aの外部に位置するように形成する理由は、主として測定誤差を低減するためである。 The conductor films 41 to 44 ( conductor films 41a, 41b, 42a, 42b, 43a, 43b, 44a, 44b) all extend from the inside (inside) to the outside (outside) of the diaphragm portion 10a in plan view. It is formed on the insulating film 30 so as to exist. That is, the conductor films 41 to 44 are formed such that a part of the conductor films 41 to 44 is located outside (outside) the diaphragm portion 10a in plan view. The reason why a part of the conductor films 41 to 44 is formed so as to be located outside the diaphragm portion 10a in plan view is mainly to reduce measurement errors.
 ダイヤフラム部10aの上方(ダイヤフラム部10aの+Z側における絶縁膜30上)に金属配線が存在すると、金属配線の変形によりダイヤフラム部10aに大きな応力変化が現れて測定圧力に誤差が生ずる。本実施形態では、図1に示す通り、金属配線51~54を平面視でダイヤフラム部10aの外側に形成するとともに、導電体膜41~44の一部を平面視でダイヤフラム部10aの外側に位置するように形成し、金属配線51~54と導電体膜41~44との接続を、ダイヤフラム部10aの外側(平面視での外側、外部)で行うようにしている。このようにして、金属配線51~54の変形による応力がダイヤフラム部10aに加わるのを防ぐことで、測定圧力に誤差が生ずるのを防止している。 If a metal wiring exists above the diaphragm portion 10a (on the insulating film 30 on the + Z side of the diaphragm portion 10a), a large stress change appears in the diaphragm portion 10a due to the deformation of the metal wiring, resulting in an error in measurement pressure. In the present embodiment, as shown in FIG. 1, the metal wirings 51 to 54 are formed outside the diaphragm portion 10a in a plan view, and part of the conductor films 41 to 44 are positioned outside the diaphragm portion 10a in a plan view. The metal wirings 51 to 54 and the conductor films 41 to 44 are connected to each other outside the diaphragm portion 10a (outside in plan view, outside). In this way, the stress due to the deformation of the metal wirings 51 to 54 is prevented from being applied to the diaphragm portion 10a, thereby preventing an error in the measurement pressure.
 尚、上記の構成とはせずに、平面視でダイヤフラム部10aの内側に形成された導電体膜と平面視でダイヤフラム部10aの外側に形成された金属配線とを配線によって接続した構成にすることも考えられる。具体的には、上記の導電体膜とダイヤフラム部10aの表面とを接続する第1コンタクト部と、上記の金属配線と半導体基板10の表面とを接続する第2コンタクト部とが形成され、これら第1コンタクト部と第2コンタクト部とが、半導体基板10(ダイヤフラム部10a)の表面に形成された拡散配線で接続された構成である。しかしながら、このような構成では、ダイヤフラム部10a上の絶縁膜30を削って第1コンタクト部を形成する必要があり、応力が第1コンタクト部に集中しやすい構造となることから、センサ感度が低下してしまう。 Instead of the above configuration, the conductive film formed inside the diaphragm portion 10a in plan view and the metal wiring formed outside the diaphragm portion 10a in plan view are connected by wiring. It is also possible. Specifically, a first contact portion that connects the conductor film and the surface of the diaphragm portion 10a and a second contact portion that connects the metal wiring and the surface of the semiconductor substrate 10 are formed. The first contact portion and the second contact portion are connected by a diffusion wiring formed on the surface of the semiconductor substrate 10 (diaphragm portion 10a). However, in such a configuration, it is necessary to form the first contact portion by cutting the insulating film 30 on the diaphragm portion 10a, and the stress is likely to concentrate on the first contact portion, resulting in a decrease in sensor sensitivity. Resulting in.
 また、導電体膜(導電領域)41~44(導電体膜41a,41b,42a,42b,43a,43b,44a,44b)は、少なくともダイヤフラム部10a上における平面視形状が、図1に示す通り、ダイヤフラム部10aの中央部Qに対して点対称形状に配置される。導電体膜41~44を点対称形状に配置する理由は、主として、半導体圧力センサ1の出力に誤差が生ずるのを防止するためである。 Further, the conductor films (conductive regions) 41 to 44 ( conductor films 41a, 41b, 42a, 42b, 43a, 43b, 44a, 44b) have at least a plan view shape on the diaphragm portion 10a as shown in FIG. These are arranged in a point-symmetric shape with respect to the central portion Q of the diaphragm portion 10a. The reason why the conductor films 41 to 44 are arranged in a point-symmetrical shape is mainly to prevent an error from occurring in the output of the semiconductor pressure sensor 1.
 半導体圧力センサ1では、ダイヤフラム部10aが圧力を受けて撓んだ際に、ダイヤフラム部10aの中央部Qを挟んで対向する位置に配置されたピエゾ抵抗(ピエゾ抵抗11およびピエゾ抵抗13、或いはピエゾ抵抗12およびピエゾ抵抗14)に同じ応力変化が生ずることが望ましい。このため、ピエゾ抵抗11~14は、図1に示す通り、ダイヤフラム部10aの中央部Qに対して点対称に配置されている。ピエゾ抵抗11~14に対応して形成されている導電体膜41~44の平面視形状(ダイヤフラム部10a上における平面視形状)が、ダイヤフラム部10aの中央部Qに対して非対称である場合には、ピエゾ抵抗11~14に加わる応力が非対称となって、半導体圧力センサ1の出力に誤差が生ずる。 In the semiconductor pressure sensor 1, when the diaphragm portion 10 a is bent under pressure, the piezoresistors (piezoresistor 11 and piezoresistor 13 or piezoresistor 13 or piezoresistors 13) disposed at positions facing each other with the central portion Q of the diaphragm portion 10 a interposed therebetween. It is desirable that the same stress changes occur in the resistor 12 and the piezoresistor 14). Therefore, as shown in FIG. 1, the piezoresistors 11 to 14 are arranged point-symmetrically with respect to the central portion Q of the diaphragm portion 10a. When the planar view shapes (plan view shapes on the diaphragm portion 10a) of the conductor films 41 to 44 formed corresponding to the piezoresistors 11 to 14 are asymmetric with respect to the central portion Q of the diaphragm portion 10a. In this case, the stress applied to the piezoresistors 11 to 14 becomes asymmetric, and an error occurs in the output of the semiconductor pressure sensor 1.
 本実施形態では、図1に示す通り、導電体膜41~44の平面視形状(ダイヤフラム部10a上における平面視形状)を、ダイヤフラム部10aの中央部Qに対して点対称形状にすることで、半導体圧力センサ1の出力に誤差が生ずるのを防止している。尚、導電体膜41~44のダイヤフラム部10a上における平面視形状のみならず、導電体膜41~44の全体形状(平面視でダイヤフラム部10aの外側に延在する部分の形状を含む)を、ダイヤフラム部10aの中央部Qに対して点対称形状にしても良い。 In the present embodiment, as shown in FIG. 1, the shape of the conductor films 41 to 44 in a plan view (a plan view shape on the diaphragm portion 10a) is made point-symmetric with respect to the central portion Q of the diaphragm portion 10a. Thus, an error in the output of the semiconductor pressure sensor 1 is prevented. Not only the shape of the conductor films 41 to 44 in plan view on the diaphragm portion 10a but also the overall shape of the conductor films 41 to 44 (including the shape of the portion extending outside the diaphragm portion 10a in plan view). The shape may be point-symmetric with respect to the central portion Q of the diaphragm portion 10a.
 金属配線51~54は、拡散配線21~24とともにピエゾ抵抗11~14のブリッジ回路BR1(図4参照)を構成するために、絶縁膜30上に形成された配線である。金属配線51~54の材料としては、例えばアルミニウム(Al)を用いることができ、金属配線51~54の厚みは、例えば1500[nm]程度に設定される。 The metal wires 51 to 54 are wires formed on the insulating film 30 in order to constitute the bridge circuit BR1 (see FIG. 4) of the piezoresistors 11 to 14 together with the diffusion wires 21 to 24. As a material of the metal wirings 51 to 54, for example, aluminum (Al) can be used, and the thickness of the metal wirings 51 to 54 is set to, for example, about 1500 [nm].
 金属配線51は、絶縁膜30の紙面左上隅部に設けられるパッド部51a、パッド部51aから-Y方向に延びる配線部51b、及びパッド部51aから+X方向に延びる配線部51cを備える。金属配線52は、絶縁膜30の紙面右上隅部に設けられるパッド部52a、パッド部52aから-X方向に延びる配線部52b、及びパッド部52aから-Y方向に延びる配線部52cを備える。 The metal wiring 51 includes a pad portion 51a provided at the upper left corner of the insulating film 30, a wiring portion 51b extending from the pad portion 51a in the −Y direction, and a wiring portion 51c extending from the pad portion 51a in the + X direction. The metal wiring 52 includes a pad portion 52a provided at the upper right corner of the insulating film 30 in the drawing, a wiring portion 52b extending from the pad portion 52a in the −X direction, and a wiring portion 52c extending from the pad portion 52a in the −Y direction.
 金属配線53は、絶縁膜30の紙面右下隅部に設けられるパッド部53a、パッド部53aから+Y方向に延びる配線部53b、及びパッド部53aから-X方向に延びる配線部53cを備える。金属配線54は、絶縁膜30の紙面左下隅部に設けられるパッド部54a、パッド部54aから+X方向に延びる配線部54b、及びパッド部54aから+Y方向に延びる配線部54cを備える。 The metal wiring 53 includes a pad portion 53a provided at the lower right corner of the insulating film 30, a wiring portion 53b extending from the pad portion 53a in the + Y direction, and a wiring portion 53c extending from the pad portion 53a in the −X direction. The metal wiring 54 includes a pad part 54a provided at the lower left corner of the insulating film 30, a wiring part 54b extending from the pad part 54a in the + X direction, and a wiring part 54c extending from the pad part 54a in the + Y direction.
 金属配線51~54は、絶縁膜30に形成されたコンタクト部を介して拡散配線21~24と接続されている。具体的には、図2に示す通り、金属配線51(配線部51c)は、コンタクト部CNを介して拡散配線21(拡散配線21a)に接続されている。金属配線52(配線部52b)は、コンタクト部CNを介して拡散配線21(拡散配線21c)に接続されている。同様に、金属配線52(配線部52c)は、不図示のコンタクト部を介して拡散配線22(拡散配線22a)に接続されている。金属配線53(配線部53b)は、不図示のコンタクト部を介して拡散配線22(拡散配線22c)に接続されている。コンタクト部は、例えば絶縁膜30をエッチングすることによって形成され、コンタクト部に金属配線が充填されることによって、金属配線と拡散配線とが接続される。 The metal wirings 51 to 54 are connected to the diffusion wirings 21 to 24 through contact portions formed on the insulating film 30. Specifically, as shown in FIG. 2, the metal wiring 51 (wiring part 51c) is connected to the diffusion wiring 21 (diffusion wiring 21a) via the contact part CN. The metal wiring 52 (wiring part 52b) is connected to the diffusion wiring 21 (diffusion wiring 21c) via the contact part CN. Similarly, the metal wiring 52 (wiring part 52c) is connected to the diffusion wiring 22 (diffusion wiring 22a) through a contact part (not shown). The metal wiring 53 (wiring part 53b) is connected to the diffusion wiring 22 (diffusion wiring 22c) through a contact part (not shown). The contact portion is formed, for example, by etching the insulating film 30, and the metal wiring and the diffusion wiring are connected by filling the contact portion with the metal wiring.
 また、金属配線53(配線部53c)は、不図示のコンタクト部を介して拡散配線23(拡散配線23a)に接続されている。金属配線54(配線部54b)は、不図示のコンタクト部を介して拡散配線23(拡散配線23c)に接続されている。金属配線54(配線部54c)は、不図示のコンタクト部を介して拡散配線24(拡散配線24a)に接続されている。金属配線51(配線部51b)は、不図示のコンタクト部を介して拡散配線24(拡散配線24c)に接続されている。 The metal wiring 53 (wiring portion 53c) is connected to the diffusion wiring 23 (diffusion wiring 23a) through a contact portion (not shown). The metal wiring 54 (wiring portion 54b) is connected to the diffusion wiring 23 (diffusion wiring 23c) through a contact portion (not shown). The metal wiring 54 (wiring part 54c) is connected to the diffusion wiring 24 (diffusion wiring 24a) through a contact part (not shown). The metal wiring 51 (wiring part 51b) is connected to the diffusion wiring 24 (diffusion wiring 24c) through a contact part (not shown).
 図1,図2に示す通り、導電体膜(導電領域)41aは、ピエゾ抵抗11aの第一端から金属配線51(配線部51c)に向かって延びるように形成されている。また、図1,図2に示す通り、導電体膜(導電領域)41bは、ピエゾ抵抗11bの第一端から金属配線52(配線部52b)に向かって延びるように形成されている。金属配線51(配線部51c)は、コンタクト部CN及び拡散配線21aを介してピエゾ抵抗11aの第二端に接続されている。金属配線52(配線部52b)は、コンタクト部CN及び拡散配線21cを介してピエゾ抵抗11bの第二端に接続されている。従って、導電体膜41aは、絶縁膜30上において、ピエゾ抵抗11aの第一端から、ピエゾ抵抗11aの第二端に接続される金属配線51(配線部51c)に向かって延びるように形成されている。また、導電体膜41bは、絶縁膜30上において、ピエゾ抵抗11bの第一端から、ピエゾ抵抗11bの第二端に接続される金属配線52(配線部52b)に向かって延びるように形成されている。 As shown in FIGS. 1 and 2, the conductor film (conductive region) 41a is formed to extend from the first end of the piezoresistor 11a toward the metal wiring 51 (wiring portion 51c). As shown in FIGS. 1 and 2, the conductor film (conductive region) 41b is formed so as to extend from the first end of the piezoresistor 11b toward the metal wiring 52 (wiring portion 52b). The metal wiring 51 (wiring part 51c) is connected to the second end of the piezoresistor 11a via the contact part CN and the diffusion wiring 21a. The metal wiring 52 (wiring part 52b) is connected to the second end of the piezoresistor 11b via the contact part CN and the diffusion wiring 21c. Therefore, the conductor film 41a is formed on the insulating film 30 so as to extend from the first end of the piezoresistor 11a toward the metal wiring 51 (wiring part 51c) connected to the second end of the piezoresistor 11a. ing. The conductor film 41b is formed on the insulating film 30 so as to extend from the first end of the piezoresistor 11b toward the metal wiring 52 (wiring part 52b) connected to the second end of the piezoresistor 11b. ing.
 同様に、導電体膜(導電領域)42aは、絶縁膜30上において、ピエゾ抵抗12aの第一端から、ピエゾ抵抗12aの第二端に接続される金属配線52(配線部52c)に向かって延びるように形成されている。導電体膜(導電領域)42bは、絶縁膜30上において、ピエゾ抵抗12bの第一端から、ピエゾ抵抗12bの第二端に接続される金属配線53(配線部53b)に向かって延びるように形成されている。また、導電体膜(導電領域)43aは、絶縁膜30上において、ピエゾ抵抗13aの第一端から、ピエゾ抵抗13aの第二端に接続される金属配線53(配線部53c)に向かって延びるように形成されている。導電体膜(導電領域)43bは、絶縁膜30上において、ピエゾ抵抗13bの第一端から、ピエゾ抵抗13bの第二端に接続される金属配線54(配線部54b)に向かって延びるように形成されている。また、導電体膜(導電領域)44aは、絶縁膜30上において、ピエゾ抵抗14aの第一端から、ピエゾ抵抗14aの第二端に接続される金属配線54(配線部54c)に向かって延びるように形成されている。導電体膜(導電領域)44bは、絶縁膜30上において、ピエゾ抵抗14bの第一端から、ピエゾ抵抗14bの第二端に接続される金属配線51(配線部51b)に向かって延びるように形成されている。 Similarly, on the insulating film 30, the conductor film (conductive region) 42a is directed from the first end of the piezoresistor 12a to the metal wiring 52 (wiring portion 52c) connected to the second end of the piezoresistor 12a. It is formed to extend. On the insulating film 30, the conductor film (conductive region) 42b extends from the first end of the piezoresistor 12b toward the metal wiring 53 (wiring portion 53b) connected to the second end of the piezoresistor 12b. Is formed. The conductor film (conductive region) 43a extends on the insulating film 30 from the first end of the piezoresistor 13a toward the metal wiring 53 (wiring portion 53c) connected to the second end of the piezoresistor 13a. It is formed as follows. The conductor film (conductive region) 43b extends on the insulating film 30 from the first end of the piezoresistor 13b toward the metal wiring 54 (wiring portion 54b) connected to the second end of the piezoresistor 13b. Is formed. The conductor film (conductive region) 44a extends on the insulating film 30 from the first end of the piezoresistor 14a toward the metal wiring 54 (wiring portion 54c) connected to the second end of the piezoresistor 14a. It is formed as follows. The conductor film (conductive region) 44b extends on the insulating film 30 from the first end of the piezoresistor 14b toward the metal wiring 51 (wiring part 51b) connected to the second end of the piezoresistor 14b. Is formed.
 図4は、本発明の第1実施形態で構成されるブリッジ回路を示す図である。尚、図4においては、図1~図3に示す部材に相当する構成には同一の符号を付してある。図4に示す通り、ブリッジ回路BR1は、ピエゾ抵抗11(11a,11b)、ピエゾ抵抗12(12a,12b)、ピエゾ抵抗13(13a,13b)、及びピエゾ抵抗14(14a,14b)が環状に接続された回路である。また、ピエゾ抵抗14とピエゾ抵抗11との間に金属配線51が接続されている。ピエゾ抵抗11とピエゾ抵抗12との間に金属配線52が接続されている。ピエゾ抵抗12とピエゾ抵抗13との間に金属配線53が接続されている。ピエゾ抵抗13とピエゾ抵抗14との間に金属配線54が接続されている。尚、図4に示すブリッジ回路BR1は、例えば金属配線51が電源に接続され、金属配線53が接地され、金属配線52,54が電圧出力端子に接続される。 FIG. 4 is a diagram showing a bridge circuit configured in the first embodiment of the present invention. In FIG. 4, the same reference numerals are given to the components corresponding to the members shown in FIGS. As shown in FIG. 4, the bridge circuit BR1 includes a piezoresistor 11 (11a, 11b), a piezoresistor 12 (12a, 12b), a piezoresistor 13 (13a, 13b), and a piezoresistor 14 (14a, 14b). It is a connected circuit. A metal wiring 51 is connected between the piezoresistor 14 and the piezoresistor 11. A metal wiring 52 is connected between the piezoresistor 11 and the piezoresistor 12. A metal wiring 53 is connected between the piezoresistor 12 and the piezoresistor 13. A metal wiring 54 is connected between the piezoresistor 13 and the piezoresistor 14. In the bridge circuit BR1 shown in FIG. 4, for example, the metal wiring 51 is connected to the power source, the metal wiring 53 is grounded, and the metal wirings 52 and 54 are connected to the voltage output terminal.
 また、図4に示すブリッジ回路BR1では、ピエゾ抵抗11(11a,11b)、ピエゾ抵抗12(12a,12b)、ピエゾ抵抗13(13a,13b)、及びピエゾ抵抗14(14a,14b)に対応して、導電体膜41(41a,41b)、導電体膜42(42a,42b)、導電体膜43(43a,43b)、及び導電体膜44(44a,44b)がそれぞれ設けられている。そして、導電体膜41a,41b,42a,42b,43a,43b,44a,44bは、対応するピエゾ抵抗11a,11b,12a,12b,13a,13b,14a,14bの第二端にそれぞれ接続されている。 Further, the bridge circuit BR1 shown in FIG. 4 corresponds to the piezoresistor 11 (11a, 11b), the piezoresistor 12 (12a, 12b), the piezoresistor 13 (13a, 13b), and the piezoresistor 14 (14a, 14b). The conductor film 41 (41a, 41b), the conductor film 42 (42a, 42b), the conductor film 43 (43a, 43b), and the conductor film 44 (44a, 44b) are provided. The conductor films 41a, 41b, 42a, 42b, 43a, 43b, 44a, 44b are connected to the second ends of the corresponding piezoresistors 11a, 11b, 12a, 12b, 13a, 13b, 14a, 14b, respectively. Yes.
 以上の構成を有する半導体圧力センサ1において、ダイヤフラム部10aに圧力が加わるとダイヤフラム部10aに撓みが生ずる。すると、ダイヤフラム部10aの撓みに応じた応力が、ピエゾ抵抗11(11a,11b)、ピエゾ抵抗12(12a,12b)、ピエゾ抵抗13(13a,13b)、及びピエゾ抵抗14(14a,14b)に作用し、抵抗値が変化する。このような抵抗値の変化が生ずると、金属配線52,54が接続された電圧出力端子間の電圧が変化し、電圧出力端子間の電圧変化を検出することによってダイヤフラム部10aに加わる圧力を求めることができる。 In the semiconductor pressure sensor 1 having the above configuration, when pressure is applied to the diaphragm portion 10a, the diaphragm portion 10a bends. Then, stress corresponding to the deflection of the diaphragm portion 10a is applied to the piezoresistors 11 (11a, 11b), piezoresistors 12 (12a, 12b), piezoresistors 13 (13a, 13b), and piezoresistors 14 (14a, 14b). Acts and the resistance value changes. When such a change in resistance value occurs, the voltage between the voltage output terminals to which the metal wirings 52 and 54 are connected changes, and the pressure applied to the diaphragm portion 10a is obtained by detecting the voltage change between the voltage output terminals. be able to.
 ここで、ピエゾ抵抗と導電体膜との間の電位差について考察する。ここでは理解を容易にするために、電源電圧が4[V]であり、ピエゾ抵抗11a,11b,12a,12b,13a,13b,14a,14bの抵抗値が全て等しいと仮定する。従来の半導体圧力センサのように、導電体膜が全てのピエゾ抵抗を覆うように形成されている場合には、導電体膜とピエゾ抵抗との電位差は最大で電源電圧(4[V])と同程度になる。これに対し、本実施形態では、ピエゾ抵抗に対応する導電体膜(導電領域)が個別に形成されており、対応するピエゾ抵抗の第二端に接続されているため、導電体膜とピエゾ抵抗との電位差は最大で個々のピエゾ抵抗の電圧降下と同程度(1[V])になり、従来よりも大幅に電位差を小さくすることができる。これにより、従来よりも測定誤差を低減することができる。 Here, the potential difference between the piezoresistor and the conductor film is considered. Here, for easy understanding, it is assumed that the power supply voltage is 4 [V] and the resistance values of the piezoresistors 11a, 11b, 12a, 12b, 13a, 13b, 14a, and 14b are all equal. When the conductor film is formed so as to cover all the piezoresistors as in the conventional semiconductor pressure sensor, the potential difference between the conductor film and the piezoresistors is a maximum of the power supply voltage (4 [V]). It becomes the same level. On the other hand, in the present embodiment, the conductor film (conductive region) corresponding to the piezoresistor is individually formed and connected to the second end of the corresponding piezoresistor. The maximum potential difference is approximately the same as the voltage drop of each piezoresistor (1 [V]), and the potential difference can be significantly reduced as compared with the conventional case. Thereby, a measurement error can be reduced as compared with the conventional case.
 以上の通り、本実施形態では、ブリッジ回路BR1を構成するピエゾ抵抗11a,11b,12a,12b,13a,13b,14a,14bの各々に対応する導電体膜41a,41b,42a,42b,43a,43b,44a,44bを絶縁膜30上に個別に設けている。そして、導電体膜41a,41b,42a,42b,43a,43b,44a,44bを、対応するピエゾ抵抗11a,11b,12a,12b,13a,13b,14a,14bの第二端に接続するようにしている。これにより、ピエゾ抵抗と、対応する導電体膜との間の電位差を従来よりも小さくすることができ、従来よりも測定誤差を低減することが可能である。 As described above, in the present embodiment, the conductor films 41a, 41b, 42a, 42b, 43a corresponding to each of the piezoresistors 11a, 11b, 12a, 12b, 13a, 13b, 14a, 14b constituting the bridge circuit BR1. 43b, 44a, and 44b are individually provided on the insulating film 30. The conductor films 41a, 41b, 42a, 42b, 43a, 43b, 44a, 44b are connected to the second ends of the corresponding piezoresistors 11a, 11b, 12a, 12b, 13a, 13b, 14a, 14b. ing. Thereby, the potential difference between the piezoresistor and the corresponding conductor film can be made smaller than before, and the measurement error can be reduced more than before.
 また、本実施形態では、従来のように導電体膜が全てのピエゾ抵抗を覆うように形成されている訳ではなく、導電領域がピエゾ抵抗の各々を平面視で覆うように個別に形成されていることから、導電体膜とダイヤフラム部10a(或いは、絶縁膜30)との熱膨張係数の差によって生ずる応力を小さくすることができる。これによっても、測定誤差を低減することが可能である。 In the present embodiment, the conductive film is not formed so as to cover all the piezoresistors as in the prior art, but the conductive regions are individually formed so as to cover each of the piezoresistors in plan view. Therefore, the stress generated by the difference in thermal expansion coefficient between the conductor film and the diaphragm portion 10a (or the insulating film 30) can be reduced. This also makes it possible to reduce measurement errors.
〔第2実施形態〕
 図5は、本発明の第2実施形態で構成されるブリッジ回路を示す図である。尚、図5においては、図4に示す構成と同じ部材には同一の符号を付してある。図5に示す通り、本実施形態で構成されるブリッジ回路BR2は、図4に示すブリッジ回路BR1と同様に、ピエゾ抵抗11(11a,11b)、ピエゾ抵抗12(12a,12b)、ピエゾ抵抗13(13a,13b)、及びピエゾ抵抗14(14a,14b)が環状に接続された回路である。ピエゾ抵抗14とピエゾ抵抗11との間に金属配線51が接続されている。ピエゾ抵抗11とピエゾ抵抗12との間に金属配線52が接続されている。ピエゾ抵抗12とピエゾ抵抗13との間に金属配線53が接続されている。ピエゾ抵抗13とピエゾ抵抗14との間に金属配線54が接続されている。
[Second Embodiment]
FIG. 5 is a diagram showing a bridge circuit configured in the second embodiment of the present invention. In FIG. 5, the same members as those shown in FIG. 4 are denoted by the same reference numerals. As shown in FIG. 5, the bridge circuit BR2 configured in the present embodiment is similar to the bridge circuit BR1 shown in FIG. 4. The piezoresistor 11 (11a, 11b), the piezoresistor 12 (12a, 12b), and the piezoresistor 13 (13a, 13b) and a piezoresistor 14 (14a, 14b) are connected in a ring shape. A metal wiring 51 is connected between the piezoresistor 14 and the piezoresistor 11. A metal wiring 52 is connected between the piezoresistor 11 and the piezoresistor 12. A metal wiring 53 is connected between the piezoresistor 12 and the piezoresistor 13. A metal wiring 54 is connected between the piezoresistor 13 and the piezoresistor 14.
 但し、本実施形態で構成されるブリッジ回路BR2は、図4に示すブリッジ回路BR1とは異なり、導電体膜(導電領域)41a,41b,42a,42b,43a,43b,44a,44bが、対応するピエゾ抵抗11a,11b,12a,12b,13a,13b,14a,14bの第一端にそれぞれ接続されている。つまり、本実施形態では、図1に示す導電体膜41~44が、金属配線51~52に接続されておらず、拡散配線21~24に接続されている点が、第1実施形態とは異なる。 However, the bridge circuit BR2 configured in this embodiment is different from the bridge circuit BR1 shown in FIG. 4 in that the conductor films (conductive regions) 41a, 41b, 42a, 42b, 43a, 43b, 44a, 44b are supported. The piezoresistors 11a, 11b, 12a, 12b, 13a, 13b, 14a, 14b are respectively connected to the first ends. That is, in the present embodiment, the conductor films 41 to 44 shown in FIG. 1 are not connected to the metal wirings 51 to 52, but are connected to the diffusion wirings 21 to 24, which is different from the first embodiment. Different.
 具体的に、導電体膜41(41a,41b)は、金属配線51,52(配線部51c,52b)に接続されておらず、拡散配線21(21b)に接続されている。また、導電体膜42(42a,42b)は、金属配線52,53(配線部52c,53b)に接続されておらず、拡散配線22(22b)に接続されている。また、導電体膜43(43a,43b)は、金属配線53,54(配線部53c,54b)に接続されておらず、拡散配線23(23b)に接続されている。また、導電体膜44(44a,44b)は、金属配線54,51(配線部54c,51b)に接続されておらず、拡散配線24(24b)に接続されている。 Specifically, the conductor film 41 (41a, 41b) is not connected to the metal wirings 51, 52 ( wiring portions 51c, 52b), but is connected to the diffusion wiring 21 (21b). The conductor film 42 (42a, 42b) is not connected to the metal wirings 52, 53 ( wiring portions 52c, 53b), but is connected to the diffusion wiring 22 (22b). The conductor film 43 (43a, 43b) is not connected to the metal wirings 53, 54 ( wiring portions 53c, 54b), but is connected to the diffusion wiring 23 (23b). The conductor film 44 (44a, 44b) is not connected to the metal wirings 54, 51 ( wiring portions 54c, 51b), but is connected to the diffusion wiring 24 (24b).
 以上の通り、本実施形態に係る半導体圧力センサは、ピエゾ抵抗11a,11b,12a,12b,13a,13b,14a,14bに対する導電体膜41a,41b,42a,42b,43a,43b,44a,44bの接続点の位置が異なるだけで、基本的な構成は、第1実施形態に係る半導体圧力センサと同じである。このため、本実施形態においても、従来よりも測定誤差を低減することが可能である。 As described above, the semiconductor pressure sensor according to the present embodiment has the conductor films 41a, 41b, 42a, 42b, 43a, 43b, 44a, 44b for the piezoresistors 11a, 11b, 12a, 12b, 13a, 13b, 14a, 14b. The basic configuration is the same as that of the semiconductor pressure sensor according to the first embodiment, except that the positions of the connection points are different. For this reason, also in this embodiment, it is possible to reduce a measurement error compared with the past.
〔第3実施形態〕
 図6A~6Cは、本発明の第3実施形態で構成されるブリッジ回路を示す図である。尚、図6A~6Cにおいても、図5と同様に、図4に示す構成と同じ部材には同一の符号を付してある。上述した第1実施形態および第2実施形態に係る半導体圧力センサは、ピエゾ抵抗11~14が、一端が互いに接続されて近接配置された一対のピエゾ抵抗をそれぞれ備えており、導電体膜(導電領域)41~44が、ピエゾ抵抗11~14が備える一対のピエゾ抵抗に対応して形成された一対の導電体膜をそれぞれ備える構成を有していた。これに対し、本実施形態に係る半導体圧力センサは、ピエゾ抵抗11~14の各々が1つの素子から構成され、ピエゾ抵抗11~14に対して導電体膜41~44がそれぞれ設けられた構成を有している。
[Third Embodiment]
6A to 6C are diagrams showing a bridge circuit configured in the third embodiment of the present invention. 6A to 6C, like FIG. 5, the same members as those shown in FIG. 4 are denoted by the same reference numerals. In the semiconductor pressure sensor according to the first embodiment and the second embodiment described above, the piezoresistors 11 to 14 each include a pair of piezoresistors arranged in close proximity with one end connected to each other. (Regions) 41 to 44 have a configuration including a pair of conductor films formed corresponding to the pair of piezoresistors included in the piezoresistors 11 to 14, respectively. In contrast, the semiconductor pressure sensor according to the present embodiment has a configuration in which each of the piezoresistors 11 to 14 is composed of one element, and the conductor films 41 to 44 are provided for the piezoresistors 11 to 14, respectively. Have.
 このため、本実施形態で構成されるブリッジ回路BR3は、図6A~6Cに示す通り、4つのピエゾ抵抗11~14が環状に接続されている。また、ピエゾ抵抗14とピエゾ抵抗11との間に金属配線51が接続されている。ピエゾ抵抗11とピエゾ抵抗12との間に金属配線52が接続されている。ピエゾ抵抗12とピエゾ抵抗13との間に金属配線53が接続されている。ピエゾ抵抗13とピエゾ抵抗14との間に金属配線54が接続されている。
導電体膜41~44は、それぞれピエゾ抵抗11~14に対応して設けられていればよく、ピエゾ抵抗11~14に対する導電体膜41~44の接続点の位置は任意である。
Therefore, in the bridge circuit BR3 configured in the present embodiment, as shown in FIGS. 6A to 6C, four piezoresistors 11 to 14 are connected in a ring shape. A metal wiring 51 is connected between the piezoresistor 14 and the piezoresistor 11. A metal wiring 52 is connected between the piezoresistor 11 and the piezoresistor 12. A metal wiring 53 is connected between the piezoresistor 12 and the piezoresistor 13. A metal wiring 54 is connected between the piezoresistor 13 and the piezoresistor 14.
The conductor films 41 to 44 need only be provided corresponding to the piezoresistors 11 to 14, respectively, and the positions of the connection points of the conductor films 41 to 44 to the piezoresistors 11 to 14 are arbitrary.
 例えば、図6Aに示す通り、導電体膜41~44は、ピエゾ抵抗11~14の第一端に接続されていてもよい。図6Bに示す通り、導電体膜41~44は、ピエゾ抵抗11~14の第二端に接続されていてもよい。図6Aに示す例では、導電体膜41および導電体膜44が金属配線51に接続されて同電位になり、導電体膜42および導電体膜43が金属配線53に接続されて同電位になる。また、図6Bに示す例では、導電体膜41および導電体膜42が金属配線52に接続されて同電位になり、導電体膜43および導電体膜44が金属配線54に接続されて同電位になる。 For example, as shown in FIG. 6A, the conductor films 41 to 44 may be connected to the first ends of the piezoresistors 11 to 14. As shown in FIG. 6B, the conductor films 41 to 44 may be connected to the second ends of the piezoresistors 11 to 14. In the example shown in FIG. 6A, the conductor film 41 and the conductor film 44 are connected to the metal wiring 51 to have the same potential, and the conductor film 42 and the conductor film 43 are connected to the metal wiring 53 to have the same potential. . In the example shown in FIG. 6B, the conductor film 41 and the conductor film 42 are connected to the metal wiring 52 to have the same potential, and the conductor film 43 and the conductor film 44 are connected to the metal wiring 54 to have the same potential. become.
 また、図6Cに示す通り、導電体膜41がピエゾ抵抗11の第一端に接続され、導電体膜42がピエゾ抵抗12の第二端に接続され、導電体膜43がピエゾ抵抗13の第一端に接続され、導電体膜44がピエゾ抵抗14の第二端に接続されていてもよい。図6Cに示す例では、導電体膜41~44が異なる金属配線51~54にそれぞれ接続されることになる。つまり、導電体膜41が金属配線51に接続され、導電体膜42が金属配線52に接続され、導電体膜43が金属配線53に接続され、導電体膜44が金属配線54に接続される。 6C, the conductor film 41 is connected to the first end of the piezoresistor 11, the conductor film 42 is connected to the second end of the piezoresistor 12, and the conductor film 43 is connected to the first end of the piezoresistor 13. The conductor film 44 may be connected to the second end of the piezoresistor 14. In the example shown in FIG. 6C, the conductor films 41 to 44 are connected to different metal wirings 51 to 54, respectively. That is, the conductor film 41 is connected to the metal wiring 51, the conductor film 42 is connected to the metal wiring 52, the conductor film 43 is connected to the metal wiring 53, and the conductor film 44 is connected to the metal wiring 54. .
 以上の通り、本実施形態に係る半導体圧力センサは、ピエゾ抵抗11~14が1つの素子から構成され、ピエゾ抵抗11~14に対応して導電体膜41~44がそれぞれ設けられた構成を有する。このように、本実施形態に係る半導体圧力センサは、第1実施形態および第2実施形態に係る半導体圧力センサとは、ピエゾ抵抗及び導電体膜の数が異なるものの、ピエゾ抵抗の各々に対応して個別に導電体膜が形成されており、導電体膜が対応するピエゾ抵抗の第一端又は第二端に接続されている点においては、第1実施形態および第2実施形態と同様である。このため、本実施形態においても、従来よりも測定誤差を低減することが可能である。 As described above, the semiconductor pressure sensor according to the present embodiment has a configuration in which the piezoresistors 11 to 14 are composed of one element, and the conductor films 41 to 44 are provided corresponding to the piezoresistors 11 to 14, respectively. . As described above, the semiconductor pressure sensor according to the present embodiment corresponds to each of the piezoresistors although the number of piezoresistors and conductor films is different from the semiconductor pressure sensor according to the first embodiment and the second embodiment. The conductive film is individually formed and is the same as the first and second embodiments in that the conductive film is connected to the first end or the second end of the corresponding piezoresistor. . For this reason, also in this embodiment, it is possible to reduce a measurement error compared with the past.
〔第4実施形態〕
 図7は、本発明の第4実施形態で構成されるブリッジ回路を示す図である。尚、図7においても、図5,図6A~6Cと同様に、図4に示す構成と同じ部材には同一の符号を付してある。上述した第1~第3実施形態に係る半導体圧力センサは何れも、1つのピエゾ抵抗に対応して1つの導電体膜が形成されている構成を有していた。これに対し、本実施形態に係る半導体圧力センサは、1つのピエゾ抵抗に対応して複数の導電体膜(導電領域)が形成されている構成を有する。
[Fourth Embodiment]
FIG. 7 is a diagram showing a bridge circuit configured in the fourth embodiment of the present invention. In FIG. 7 as well, like FIG. 5 and FIGS. 6A to 6C, the same members as those shown in FIG. Each of the semiconductor pressure sensors according to the first to third embodiments described above has a configuration in which one conductor film is formed corresponding to one piezoresistor. On the other hand, the semiconductor pressure sensor according to the present embodiment has a configuration in which a plurality of conductor films (conductive regions) are formed corresponding to one piezoresistor.
 具体的に、第1実施形態および第2実施形態に係る半導体圧力センサでは、ピエゾ抵抗11(11a,11b)、ピエゾ抵抗12(12a,12b)、ピエゾ抵抗13(13a,13b)、及びピエゾ抵抗14(14a,14b)に対応して、導電体膜41(41a,41b)、導電体膜42(42a,42b)、導電体膜43(43a,43b)、及び導電体膜44(44a,44b)がそれぞれ形成されていた。また、第3実施形態では、ピエゾ抵抗11~14に対して導電体膜41~44がそれぞれ形成されていた。 Specifically, in the semiconductor pressure sensor according to the first and second embodiments, the piezoresistor 11 (11a, 11b), the piezoresistor 12 (12a, 12b), the piezoresistor 13 (13a, 13b), and the piezoresistor. 14 (14a, 14b), conductor film 41 (41a, 41b), conductor film 42 (42a, 42b), conductor film 43 (43a, 43b), and conductor film 44 (44a, 44b). ) Were formed. In the third embodiment, the conductor films 41 to 44 are formed for the piezoresistors 11 to 14, respectively.
 これに対し、本実施形態に係る半導体圧力センサは、1つのピエゾ抵抗11に対応して2つの導電体膜(導電領域)41a,41bから構成される導電体膜41が対応して形成されており、1つのピエゾ抵抗12に対応して2つの導電体膜42a,42bから構成される導電体膜42が対応して形成されている。同様に、1つのピエゾ抵抗13に対応して2つの導電体膜43a,43bから構成される導電体膜43が対応して形成されており、1つのピエゾ抵抗14に対応して2つの導電体膜44a,44bから構成される導電体膜44が対応して形成されている。つまり、本実施形態に係る半導体圧力センサは、図4に示すブリッジ回路BR1を構成するピエゾ抵抗11~14(一対のピエゾ抵抗をそれぞれ備えるピエゾ抵抗)を、図6A~6Cに示すように各々が1つの素子から構成されるピエゾ抵抗11~14に代えた構成である。 On the other hand, in the semiconductor pressure sensor according to the present embodiment, a conductor film 41 composed of two conductor films (conductive regions) 41a and 41b is formed corresponding to one piezoresistor 11 and correspondingly formed. A conductor film 42 composed of two conductor films 42 a and 42 b is formed corresponding to one piezoresistor 12. Similarly, a conductor film 43 composed of two conductor films 43 a and 43 b is formed corresponding to one piezoresistor 13, and two conductors corresponding to one piezoresistor 14. A conductor film 44 composed of the films 44a and 44b is formed correspondingly. That is, in the semiconductor pressure sensor according to the present embodiment, the piezoresistors 11 to 14 (piezoresistors each having a pair of piezoresistors) constituting the bridge circuit BR1 shown in FIG. This is a configuration that replaces the piezoresistors 11 to 14 formed of one element.
 以上の通り、本実施形態に係る半導体圧力センサは、ピエゾ抵抗11~14が1つの素子から構成され、ピエゾ抵抗11~14に対応して複数の導電体膜がそれぞれ設けられた構成を有する。このように、本実施形態に係る半導体圧力センサにおいても、ピエゾ抵抗の各々に対応して個別に導電体膜が形成されており、導電体膜が対応するピエゾ抵抗の第一端又は第二端に接続されている点においては、第1~第3実施形態と同様である。このため、本実施形態においても、従来よりも測定誤差を低減することが可能である。 As described above, the semiconductor pressure sensor according to the present embodiment has a configuration in which the piezoresistors 11 to 14 are composed of one element, and a plurality of conductor films are provided corresponding to the piezoresistors 11 to 14, respectively. Thus, also in the semiconductor pressure sensor according to the present embodiment, the conductor film is individually formed corresponding to each of the piezoresistors, and the first end or the second end of the piezoresistor corresponding to the conductor film. This is the same as the first to third embodiments in that it is connected to. For this reason, also in this embodiment, it is possible to reduce a measurement error compared with the past.
〔第5実施形態〕
 図8は、本発明の第5実施形態で構成されるブリッジ回路を示す図である。尚、図8においても、図5~図7と同様に、図4に示す構成と同じ部材には同一の符号を付してある。本実施形態に係る半導体圧力センサは、ピエゾ抵抗11~14の各々に設けられるピエゾ抵抗の数、及び導電体膜41~44の各々に設けられる導電体膜(導電領域)の数を、第1実施形態および第2実施形態よりも増加させた構成を有する。具体的に、本実施形態に係る半導体圧力センサは、ピエゾ抵抗11~14の各々に4つのピエゾ抵抗が設けられており、導電体膜41~44の各々に4つの導電体膜が設けられている。
[Fifth Embodiment]
FIG. 8 is a diagram showing a bridge circuit configured in the fifth embodiment of the present invention. Also in FIG. 8, the same members as those shown in FIG. 4 are denoted by the same reference numerals as in FIGS. In the semiconductor pressure sensor according to the present embodiment, the number of piezoresistors provided in each of the piezoresistors 11 to 14 and the number of conductor films (conductive regions) provided in each of the conductor films 41 to 44 are set as follows. The configuration is increased from that in the embodiment and the second embodiment. Specifically, in the semiconductor pressure sensor according to the present embodiment, each of the piezoresistors 11 to 14 is provided with four piezoresistors, and each of the conductor films 41 to 44 is provided with four conductor films. Yes.
 図8に示す通り、本実施形態で構成されるブリッジ回路BR5は、ピエゾ抵抗11(11a~11d)、ピエゾ抵抗12(12a~12d)、ピエゾ抵抗13(13a~13d)、及びピエゾ抵抗14(14a~14d)が環状に接続された構成を有する。ピエゾ抵抗14とピエゾ抵抗11との間に金属配線51が接続されている。ピエゾ抵抗11とピエゾ抵抗12との間に金属配線52が接続されている。ピエゾ抵抗12とピエゾ抵抗13との間に金属配線53が接続されている。ピエゾ抵抗13とピエゾ抵抗14との間に金属配線54が接続されている。 As shown in FIG. 8, the bridge circuit BR5 configured in this embodiment includes a piezoresistor 11 (11a to 11d), a piezoresistor 12 (12a to 12d), a piezoresistor 13 (13a to 13d), and a piezoresistor 14 ( 14a to 14d) are connected in a ring shape. A metal wiring 51 is connected between the piezoresistor 14 and the piezoresistor 11. A metal wiring 52 is connected between the piezoresistor 11 and the piezoresistor 12. A metal wiring 53 is connected between the piezoresistor 12 and the piezoresistor 13. A metal wiring 54 is connected between the piezoresistor 13 and the piezoresistor 14.
 具体的に、ピエゾ抵抗11aの第一端とピエゾ抵抗11bの第一端とは互いに接続されている。ピエゾ抵抗11cの第一端とピエゾ抵抗11dの第一端とは互いに接続されている。ピエゾ抵抗11bの第二端とピエゾ抵抗11cの第二端とが互いに接続されている。ピエゾ抵抗12aの第一端とピエゾ抵抗12bの第一端とは互いに接続されている。ピエゾ抵抗12cの第一端とピエゾ抵抗12dの第一端とは互いに接続されている。ピエゾ抵抗12bの第二端とピエゾ抵抗12cの第二端とが互いに接続されている。 Specifically, the first end of the piezoresistor 11a and the first end of the piezoresistor 11b are connected to each other. The first end of the piezoresistor 11c and the first end of the piezoresistor 11d are connected to each other. The second end of the piezoresistor 11b and the second end of the piezoresistor 11c are connected to each other. The first end of the piezoresistor 12a and the first end of the piezoresistor 12b are connected to each other. The first end of the piezoresistor 12c and the first end of the piezoresistor 12d are connected to each other. The second end of the piezoresistor 12b and the second end of the piezoresistor 12c are connected to each other.
 同様に、ピエゾ抵抗13aの第一端とピエゾ抵抗13bの第一端とは互いに接続されている。ピエゾ抵抗13cの第一端とピエゾ抵抗13dの第一端とは互いに接続されている。ピエゾ抵抗13bの第二端とピエゾ抵抗13cの第二端とが互いに接続されている。ピエゾ抵抗14aの第一端とピエゾ抵抗14bの第一端とは互いに接続されている。ピエゾ抵抗14cの第一端とピエゾ抵抗14dの第一端とは互いに接続されている。ピエゾ抵抗14bの第二端とピエゾ抵抗14cの第二端とが互いに接続されている。 Similarly, the first end of the piezoresistor 13a and the first end of the piezoresistor 13b are connected to each other. The first end of the piezoresistor 13c and the first end of the piezoresistor 13d are connected to each other. The second end of the piezoresistor 13b and the second end of the piezoresistor 13c are connected to each other. The first end of the piezoresistor 14a and the first end of the piezoresistor 14b are connected to each other. The first end of the piezoresistor 14c and the first end of the piezoresistor 14d are connected to each other. The second end of the piezoresistor 14b and the second end of the piezoresistor 14c are connected to each other.
 また、図8に示すブリッジ回路BR5では、ピエゾ抵抗11(11a~11d)、ピエゾ抵抗12(12a~12d)、ピエゾ抵抗13(13a~13d)、及びピエゾ抵抗14(14a~14d)に対応して、導電体膜41(41a~41d)、導電体膜42(42a~42d)、導電体膜43(43a~43d)、及び導電体膜44(44a~44d)がそれぞれ設けられている。そして、導電体膜41a~41d,42a~42d,43a~43d,44a~44dは、対応するピエゾ抵抗11a~11d,12a~12d,13a~13d,14a~14dの第二端にそれぞれ接続されている。 8 corresponds to the piezoresistors 11 (11a to 11d), the piezoresistors 12 (12a to 12d), the piezoresistors 13 (13a to 13d), and the piezoresistors 14 (14a to 14d). The conductive film 41 (41a to 41d), the conductive film 42 (42a to 42d), the conductive film 43 (43a to 43d), and the conductive film 44 (44a to 44d) are provided. The conductor films 41a to 41d, 42a to 42d, 43a to 43d, 44a to 44d are connected to the second ends of the corresponding piezoresistors 11a to 11d, 12a to 12d, 13a to 13d, and 14a to 14d, respectively. Yes.
 図9は、本発明の第5実施形態に係る半導体圧力センサの要部構成を示す平面図であり、図2に相当する構成である。尚、図9においては、図2に示す構成と同じ部材には同一の符号を付してある。前述の通り、本実施形態に係る半導体圧力センサは、ピエゾ抵抗11~14の各々に設けられるピエゾ抵抗の数、及び導電体膜41~44の各々に設けられる導電体膜の数を、第1実施形態の2倍にした構成を有する。このため、図1中の符号Xで指し示されている部分の構成は、図9に示す通り、概ね図2に示す構成をX方向に2つ並べた構成になっている。 FIG. 9 is a plan view showing the main configuration of a semiconductor pressure sensor according to the fifth embodiment of the present invention, which corresponds to FIG. In FIG. 9, the same members as those shown in FIG. As described above, in the semiconductor pressure sensor according to the present embodiment, the number of piezoresistors provided in each of the piezoresistors 11 to 14 and the number of conductor films provided in each of the conductor films 41 to 44 are set as follows. The configuration is twice that of the embodiment. For this reason, the configuration of the part indicated by the symbol X in FIG. 1 is generally a configuration in which two configurations shown in FIG. 2 are arranged in the X direction as shown in FIG.
 具体的に、ピエゾ抵抗11に設けられたピエゾ抵抗11a~11dはいずれも、Y方向に延びるように(長手方向が同じ方向になるように)形成されており、ピエゾ抵抗11a~11dは、X方向に並べて配列されている。拡散配線21は、ピエゾ抵抗11aの第二端に接続された拡散配線21a、ピエゾ抵抗11aの第一端とピエゾ抵抗11bの第一端とを互いに接続する拡散配線21b、及びピエゾ抵抗11bの第二端に接続された拡散配線21c、ピエゾ抵抗11cの第二端に接続された拡散配線21d、ピエゾ抵抗11cの第一端とピエゾ抵抗11dの第一端とを互いに接続する拡散配線21e、及びピエゾ抵抗11dの第二端に接続された拡散配線21fから構成される。 Specifically, each of the piezoresistors 11a to 11d provided in the piezoresistor 11 is formed so as to extend in the Y direction (the longitudinal direction is the same direction), and the piezoresistors 11a to 11d are X Arranged side by side. The diffusion line 21 includes a diffusion line 21a connected to the second end of the piezoresistor 11a, a diffusion line 21b connecting the first end of the piezoresistor 11a and the first end of the piezoresistor 11b, and the first of the piezoresistor 11b. A diffusion line 21c connected to two ends, a diffusion line 21d connected to the second end of the piezoresistor 11c, a diffusion line 21e connecting the first end of the piezoresistor 11c and the first end of the piezoresistor 11d, and It comprises a diffusion wiring 21f connected to the second end of the piezoresistor 11d.
 導電体膜41は、ピエゾ抵抗11aに対応し、ピエゾ抵抗11aを平面視で覆うように形成された導電体膜41aと、ピエゾ抵抗11bに対応し、ピエゾ抵抗11bを平面視で覆うように形成された導電体膜41bと、ピエゾ抵抗11cに対応し、ピエゾ抵抗11cを平面視で覆うように形成された導電体膜41cと、ピエゾ抵抗11dに対応し、ピエゾ抵抗11dを平面視で覆うように形成された導電体膜41dとを備える。尚、導電体膜41bと導電体膜41cとは、-Y側の端部が接続されている。 The conductor film 41 corresponds to the piezoresistor 11a, and is formed so as to cover the piezoresistor 11a in plan view, and to correspond to the piezoresistor 11b and to cover the piezoresistor 11b in plan view. Corresponding to the conductive film 41b and the piezoresistor 11c, the conductive film 41c formed to cover the piezoresistor 11c in plan view, and to correspond to the piezoresistor 11d and to cover the piezoresistor 11d in plan view And a conductor film 41d formed on the substrate. The conductive film 41b and the conductive film 41c are connected at the end on the -Y side.
 導電体膜41a~41dは何れも、対応するピエゾ抵抗11a~11dの第二端にそれぞれ接続される。具体的に、導電体膜41aは、金属配線51及び拡散配線21aを介して対応するピエゾ抵抗11aの第二端に接続され、導電体膜41b,41cは、金属配線55及び拡散配線21c,21dを介して対応するピエゾ抵抗11b,11cの第二端にそれぞれ接続され、導電体膜41dは、金属配線52及び拡散配線21fを介して対応するピエゾ抵抗11dの第二端に接続される。尚、上記の金属配線55は、拡散配線21c、拡散配線21d、及び導電体膜41b,41cを接続するために、絶縁膜30上に形成された配線である。 The conductor films 41a to 41d are all connected to the second ends of the corresponding piezoresistors 11a to 11d, respectively. Specifically, the conductor film 41a is connected to the second end of the corresponding piezoresistor 11a via the metal wiring 51 and the diffusion wiring 21a, and the conductor films 41b and 41c are connected to the metal wiring 55 and the diffusion wirings 21c and 21d. Are connected to the second ends of the corresponding piezoresistors 11b and 11c, respectively, and the conductor film 41d is connected to the second end of the corresponding piezoresistors 11d via the metal wiring 52 and the diffusion wiring 21f. The metal wiring 55 is a wiring formed on the insulating film 30 in order to connect the diffusion wiring 21c, the diffusion wiring 21d, and the conductor films 41b and 41c.
 以上の通り、本実施形態に係る半導体圧力センサは、ピエゾ抵抗11~14の各々に設けられるピエゾ抵抗の数、及び導電体膜41~44の各々に設けられる導電体膜の数が異なるだけで、基本的な構成は、第1実施形態に係る半導体圧力センサと同じである。このため、本実施形態においても、従来よりも測定誤差を低減することが可能である。 As described above, the semiconductor pressure sensor according to the present embodiment differs only in the number of piezoresistors provided in each of the piezoresistors 11 to 14 and the number of conductor films provided in each of the conductor films 41 to 44. The basic configuration is the same as that of the semiconductor pressure sensor according to the first embodiment. For this reason, also in this embodiment, it is possible to reduce a measurement error compared with the past.
 以上、本発明の実施形態について説明したが、本発明は上記実施形態に制限されることなく、本発明の範囲内で自由に変更が可能である。例えば、上述した実施形態では、ダイヤフラム部10aの平面視形状が矩形形状である半導体圧力センサ1を例に挙げて説明したが、ダイヤフラム部10aの平面視形状は矩形形状に制限されることはなく、任意の形状(例えば、円形形状)であってよい。 As mentioned above, although embodiment of this invention was described, this invention is not restrict | limited to the said embodiment, It can change freely within the scope of the present invention. For example, in the above-described embodiment, the semiconductor pressure sensor 1 in which the planar shape of the diaphragm portion 10a is rectangular has been described as an example, but the planar shape of the diaphragm portion 10a is not limited to the rectangular shape. Any shape (for example, a circular shape) may be used.
 また、上述した実施形態では、ピエゾ抵抗11~14の表面及び拡散配線21~24の表面を含む半導体基板10の表面の全面に(全面を覆うように)絶縁膜30が形成されている例について説明した。しかしながら、ダイヤフラム部10aの上方(ピエゾ抵抗11~14、拡散配線21~24、及び導電体膜41~44が形成された部分を除く)の絶縁膜30は省かれていてもよい。 In the above-described embodiment, an example in which the insulating film 30 is formed on the entire surface of the semiconductor substrate 10 including the surfaces of the piezoresistors 11 to 14 and the surfaces of the diffusion wirings 21 to 24 (so as to cover the entire surface). explained. However, the insulating film 30 above the diaphragm portion 10a (except for the portion where the piezoresistors 11 to 14, the diffusion wirings 21 to 24, and the conductor films 41 to 44 are formed) may be omitted.
1…半導体圧力センサ
10…半導体基板
10a…ダイヤフラム部
11~14…ピエゾ抵抗
11a~11d…ピエゾ抵抗
12a~12d…ピエゾ抵抗
13a~13d…ピエゾ抵抗
14a~14d…ピエゾ抵抗
21~24…拡散配線
30…絶縁膜
41~44…導電体膜(導電領域)
41a~41d…導電体膜(導電領域)
42a~42d…導電体膜(導電領域)
43a~43d…導電体膜(導電領域)
44a~44d…導電体膜(導電領域)
51~54…金属配線
BR1~BR5…ブリッジ回路
CN…コンタクト部
DESCRIPTION OF SYMBOLS 1 ... Semiconductor pressure sensor 10 ... Semiconductor substrate 10a ... Diaphragm part 11-14 ... Piezoresistor 11a-11d ... Piezoresistor 12a-12d ... Piezoresistor 13a-13d ... Piezoresistor 14a-14d ... Piezoresistor 21-24 ... Diffusion wiring 30 ... Insulating films 41 to 44 ... Conductor film (conductive region)
41a to 41d ... Conductor film (conductive region)
42a to 42d ... Conductor film (conductive region)
43a to 43d ... Conductor film (conductive region)
44a to 44d ... Conductor film (conductive region)
51 to 54 Metal wiring BR1 to BR5 Bridge circuit CN Contact portion

Claims (8)

  1.  半導体圧力センサであって、
     ダイヤフラム部を有する半導体基板と、
     前記ダイヤフラム部の表面に形成された複数のピエゾ抵抗と、
     前記複数のピエゾ抵抗を接続してブリッジ回路を構成する複数の配線と、
     前記複数のピエゾ抵抗の表面を含む前記半導体基板の表面を覆うように形成された絶縁膜と、
     前記複数のピエゾ抵抗に対応して前記絶縁膜上に個別に形成された複数の導電領域を有する導電体膜と、を備え、
     少なくとも一つの導電領域は、一のピエゾ抵抗の第一端又は第二端に接続されている、
     半導体圧力センサ。
    A semiconductor pressure sensor,
    A semiconductor substrate having a diaphragm portion;
    A plurality of piezoresistors formed on the surface of the diaphragm portion;
    A plurality of wires connecting the plurality of piezoresistors to form a bridge circuit;
    An insulating film formed to cover the surface of the semiconductor substrate including the surfaces of the plurality of piezoresistors;
    A conductor film having a plurality of conductive regions individually formed on the insulating film corresponding to the plurality of piezoresistors,
    At least one conductive region is connected to a first end or a second end of one piezoresistor;
    Semiconductor pressure sensor.
  2.  前記複数の導電領域のうち少なくとも一つは、前記ピエゾ抵抗を平面視で覆うように前記絶縁膜上に形成されている、請求項1に記載の半導体圧力センサ。 The semiconductor pressure sensor according to claim 1, wherein at least one of the plurality of conductive regions is formed on the insulating film so as to cover the piezoresistor in a plan view.
  3.  前記複数の配線のうち少なくとも一つは、前記絶縁膜上に形成された第1配線であり、
     前記複数の配線のうち少なくとも一つは、前記ダイヤフラム部の前記表面に形成され、前記絶縁膜に形成されたコンタクト部を介して前記第1配線に接続されている第2配線である、
     請求項1又は請求項2に記載の半導体圧力センサ。
    At least one of the plurality of wirings is a first wiring formed on the insulating film,
    At least one of the plurality of wirings is a second wiring formed on the surface of the diaphragm portion and connected to the first wiring via a contact portion formed in the insulating film.
    The semiconductor pressure sensor according to claim 1 or 2.
  4.  前記第1配線は前記ピエゾ抵抗の前記第一端又は前記第二端に接続され、
     前記導電領域は、前記絶縁膜上において、前記ピエゾ抵抗の前記第一端又は前記第二端から前記第1配線に向かって延びるように形成されている、請求項3に記載の半導体圧力センサ。
    The first wiring is connected to the first end or the second end of the piezoresistor;
    The semiconductor pressure sensor according to claim 3, wherein the conductive region is formed on the insulating film so as to extend from the first end or the second end of the piezoresistor toward the first wiring.
  5.  前記複数のピエゾ抵抗は、一端が互いに接続された第1ピエゾ抵抗と第2ピエゾ抵抗とを備え、
     前記複数の導電領域のうち少なくとも一つは、前記第1ピエゾ抵抗に対応して形成された第1導電領域であり、
     前記複数の導電領域のうち少なくとも一つは、前記第2ピエゾ抵抗に対応して形成された第2導電領域である、請求項1から請求項4の何れか一項に記載の半導体圧力センサ。
    The plurality of piezoresistors include a first piezoresistor and a second piezoresistor, one end of which is connected to each other,
    At least one of the plurality of conductive regions is a first conductive region formed corresponding to the first piezoresistor,
    5. The semiconductor pressure sensor according to claim 1, wherein at least one of the plurality of conductive regions is a second conductive region formed corresponding to the second piezoresistor. 6.
  6.  前記第1ピエゾ抵抗と前記第2ピエゾ抵抗とは、前記第1ピエゾ抵抗の長手方向と前記第2ピエゾ抵抗の長手方向とが同じ方向になるように並べて形成されている、請求項5に記載の半導体圧力センサ。 6. The first piezoresistor and the second piezoresistor are formed side by side so that the longitudinal direction of the first piezoresistor and the longitudinal direction of the second piezoresistor are in the same direction. Semiconductor pressure sensor.
  7.  前記複数の導電領域は、前記複数の導電領域の一部が平面視で前記ダイヤフラム部の外側に位置するように前記絶縁膜上に形成されている、請求項1から請求項6の何れか一項に記載の半導体圧力センサ。 The plurality of conductive regions are formed on the insulating film so that a part of the plurality of conductive regions is positioned outside the diaphragm portion in a plan view. The semiconductor pressure sensor according to item.
  8.  前記複数の導電領域の前記ダイヤフラム部上における平面視形状は、前記ダイヤフラム部の中央部に対して点対称形状である、請求項1から請求項7の何れか一項に記載の半導体圧力センサ。 The semiconductor pressure sensor according to any one of claims 1 to 7, wherein a shape of the plurality of conductive regions in a plan view on the diaphragm portion is a point-symmetric shape with respect to a central portion of the diaphragm portion.
PCT/JP2016/077850 2015-10-28 2016-09-21 Semiconductor pressure sensor WO2017073207A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63147846U (en) * 1987-03-18 1988-09-29
US20020003274A1 (en) * 1998-08-27 2002-01-10 Janusz Bryzek Piezoresistive sensor with epi-pocket isolation
JP2012002646A (en) * 2010-06-16 2012-01-05 Mitsumi Electric Co Ltd Piezoresistance pressure sensor
JP2014206514A (en) * 2013-04-16 2014-10-30 パナソニック株式会社 Pressure sensor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63147846U (en) * 1987-03-18 1988-09-29
US20020003274A1 (en) * 1998-08-27 2002-01-10 Janusz Bryzek Piezoresistive sensor with epi-pocket isolation
JP2012002646A (en) * 2010-06-16 2012-01-05 Mitsumi Electric Co Ltd Piezoresistance pressure sensor
JP2014206514A (en) * 2013-04-16 2014-10-30 パナソニック株式会社 Pressure sensor

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