WO2017066309A1 - Structure and method of fabricating three-dimensional (3d) metal-insulator-metal (mim) capacitor and resistor in semi-additive plating metal wiring - Google Patents

Structure and method of fabricating three-dimensional (3d) metal-insulator-metal (mim) capacitor and resistor in semi-additive plating metal wiring Download PDF

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Publication number
WO2017066309A1
WO2017066309A1 PCT/US2016/056621 US2016056621W WO2017066309A1 WO 2017066309 A1 WO2017066309 A1 WO 2017066309A1 US 2016056621 W US2016056621 W US 2016056621W WO 2017066309 A1 WO2017066309 A1 WO 2017066309A1
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Prior art keywords
layer
polymer
substrate
metal
atop
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PCT/US2016/056621
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French (fr)
Inventor
Guan Huei See
Chin Hock Toh
Glen T. Mori
Arvind Sundarrajan
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Applied Materials Inc
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Applied Materials Inc
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Priority to CN201680056616.8A priority Critical patent/CN108140730B/en
Priority to KR1020187013480A priority patent/KR102619021B1/en
Publication of WO2017066309A1 publication Critical patent/WO2017066309A1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H10B63/22—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the metal-insulator-metal type
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/40—Resistors
    • H10D1/47—Resistors having no potential barriers
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H10P14/69392—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing hafnium, e.g. HfO2
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H10P14/69393—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing tantalum, e.g. Ta2O5
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    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
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    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
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    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/286—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of organic materials
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/035—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers
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    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H10W20/496—Capacitor integral with wiring layers
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/498—Resistive arrangements or effects of, or between, wiring layers
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    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
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    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers

Definitions

  • Embodiments of the present disclosure generally relate to three- dimensional metal-insulator-metal (“3D MIM”) capacitors and resistors in integrated circuits.
  • 3D MIM three- dimensional metal-insulator-metal
  • a semiconductor memory device generally comprises a plurality of memory cells which are used to store a large quantity of information.
  • Each memory cell includes a capacitor for storing electric charge and a corresponding field effect transistor for opening and closing charging and discharging passages of the capacitor.
  • Capacitors are one component that can occupy considerable area on a semiconductor die depending on the size of the capacitor and/or the number of capacitors on the die.
  • a capacitor used in a semiconductor memory device is a metal-insulator-metal (MIM) capacitor.
  • MIM capacitor is two- dimensional (2D).
  • a 2D MIM capacitor has two facing metal plates which are planar and substantially parallel to each other and to the substrate.
  • One method of increasing the capacitance of a MIM capacitor is to increase the sizes of the metal plates.
  • increasing the sizes of the metal plates will consume more surface area of the substrate. Accordingly, a need exists to reduce the surface area on the substrate occupied by a capacitor without sacrificing the capacitance.
  • a method of processing a substrate includes: providing a substrate having a polymer dielectric layer, a metal pad formed within the polymer dielectric layer and a first metal layer formed atop the polymer dielectric layer; depositing a polymer layer atop the substrate; patterning the polymer layer to form a plurality of openings to a top surface of the first metal layer, wherein the plurality of openings comprises a first opening formed proximate the metal pad; depositing a first barrier layer atop the polymer layer and within the plurality of openings formed in the polymer layer; depositing a dielectric layer atop the first barrier layer and within the plurality of openings formed in the polymer layer; etching the dielectric layer and the first barrier layer from within the first opening and a field region of the polymer layer; depositing a second barrier layer atop the substrate; depositing a second metal layer atop the substrate wherein the second metal layer fills the pluralit
  • a method of processing a substrate includes: providing a substrate having a patterned polymer dielectric layer comprising a plurality of openings; depositing a first barrier layer atop the substrate; depositing a dielectric layer atop the first barrier layer; depositing a second barrier layer atop the dielectric layer; and depositing a metal pad atop a portion of a field region of the patterned polymer dielectric layer.
  • a substrate includes: a polymer dielectric layer; a metal pad filling an opening in the polymer dielectric layer; a patterned first metal layer atop the polymer dielectric layer and conductively coupled to the metal pad; a polymer layer atop the substrate, wherein the polymer layer comprises a plurality of openings etched to a top surface of the patterned first metal layer, wherein the plurality of openings comprises a first opening formed proximate the metal pad; a barrier layer atop the polymer layer and within the plurality of openings in the polymer layer; a dielectric layer atop the barrier layer and within the plurality of openings in the polymer layer; a second barrier layer atop the substrate; and a second metal layer atop the substrate wherein the second metal layer fills the plurality of openings, and wherein the barrier layer, the dielectric layer and the second metal layer are not formed atop a portion of a field region of the substrate.
  • Figure 1 depicts a flow chart of a method for processing a substrate in accordance with some embodiments of the present disclosure.
  • Figures 2A-G depict the stages of processing a substrate in accordance with some embodiments of the present disclosure.
  • Figures 3A-3G depict embodiments of forming a 3-dimensional resistor in accordance with some embodiments of the present disclosure.
  • Figure 4 depicts a flow chart of a method for processing a substrate in accordance with some embodiments of the present disclosure.
  • Figure 5 depicts a flow chart of a method for processing a substrate in accordance with some embodiments of the present disclosure.
  • inventive methods advantageously facilitate an improved 3-dimensional (3D) metal-insulator- metal (MIM) capacitor and method of forming a 3D MIM capacitor having reduced resistance, enhanced system performance of overall system (i.e. of die connection to pad), and enhanced surface area over the same footprint in view of traditional 2- dimensional MIM structures.
  • MIM metal-insulator- metal
  • Figure 1 depicts a flow chart of a method 100 for processing a substrate in accordance with some embodiments of the present disclosure.
  • the method 100 is described herein with respect to the structure depicted in Figures 2A-2G.
  • the method 100 of the present disclosure may be performed in a single process chamber capable of performing both etching and deposition.
  • a suitable process chamber may be a standalone process chamber, or part of a cluster tool.
  • the inventive methods disclosed herein may be performed in separate chambers that also may be standalone or part of a cluster tool.
  • the method 100 generally begins at 102, as depicted in Figure 2A, by providing a substrate 200 having a polymer dielectric layer 202, a metal pad 206 formed within the polymer dielectric layer 202 and a first metal layer 204 formed atop the polymer dielectric layer 202.
  • the metal pad 206 is formed within an opening 224 in the polymer dielectric layer 202.
  • the metal pad 206 fills the opening 224 to a top surface of the substrate 200.
  • a die 226 is optionally embedded in the substrate 200.
  • the die can be any known suitable die material, such as silicon, used in wafer packaging.
  • the substrate 200 may be any suitable substrate material used in semiconductor manufacturing processes.
  • the substrate 200 may be one of silicon, glass, ceramic, or dielectric.
  • the polymer dielectric layer 202 may comprise any suitable polymer dielectric material such as polyimide or polybenzoxazole, or the like.
  • the metal pad 206 and the first metal layer 204 may comprise any suitable conductive material used to form a metal interconnect such as copper (Cu), aluminum (Al), or the like.
  • the first metal layer 204 is a redistribution layer (i.e. a layer to redirect connectivity to the pad) provided over the polymer dielectric layer 202.
  • the first metal layer 204 may be formed using a plating process or deposition process, such as a physical vapor deposition process, used in a semiconductor manufacturing processes.
  • a polymer layer 208 is spin- coated over the substrate 200.
  • the polymer layer 208 may be deposited using any suitable spin-coating process or lithographic process.
  • the polymer layer 208 is a polybenzoxazole (PBO) layer, a polyimide layer, a benzocyclobutene (BCB) layer, an epoxy layer, or a photo-sensitive material layer
  • the polymer layer 208 is patterned to form a plurality of openings 210.
  • the plurality of openings 210 are formed to a top surface 216 of the first metal layer 204.
  • the plurality of openings 210 comprises a first opening 218 formed proximate the metal pad 206.
  • the patterning process may be any suitable lithographic process for forming openings in the polymer layer 208.
  • the plurality of openings 210 may be a feature such as a via, a trench, or the like.
  • a first barrier layer 212 is conformally deposited atop the substrate 200.
  • the first barrier layer 212 is deposited atop, or directly atop, the polymer layer 208 and within the plurality of openings 210 formed in the polymer layer 208.
  • the first barrier layer 212 is deposited atop the field region of the polymer layer 208 and along the sidewalls of the plurality of openings 210 and the bottom of the plurality of openings 210.
  • the first barrier layer 212 may be deposited using any suitable deposition process, for example a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), or the like.
  • the first barrier layer 212 is a conductive material, such as titanium (Ti) or titanium nitride (TiN).
  • a dielectric layer 214 is conformally deposited over the first barrier layer 212.
  • the dielectric layer 214 is deposited atop, or directly atop, the first barrier layer 212 and within the plurality of openings 210 formed in the polymer layer 208.
  • the dielectric layer 214 is deposited atop the field region of the first barrier layer 212 and along the sidewalls of the plurality of openings 210 and the bottom of the plurality of openings 210.
  • the dielectric layer 214 may be deposited using any suitable deposition process, for example a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), or the like.
  • PVD physical vapor deposition process
  • CVD chemical vapor deposition process
  • ALD atomic layer deposition process
  • the dielectric layer 214 is a nitride film or a high-k dielectric material, such as hafnium oxide (Hf02), silicon nitride (Si3N 4 ), or tantalum oxide (Ta 2 05).
  • Hf02 hafnium oxide
  • Si3N 4 silicon nitride
  • Ta 2 05 tantalum oxide
  • the dielectric layer 214 and the first barrier layer 212 are etched from within the first opening 218 and from a field region 220 of the polymer layer 208.
  • the dielectric layer 214 and the first barrier layer 212 may be etched using a patterned photoresist layer (not shown).
  • a photoresist material can be deposited on the substrate 200 and then exposed to light filtered by a reticle, such as a glass plate that is patterned with exemplary feature geometries that block light from propagating through the reticle.
  • the photoresist layer may comprise any photoresist materials suitable to provide a template to facilitate etching the layers 212, 214 from within the first opening 218 and from a field region 220 of the polymer layer 208.
  • the photoresist material may be a positive or negative photoresist and/or a DUV or EUV (deep ultraviolet or extreme ultraviolet) photoresist and may comprise one or more of polymers, organic compounds (e.g., comprising carbon, hydrogen and oxygen), an amorphous carbon, such as Advanced Patterning Film (APF), available from Applied Materials, Inc., located in Santa Clara, California, a tri- layer resist (e.g., a photoresist layer, a Si-rich anti-reflective coating (ARC) layer, and a carbon-rich ARC, or bottom ARC (BARC) layer), a spin-on hardmask (SOH), or the like.
  • the layers 212, 214 are etched to remove the material from the areas that are no longer protected by the photoresist material.
  • the photoresist material is then completely stripped from the substrate 200.
  • a second barrier layer 228 and a second metal layer 222 are deposited atop the substrate 200.
  • the second barrier layer 228 is conformally deposited atop the substrate 200 and within the plurality of openings 210 formed in the polymer layer 208.
  • the second barrier layer 228 may be deposited using any suitable deposition process, for example a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), or the like.
  • the second barrier layer 228 is a conductive material, such as titanium (Ti) or titanium nitride (TiN).
  • the second metal layer 222 is deposited atop the substrate 200 and fills the plurality of openings 210.
  • the second metal layer 222 may be deposited using any suitable deposition process, for example a electroplating process.
  • the second metal layer 222 may comprise any suitable conductive material used to form a metal interconnect such as copper (Cu), aluminum (Al), or the like.
  • the layers 212, 214, 228, 222 are etched from a portion of the field region 220 of the polymer layer 208.
  • the layers 212, 214, 228, 222 may be etched using a patterned photoresist layer (not shown) as described above.
  • the photoresist layer may comprise any photoresist materials suitable to provide a template to facilitate etching the layers 212, 214, 228, 222.
  • the layers 212, 214, 228, 222 are etched to remove the material from the areas that are no longer protected by the photoresist material. The photoresist material is then completely stripped from the substrate 200.
  • Figure 4 depicts a flow chart of a method 400 for processing a substrate in accordance with some embodiments of the present disclosure.
  • the method 400 is described herein with respect to the structure depicted in Figures 3A-3C.
  • the method 400 of the present disclosure may be performed in a single process chamber capable of performing both etching and deposition.
  • a suitable process chamber may be a standalone process chamber, or part of a cluster tool.
  • the inventive methods disclosed herein may be performed in separate chambers that also may be standalone or part of a cluster tool.
  • Figures 3A-3C depicts one embodiment of forming a 3-dimensional resistor in accordance with some embodiments of the present disclosure.
  • the method 400 generally begins at 402, as depicted in Figure 3A by providing a substrate 300 having a patterned polymer dielectric layer 302 comprising a plurality of openings 304.
  • the substrate 300 may be any suitable substrate material used in semiconductor manufacturing processes.
  • the substrate 300 may be one of silicon, glass, ceramic, or dielectric.
  • the patterned polymer dielectric layer 302 may comprise any suitable polymer dielectric material such as polyimide or polybenzoxazole, or the like.
  • the patterned polymer dielectric layer 302 may be patterned using any suitable etch lithographic process, such as a plasma etching process, for forming openings in a polymer material.
  • a first barrier layer 306 is deposited atop the substrate 300.
  • the first barrier layer 306 is deposited atop the patterned polymer dielectric layer 302 and within the plurality of openings 304 formed in the patterned polymer dielectric layer 302.
  • the first barrier layer 306 is deposited atop the field region of the patterned polymer dielectric layer 302 and along the sidewalls of the plurality of openings 304 and the bottom of the plurality of openings 304.
  • the first barrier layer 306 may be deposited using any suitable deposition process, for example a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), or the like.
  • the first barrier layer 306 is a conductive material, such as titanium (Ti) or titanium nitride (TiN).
  • a dielectric layer 308 is deposited over the first barrier layer 306.
  • the dielectric layer 308 is deposited atop the first barrier layer 306 and within the plurality of openings 304 formed in the patterned polymer dielectric layer 302.
  • the dielectric layer 308 may be deposited using any suitable deposition process, for example a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), or the like.
  • the dielectric layer 308 is a nitride film or a high-k dielectric material, such as hafnium oxide (Hf0 2 ), silicon nitride (Si3N 4 ), tantalum oxide (Ta 2 Os).
  • a second barrier layer 318 is conformally deposited atop the substrate 200, for example directly atop the dielectric layer 308, and within the plurality of openings 210 formed in the polymer layer 208.
  • the second barrier layer 318 may be deposited using any suitable deposition process, for example a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), or the like.
  • the second barrier layer is a conductive material, such as titanium (Ti) or titanium nitride (TiN).
  • the layers 306, 308, 318 are etched from a portion of the field region 314 of the patterned polymer dielectric layer 302.
  • the layers 306, 308, 318 may be etched using a patterned photoresist layer (not shown) as described above.
  • a metal pad 310 connection is formed atop a portion of the field region of the patterned polymer dielectric layer 302.
  • the metal pad 310 may comprise any suitable conductive material used to form a metal interconnect such as copper (Cu).
  • Figure 5 depicts a flow chart of a method 500 for processing a substrate in accordance with some embodiments of the present disclosure.
  • the method 500 is described herein with respect to the structure depicted in Figures 3D-3G.
  • the method 500 of the present disclosure may be performed in a single process chamber capable of performing both etching and deposition.
  • a suitable process chamber may be a standalone process chamber, or part of a cluster tool.
  • the inventive methods disclosed herein may be performed in separate chambers that also may be standalone or part of a cluster tool.
  • Figures 3D-3G depict one embodiment of forming a 3-dimensional resistor in accordance with some embodiments of the present disclosure.
  • the method 500 generally begins at 502, and as depicted in Figure 3D by providing a substrate 300 with a patterned metal layer 312.
  • the substrate 300 may be any suitable substrate material used in semiconductor manufacturing processes.
  • the substrate 300 may be one of silicon, glass, ceramic, or dielectric.
  • the patterned metal layer 312 may comprise any suitable conductive material used to form a metal interconnect such as copper (Cu).
  • a patterned polymer dielectric layer 302 comprising a plurality of openings 304 is formed atop the substrate 300.
  • a portion of the plurality of openings 304 is formed atop the patterned metal layer 312 such that a portion of the plurality of openings 304 exposes a top surface of the patterned metal layer 312.
  • the patterned polymer dielectric layer 302 may comprise any suitable polymer dielectric material such as polyimide or polybenzoxazole, or the like.
  • the patterned polymer dielectric layer 302 may be patterned using any suitable etch lithographic process, such as a plasma etching process, for forming openings in a polymer material.
  • a first barrier layer 306 is deposited atop the substrate 300.
  • the first barrier layer 306 is deposited atop the patterned polymer dielectric layer 302 and within the plurality of openings 304 formed in the patterned polymer dielectric layer 302.
  • the first barrier layer 306 is deposited atop the field region of the patterned polymer dielectric layer 302 and along the sidewalls of the plurality of openings 304 and the bottom of the plurality of openings 304.
  • the first barrier layer 306 may be deposited using any suitable deposition process, for example a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), or the like.
  • the first barrier layer 306 is a conductive material, such as titanium (Ti) or titanium nitride (TiN).
  • a dielectric layer 308 is deposited over the first barrier layer 306.
  • the dielectric layer 308 is deposited atop the first barrier layer 306 and within the plurality of openings 304 formed in the patterned polymer dielectric layer 302.
  • the dielectric layer 308 may be deposited using any suitable deposition process, for example a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), or the like.
  • the dielectric layer 308 is a nitride film or a high-k dielectric material, such as hafnium oxide (Hf0 2 ), silicon nitride (Si 3 N 4 ), tantalum oxide (Ta 2 0 5 ).
  • the dielectric layer 308 and the first barrier layer 306 are then removed from within a first opening 316 of the patterned polymer dielectric layer 302.
  • the layers 306, 308, may be etched from within a first opening 316 of the patterned polymer dielectric layer 302 using a patterned photoresist layer (not shown) as described above.
  • a second barrier layer 318 is conformally deposited atop the substrate 200 and within the plurality of openings 304 formed in the patterned polymer dielectric layer 302.
  • the second barrier layer 318 may be deposited using any suitable deposition process, for example a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), or the like.
  • the second barrier layer is a conductive material, such as titanium (Ti) or titanium nitride (TiN).
  • the layers 306, 308, 318 are etched from within a first opening 316 of the patterned polymer dielectric layer 302 using a patterned photoresist layer (not shown) as described above.
  • a metal pad 310 connection is formed to the patterned metal layer 312.
  • the metal pad 310 is formed atop a portion of the field region of the patterned polymer dielectric layer 302.
  • the metal pad 310 may comprise any suitable conductive material used to form a metal interconnect such as copper (Cu).
  • the conductive material of the metal pad 310 is deposited within the first opening 316 of the patterned polymer dielectric layer 302 to fill the first opening 316.

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Abstract

Methods of processing a substrate include: providing a substrate having a polymer dielectric layer, a metal pad formed within the polymer dielectric layer and a first metal layer formed atop the polymer dielectric layer; depositing a polymer layer atop the substrate; patterning the polymer layer to form a plurality of openings, wherein the plurality of openings comprises a first opening formed proximate the metal pad; depositing a first barrier layer atop the polymer layer; depositing a dielectric layer atop the first barrier layer; etching the dielectric layer and the first barrier layer from within the first opening and a field region of the polymer layer; depositing a second barrier layer atop the substrate; depositing a second metal layer atop the substrate wherein the second metal layer fills the plurality of openings; and etching the second metal layer from a portion of the field region of the polymer layer.

Description

STRUCTURE AND METHOD OF FABRICATING THREE-DIMENSIONAL (3D) METAL-INSULATOR-METAL (MIM) CAPACITOR AND RESISTOR IN SEMI- ADDITIVE PLATING METAL WIRING
FIELD
[0001] Embodiments of the present disclosure generally relate to three- dimensional metal-insulator-metal ("3D MIM") capacitors and resistors in integrated circuits.
BACKGROUND
[0002] A semiconductor memory device generally comprises a plurality of memory cells which are used to store a large quantity of information. Each memory cell includes a capacitor for storing electric charge and a corresponding field effect transistor for opening and closing charging and discharging passages of the capacitor. As the size of semiconductor devices continues to shrink, the area occupied by each component of a semiconductor device should be decreased. Capacitors are one component that can occupy considerable area on a semiconductor die depending on the size of the capacitor and/or the number of capacitors on the die.
[0003] One example of a capacitor used in a semiconductor memory device is a metal-insulator-metal (MIM) capacitor. A traditional MIM capacitor is two- dimensional (2D). A 2D MIM capacitor has two facing metal plates which are planar and substantially parallel to each other and to the substrate. One method of increasing the capacitance of a MIM capacitor is to increase the sizes of the metal plates. However, increasing the sizes of the metal plates will consume more surface area of the substrate. Accordingly, a need exists to reduce the surface area on the substrate occupied by a capacitor without sacrificing the capacitance.
[0004] Accordingly, the inventors have developed an improved 3-dimensional metal-insulator-metal (3D MIM) capacitor and method of forming a 3D MIM capacitor. SUMMARY
[0005] Methods for processing a substrate are provided herein. In some embodiments, a method of processing a substrate includes: providing a substrate having a polymer dielectric layer, a metal pad formed within the polymer dielectric layer and a first metal layer formed atop the polymer dielectric layer; depositing a polymer layer atop the substrate; patterning the polymer layer to form a plurality of openings to a top surface of the first metal layer, wherein the plurality of openings comprises a first opening formed proximate the metal pad; depositing a first barrier layer atop the polymer layer and within the plurality of openings formed in the polymer layer; depositing a dielectric layer atop the first barrier layer and within the plurality of openings formed in the polymer layer; etching the dielectric layer and the first barrier layer from within the first opening and a field region of the polymer layer; depositing a second barrier layer atop the substrate; depositing a second metal layer atop the substrate wherein the second metal layer fills the plurality of openings; and etching the second metal layer from a portion of the field region of the polymer layer.
[0006] In some embodiments, a method of processing a substrate, includes: providing a substrate having a patterned polymer dielectric layer comprising a plurality of openings; depositing a first barrier layer atop the substrate; depositing a dielectric layer atop the first barrier layer; depositing a second barrier layer atop the dielectric layer; and depositing a metal pad atop a portion of a field region of the patterned polymer dielectric layer.
[0007] A substrate includes: a polymer dielectric layer; a metal pad filling an opening in the polymer dielectric layer; a patterned first metal layer atop the polymer dielectric layer and conductively coupled to the metal pad; a polymer layer atop the substrate, wherein the polymer layer comprises a plurality of openings etched to a top surface of the patterned first metal layer, wherein the plurality of openings comprises a first opening formed proximate the metal pad; a barrier layer atop the polymer layer and within the plurality of openings in the polymer layer; a dielectric layer atop the barrier layer and within the plurality of openings in the polymer layer; a second barrier layer atop the substrate; and a second metal layer atop the substrate wherein the second metal layer fills the plurality of openings, and wherein the barrier layer, the dielectric layer and the second metal layer are not formed atop a portion of a field region of the substrate.
[0008] Other and further embodiments of the present disclosure are described below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] Embodiments of the present disclosure, briefly summarized above and discussed in greater detail below, can be understood by reference to the illustrative embodiments of the disclosure depicted in the appended drawings. However, the appended drawings illustrate only typical embodiments of the disclosure and are therefore not to be considered limiting of scope, for the disclosure may admit to other equally effective embodiments.
[0010] Figure 1 depicts a flow chart of a method for processing a substrate in accordance with some embodiments of the present disclosure.
[0011] Figures 2A-G depict the stages of processing a substrate in accordance with some embodiments of the present disclosure.
[0012] Figures 3A-3G depict embodiments of forming a 3-dimensional resistor in accordance with some embodiments of the present disclosure.
[0013] Figure 4 depicts a flow chart of a method for processing a substrate in accordance with some embodiments of the present disclosure.
[0014] Figure 5 depicts a flow chart of a method for processing a substrate in accordance with some embodiments of the present disclosure.
[0015] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.
DETAILED DESCRIPTION
[0016] Methods for processing a substrate are provided herein. The inventive methods advantageously facilitate an improved 3-dimensional (3D) metal-insulator- metal (MIM) capacitor and method of forming a 3D MIM capacitor having reduced resistance, enhanced system performance of overall system (i.e. of die connection to pad), and enhanced surface area over the same footprint in view of traditional 2- dimensional MIM structures.
[0017] Figure 1 depicts a flow chart of a method 100 for processing a substrate in accordance with some embodiments of the present disclosure. The method 100 is described herein with respect to the structure depicted in Figures 2A-2G. The method 100 of the present disclosure may be performed in a single process chamber capable of performing both etching and deposition. Such a suitable process chamber may be a standalone process chamber, or part of a cluster tool. Alternatively, the inventive methods disclosed herein may be performed in separate chambers that also may be standalone or part of a cluster tool.
[0018] The method 100 generally begins at 102, as depicted in Figure 2A, by providing a substrate 200 having a polymer dielectric layer 202, a metal pad 206 formed within the polymer dielectric layer 202 and a first metal layer 204 formed atop the polymer dielectric layer 202. The metal pad 206 is formed within an opening 224 in the polymer dielectric layer 202. In some embodiments, the metal pad 206 fills the opening 224 to a top surface of the substrate 200. In some embodiments, a die 226 is optionally embedded in the substrate 200. The die can be any known suitable die material, such as silicon, used in wafer packaging. The substrate 200 may be any suitable substrate material used in semiconductor manufacturing processes. For example, the substrate 200 may be one of silicon, glass, ceramic, or dielectric. The polymer dielectric layer 202 may comprise any suitable polymer dielectric material such as polyimide or polybenzoxazole, or the like. The metal pad 206 and the first metal layer 204 may comprise any suitable conductive material used to form a metal interconnect such as copper (Cu), aluminum (Al), or the like. The first metal layer 204 is a redistribution layer (i.e. a layer to redirect connectivity to the pad) provided over the polymer dielectric layer 202. In some embodiments, the first metal layer 204 may be formed using a plating process or deposition process, such as a physical vapor deposition process, used in a semiconductor manufacturing processes. [0019] Next at 104, and as depicted in Figure 2B, a polymer layer 208 is spin- coated over the substrate 200. The polymer layer 208 may be deposited using any suitable spin-coating process or lithographic process. In some embodiments, the polymer layer 208 is a polybenzoxazole (PBO) layer, a polyimide layer, a benzocyclobutene (BCB) layer, an epoxy layer, or a photo-sensitive material layer
[0020] Next, at 106, and as depicted in Figure 2C, the polymer layer 208 is patterned to form a plurality of openings 210. The plurality of openings 210 are formed to a top surface 216 of the first metal layer 204. The plurality of openings 210 comprises a first opening 218 formed proximate the metal pad 206. In some embodiments, the patterning process may be any suitable lithographic process for forming openings in the polymer layer 208. In some embodiments, the plurality of openings 210 may be a feature such as a via, a trench, or the like.
[0021] Next at 108, and as depicted in Figure 2D, a first barrier layer 212 is conformally deposited atop the substrate 200. The first barrier layer 212 is deposited atop, or directly atop, the polymer layer 208 and within the plurality of openings 210 formed in the polymer layer 208. The first barrier layer 212 is deposited atop the field region of the polymer layer 208 and along the sidewalls of the plurality of openings 210 and the bottom of the plurality of openings 210. The first barrier layer 212 may be deposited using any suitable deposition process, for example a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), or the like. In some embodiments, the first barrier layer 212 is a conductive material, such as titanium (Ti) or titanium nitride (TiN).
[0022] Next, at 1 10, and as depicted in Figure 2D, a dielectric layer 214 is conformally deposited over the first barrier layer 212. The dielectric layer 214 is deposited atop, or directly atop, the first barrier layer 212 and within the plurality of openings 210 formed in the polymer layer 208. The dielectric layer 214 is deposited atop the field region of the first barrier layer 212 and along the sidewalls of the plurality of openings 210 and the bottom of the plurality of openings 210. The dielectric layer 214 may be deposited using any suitable deposition process, for example a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), or the like. In some embodiments, the dielectric layer 214 is a nitride film or a high-k dielectric material, such as hafnium oxide (Hf02), silicon nitride (Si3N4), or tantalum oxide (Ta205).
[0023] Next, at 1 12, and as depicted in Figure 2E, the dielectric layer 214 and the first barrier layer 212 are etched from within the first opening 218 and from a field region 220 of the polymer layer 208. In some embodiments, the dielectric layer 214 and the first barrier layer 212 may be etched using a patterned photoresist layer (not shown). For example, a photoresist material can be deposited on the substrate 200 and then exposed to light filtered by a reticle, such as a glass plate that is patterned with exemplary feature geometries that block light from propagating through the reticle. After passing through the reticle, the light contacts the surface of the photoresist material and changes the chemical composition of the photoresist material such that a developer can remove a portion of the photoresist material. In the case of positive photoresist materials, the exposed regions are removed, and in the case of negative photoresist materials, the unexposed regions are removed. The photoresist layer may comprise any photoresist materials suitable to provide a template to facilitate etching the layers 212, 214 from within the first opening 218 and from a field region 220 of the polymer layer 208. For example, in some embodiments, the photoresist material may be a positive or negative photoresist and/or a DUV or EUV (deep ultraviolet or extreme ultraviolet) photoresist and may comprise one or more of polymers, organic compounds (e.g., comprising carbon, hydrogen and oxygen), an amorphous carbon, such as Advanced Patterning Film (APF), available from Applied Materials, Inc., located in Santa Clara, California, a tri- layer resist (e.g., a photoresist layer, a Si-rich anti-reflective coating (ARC) layer, and a carbon-rich ARC, or bottom ARC (BARC) layer), a spin-on hardmask (SOH), or the like. Thereafter, the layers 212, 214 are etched to remove the material from the areas that are no longer protected by the photoresist material. The photoresist material is then completely stripped from the substrate 200.
[0024] Next, at 1 13 and 1 14, and as depicted in Figure 2F, a second barrier layer 228 and a second metal layer 222, are deposited atop the substrate 200. The second barrier layer 228 is conformally deposited atop the substrate 200 and within the plurality of openings 210 formed in the polymer layer 208. The second barrier layer 228 may be deposited using any suitable deposition process, for example a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), or the like. In some embodiments, the second barrier layer 228 is a conductive material, such as titanium (Ti) or titanium nitride (TiN). The second metal layer 222 is deposited atop the substrate 200 and fills the plurality of openings 210. The second metal layer 222 may be deposited using any suitable deposition process, for example a electroplating process. The second metal layer 222 may comprise any suitable conductive material used to form a metal interconnect such as copper (Cu), aluminum (Al), or the like.
[0025] Next, at 1 16, and depicted in Figure 2G, the layers 212, 214, 228, 222 are etched from a portion of the field region 220 of the polymer layer 208. In some embodiments, the layers 212, 214, 228, 222 may be etched using a patterned photoresist layer (not shown) as described above. The photoresist layer may comprise any photoresist materials suitable to provide a template to facilitate etching the layers 212, 214, 228, 222. The layers 212, 214, 228, 222 are etched to remove the material from the areas that are no longer protected by the photoresist material. The photoresist material is then completely stripped from the substrate 200.
[0026] Figure 4 depicts a flow chart of a method 400 for processing a substrate in accordance with some embodiments of the present disclosure. The method 400 is described herein with respect to the structure depicted in Figures 3A-3C. The method 400 of the present disclosure may be performed in a single process chamber capable of performing both etching and deposition. Such a suitable process chamber may be a standalone process chamber, or part of a cluster tool. Alternatively, the inventive methods disclosed herein may be performed in separate chambers that also may be standalone or part of a cluster tool.
[0027] Figures 3A-3C depicts one embodiment of forming a 3-dimensional resistor in accordance with some embodiments of the present disclosure. The method 400 generally begins at 402, as depicted in Figure 3A by providing a substrate 300 having a patterned polymer dielectric layer 302 comprising a plurality of openings 304. In some embodiments, the substrate 300 may be any suitable substrate material used in semiconductor manufacturing processes. For example, the substrate 300 may be one of silicon, glass, ceramic, or dielectric. The patterned polymer dielectric layer 302 may comprise any suitable polymer dielectric material such as polyimide or polybenzoxazole, or the like. In some embodiments, the patterned polymer dielectric layer 302 may be patterned using any suitable etch lithographic process, such as a plasma etching process, for forming openings in a polymer material.
[0028] Next, at 404, and as depicted in Figure 3B a first barrier layer 306 is deposited atop the substrate 300. The first barrier layer 306 is deposited atop the patterned polymer dielectric layer 302 and within the plurality of openings 304 formed in the patterned polymer dielectric layer 302. The first barrier layer 306 is deposited atop the field region of the patterned polymer dielectric layer 302 and along the sidewalls of the plurality of openings 304 and the bottom of the plurality of openings 304. The first barrier layer 306 may be deposited using any suitable deposition process, for example a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), or the like. In some embodiments, the first barrier layer 306 is a conductive material, such as titanium (Ti) or titanium nitride (TiN).
[0029] Next, at 406, and as depicted in Figure 3C, a dielectric layer 308 is deposited over the first barrier layer 306. The dielectric layer 308 is deposited atop the first barrier layer 306 and within the plurality of openings 304 formed in the patterned polymer dielectric layer 302. The dielectric layer 308 may be deposited using any suitable deposition process, for example a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), or the like. In some embodiments, the dielectric layer 308 is a nitride film or a high-k dielectric material, such as hafnium oxide (Hf02), silicon nitride (Si3N4), tantalum oxide (Ta2Os).
[0030] Next, at 407, following deposition of the dielectric layer 308 a second barrier layer 318 is conformally deposited atop the substrate 200, for example directly atop the dielectric layer 308, and within the plurality of openings 210 formed in the polymer layer 208. The second barrier layer 318 may be deposited using any suitable deposition process, for example a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), or the like. In some embodiments, the second barrier layer is a conductive material, such as titanium (Ti) or titanium nitride (TiN). Next, the layers 306, 308, 318 are etched from a portion of the field region 314 of the patterned polymer dielectric layer 302. In some embodiments, the layers 306, 308, 318 may be etched using a patterned photoresist layer (not shown) as described above.
[0031] Next at 408, and as depicted in Figure 3C a metal pad 310 connection is formed atop a portion of the field region of the patterned polymer dielectric layer 302. The metal pad 310 may comprise any suitable conductive material used to form a metal interconnect such as copper (Cu).
[0032] Figure 5 depicts a flow chart of a method 500 for processing a substrate in accordance with some embodiments of the present disclosure. The method 500 is described herein with respect to the structure depicted in Figures 3D-3G. The method 500 of the present disclosure may be performed in a single process chamber capable of performing both etching and deposition. Such a suitable process chamber may be a standalone process chamber, or part of a cluster tool. Alternatively, the inventive methods disclosed herein may be performed in separate chambers that also may be standalone or part of a cluster tool.
[0033] Figures 3D-3G depict one embodiment of forming a 3-dimensional resistor in accordance with some embodiments of the present disclosure. The method 500 generally begins at 502, and as depicted in Figure 3D by providing a substrate 300 with a patterned metal layer 312. In some embodiments, the substrate 300 may be any suitable substrate material used in semiconductor manufacturing processes. For example, the substrate 300 may be one of silicon, glass, ceramic, or dielectric. In some embodiments, the patterned metal layer 312 may comprise any suitable conductive material used to form a metal interconnect such as copper (Cu).
[0034] Next, at 504, and as depicted in Figure 3E, a patterned polymer dielectric layer 302 comprising a plurality of openings 304 is formed atop the substrate 300. A portion of the plurality of openings 304 is formed atop the patterned metal layer 312 such that a portion of the plurality of openings 304 exposes a top surface of the patterned metal layer 312. The patterned polymer dielectric layer 302 may comprise any suitable polymer dielectric material such as polyimide or polybenzoxazole, or the like. In some embodiments, the patterned polymer dielectric layer 302 may be patterned using any suitable etch lithographic process, such as a plasma etching process, for forming openings in a polymer material.
[0035] Next, at 506, and as depicted in Figure 3F a first barrier layer 306 is deposited atop the substrate 300. The first barrier layer 306 is deposited atop the patterned polymer dielectric layer 302 and within the plurality of openings 304 formed in the patterned polymer dielectric layer 302. The first barrier layer 306 is deposited atop the field region of the patterned polymer dielectric layer 302 and along the sidewalls of the plurality of openings 304 and the bottom of the plurality of openings 304. The first barrier layer 306 may be deposited using any suitable deposition process, for example a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), or the like. In some embodiments, the first barrier layer 306 is a conductive material, such as titanium (Ti) or titanium nitride (TiN).
[0036] Next, at 508, and as depicted in Figure 3F, a dielectric layer 308 is deposited over the first barrier layer 306. The dielectric layer 308 is deposited atop the first barrier layer 306 and within the plurality of openings 304 formed in the patterned polymer dielectric layer 302. The dielectric layer 308 may be deposited using any suitable deposition process, for example a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), or the like. In some embodiments, the dielectric layer 308 is a nitride film or a high-k dielectric material, such as hafnium oxide (Hf02), silicon nitride (Si3N4), tantalum oxide (Ta205). The dielectric layer 308 and the first barrier layer 306 are then removed from within a first opening 316 of the patterned polymer dielectric layer 302. In some embodiments, the layers 306, 308, may be etched from within a first opening 316 of the patterned polymer dielectric layer 302 using a patterned photoresist layer (not shown) as described above.
[0037] Following deposition of the dielectric layer 308 a second barrier layer 318 is conformally deposited atop the substrate 200 and within the plurality of openings 304 formed in the patterned polymer dielectric layer 302. The second barrier layer 318 may be deposited using any suitable deposition process, for example a physical vapor deposition process (PVD), a chemical vapor deposition process (CVD), an atomic layer deposition process (ALD), or the like. In some embodiments, the second barrier layer is a conductive material, such as titanium (Ti) or titanium nitride (TiN). Next, the layers 306, 308, 318 are etched from within a first opening 316 of the patterned polymer dielectric layer 302 using a patterned photoresist layer (not shown) as described above.
[0038] Next at 510, and as depicted in Figure 3G, a metal pad 310 connection is formed to the patterned metal layer 312. The metal pad 310 is formed atop a portion of the field region of the patterned polymer dielectric layer 302. The metal pad 310 may comprise any suitable conductive material used to form a metal interconnect such as copper (Cu). The conductive material of the metal pad 310 is deposited within the first opening 316 of the patterned polymer dielectric layer 302 to fill the first opening 316.
[0039] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof.

Claims

Claims:
1 . A method of processing a substrate, comprising:
providing a substrate having a polymer dielectric layer, a metal pad formed within the polymer dielectric layer and a first metal layer formed atop the polymer dielectric layer;
depositing a polymer layer atop the substrate;
patterning the polymer layer to form a plurality of openings to a top surface of the first metal layer, wherein the plurality of openings comprises a first opening formed proximate the metal pad;
depositing a first barrier layer atop the polymer layer and within the plurality of openings formed in the polymer layer;
depositing a dielectric layer atop the first barrier layer and within the plurality of openings formed in the polymer layer;
etching the dielectric layer and the first barrier layer from within the first opening and a field region of the polymer layer;
depositing a second barrier layer atop the substrate;
depositing a second metal layer atop the substrate wherein the second metal layer fills the plurality of openings; and
etching the second metal layer from a portion of the field region of the polymer layer.
2. The method of claim 1 , wherein the substrate is one of silicon, glass, ceramic, or dielectric.
3. The method of claim 1 , wherein the metal pad is copper.
4. The method of any of claims 1 to 3, wherein at least one of the first metal layer or the second metal layer is a copper or aluminum layer.
5. The method of any of claims 1 to 3, wherein the polymer dielectric layer is polyimide or polybenzoxazole.
6. The method of any of claims 1 to 3, wherein the polymer layer is one of a polybenzoxazole (PBO) layer, a polyimide layer, a benzocyclobutene (BCB) layer, an epoxy layer, or a photo-sensitive material layer.
7. The method of any of claims 1 to 3, wherein the first barrier layer is titanium.
8. The method of any of claims 1 to 3, wherein the dielectric layer is hafnium oxide (HfO2), silicon nitride (Si3N4), or tantalum oxide (Ta2O5).
9. A method of processing a substrate, comprising:
providing a substrate having a patterned polymer dielectric layer comprising a plurality of openings;
depositing a first barrier layer atop the substrate;
depositing a dielectric layer atop the first barrier layer;
depositing a second barrier layer atop the dielectric layer; and
depositing a metal pad atop a portion of a field region of the patterned polymer dielectric layer.
10. The method of claim 9, wherein at least one of:
the substrate is one of silicon, glass, ceramic, or dielectric;
the metal pad is copper;
the patterned polymer dielectric layer is one of a polybenzoxazole (PBO) layer, a polyimide layer, a benzocyclobutene (BCB) layer, an epoxy layer, or a photo-sensitive material layer;
wherein the first barrier layer is titanium; or
the dielectric layer is one of hafnium oxide (HfO2), silicon nitride (Si3N4), tantalum oxide (Ta2Os).
1 1 . A substrate, comprising:
a polymer dielectric layer;
a metal pad filling an opening in the polymer dielectric layer; a patterned first metal layer atop the polymer dielectric layer and conductively coupled to the metal pad;
a polymer layer atop the substrate, wherein the polymer layer comprises a plurality of openings etched to a top surface of the patterned first metal layer, wherein the plurality of openings comprises a first opening formed proximate the metal pad;
a barrier layer atop the polymer layer and within the plurality of openings in the polymer layer;
a dielectric layer atop the barrier layer and within the plurality of openings in the polymer layer;
a second barrier layer atop the substrate; and
a second metal layer atop the substrate wherein the second metal layer fills the plurality of openings, and wherein the barrier layer, the dielectric layer and the second metal layer are not formed atop a portion of a field region of the substrate.
12. The substrate of claim 1 1 , wherein the polymer dielectric layer is polyimide or polybenzoxazole.
13. The substrate of claim 1 1 , wherein the polymer layer is one of a polybenzoxazole (PBO) layer, a polyimide layer, a benzocyclobutene (BCB) layer, an epoxy layer, or a photo-sensitive material layer.
14. The substrate of claim 1 1 , wherein the second metal layer is a copper or aluminum layer.
15. The substrate of claim 1 1 , wherein the dielectric layer is hafnium oxide (Hf02), silicon nitride (Si3N4), or tantalum oxide (Ta205).
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