WO2017062060A1

WO2017062060A1 - In-situ laser assisted processes in focused ion beam applications

Info

Publication number: WO2017062060A1
Application number: PCT/US2016/025223
Authority: WO
Inventors: Shida Tan; Richard H. Livengood
Original assignee: Intel Corporation
Priority date: 2015-10-07
Filing date: 2016-03-31
Publication date: 2017-04-13
Also published as: TW201724188A

Abstract

In-situ laser assisted processes in focused ion beam applications are described. In an example, a method of patterning, milling, or imaging a sample involves providing real time localized substrate heating using a pulsed focused laser beam that irradiates the sample simultaneously as the ion beam is used during the patterning, milling, or imaging. Other embodiments may be described and/or claimed.

Description

ΓΝ-SITU LASER ASSISTED PROCESSES IN FOCUSED ION BEAM

APPLICATIONS

CROSS REFERENCE TO RELATED APPLICATIONS

The present application claims priority to U.S. Provisional Patent Application No. 62/238,619, filed October 7, 2015 and titled "IN-SITU LASER ASSISTED

PROCESSES IN FOCUSED ION BEAM APPLICATIONS," the entire disclosure of which is hereby incorporated by reference.

TECHNICAL FIELD

Embodiments of the present di sclosure are in the field of semiconductor processing and, in particular, in-situ laser assisted processes in focused ion beam applications.

BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips.

Focused ion beam (FIB) induced processing is widely used for nanotechnology prototyping. Applications range from direct-write lithography and or nano-machining for graphene, plasmonics, nanoelectromechanical systems (NEMS), and semiconductor devices. FIB is also extensively used in these fields for defect isolation and metrology applications for circuit and interconnect analysis. Novel ion beams and novel processes are under constant investigation to achieve better imaging resolution and process acuity.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 schematically illustrates a system for laser-assisted focused ion beam processing, in accordance with various embodiments.

Figure 2 is a schematic illustrating a system having a laser source mounted onto a focused ion beam device (e.g., gas field ion microscope), in accordance with various embodiments. Figure 3 is a schematic illustrating another system having a laser source and a focused ion beam device, in accordance with various embodiments.

Figure 4 is a flow diagram of a method for using a laser-assisted focused ion beam process on a semiconductor device, in accordance with various embodiments.

Figure 5 includes transmission electron microscope (TEM) micrographs 500a-d from a "No Laser" experiment showing typical damage formation and implantation evolution of a helium beam in single crystalline Si substrate; TEM micrographs 500e-h from samples prepared by introduction of in-situ pulsed laser annealing; TEM images SOOi and 500j showing ion beam induced damage without and with laser assist, respectively for the regions denoted by hatched boxes in images 500c and 500d, respectively; image 500k showing selected area electron diffraction (SAED) patterns and image 5001 showing a TEM cross-section with five times higher photon/ion flux than used for image 500h, in accordance with various embodiments.

Figure 6 illustrates a plan view and corresponding cross-sectional view of a metallization structure, in accordance with an embodiment of the present disclosure.

Figure 7A illustrates a cross-sectional view of a non-planar semiconductor device having fins, in accordance with an embodiment of the present disclosure.

Figure 7B illustrates a plan view taken along the a-a' axis of the semiconductor device of Figure 7 A, in accordance with an embodiment of the present disclosure.

Figure 8 illustrates a computing device in accordance with one implementation of the disclosure.

Figure 9 illustrates a block diagram of an exemplary computer system, in accordance with an embodiment of the present disclosure.

Figure 10 illustrates an interposer implementing one or more embodiments of the disclosure.

Figure 11 illustrates a computing device built in accordance with an embodiment of the disclosure.

DESCRIPTION OF THE EMBODIMENTS

In-situ laser assisted processes in focused ion beam applications are described. In the following description, numerous specific details are set forth, such as specific tooling, integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as semiconductor device operations, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. In some cases, various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present disclosure; however, the order of description should not be construed to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

One or more embodiments described herein are directed to in-situ laser assisted processes in focused ion beam (FIB) applications. Applications may include one or more of preventing/reducing ion beam-induced damage, circuit editing, failure analysis, mask repair, focused ion beam technologies, gas field ionization sources, use of helium in semiconductor processing, in-situ laser annealing, use of light element ions (e.g., helium and/or neon), metrology, nanofabrication, use of neon in semiconductor processing, pulsed laser application, sample preparation techniques, transmission electron

microscope (TEM) sample preparation, compound semiconductor (HI through V) applications, or metal-oxide-semiconductor (MOS)/complementary MOS (CMOS) applications.

To provide context, one of the key limitations of using an ion beam for patterning, imaging, or nano-machining is the sub-surface damage caused through nuclear interaction between the primary ion beam particle and the atomic structure of the substrate being irradiated. Although this is true for all ion beams, it is particularly problematic with lighter element ions such as Helium and Neon beams, which have a much larger interaction volume compared with heavier ions traditionally used for ion machining (e.g. Gallium, Xenon, and Argon). Additionally, the lighter element ions are also prone to sub-surface trapping (e.g., similar to what occurs with ion implanters), which changes both the structural and material properties of the substrate (and potentially causes strain or deformation in the structure). Helium and neon based Gas Field Ion Source (GFIS) FIB has recently been used more extensively for patterning, imaging, and nanomachining applications traditionally performed using scanning electron microscope (SEM) or Gallium FIB respectively.

Helium and Neon demonstrate 0.5 nm to 1.5 nm resolution compared to the 3 nm offered by traditional Ga+ FIB. Although successful deposition and etching using He+ and Ne+ FIB are demonstrated with better performance compared to the Ga+ FIB, they also have a higher sub-surface damage and implantation deeper and higher in density which could negatively affect device performance.

To provide further context, substrate heating up to 120 degree Celsius (C) or greater during the ion beam induced processes has been reported to eliminate helium subsurface implantation. However, the entire sample needs to be raised to an elevated temperature. In addition, the ion beam induced defects have not been demonstrated to reduce with the heating process limited at 100+ C. Again, it is to be appreciated that, generally, use of a focused ion beam creates implantation and damages to the substrate during imaging, machining, ion beam induced deposition (IBID), and implant

applications. When applied to crystalline materials, ion species with lower atomic weight or that are gaseous in nature tend to aggregate in the form of nanoscopic bubbles. With increasing ion dose, the aggregated implant species cause the local material density change and eventually result in sample surface deformation (at >1E-18 ions/cm2).

Furthermore, 400+ degree C thermal annealing to recrystallize the substrate and remove di slocation defects is used as part of the semiconductor transistor manufacturing process. This is performed to remove defects introduced during doping implantation step. Laser usage has been implemented in-situ to volatilize organic compounds during IBID of metallo-organic compounds to improve IBID metal purity and material properties. However, neither of these state-of-the-art techniques are practical with fully processed and packaged devices due to the invasiveness of the high temperature and or the engineering limitations of heating an entire package and die substrate in a vacuum system required for FIB applications.

In accordance with one or more embodiments of the present disclosure, ion beam induced sub-surface damage is eliminated (or at least mitigated) by providing real time localized substrate heating using a focused laser beam that irradiates the sample simultaneously as the ion beam is used during a patterning, milling, or imaging application. In some embodiments, the focused laser beam may be a pulsed laser beam.

More specifically, a pulsed laser with an appropriate wavelength that matches the bandgap of the material can be used to create controllable, localized, and synchronized heating to the substrate during the ion beam induced processes. This localized and targeted heating enables the diffusion of the implanted ion species, thus eliminating deformation of the ion irradiated area. The wavelength and energy of the laser beam may be tuned to match the damage density creation rate induced by the ion beam to further anneal out the defects created in the ion beam irradiation processes. This in-situ pulsed laser process can benefit FIB systems with a range of source technologies and ion species. It is particularly beneficial to ion species with lower atomic weight or gaseous in nature, which include but not limited to source technologies such as liquid metal ion source (LMIS), gas field ionization source (GFIS), plasma source, cold atom source and ion species like The approach

is also applicable to other ion beam species under particular conditions.

In accordance with an embodiment of the present disclosure, processes described herein are in-situ and localized only to the ion irradiation area. Thus, the overall invasiveness to the sample is much less compared to the global heating process used in wafer manufacturing or other reported global heating applications. The wavelength of the laser probe can be designed to target the area of interest. The spot size of the annealing area can be limited to tens of micrometers instead of the entire sample.

The global heating process only demonstrated the effectiveness in driving out the implanted helium. In accordance with one or more embodiments described herein, in order to achieve damage density reduction, the sample needs to be heated to a higher temperature which will be damaging to the sample or the packaging of the device.

Localized annealing (heating) is less invasive to other areas of the substrate, which may otherwise cause undesired changes to material properties if heated globally. Localized heating of the substrate enables use on packaged devices, which are subject to die delamination when heated above 1 SO deg. C. In an embodiment, localized heating eliminates the risk of thermal drift of the sample during process heating ramp up and ramp down. The global heating could not be applied universally to samples with geometries not easily integrated with heaters. Localized heating enables annealing on vacuum based tools where integrating a global substrate heating solution is very costly and or is impossible.

Furthermore, the pulsed laser enables periodic delivery of energy to enable diffusion of the ions from the FIB, without increasing the steady state temperature of the region of the semiconductor device as much as a continuous-wave laser of the same power/energy. In some embodiments, the duty cycle of the pulsed laser may be 50% or less, such as less than 50%, 25% or less, or 10% or less. For example, in some embodiments, the duty cycle may be about 0.1% to about 50%. Additionally, or alternatively, the pulse width of the pulsed laser may be about 10 femtoseconds (fs) to about 100 milliseconds (ms). In one non-limiting example, the pulsed laser may have a pulse width of about 100 microseconds (μβ) and/or a duty cycle of about 1% (e.g., corresponding to a 100 Hertz frequency). During the on portion of the duty cycle, the pulsed laser may oscillate at the wavelength of the laser. During the off portion of the duty cycle, the pulsed laser may be off (e.g., may not transmit significant energy).

In various embodiments, the pulsed laser may have a power of about 1 milliwatt (mW) to about 1 Watt (W). The duty cycle, pulse length, and/or power level of the pulsed laser may be selected based on, for example, the ion species of the FIB and/or the material or materials in the region of the semiconductor device to which the pulsed laser is applied.

The pulsed laser may heat the region of the semiconductor device during the on portion (irradiation period) of the pulsed laser. For example, the pulsed laser may irradiate the region to over 100 degrees Celsius in some embodiments. In some embodiments, a silicon region irradiated with the pulsed laser may reach a temperature of over 300 degrees Celsius. The temperature of the region may reduce (e.g., exponentially) during the off portion of the pulsed laser.

In other embodiments, a continuous-wave laser may be used. The continuous- wave laser may have a lower power level than when a pulsed laser is used. For example, the continuous-wave laser may have a power of about 1 mW to about 1 W. As discussed above, the wavelength of the laser beam may be selected based on the material or materials included in the region of the semiconductor device to which the laser is applied. In some embodiments, the wavelength of the laser may be about 157 nanometers (nm) to about 1570 nm. In accordance with one or more embodiments described herein, a pulsed-laser probe is integrated to a FIB tool (e.g., Zeiss NanoFAB FIB) system. During the FIB processes involving use of light element ion (e.g., He+ or Ne+) in operation, a pulsed laser is synchronized with ion beam patterning at an appropriate power density. In an embodiment, duty cycle is introduced to mitigate the cumulative helium ion-beam damage that otherwise occurs at room temperature. The FIB tool may apply a focused ion beam to a first region of a semiconductor device. The laser probe may apply the laser beam to a second region of the semiconductor device that overlaps with the first region. In some embodiments, the second region may be larger than the first region and may include the first region. Thus, the focused laser beam may be applied to a selected portion of the semiconductor device without applying the energy to the entire

semiconductor device.

Figure 1 is a block diagram to illustrate a system 100 for laser-assisted FIB processing, in accordance with various embodiments. The system 100 includes a laser source 102 and a FIB source 104. The system 100 may further include a controller 106 coupled to the laser source 102 and/or the FIB source 104 to control the operation of the laser source 102 and/or FIB source 104. The FIB source 104 may apply an ion beam 108 to a region of a sample 110. The laser source 102 may apply a laser 112 to the region of the sample 110 at the same time that the FIB source 104 applies the ion beam 108. In some embodiments, the laser 112 may be a pulsed laser. The laser source 102 may apply the laser 112 to the sample 110 directly or indirectly (e.g., via one or more mirrors).

The controller 106 may control the timing of the application of the ion beam 108 and/or laser 112 so that they are applied to the sample 110 at the same time.

Additionally, or alternatively, the controller 106 may control one or more parameters of the laser 112, such as the duty cycle, pulse width, and/or power.

Figure 2 is a schematic illustrating a system 200 that shows one example implementation of the system 100, in accordance with various embodiments. System 200 may include a pulsed laser source 202 and a focused ion beam device 204. The focused ion beam device 204 may be an FIB microscope, such as a gas field ion microscope. The pulsed laser source 202 may or may not be physically coupled with the focused ion beam device 204. In some embodiments, the system 200 may further include a gas injection system (GIS) 206. The pulsed laser source 202 may apply a pulsed laser 208 to a region of a sample (eg., a semiconductor device) at the same time that the focused ion beam device 204 applies an ion beam 210 to the region of the sample, as further discussed herein. The sample may be disposed on a sample holder 212.

Figure 3 is a schematic illustrating another system 300 for laser-assisted focused ion beam processing, in accordance with various embodiments. System 300 may be another example implementation of the system 100. The system 300 may include a FIB device 306 and a laser source 320. The system 300 may further include a controller 306 coupled to the FIB device 306 and/or laser source 320. The controller 304 may be any suitable device, such as a microprocessor, a central processing unit (CPU), and/or a programmable controller. The laser source 320 may apply a laser (e.g., a pulsed laser) to a selected region of a semiconductor device 302 at the same time mat the FIB device 306 applies an ion beam to the selected region of the sample, as farmer discussed herein.

The system 300 may further include a chamber 310 having cover 308. An end 312 of the column 314 of the FIB device 306 may protrude through the cover 308 and extend into the chamber 310 when the cover 308 is attached to a base enclosure portion 316 ofthe chamber 310.

. In some embodiments, the light source 320 may be removably attached to a fixture 322. The fixture 322 may be coupled to a viewing port 324 mounted to the cover 308 ofthe chamber 310. Mirrors 326 and 328 may be mounted on the fixture 322. The mirrors 326 and 328 may be attached to the fixture 322 by slide rails 330 and 332 that permit^' adjustment of the mirrors 326 and 328 to focus the laser source 320 on a precise, selected location on the semiconductor device 302. Additional mirrors 334 and 336 may be mounted on the underside 338 of the cover 308. The mirrors 334 and 336 may be mounted to the cover 308 by fixtures 340 and 342 mat permit adjustment of the mirrors to coordinate with mirrors 326 and 328 to facilitate focusing the laser source 320 on the selected location on the semiconductor device 302.

While the example shown in Figure 3 uses mirrors and other reflective Optics to direct the focused laser source 320 on the precise, selected location on the semiconductor device 302 any arrangement for directing the laser source 320 on the semiconductor device 302 may be used. For example, a light pipe or fiber optic delivery system may be utilized to direct the energy, on the precise, selected location on the semiconductor device 302. The systems 200 and 300 are merely two example implementations of the system

100, and it will be apparent that other implementations of the system 100 or alternative systems may be used for the laser-assisted FIB process described herein.

Figure 4 illustrates a method 400 for laser-assisted FIB processing of a semiconductor device, in accordance with various embodiments. In some embodiments, the system 100, system 200, and/or system 300 may perform the method 400.

At 402, the method 400 may include applying a focused ion beam to a region of a semiconductor device. The focused ion beam may be applied by a focused ion beam device, such as focused ion beam device 104, 204, and/or 306.

At 404, the method 400 may include applying, simultaneously with the applying the focused ion beam, a focused laser beam to the region of the semiconductor device to heat the region. In some embodiments, the focused laser beam may be a pulsed laser. In other embodiments, the focused laser beam may be a continuous-wave laser.

In an embodiment, applications of embodiments described herein (e.g., using the system 100, system 200, system 300, and/or method 400) may include one or more of, but are not limited to: (1) implementation as part of FIB nanomachining for circuit rewiring during new product process or design debug to reduce damage induced during FIB machining process, (2) implementation as part of FIB TEM or Atom probe (3D tomography) sample prep to reduce damage induced during FIB machining process, (3) implementation as part of FIB cross section during defect isolation (failure analysis), where defect is cross-sectioned or further isolated using FIB machining, (4)

implementation as part of lithography mask defect repair, where ion beam damage and substrate deformation can change the exposure area or change the properties of the illumination, e.g., transmission, altering phase change, reflection, etc., (5)

implementation as part of FIB IBID, to reduce or eliminate sub surface damage induced by ion beam irradiation during IBID process, (6) implementation as applicable to both circuit rewiring, defect isolation, mask repair, and sample preparation, (7)

implementation as part of FIB imaging or metrology tool to reduce or eliminate damage during FIB irradiation (e.g., scanning electron (SE) imaging high resolution microscopy, ion beam induced charge microscopy (IBIC), secondary ion mass spectroscopy (SIMS), Rutherford backscattering spectrometry (RBS), etc.), (8) implementation as part of FIB direct write nano-fabrication process in nano-electro-mechanical systems (NEMS), micro-electro-mechanical systems (MEMS), plasmonic, graphene, and/or other nano-machining / prototyping applications, (9) implementation as part of direct write nano pattering of nano structures or nanolithography, or (10) implementation in device prototyping and mask writing, for example, (11) implementation in lithography mask defect repair (nanomachining and IBID) for reflected masks (e.g., EUV mask) and projection transmission masks (e.g. phase shift masks).

It has been clearly demonstrated (on a non-idealized setup) that the effectiveness of applying in-situ laser to drive out the ion implantation and ion beam induced damage in Silicon is very evident. Two sets of experiments have been conducted under identical ion beam and material conditions. Referring to Figure 5, TEM micrographs 500a-d show TEM cross-sections of 25 keV He+ exposures of varying dose (1E15 ion/cm², 1E17 ion/cm², 5E17 ion/cm², and 1E18 ion/cm², respectively) without a laser applied. The TEM micrographs 500a-d from the "No Laser" experiment showed typical damage formation and implantation evolution of a helium beam in single crystalline Si substrate. At 5E17 ion/cm² dose, the Si substrate is completely amorphized. At 1E18 ion/cm², the Si substrate was deformed.

The TEM micrographs 500e-h are shown with the introduction of in-situ pulsed laser annealing as described herein. The pulsed laser used for the TEM micrographs 500e-h applied a 1.3E6 photon/ion flux. As shown, the ion beam induced crystalline structure damage is partially annealed and the implanted helium was driven out effectively.

TEM image 500i shows ion beam induced damage without laser assist for the region denoted by the hatched box in image 500c for a He+ dose of 5E17 ions/cm². TEM image 500j shows ion beam induced damage with laser assist for the region denoted by the hatched box in image 500g for a He+ dose of 5E17 ions/cm². Image 500k shows selected area electron diffraction (SAED) patterns and image 5001 shows a TEM cross- section of an exposure of 1E18 He+ ions/cm² with five times higher photon/ion flux (e.g., 6.6E6 photon/ion) than used for image 500h. The dashed circles in image 5001 show where SAED was conducted.

In an embodiment, applications herein enable use of novel light element ion beam techniques, which has higher resolution, nanomachining precision, nano-patterning precision than the current Ga+ FIB and SEM. Approaches described herein can be applied to enable scaling for applications ranging from Metrology, failure analysis (FA), fault isolation (FI), material analysis (MA), low yield analysis (LYA), circuit edit, and mask repair. Without implementations of embodiments described herein, the effective operating window of the He+, Ne+, and other new light element ion beam will be limited.

More generally, referring to all of the above-described aspects of embodiments of the present disclosure, an in-situ laser assisted process for a focused ion beam application may be implemented during fabrication of a metallization layer in a semiconductor device. It is to be appreciated that a metallization layer having lines with line cuts (or plugs) and having associated vias may be fabricated above a substrate and, in one embodiment, may be fabricated above a previous metallization layer. As an example, Figure 6 illustrates a plan view and corresponding cross-sectional view of a previous layer metallization structure, in accordance with an embodiment of the present disclosure. Referring to Figure 6, a starting structure 1200 includes a pattern of metal lines 1202 and interlayer dielectric (ILD) lines 1204. The starting structure 1200 may be patterned in a grating-like pattern with metal lines spaced at a constant pitch and having a constant width, as is depicted in Figure 6. Although not shown, the lines 1202 may have interruptions (i.e., cuts or plugs) at various locations along the lines. The pattern, for example, may be fabricated by a pitch halving or pitch quartering approach. Some of the lines may be associated with underlying vias, such as line 1202' shown as an example in the cross-sectional view.

In an embodiment, fabrication of a metallization layer on the previous

metallization structure of Figure 6 begins with formation of an interlayer dielectric (ILD) material above the structure 1200. A hardmask material layer may then be formed on the ILD layer. The hardmask material layer may be patterned to form a grating of unidirectional lines orthogonal to the lines 1202 of 1200. In one embodiment, the grating of unidirectional hardmask lines is fabricated using conventional lithography (e.g., photoresist and other associated layers) and may have a line density defined by a pitch- halving, pitch-quartering etc. approach as described above. The grating of hardmask lines leaves exposed a grating region of the underlying ILD layer. It is these exposed portions of the ILD layer that are ultimately patterned for metal line formation, via formation, and plug formation. For example, in an embodiment, via locations are patterned in regions of the exposed ILD. The patterning may involve formation of a resist layer and patterning of the resist layer to provide via opening locations which may be etched into the ILD regions.

The lines of overlying hardmask can be used to confine the vias to only regions of the exposed ILD, with overlap accommodated by the hardmask lines which can effectively be used as an etch stop. Plug (or cut) locations may also be patterned in exposed regions of the ILD, as confined by the overlying hardmask lines, in a separate processing operation. The fabrication of cuts or plugs effectively preserves regions of ILD that will ultimately interrupt metal lines fabricated therein.

Metal lines may then be fabricated using a damascene approach, in which exposed portions of the ILD (those portions between the hardmask lines and not protected by a plug preservation layer, such as a resist layer patterned during "cutting") are partially recessed. The recessing may further extend the via locations to open metal lines from the underlying metallization structure. The partially recessed ILD regions are then filled with metal (a process which may also involve filling the via locations), e.g., by plating and CMP processing, to provide metal lines between the overlying hardmask lines. The hardmask lines may ultimately be removed for completion of a metallization structure. It is to be appreciated that the above ordering of line cuts, via formation, and ultimate line formation is provided only as an example.

In an embodiment, as used throughout the present description, interlayer dielectric (ILD) material is composed of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (Si0₂)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (C VD), physical vapor deposition (PVD), or by other deposition methods.

In an embodiment, as is also used throughout the present description, interconnect material is composed of one or more metal or other conductive structures. A common example is the use of copper lines and structures that may or may not include barrier layers between the copper and surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnect lines may include barrier layers, stacks of different metals or alloys, etc. The interconnect lines are also sometimes referred to in the arts as traces, wires, lines, metal, or simply interconnect.

In an embodiment, as is also used throughout the present description, hardmask materials are composed of dielectric materials different from the interlayer dielectric material. In some embodiments, a hardmask layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, a hardmask material includes a metal species. For example, a hardmask or other overlying material may include a layer of a nitride of titanium or another metal (e.g., titanium nitride). Potentially lesser amounts of other materials, such as oxygen, may be included in one or more of these layers. Alternatively, other hardmask layers known in the arts may be used depending upon the particular implementation. The hardmask layers maybe formed by CVD, PVD, or by other deposition methods.

In various embodiments, the in-situ laser assisted FIB process described herein may be used for one or more aspects associated with the metallization structure of Figure 6. For example, the in-situ laser assisted FIB process may be used to pattern, edit or correct defects in the hardmask layer and/or other layers, and/or for imaging.

It is to be appreciated that the layers and materials described in association with Figure 6 are typically formed on or above an underlying semiconductor substrate or structure, such as underlying device layer(s) of an integrated circuit. In an embodiment, an underlying semiconductor substrate represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The semiconductor substrate, depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, the structure depicted in Figure 3 may be fabricated on underlying lower level interconnect layers.

Implementations of embodiments of the disclosure may be formed or carried out on a substrate, such as a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure.

A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the disclosure, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all- around gate transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only planar transistors, it should be noted that the disclosure may also be carried out using nonplanar transistors.

In various embodiments, the MOS transistors may include a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (SiO₂) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-rype workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

In some implementations, the gate electrode may consist of a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack. As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an

etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

One or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (S1O₂), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

In various embodiments, an in-situ laser assisted process for a focused ion beam application is implemented during fabrication of semiconductor devices, such as PMOS or NMOS devices of an integrated circuit. For example, the in-situ laser-assisted FIB process may be used for failure analysis, fault isolation, low yield analysis, circuit editing, metrology, material analysis, mask repair, and/or imaging of the integrated circuit. As an example of a completed device, Figures 7 A and 7B illustrate a cross- sectional view and a plan view (taken along the a-a' axis of the cross-sectional view), respectively, of a non-planar semiconductor device having a plurality of fins, in accordance with an embodiment of the present disclosure.

Referring to Figure 7 A, a semiconductor structure or device 1300 includes a non- planar active region (e.g., a fin structure including protruding fin portion 1304 and sub- fin region 1305) formed from substrate 1302, and within isolation region 1306. A gate line 1308 is disposed over the protruding portions 1304 of the non-planar active region as well as over a portion of the isolation region 1306. As shown, gate line 1308 includes a gate electrode 1350 and a gate dielectric layer 1352. In one embodiment, gate line 1308 may also include a dielectric cap layer 1354. A gate contact 1314, and overlying gate contact via 1316 are also seen from this perspective, along with an overlying metal interconnect 1360, all of which are disposed in inter-layer dielectric stacks or layers 1370. Also seen from the perspective of Figure 7A, the gate contact 1314 is, in one embodiment, disposed over isolation region 1306, but not over the non-planar active regions.

Referring to Figure 7B, the gate line 1308 is shown as disposed over the protruding fin portions 1304. Source and drain regions 1304A and 1304B of the protruding fin portions 1304 can be seen from this perspective. In one embodiment, the source and drain regions 1304A and 1304B are doped portions of original material of the protruding fin portions 1304. In another embodiment, the material of the protruding fin portions 1304 is removed and replaced with another semiconductor material, e.g., by epitaxial deposition. In either case, the source and drain regions 1304 A and 1304B may extend below the height of dielectric layer 1306, i.e., into the sub-fin region 1305.

In an embodiment, the semiconductor structure or device 1300 is a non-planar device such as, but not limited to, a fin-FET or a tri-gate device. In such an embodiment, a corresponding semiconducting channel region is composed of or is formed in a three- dimensional body. In one such embodiment, the gate electrode stacks of gate lines 1308 surround at least a top surface and a pair of sidewalls of the three-dimensional body.

In various embodiments, the in-situ laser-assisted FIB process described herein may be used for one or more aspects associated with the device 1300 of Figures 7A-B. For example, the in-situ laser-assisted FIB process may be used to image device 1300, to machine large access holes through the substrate to provide access to device 1300, to pattern one or more layers of device 1300, to cut transistors or interconnect layers, to trim transistor devices or inter-connect layers, to perform direct-write ion implantation to alter device properties, reconnect signal routing metal layers, to correct defects in one or more layers of device through removing or adding materials, to fabricating MIS or MIM capacitor to connect to device, to build a resistor to connect in series with device 1300, to fabricate a mechanical probe pad coupled with device 1300, to connect spare circuitry (sometimes referred to as bonus gates), or to machine image access holes to device 1300 to enable optical or electron beam base probing, etc.

Embodiments disclosed herein may be used to manufacture a wide variety of different types of integrated circuits and/or microelectronic devices. Examples of such integrated circuits include, but are not limited to, processors, chipset components, graphics processors, digital signal processors, micro-controllers, and the like. In other embodiments, semiconductor memory may be manufactured. Moreover, the integrated circuits or other microelectronic devices may be used in a wide variety of electronic devices known in the arts. For example, in computer systems (e.g., desktop, laptop, server), cellular phones, personal electronics, etc. The integrated circuits may be coupled with a bus and other components in the systems. For example, a processor may be coupled by one or more buses to a memory, a chipset, etc. Each of the processor, the memory, and the chipset, may potentially be manufactured using the approaches disclosed herein.

Figure 8 illustrates a computing device 1400 in accordance with one

implementation of the disclosure. The computing device 1400 houses a board 1402. The board 1402 may include a number of components, including but not limited to a processor 1404 and at least one communication chip 1406. The processor 1404 is physically and electrically coupled to the board 1402. In some implementations the at least one communication chip 1406 is also physically and electrically coupled to the board 1402. In further implementations, the communication chip 1406 is part of the processor 1404.

Depending on its applications, computing device 1400 may include other components that may or may not be physically and electrically coupled to the board 1402. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 1406 enables wireless communications for the transfer of data to and from the computing device 1400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1406 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 1400 may include a plurality of communication chips 1406. For instance, a first communication chip 1406 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1406 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1404 of the computing device 1400 includes an integrated circuit die packaged within the processor 1404. In some implementations of the disclosure, the integrated circuit die of the processor includes one or more structures fabricated using an in-situ laser assisted process for a focused ion beam application, in accordance with implementations of embodiments of the disclosure. In some embodiments, the in-situ laser assisted FIB process may be performed on the processor 1404 in package form (e.g., for circuit editing, imaging, etc.). The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The communication chip 1406 also includes an integrated circuit die packaged within the communication chip 1406. In accordance with another implementation of embodiments of the disclosure, the integrated circuit die of the communication chip includes one or more structures fabricated using an in-situ laser assisted process for a focused ion beam application, in accordance with implementations of embodiments of the disclosure. In some embodiments, the in-situ laser assisted FIB process may be performed on the communication chip 1406 in package form (e.g., for circuit editing, imaging, etc.).

In further implementations, another component housed within the computing device 1400 may contain an integrated circuit die that includes one or more structures fabricated using an in-situ laser assisted process for a focused ion beam application, in accordance with implementations of embodiments of the disclosure.

In various implementations, the computing device 1400 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 1400 may be any other electronic device that processes data.

Embodiments of the present disclosure may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process (e.g., method 400) according to embodiments of the present disclosure. In one embodiment, the computer system is coupled with a system having a pulsed laser delivery system mounted onto a gas field ion microscope such as described in association with Figures 1, 2, and/or 3. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium (e.g., read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium (electrical, optical, acoustical or other form of propagated signals (e.g., infrared signals, digital signals, etc.)), etc. Figure 9 illustrates a diagrammatic representation of a machine in the exemplary form of a computer system 1500 within which a set of instructions, for causing the machine to perform any one or more of the methodologies described herein (e.g., method 400), may be executed. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a Local Area Network (LAN), an intranet, an extranet, or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines (e.g., computers) that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies described herein.

The exemplary computer system 1500 includes a processor 1502, a main memory

1504 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1506 (e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory 1518 (e.g., a data storage device), which communicate with each other via a bus 1530.

Processor 1502 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processor 1502 may be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, processor implementing other instruction sets, or processors

implementing a combination of instruction sets. Processor 1502 may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. Processor 1502 is configured to execute the processing logic 1526 for performing the operations described herein. The computer system 1500 may further include a network interface device 1508.

The computer system 1500 also may include a video display unit 1510 (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 1512 (e.g., a keyboard), a cursor control device 1514 (e.g., a mouse), and a signal generation device 1516 (e.g., a speaker).

The secondary memory 1518 may include a machine-accessible storage medium

(or more specifically a computer-readable storage medium) 1532 on which is stored one or more sets of instructions (e.g., software 1522) embodying any one or more of the methodologies or functions described herein. The software 1522 may also reside, completely or at least partially, within the main memory 1504 and/or within the processor 1502 during execution thereof by the computer system 1500, the main memory 1504 and the processor 1502 also constituting machine-readable storage media. The software 1522 may further be transmitted or received over a network 1520 via the network interface device 1508.

While the machine-accessible storage medium 1532 is shown in an exemplary embodiment to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media.

Figure 10 illustrates an interposer 1600 that be manufactured and/or processed in accordance with one or more embodiments of the laser-assisted FIB process described herein. The interposer 1600 is an intervening substrate used to bridge a first substrate 1602 to a second substrate 1604. The first substrate 1602 may be, for instance, an integrated circuit die. The second substrate 1604 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 1600 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 1600 may couple an integrated circuit die to a ball grid array (BGA) 1606 that can subsequently be coupled to the second substrate 1604. In some embodiments, the first and second substrates 1602/1604 are attached to opposing sides of the interposer 1600. In other embodiments, the first and second substrates 1602/1604 are attached to the same side of the interposer 1600. And in further embodiments, three or more substrates are interconnected by way of the interposer 1600.

The interposer 1600 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group ΙΠ-V and group IV materials.

The interposer may include metal interconnects 1608 and vias 1610, including but not limited to through-silicon vias (TSVs) 1612. The interposer 1600 may further include embedded devices 1614, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1600.

The laser-assisted FIB process described herein may be used in one or more aspects of the fabrication and/or imaging of the interposer 1600. For example, the in-situ laser-assisted FIB process may be used to image interposer 1600, to machine access holes, to pattern one or more layers of interposer 1600, to cut transistor or interconnect layers, to trim transistor devices or interconnect layers, to perform direct-write ion implantation to alter device properties, to reconnect signal routing metal layers, to correct defects in one or more layers of the interposer 1600 through removing or adding materials, or to machine image access holes to interposer 1600 to enable optical or electron beam base probing, etc.

Figure 11 illustrates a computing device 1700 in accordance with one

embodiment of the disclosure. The computing device 1700 may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, these components are fabricated onto a single system-on-a-chip (SoC) die rather than a motherboard. The components in the computing device 1700 include, but are not limited to, an integrated circuit die 1702 and at least one communication chip 1708. In some implementations the communication chip 1708 is fabricated as part of the integrated circuit die 1702. The integrated circuit die 1702 may include a CPU 1704 as well as on-die memory 1706, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STTM-RAM).

Computing device 1700 may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory 1710 (e.g., DRAM), non-volatile memory 1712 (e.g., ROM or flash memory), a graphics processing unit 1714 (GPU), a digital signal processor 1716, a crypto processor 1742 (a specialized processor that executes cryptographic algorithms within hardware), a chipset 1720, an antenna 1722, a display or a touchscreen display 1724, a touchscreen controller 1726, a battery 1729 or other power source, a power amplifier (not shown), a global positioning system (GPS) device 1728, a compass 1730, a motion coprocessor or sensors 1732 (that may include an accelerometer, a gyroscope, and a compass), a speaker 1734, a camera 1736, user input devices 1738 (such as a keyboard, mouse, stylus, and touchpad), and a mass storage device 1740 (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communications chip 1708 enables wireless communications for the transfer of data to and from the computing device 1700. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1708 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 1700 may include a plurality of communication chips 1708. For instance, a first communication chip 1708 may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 1708 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

In various embodiments, the processor 1704 of the computing device 1700 may include one or more structures fabricated using an in-situ laser assisted process for a focused ion beam application, in accordance with implementations of embodiments of the disclosure. In some embodiments, the laser-assisted FIB process may be performed on the processor 1704 when in the form of an integrated circuit package (e.g., for circuit editing and/or imaging). The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip 1708 may additionally or alternatively include one or more structures fabricated using an in-situ laser assisted process for a focused ion beam application, in accordance with implementations of embodiments of the disclosure. In some embodiments, the laser-assisted FIB process may be performed on the

communication chip 1708 when in the form of an integrated circuit package (e.g., for circuit editing and/or imaging).

In further embodiments, another component housed within the computing device 1700 may contain one or more structures fabricated using an in-situ laser assisted process for a focused ion beam application, in accordance with implementations of embodiments of the disclosure.

In various embodiments, the computing device 1700 may be a laptop computer, a netbook computer, a notebook computer, an ultrabook computer, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 1700 may be any other electronic device that processes data.

Some non-limiting Examples of various embodiments are presented below.

Example 1 is a method for laser-assisted focused ion beam processing, the method comprising: applying a focused ion beam to a region of a semiconductor device; and applying, simultaneously with the applying the focused ion beam, a focused laser beam to the region of the semiconductor device to heat the region.

Example 2 is the method of Example 1, wherein the focused laser beam is a pulsed laser beam.

Example 3 is the method of Example 2, wherein the pulsed laser beam has a duty cycle that is 0.1% to 50%.

Example 4 is the method of Example 1, wherein a wavelength of the focused laser beam is 157 nm to 1570 nm.

Example 5 is the method of Example 1, wherein the region includes a mask and wherein the applying the focused ion beam includes repairing a defect in the mask.

Example 6 is the method of Example 1, wherein the semiconductor device is an integrated circuit package.

Example 7 is the method of Example 6, wherein the applying the focused ion beam is to edit a circuit of the integrated circuit package.

Example 8 is the method of Example 1, wherein the applying the focused ion beam is performed as part of a defect analysis process, a defect repair process, a prototyping process, or an imaging process.

Example 9 is the method of any one of Examples 1 to 8, wherein the focused ion beam includes ions and wherein the applying the focused laser beam is to cause the ions to diffuse in the region and prevent defects.

Example 10 is the method of any one of Examples 1 to 8, wherein the focused ion beam includes

Example 11 is a system for laser-assisted focused ion beam processing, the system comprising: a focused ion beam device to apply a focused ion beam to a first region of an semiconductor device; and a focused laser source to apply, simultaneously with the applied focused ion beam, a focused laser beam to a second region of the semiconductor device to heat the second region, wherein the second region overlaps with the first region.

Example 12 is the system of Example 11 , wherein the focused laser beam is a pulsed laser beam.

Example 13 is the system of Example 12, wherein the pulsed laser beam has a duty cycle that is 0.1% to 50%. Example 14 is the system of Example 11, wherein the region includes a mask and wherein the applied the focused ion beam is to repair a defect in the mask.

Example 15 is the system of Example 11, wherein the semiconductor device is an integrated circuit package.

Example 16 is the system of Example 11, wherein the applied focused ion beam is to analyze a defect in the semiconductor device, repair a defect in the semiconductor device, or image the semiconductor device.

Example 17 is the system of any one of Examples 11 to 16, wherein the focused ion beam includes ions and wherein the applied focused laser beam is to cause the ions to diffuse and prevent defects.

Example 18 is the system of any one of Examples 11 to 16, wherein the focused ion beam includes

Example 19 is a circuit fabrication method comprising: providing an integrated circuit device; applying a focused ion beam to a region of the integrated circuit device; and applying, simultaneously with the applying the focused ion beam, a pulsed focused laser beam to the region of the integrated circuit device to heat the region, wherein the pulsed focused laser beam has a duty cycle that is 50% or less.

Example 20 is the method of Example 19, wherein a wavelength of the pulsed focused laser beam is 157 nanometers (nm) to 1570 nm.

Example 21 is the method of Example 19, wherein the region includes a mask and wherein the applying the focused ion beam includes repairing a defect in the mask.

Example 22 is the method of Example 19, wherein the region is a first region, and wherein the pulsed focused laser beam is applied to a second region of the integrated circuit device that includes the first region.

Example 23 is the method of any one of Examples 19 to 22, wherein the integrated circuit device is an integrated circuit package.

The above description of illustrated implementations of embodiments of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms described. While specific implementations of, and examples for, the disclosed embodiments are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the present disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosed embodiments in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosed embodiments to the specific implementations disclosed in the specification and the claims. Rather, the scope of the claimed embodiments is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

Claims

CLAIMS What is claimed is:

1. A method for laser-assisted focused ion beam processing, the method comprising:

applying a focused ion beam to a region of a semiconductor device; and applying, simultaneously with the applying the focused ion beam, a focused laser beam to the region of the semiconductor device to heat the region.

2. The method of claim 1, wherein the focused laser beam is a pulsed laser beam.

3. The method of claim 2, wherein the pulsed laser beam has a duty cycle that is 0.1% to 50%.

4. The method of claim 1 , wherein a wavelength of the focused laser beam is

157 nm to 1570 nm.

5. The method of claim 1, wherein the region includes a mask and wherein the applying the focused ion beam includes repairing a defect in the mask.

6. The method of claim 1, wherein the semiconductor device is an integrated circuit package.

7. The method of claim 6, wherein the applying the focused ion beam is to edit a circuit of the integrated circuit package.

8. The method of claim 1, wherein the applying the focused ion beam is performed as part of a defect analysis process, a defect repair process, a prototyping process, or an imaging process.

9. The method of any one of claims 1 to 8, wherein the focused ion beam includes ions and wherein the applying the focused laser beam is to cause the ions to diffuse in the region and prevent defects.

10. The method of any one of claims 1 to 8, wherein the focused ion beam includes

11. A system for laser-assisted focused ion beam processing, the system comprising:

a focused ion beam device to apply a focused ion beam to a first region of an semiconductor device; and

a focused laser source to apply, simultaneously with the applied focused ion beam, a focused laser beam to a second region of the semiconductor device to heat the second region, wherein the second region overlaps with the first region.

12. The system of claim 11, wherein the focused laser beam is a pulsed laser beam.

13. The system of claim 12, wherein the pulsed laser beam has a duty cycle that is 0.1% to 50%.

14. The system of claim 1 1, wherein the region includes a mask and wherein the applied the focused ion beam is to repair a defect in the mask.

15. The system of claim 11, wherein the semiconductor device is an integrated circuit package.

16. The system of claim 11, wherein the applied focused ion beam is to analyze a defect in the semiconductor device, repair a defect in the semiconductor device, or image the semiconductor device.

17. The system of any one of claims 11 to 16, wherein the focused ion beam includes ions and wherein the applied focused laser beam is to cause the ions to diffuse and prevent defects.

18. The system of any one of claims 11 to 16, wherein the focused ion beam includes

19. A circuit fabrication method comprising:

providing an integrated circuit device;

applying a focused ion beam to a region of the integrated circuit device; and

applying, simultaneously with the applying the focused ion beam, a pulsed focused laser beam to the region of the integrated circuit device to heat the region, wherein the pulsed focused laser beam has a duty cycle that is 50% or less.

20. The method of claim 19, wherein a wavelength of the pulsed focused laser beam is 157 nanometers (nm) to 1570 nm.

21. The method of claim 19, wherein the region includes a mask and wherein the applying the focused ion beam includes repairing a defect in the mask.

22. The method of claim 19, wherein the region is a first region, and wherein the pulsed focused laser beam is applied to a second region of the integrated circuit device that includes the first region.

23. The method of any one of claims 19 to 22, wherein the integrated circuit device is an integrated circuit package.