WO2017039583A1 - Use of sacrificial material to compensate for thickness variation in microelectronic substrates - Google Patents
Use of sacrificial material to compensate for thickness variation in microelectronic substrates Download PDFInfo
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- WO2017039583A1 WO2017039583A1 PCT/US2015/047440 US2015047440W WO2017039583A1 WO 2017039583 A1 WO2017039583 A1 WO 2017039583A1 US 2015047440 W US2015047440 W US 2015047440W WO 2017039583 A1 WO2017039583 A1 WO 2017039583A1
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- sacrificial material
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W99/00—Subject matter not provided for in other groups of this subclass
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
- H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
- H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/69—Insulating materials thereof
- H10W70/695—Organic materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/0711—Apparatus therefor
- H10W72/07178—Means for aligning
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07202—Connecting or disconnecting of bump connectors using auxiliary members
- H10W72/07204—Connecting or disconnecting of bump connectors using auxiliary members using temporary auxiliary members, e.g. sacrificial coatings
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
- H10W72/07202—Connecting or disconnecting of bump connectors using auxiliary members
- H10W72/07204—Connecting or disconnecting of bump connectors using auxiliary members using temporary auxiliary members, e.g. sacrificial coatings
- H10W72/07207—Temporary substrates, e.g. removable substrates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
- H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/321—Structures or relative sizes of die-attach connectors
- H10W72/325—Die-attach connectors having a filler embedded in a matrix
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
- H10W72/351—Materials of die-attach connectors
- H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
- H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Definitions
- Example 24 the subject matter of Example 19 can optionally include attaching an additional microelectronic device to the microelectronic substrate front surface.
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- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
A microelectronic package may be fabricated by forming a microelectronic substrate having a front surface and a back surface, transferring thickness variation in the microelectronic substrate to the microelectronic substrate back surface by attaching the microelectronic substrate front surface to a first fixture, forming a sacrificial material over the microelectronic substrate back surface having a first surface opposing the microelectronic substrate back surface, removing the microelectronic substrate from the first substrate, attaching the sacrificial material first surface to a second fixture, and attaching at least one microelectronic device to the microelectronic substrate front surface. In another embodiment, a releasing layer may be disposed between the microelectronic substrate back surface and the sacrificial material.
Description
USE OF SACRIFICIAL MATERIAL TO COMPENSATE FOR THICKNESS VARIATION IN MICROELECTRONIC SUBSTRATES
TECHNICAL FIELD
Embodiments of the present description generally relate to the field of fabricating microelectronic packages, and, more particularly, using a sacrificial material to compensation for thickness variation in a microelectronic substrate during the attachment of microelectronic devices thereto.
BACKGROUND
The microelectronic industry is continually striving to produce ever faster and smaller microelectronic packages for use in various electronic products, including, but not limited to, computer server products and portable products, such as portable computers, electronic tablets, cellular phones, digital cameras, and the like. As these goals are achieved, the fabrication of the microelectronic packages becomes more challenging. Some of the challenges may relate to thickness variations in microelectronic substrates used in the fabrication of the microelectronic packages. These thickness variations may result in difficulties in attaching microelectronic devices to the microelectronic substrate. Therefore, it is important to develop new processes to mitigate these microelectronic substrate thickness variations.
BRIEF DESCRIPTION OF THE DRAWINGS
The subject matter of the present disclosure is particularly pointed out and distinctly claimed in the concluding portion of the specification. The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. It is understood that the accompanying drawings depict only several embodiments in accordance with the present disclosure and are, therefore, not to be considered limiting of its scope. The disclosure will be described with additional specificity and detail through use of the accompanying drawings, such that the advantages of the present disclosure can be more readily ascertained, in which:
FIG. 1 illustrates a cross-sectional view of the attachment of a microelectronic device to a microelectronic substrate, as known in the art.
FIGs. 2-6 illustrate cross-sectional views of a process of fabricating a microelectronic package, according to an embodiment of the present description.
FIG. 7 is a flow chart of a process of fabricating a microelectronic package, according to the embodiment described in FIGs. 2-6 of the present description.
FIGs. 8-11 illustrate cross-sectional views of various processes of forming a sacrificial
material, according to embodiments of the present description.
FIGs. 12-15 illustrate cross-sectional views of a process of fabricating a microelectronic package, according to another embodiment of the present description.
FIG. 16 is a flow chart of a process of fabricating a microelectronic package, according to the embodiment describe in FIGs. 12-16 of the present description.
FIG. 17 illustrates an alternate size fabrication of a sacrificial material, according to an embodiment of the present description.
FIG. 18 illustrates a computing device in accordance with one implementation of the present description.
DESCRIPTION OF EMBODIMENTS
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter. References within this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present description. Therefore, the use of the phrase "one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled. In the drawings, like numerals refer to the same or similar elements or functionality throughout the several views, and that elements depicted therein are not necessarily to scale with one another, rather individual elements may be enlarged or reduced in order to more easily comprehend the elements in the context of the present description.
The terms "over", "to", "between" and "on" as used herein may refer to a relative position of one layer with respect to other layers. One layer "over" or "on" another layer or bonded "to" another layer may be directly in contact with the other layer or may have one or more
intervening layers. One layer "between" layers may be directly in contact with the layers or may have one or more intervening layers.
In the production of microelectronic packages, microelectronic devices are generally mounted on microelectronic substrates, such as interposers, which provide electrical
communication routes between the microelectronic devices within the microelectronic package and/or with external components. As shown in FIG. 1, a back surface 114 of a microelectronic substrate 110 may be adhered to a first surface 122 of a first fixture 120, such as a vacuum pedestal (shown) wherein a suction force through vias 124 therein holds the microelectronic substrate 110 in place. As will be understood to those skilled in the art, the adherence of the microelectronic substrate back surface 114 to the first fixture first surface 122 flattens the microelectronic substrate back surface 114 to the first fixture first surface 122, thereby transferring any thickness variations (shown generically as element Tv) to an opposing microelectronic substrate front surface 112, thereby making it uneven or non-planar. Therefore, when attachment structures 130, such as solder balls (shown), are attached to bond pads 118 on the microelectronic substrate front surface 112, the attachment structures 130 may have varying heights (shown generically as element Hv). As shown in FIG. 1, the height variation Hv may result in the attachment structures 130 not properly contacting corresponding bond pads 144 on an active surface 142 of a microelectronic device 140 during the attachment of the
microelectronic device 140 to the microelectronic substrate 110, such as by thermo compression bonding. This improper contact may result in defects, such as non-contact opens 132, as will be understood to those skilled in the art.
Embodiments of the present description include methods of mitigating thickness variation within a microelectronic substrate through the use of a sacrificial material during the attachment of microelectronic devices to the microelectronic substrate. In one embodiment, a
microelectronic package may be fabricated by forming a microelectronic substrate having a front surface and a back surface, transferring thickness variation in the microelectronic substrate to the microelectronic substrate back surface by attaching the microelectronic substrate front surface to a first fixture, forming a sacrificial material over the microelectronic substrate back surface having a first surface opposing the microelectronic substrate back surface, removing the microelectronic substrate from the first substrate, attaching the sacrificial material first surface to a second fixture, and attaching at least one microelectronic device to the microelectronic substrate front surface. In another embodiment, a releasing layer may be disposed between the microelectronic substrate back surface and the sacrificial material.
FIGs. 2-6 illustrate one embodiment of fabricating a microelectronic package utilizing a
sacrificial material. As shown in FIG. 2, the microelectronic substrate front surface 112 may be adhered to the first fixture first surface 122. Although the first fixture 120 is illustrated as a vacuum pedestal, it is not so limited. The first fixture 120 may be any appropriate structure and the microelectronic substrate front surface 112 may be adhered thereto with an adhesive (not shown). The adherence of the microelectronic substrate front surface 112 to the first fixture first surface 122 flattens the microelectronic substrate front surface 112 to the first fixture first surface 122, thereby transferring any thickness variations Tv to the microelectronic substrate back surface 114, thereby making it uneven or non-planar. It is noted that additional microelectronic devices 135, such as capacitors or the like, may be attached to the
microelectronic substrate back surface 114.
The microelectronic substrate 110 may be composed of a plurality of dielectric layers (not shown) and conductive routes (not shown) formed through and on the dielectric layers. The dielectric layers may be made of any appropriate materials, including, but not limited to, liquid crystal polymer, epoxy resin, bismaleimine triazine resin, polybenzoxazole, polyimide material, silica-filled epoxy, and the like. The conductive routes may be made of any appropriate conductive material, including, but not limited to, copper, gold, silver, nickel, aluminum, and the like. The conductive routes may provide electrical communication routes between various components that may be attached to the microelectronic substrate 110, as will be understood to those skilled in the art. The microelectronic substrate bond pads 118 may be in electrical communication with the conductive routes.
As shown in FIG. 3, a sacrificial material 150 may be formed over the microelectronic substrate back surface 114. The sacrificial material 150 may have a first surface 152 opposing the microelectronic substrate back surface 114, wherein the sacrificial material first surface 152 may be substantially planar to the first fixture first surface 122. The sacrificial material 150 may be any appropriate material, including but not limited to photoresist materials, low viscosity polymers, and inorganic material pastes. In one embodiment, the sacrificial material 150 may be a dielectric material.
As shown in FIG. 4, the microelectronic substrate 110 may be removed from the first fixture 120 (see FIG. 3) and sent to further substrate processing, including but not limited to, formation of the attachment structures 130, singulation, visual inspection, and the like. The specific components and operations of these processes are well known in the art and for the sake of brevity and conciseness will not be discussed or illustrated herein.
The attachment structures 130 can be made of any appropriate material, including, but not limited to, solders materials. The solder materials may be any appropriate material, including
but not limited to, lead/tin alloys, such as 63% tin / 37% lead solder, or lead-free solders, such a pure tin or high tin content alloys (e.g. 90% or more tin), such as tin/bismuth, eutectic tin/silver, ternary tin/silver/copper, eutectic tin/copper, and similar alloys.
As shown in FIG. 5, the sacrificial material first surface 152 may then be attached to a first surface 162 of a second fixture 160, wherein the microelectronic device 140 may attached by the corresponding microelectronic device bond pads 144 to the attachment structure 130, such as by thermo compression bonding. It is understood that the second fixture 160 may be the same fixture as first fixture 120. As the sacrificial material first surface 152 contacts the second fixture first surface 162, substantially no thickness variations in the microelectronic substrate 110 are transferred to the microelectronic substrate front surface 112. Thus, the attachment structures 130 may have substantially the same height H; such that proper contact is made between each attachment structure 130 and its corresponding microelectronic device bond pad 144. As further shown in FIG. 5, further additional microelectronic devices 145 may attached to the microelectronic substrate front surface 112.
The microelectronic device 140 may be any appropriate microelectronic device including, but not limited to a microprocessor, a chipset, a graphics device, a wireless device, a memory device, an application specific integrated circuit, and the like. The microelectronic device bond pads 144 may be in electrical communication with integrated circuitry (not shown) within the microelectronic device 140.
As shown in FIG. 6, the microelectronic substrate 110 may be removed from the second fixture 160, wherein further processing, such as disposing an underfill material 170 between the microelectronic device 140 and the microelectronic substrate 110, may be performed, and wherein the sacrificial material 150 (see FIG. 5) may be removed to form a microelectronic package 100. The underfill material 170 may be used to increase structural stability and prevent potential contaminants from affecting the attachment structures 130, and may be any appropriate material, including, but not limited to, epoxy materials. The process used to remove the sacrificial material 150 may depend on what material is used to form the sacrificial material 150; however, such removal processes may include, but are not limited to, wet etching, dry etching, and the like.
FIG. 7 is a flow chart of a process 200 of fabricating a microelectronic package according to an embodiment of the present description, such as illustrated in FIGs. 3-6. As set forth in block 202, a microelectronic substrate may be formed having a front surface and a back surface. The microelectronic substrate front surface may be attached to a first fixture, as set forth in block 204. As set forth in block 206, a sacrificial material may be formed over the microelectronic
substrate back surface, wherein the sacrificial material has a first surface opposing the microelectronic substrate back surface. The microelectronic substrate may be removed from the first fixture, as set forth in block 208. As set forth in block 210, the sacrificial material first surface may be attached to a second fixture. At least one microelectronic device may be attached to the microelectronic substrate front surface, as set forth in block 212. The sacrificial material may be removed, as set forth in block 214.
FIGs. 8-11 illustrate processes for forming the sacrificial material 150. As shown in FIG. 8, the sacrificial material 150 may be molded, wherein a mold chase 180 may be placed over the microelectronic substrate 110 and the sacrificial material 150 may be injected into the mold chase 180 through a mold chase opening 182. As shown in FIG. 9, the sacrificial material 150 may be deposited over the microelectronic substrate 110 with a slit coater 184. As shown in FIG. 10, the sacrificial material 150 may be laminated on the microelectronic substrate 110 by applying a laminate of the sacrificial material 150 and backing film 186 to the microelectronic substrate 110, wherein the backing film 186 will be removed after lamination. As further shown in FIG. 10, the lamination may be assisted with a lateral motion (illustrated as arrowed line 192) or with ultrasonication (illustrated as double arrows 194). As shown in FIG. 11, the sacrificial material 150 may also be planarized, such as with a chemical mechanical polisher 198, to improve planarity. The processes illustrated in FIGs. 8-11 are well known in the art and for the sake of brevity and conciseness will not be precisely discussed or further illustrated herein.
FIGs. 12-16 illustrate another embodiment of fabricating a microelectronic package utilizing a sacrificial material. As shown in FIG. 12, the microelectronic substrate front surface 112 may be adhered to the first fixture first surface 122 and a releasing film 190 may be disposed over the microelectronic substrate back surface 114. The releasing film 190 may be any appropriate material, including, but not limited to photodegradable polymers and chemically degradable polymers.
As shown in FIG. 13, a sacrificial material 150 may be formed over the releasing film 190 in a manner as previously discussed with regard to FIGS. 8 to 11. As shown in FIG. 14, the microelectronic substrate 110 may be removed from the first fixture 120, sent to further substrate processing, the microelectronic device 140 may attached by the corresponding microelectronic device bond pads 144 to the attachment structure 130, and then sent to still further processing, as discussed with regard to FIGs. 4 and 5. As shown in FIG. 15, the releasing film 190 and the sacrificial material 150 may be removed, and additional microelectronic devices 135, such as capacitors, may thereafter be attached to the microelectronic substrate back surface 114. The releasing film 190 may be used is protect the microelectronic substrate 110 during the removal of
the sacrificial material 150 and/or to assist in the removal of the sacrificial material 150.
FIG. 16 is a flow chart of a process 300 of fabricating a microelectronic package according to an embodiment of the present description, such as illustrated in FIGs. 12-16. As set forth in block 302, a microelectronic substrate may be formed having a front surface and a back surface. The microelectronic substrate front surface may be attached to a first fixture, as set forth in block 304. As set forth in block 306, a releasing film may be formed over the microelectronic substrate back surface. A sacrificial material may be formed over the releasing film, wherein the sacrificial material has a first surface opposing the microelectronic substrate back surface, as set forth in block 308. As set forth in block 310, the microelectronic substrate may be removed from the first fixture. The sacrificial material first surface may be attached to a second fixture, as set forth in block 312. As set forth in block 314, at least one microelectronic device may be attached to the microelectronic substrate front surface. The sacrificial material and the releasing may be removed, as set forth in block 316.
As shown in FIG. 17, the sacrificial material 150 need not cover the entire microelectronic substrate back surface 114, as shown in FIG. 5, rather the sacrificial material 150 may be patterned in targeted matter, such as patterned opposite an area where the microelectronic device 140 to be attached. Furthermore, it is understood that the processes of the present description could be double-side, i.e. simultaneous fabrication on an opposing side of the first fixture first surface 122, as will be understood to those skilled in the art.
FIG. 18 illustrates an electronic or computing device 400 in accordance with one implementation of the present description. The computing device 400 houses a board 402. The board may include a number of microelectronic components, including but not limited to a processor 404, at least one communication chip 406 A, 406B, volatile memory 408 (e.g., DRAM), non-volatile memory 410 (e.g., ROM), flash memory 412, a graphics processor or CPU 414, a digital signal processor (not shown), a crypto processor (not shown), a chipset 416, an antenna, a display, a display (touchscreen display), a touchscreen controller, a battery, an audio codec (not shown), a video codec (not shown), a power amplifier (AMP), a global positioning system (GPS) device, a compass, an accelerometer (not shown), a gyroscope (not shown), a speaker, a camera, and a mass storage device (not shown) (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the microelectronic components may be physically and electrically coupled to the board 402. In some
implementations, at least one of the microelectronic components may be a part of the processor 404.
The communication chip enables wireless communications for the transfer of data to and
from the computing device. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device may include a plurality of communication chips. For instance, a first communication chip may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.
The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.
Any of the microelectronic components may include a microelectronic package formed by the methods described above.
In various implementations, the computing device may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device may be any other electronic device that processes data.
It is understood that the subject matter of the present description is not necessarily limited to specific applications illustrated in FIGs. 1-18. The subject matter may be applied to other microelectronic devices and assembly applications, as well as any appropriate electronic application, as will be understood to those skilled in the art.
The following examples pertain to further embodiments, wherein Example 1 is a method of fabricating a microelectronic package, comprising forming a microelectronic substrate having a front surface and a back surface; transferring thickness variation in the microelectronic substrate to the microelectronic substrate back surface; forming a sacrificial material over the
microelectronic substrate back surface; attaching at least one microelectronic device to the microelectronic substrate front surface; and removing the sacrificial material after attaching the
at least one microelectronic device.
In Example 2, the subject matter of Example 1 can optionally include forming the sacrificial material from a material selected from the group consisting of photoresist materials, low viscosity polymers, and inorganic material pastes.
In Example 3, the subject matter of one of Examples 1 and 2 can optionally include forming the sacrificial material comprising molding the sacrificial material over the
microelectronic substrate back surface.
In Example 4, the subject matter of one of Examples 1 and 2 can optionally include forming the sacrificial material comprising slit coating the sacrificial material over the microelectronic substrate back surface.
In Example 5, the subject matter of one of Examples 1 and 2 can optionally include forming the sacrificial material comprising laminating the sacrificial material over the microelectronic substrate back surface.
In Example 6, the subject matter of Example 1 can optionally include attaching an additional microelectronic device to the microelectronic substrate front surface.
In Example 7, the subject matter of Example 1 can optionally include attaching an additional microelectronic device to the microelectronic substrate back surface prior to forming the sacrificial material over the microelectronic substrate back surface.
In Example 8, the subject matter of Example 1 can optionally include forming a releasing film between the microelectronic substrate back surface and the sacrificial material.
In Example 9, the subject matter of Example 8 can optionally include forming the releasing film from a material selected from the group consisting of photodegradable polymers and chemically degradable polymers.
In Example 10, the subject matter of Example 8 can optionally include removing the releasing film after removing the sacrificial material.
In Example 11, the subject matter of Example 10 can optionally include attaching an additional microelectronic device to the microelectronic substrate back surface after removing the releasing film.
In Example 12, the subject matter of Example 8 can optionally include attaching an additional microelectronic device to the microelectronic substrate front surface.
The following examples pertain to further embodiments, wherein Example 13 is a method of fabricating a microelectronic package, comprising forming a microelectronic substrate having a front surface and a back surface; attaching the microelectronic substrate front surface to a first fixture; forming a sacrificial material over the microelectronic substrate back surface, wherein
the sacrificial material has a first surface opposing the microelectronic substrate back surface; removing the microelectronic substrate from the first fixture; attaching the sacrificial material first surface to a second fixture; and attaching at least one microelectronic device to the microelectronic substrate front surface.
In Example 14, the subject matter of Example 13 can optionally include removing the sacrificial material.
In Example 15, the subject matter of Example 13 can optionally include forming the sacrificial material from a material selected from the group consisting of photoresist materials, low viscosity polymers, and inorganic material pastes.
In Example 16, the subject matter of one of Examples 13 to 15 can optionally include forming the sacrificial material comprising one of molding the sacrificial material over the microelectronic substrate back surface, slit coating the sacrificial material over the
microelectronic substrate back surface, and laminating the sacrificial material over the microelectronic substrate back surface.
In Example 17, the subject matter of Example 13 can optionally include attaching an additional microelectronic device to the microelectronic substrate front surface.
In Example 18, the subject matter of Example 13 can optionally include attaching an additional microelectronic device to the microelectronic substrate back surface prior to forming the sacrificial material over the microelectronic substrate back surface.
The following examples pertain to further embodiments, wherein Example 19 is a method of fabricating a microelectronic package, comprising forming a microelectronic substrate having a front surface and a back surface; attaching the microelectronic substrate front surface to a first fixture; forming a releasing film over the microelectronic substrate back surface; forming a sacrificial material over the releasing film, wherein the sacrificial material has a first surface opposing the microelectronic substrate back surface; removing the microelectronic substrate from the first fixture; attaching the sacrificial material first surface to a second fixture; and attaching at least one microelectronic device to the microelectronic substrate front surface.
In Example 20, the subject matter of Example 19 can optionally include removing the sacrificial material and the releasing film.
In Example 21, the subject matter of Example 19 can optionally include forming the sacrificial material from a material selected from the group consisting of photoresist materials, low viscosity polymers, and inorganic material pastes.
In Example 22, the subject matter of Example 19 can optionally include forming the releasing film from a material selected from the group consisting of photodegradable polymers
and chemically degradable polymers.
In Example 23, the subject matter of one of Examples 19 to 22 can optionally include forming the sacrificial material comprising one of molding the sacrificial material over the microelectronic substrate back surface, slit coating the sacrificial material over the microelectronic substrate back surface, and laminating the sacrificial material over the microelectronic substrate back surface.
In Example 24, the subject matter of Example 19 can optionally include attaching an additional microelectronic device to the microelectronic substrate front surface.
In Example 25, the subject matter of Example 19 can optionally include attaching an additional microelectronic device to the microelectronic substrate back surface after removing the releasing film and the sacrificial material.
Having thus described in detail embodiments of the present description, it is understood that the present description defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.
Claims
1. A method of fabricating a microelectronic package, comprising:
forming a microelectronic substrate having a front surface and a back surface;
transferring thickness variation in the microelectronic substrate to the microelectronic substrate back surface;
forming a sacrificial material over the microelectronic substrate back surface;
attaching at least one microelectronic device to the microelectronic substrate front surface; and
removing the sacrificial material after attaching the at least one microelectronic device.
2. The method of claim 1, wherein forming the sacrificial material comprises forming the sacrificial material from a material selected from the group consisting of photoresist materials, low viscosity polymers, and inorganic material pastes.
3. The method of one of claims 1 and 2, wherein forming the sacrificial material comprises molding the sacrificial material over the microelectronic substrate back surface.
4. The method of one of claims 1 and 2, wherein forming the sacrificial material comprises slit coating the sacrificial material over the microelectronic substrate back surface.
5. The method of one of claims 1 and 2, wherein forming the sacrificial material comprises laminating the sacrificial material over the microelectronic substrate back surface.
6. The method of claim 1, further comprising attaching an additional microelectronic device to the microelectronic substrate front surface.
7. The method of claim 1, further comprising attaching an additional microelectronic device to the microelectronic substrate back surface prior to forming the sacrificial material over the microelectronic substrate back surface.
8. The method of claim 1, further comprising forming a releasing film between the microelectronic substrate back surface and the sacrificial material.
9. The method of claim 8, wherein forming the releasing film comprises forming the releasing film from a material selected from the group consisting of photodegradable polymers and chemically degradable polymers.
10. The method of claim 8, further comprising removing the releasing film after removing the sacrificial material.
11. The method of claim 10, further comprising attaching an additional
microelectronic device to the microelectronic substrate back surface after removing the releasing film.
12. The method of claim 8, further comprising attaching an additional microelectronic device to the microelectronic substrate front surface.
13. A method of fabricating a microelectronic package, comprising:
forming a microelectronic substrate having a front surface and a back surface;
attaching the microelectronic substrate front surface to a first fixture;
forming a sacrificial material over the microelectronic substrate back surface, wherein the sacrificial material has a first surface opposing the microelectronic substrate back surface;
removing the microelectronic substrate from the first fixture;
attaching the sacrificial material first surface to a second fixture; and
attaching at least one microelectronic device to the microelectronic substrate front surface.
14. The method of claim 13, further comprising removing the sacrificial material.
15. The method of claim 13, wherein forming the sacrificial material comprises forming the sacrificial material from a material selected from the group consisting of photoresist materials, low viscosity polymers, and inorganic material pastes.
16. The method of one of claims 13 to 15, wherein forming the sacrificial material comprises one of molding the sacrificial material over the microelectronic substrate back surface, slit coating the sacrificial material over the microelectronic substrate back surface, and
laminating the sacrificial material over the microelectronic substrate back surface.
17. The method of claim 13, further comprising attaching an additional
microelectronic device to the microelectronic substrate front surface.
18. The method of claim 13, further comprising attaching an additional
microelectronic device to the microelectronic substrate back surface prior to forming the sacrificial material over the microelectronic substrate back surface.
19. A method of fabricating a microelectronic package, comprising:
forming a microelectronic substrate having a front surface and a back surface;
attaching the microelectronic substrate front surface to a first fixture;
forming a releasing film over the microelectronic substrate back surface;
forming a sacrificial material over the releasing film, wherein the sacrificial material has a first surface opposing the microelectronic substrate back surface;
removing the microelectronic substrate from the first fixture;
attaching the sacrificial material first surface to a second fixture; and
attaching at least one microelectronic device to the microelectronic substrate front surface.
20. The method of claim 19, further comprising removing the sacrificial material and removing the releasing film.
21. The method of claim 19, wherein forming the sacrificial material comprises forming the sacrificial material from a material selected from the group consisting of photoresist materials, low viscosity polymers, and inorganic material pastes.
22. The method of claim 19, wherein forming the releasing film comprises forming the releasing film from a material selected from the group consisting of photodegradable polymers and chemically degradable polymers.
23. The method of one of claims 19 to 22, wherein forming the sacrificial material comprises one of molding the sacrificial material over the microelectronic substrate back surface, slit coating the sacrificial material over the microelectronic substrate back surface, and
laminating the sacrificial material over the microelectronic substrate back surface.
24. The method of claim 19, further comprising attaching an additional
microelectronic device to the microelectronic substrate front surface.
25. The method of claim 19, further comprising attaching an additional
microelectronic device to the microelectronic substrate back surface after removing the releasing film and the sacrificial material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/US2015/047440 WO2017039583A1 (en) | 2015-08-28 | 2015-08-28 | Use of sacrificial material to compensate for thickness variation in microelectronic substrates |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/US2015/047440 WO2017039583A1 (en) | 2015-08-28 | 2015-08-28 | Use of sacrificial material to compensate for thickness variation in microelectronic substrates |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2017039583A1 true WO2017039583A1 (en) | 2017-03-09 |
Family
ID=58188178
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/US2015/047440 Ceased WO2017039583A1 (en) | 2015-08-28 | 2015-08-28 | Use of sacrificial material to compensate for thickness variation in microelectronic substrates |
Country Status (1)
| Country | Link |
|---|---|
| WO (1) | WO2017039583A1 (en) |
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| US20080237810A1 (en) * | 2007-03-29 | 2008-10-02 | Gopalakrishnan Subramanian | Controlling substrate surface properties via colloidal coatings |
| US20110037156A1 (en) * | 2009-08-13 | 2011-02-17 | Qualcomm Incorporated | Variable Feature Interface That Induces A Balanced Stress To Prevent Thin Die Warpage |
| US20130099374A1 (en) * | 2011-10-19 | 2013-04-25 | SK Hynix Inc. | Package of electronic device including connecting bump, system including the same and method for fabricating the same |
| US20140138823A1 (en) * | 2012-11-21 | 2014-05-22 | Nvidia Corporation | Variable-size solder bump structures for integrated circuit packaging |
| US20140167255A1 (en) * | 2012-12-17 | 2014-06-19 | Princo Middle East Fze | Package structure and package method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080237810A1 (en) * | 2007-03-29 | 2008-10-02 | Gopalakrishnan Subramanian | Controlling substrate surface properties via colloidal coatings |
| US20110037156A1 (en) * | 2009-08-13 | 2011-02-17 | Qualcomm Incorporated | Variable Feature Interface That Induces A Balanced Stress To Prevent Thin Die Warpage |
| US20130099374A1 (en) * | 2011-10-19 | 2013-04-25 | SK Hynix Inc. | Package of electronic device including connecting bump, system including the same and method for fabricating the same |
| US20140138823A1 (en) * | 2012-11-21 | 2014-05-22 | Nvidia Corporation | Variable-size solder bump structures for integrated circuit packaging |
| US20140167255A1 (en) * | 2012-12-17 | 2014-06-19 | Princo Middle East Fze | Package structure and package method |
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