WO2017024454A1 - 像素电路及其驱动方法、显示面板 - Google Patents

像素电路及其驱动方法、显示面板 Download PDF

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Publication number
WO2017024454A1
WO2017024454A1 PCT/CN2015/086409 CN2015086409W WO2017024454A1 WO 2017024454 A1 WO2017024454 A1 WO 2017024454A1 CN 2015086409 W CN2015086409 W CN 2015086409W WO 2017024454 A1 WO2017024454 A1 WO 2017024454A1
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Prior art keywords
transistor
driving
pixel circuit
voltage
turned
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PCT/CN2015/086409
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English (en)
French (fr)
Inventor
余晓军
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深圳市柔宇科技有限公司
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Application filed by 深圳市柔宇科技有限公司 filed Critical 深圳市柔宇科技有限公司
Priority to US15/738,440 priority Critical patent/US10535298B2/en
Priority to JP2018500930A priority patent/JP2018523844A/ja
Priority to PCT/CN2015/086409 priority patent/WO2017024454A1/zh
Priority to KR1020187001363A priority patent/KR20180032560A/ko
Priority to CN201580002977.XA priority patent/CN106688030A/zh
Priority to EP15900652.7A priority patent/EP3333837B1/en
Publication of WO2017024454A1 publication Critical patent/WO2017024454A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen

Definitions

  • the present invention relates to a light-emitting display panel, and more particularly to a pixel circuit capable of compensating for a threshold voltage variation, a driving method thereof, and a display panel having the pixel circuit.
  • Organic Light Emitting Diode has been increasingly used as a current-type light-emitting device in high-performance organic light-emitting display panels.
  • the existing OLED display panel pixel circuit includes a driver transistor (Transistor) MD, a switching transistor M1, a capacitor C ST, and a device illuminating device, that is, 2T1C.
  • the organic light emitting device includes an organic light emitting diode D OLED and a sensing capacitor C OLED of its own.
  • the transistor M1 is connected to the data signal V DATA and is controlled by the scan signal V SCAN
  • the driving transistor MD is connected to the pixel power source V DD and is also connected to the data signal V DATA through the transistor M1
  • the pixel power source V DD and the transistor are respectively connected across the capacitor C ST
  • the node A between the M1 and the driving transistor MD, the organic light emitting diode D OLED and the sensing capacitor C OLED are connected in parallel between the transistor MD and the external power source V SS .
  • the voltage of the external power source V SS is lower than the voltage of the pixel power source V DD , and may be, for example, a ground voltage.
  • the data signal V DATA starts to charge the capacitor C ST , and then the voltage in the capacitor C ST is applied to the gate of the driving transistor MD, thereby turning on the driving transistor.
  • the MD causes a current to flow through the organic light emitting device to emit light.
  • the current supplied to the organic light emitting device through the driving transistor MD is calculated by the following formula:
  • I OLED 1/2* ⁇ (V GS -V TH ) 2 ---Formula 1
  • the I OLED is a current flowing through the organic light emitting device
  • V GS is a voltage applied between the gate and the source of the driving transistor MD
  • V GS is determined by the voltage across the C ST
  • V TH is a threshold voltage of the driving transistor MD
  • ⁇ is the gain factor of the drive transistor MD, which is determined by the device size and the semiconductor carrier mobility.
  • an embodiment of the present invention provides a pixel circuit that can reduce the brightness by a change in threshold voltage
  • a pixel circuit comprising: a light emitting diode; a driving transistor; a first transistor connected between a data line and the driving transistor, and a gate connected to a first scan line; and a second transistor connected to the a first power line and the driving transistor, and a gate thereof connected to a second scan line; a third transistor connected between the gate of the driving transistor and the second transistor, and a gate connected thereto a third scan line; and a driving capacitor connected between the gate of the driving transistor and the first power line; wherein the driving transistor is further connected to a second power line through the light emitting diode.
  • a display panel comprising: a plurality of arrays of pixel circuits as described in the preceding paragraph; a scan driving unit for respectively providing scan signals to the first to third scan lines; and a data driving unit for using the data
  • the line provides a data signal; a first power source for providing a first power voltage to the first power line; and a second power source for providing a second power voltage to the second power line.
  • a driving method of a pixel circuit is applied to the pixel circuit described in the preceding paragraph, the driving transistor has a threshold voltage, and the driving method comprises: turning the first to third driving transistors, and the potential of the driving capacitor is changed a first voltage provided for the first power line; turning on the first and third driving transistors, turning off the second transistor, the data line passing through the first transistor The driving transistor outputs a data voltage, and the driving capacitor sequentially discharges to the data line through the third, driving and first transistors until a potential of one end of the driving capacitor connected to the driving transistor is a sum of the data voltage and the threshold voltage; And turning on the second transistor, the first and third transistors are turned off, and the driving capacitor drives the driving transistor to be turned on to cause the first voltage provided by the first power line to drive the light emitting element to emit light.
  • the current flowing through the light-emitting element is only related to the data signal supplied from the data line, thereby reducing the influence of the change in the threshold voltage on the current flowing through the light-emitting element.
  • FIG. 1 is a schematic diagram of a conventional pixel circuit.
  • FIG. 2 is a schematic view of a frame of a display panel of the present invention.
  • FIG. 3 is a schematic diagram of a pixel circuit of the display panel of FIG. 1.
  • 4a and 4b are respectively a timing chart of the operation of the pixel circuit of FIG. 3 and a working diagram of the pixel circuit of FIG. 3 in the charging phase of the timing chart.
  • 5a and 5b are respectively a timing chart and a working diagram of the pixel circuit of FIG. 3 in the compensation phase of the timing chart.
  • 6a and 6b are respectively a timing chart and a working diagram of the pixel circuit of FIG. 3 in the transmitting phase of the timing chart.
  • 7a and 7b are respectively a timing chart and a schematic diagram of the operation of the pixel circuit of FIG. 3 in the discharge phase of the timing chart.
  • FIG. 8 is a graph showing a relationship between a threshold value of a driving transistor of the pixel circuit of FIG. 3 and a passing current; Figure.
  • FIG. 9 is a schematic diagram of a second embodiment of a pixel circuit of a display panel of the pixel circuit of FIG. 2.
  • 10a and 10b are respectively a timing chart of the operation of the pixel circuit of Fig. 9 and a working diagram of the pixel circuit of Fig. 9 in the charging phase of the timing chart.
  • the display panel 8 includes a scan driving unit 10, a data driving unit 20, an emission control driving unit 30, a display unit 40, a first power source 50, and a second power source 60.
  • the display unit 40 includes a plurality of pixel circuits arranged in a matrix. 70.
  • the scan driving unit 10, the data driving unit 20, and the emission control driving unit 30 are respectively configured to provide a scanning signal V SCAN (including a first scanning signal V SCAN1 , a second scanning signal V SCAN2 , and a third scanning signal V SCAN3 ) to each pixel circuit 70 . ), the data signal V DATA and the emission control signal V EM .
  • the first power source 50 and the second power source 60 are respectively configured to supply the first voltage V DD and the second voltage V SS to each of the pixel circuits 70.
  • the pixel circuit 70 of the first embodiment of the present invention has a first scan line for transmitting the first scan signal V SCAN1 and a second scan line for transmitting the second scan signal V SCAN2 for transmission. a third scan line of the third scan signal V SCAN3 , a first power line for transmitting the first voltage V DD , a second power line for transmitting the second voltage V SS , and a data line for transmitting the data signal V DATA a transmission line for transmitting the emission control signal V EM .
  • the pixel circuit 70 further includes:
  • a light emitting diode D OLED having an electrode connected to the second power line
  • a first transistor T1 having a control electrode connected to the first scan line and two control electrodes connected to the data line and a controlled electrode of the drive transistor TD;
  • a second transistor T2 having a control electrode connected to the second scan line and two controlled electrodes connected to the first power line and another controlled electrode of the drive transistor TD;
  • a third transistor T3 having a control electrode connected to the third scan line and two control electrodes connected to the control electrode of the drive transistor TD and the other controlled electrode;
  • a transmitting transistor TE having a control electrode connected to the emission line and two controlled electrodes thereof connected to the one controlled electrode of the driving transistor TD and the other electrode of the light emitting diode D OLED ;
  • the driving capacitor C ST has two ends connected to the control electrode of the driving transistor TD and the first power line.
  • the illuminating element is exemplified by an organic light emitting diode (OLED), but it should be understood that the present invention is not limited thereto.
  • the illuminating element may also be an inorganic light emitting diode;
  • the driving transistor TD, the first transistor T1, the second transistor T2, the third transistor T3, and the transmitting transistor TE in the example are preferably thin film field effect transistors, specifically, N-type thin film field effect transistors, but not Alternatively, it may be a P-type or other electronic device capable of implementing a switching function, such as a triode, and the skilled person can know how other types of transistors work according to the description of the following embodiments, and thus the present invention will not describe other types.
  • Transistor At this time, the voltage value of the second voltage V SS is lower than the voltage value of the first voltage V DD , such as the ground voltage.
  • the driving transistor TD comprises a control electrode and two controlled poles which are controlled to be turned on or off by the gate electrode, wherein the gate electrode is the gate G of the N-type thin film field effect transistor TD, and two controlled poles That is, its drain D and source S, the first to third transistors T1, T2, T3 and the transmitting transistor TE are similar.
  • the drain D and the source S of the first transistor T1 are respectively connected to the data line and the source S of the driving transistor TD, and the gate G is connected to the first scanning line.
  • the drain D and the source S of the second transistor T2 are respectively connected to the first power line and the drain D of the driving transistor TD, and the gate G is connected to the second scan line.
  • the drain D and the source S of the third transistor T3 are respectively connected to the source S of the second transistor T2 and the gate G of the driving transistor TD, and the gate G is connected to the third scan line.
  • the drain D of the transmitting transistor TE is connected to the source S of the driving transistor TD, and the source S is connected to the second power line through the LED D OLED , wherein the cathode of the LED D OLED is connected to the second power line, the transmitting transistor
  • the gate G of the TE is connected to the emission line.
  • the node connecting the first transistor T1, the driving transistor TD, and the transmitting transistor TE to each other is N S
  • the node connecting the second transistor T2, the driving transistor TD, and the third transistor T3 is N D
  • the node at which the driving capacitor C ST , the third transistor T3, and the driving transistor TD are connected to each other is N G .
  • the pixel circuit 70 of FIG. 3 operates in accordance with the timing diagram shown in FIG. 4a.
  • each operation cycle of the pixel circuit 70 can be divided into four stages.
  • the first stage that is, the charging stage
  • the operation of the pixel circuit 70 is as shown in FIG. 4b.
  • the voltages of nodes N D and N G are charged to the voltage of the first voltage V DD .
  • the first scan signal V SCAN1 and the emission control signal V EM are at a low level
  • the second scan signal V SCAN2 and the third scan signal V SCAN3 are at a high level
  • the first transistor T1 and the transmit transistor TE are turned off.
  • the second transistor T2 and the third transistor T3 are turned on. At this time, the first voltage V DD is transmitted to the node N G through the second transistor T2 and the third transistor T3, that is, the nodes N G and N D are all charged to the first voltage V DD . At this time, the driving transistor TD is also turned off. At this stage the data signal V DATA can be low.
  • the nodes N D and N G are charged to the sum of the voltage of the data signal V DATA and the threshold voltage V TH of the driving transistor TD, and the node N S is charged to the data.
  • the voltage of the signal V DATA Specifically, the second scan signal V SCAN2 and the emission control signal V EM are at a low level, and the first scan signal V SCAN1 and the third scan signal V SCAN3 are at a high level.
  • the V GS of the first transistor T1 is greater than its V
  • the potential of the node N S is the voltage value of the data signal V DATA
  • the driving transistor TD is also turned on
  • the potential of the node N D is also the voltage value of the data signal V DATA .
  • the third transistor T3 is also turned on, and one end of the driving capacitor C S connected to the third transistor T3 is sequentially discharged to the data line through the transistors T3, TD, T1, and the potential thereof is gradually lowered.
  • the transistors T2, TD, and TE are all turned on, and the light-emitting diode D OLED emits light.
  • the operation of the pixel circuit 70 during the transmission phase is as shown in FIG. 6b.
  • the second scan signal V SCAN2 and the emission control signal V EM are both at a high level
  • the third scan signal V SCAN3 and the first scan signal V SCAN1 are both low
  • the TE is turned on, and the first and third transistors T1 and T3 are turned off.
  • the voltage of the driving capacitor C S remains unchanged, that is, the potential of the node N G is maintained at (V DATA + V TH ), so that the driving transistor TD is also operated by the energy stored by the driving capacitor C ST .
  • the current generated by the first voltage V DD flows through the light emitting diode D OLED to cause it to emit light. According to the formula 1 mentioned in the background art, the current flowing through the light-emitting element at this time:
  • I OLED 1/2 * ⁇ (V DATA + V TH - V TH ) 2
  • the current flowing through the light-emitting element during the emission phase is only related to the data signal V DATA , thereby reducing the influence of the change in the threshold voltage on the current flowing through the light-emitting element.
  • the 5T1C structure of the present invention has a significantly lower current variation under the same threshold voltage VTH as compared with the conventional 2T1C structure, thereby improving the uniformity of the brightness of the display panel 8.
  • a discharge phase in which the drive capacitor CS is discharged to the second power line.
  • the operation of the pixel circuit 70 is as shown in FIG. 7b, the emission control signal V EM is at a high level, and the first scan signal V SCAN1 , the second scan signal V SCAN2 , and the third scan signal V SCAN3 are both Low level.
  • the emitter transistor TE is turned on, and since the potential of the node N G is still maintained at (V DATA + V TH ), the driving transistor TD is also turned on, and the first to third transistors T1, T2, and T3 are turned off.
  • the light-emitting diode D OLED is turned on, so that the potentials of the nodes N D and N S are gradually lowered by the second voltage V SS .
  • the data voltage of the next cycle is low, that is, the data voltage is lower than the voltage of the node N S , the data voltage writing is slow or even impossible to write in the next cycle compensation phase, thereby improving The response speed improves the display effect.
  • the pixel circuit 70' of another embodiment of the present invention is different from the pixel circuit 70 of the above embodiment in that the emitter transistor TE is omitted, and thus the driving transistor TD is directly connected to the light emitting diode. D OLED .
  • the driving timing diagram of the pixel circuit 70' is as shown in FIG. 10a.
  • the voltage of the node NS is charged to the voltage of the data signal V DATA
  • the voltages of the nodes N D and N G are charged to the voltage of the first voltage V DD .
  • the first scan signal V SCAN1 , the second scan signal V SCAN2 , and the third scan signal V SCAN3 are all at a high level.
  • the first to third transistors T1 to T3 are turned on, and the driving transistor TD is also turned on.
  • the first voltage V DD is transmitted to the node N G through the second transistor T2 and the third transistor T3, that is, the nodes N G and N D are all charged to the first voltage V DD .
  • the first transistor T1 is turned on, and the potential of the node N S is the voltage of the data signal V DATA .
  • the compensation phase nodes N D and N G are charged to (V DATA + V TH ), and node N S is charged to the voltage of data signal V DATA .
  • the emission stage, the transistors T2 and TD are both turned on, and the light-emitting diode D OLED emits light.
  • the working principle and the specific working process are the same as the first mode, which is well described here.
  • the pixel circuit 70' may also include a discharge phase after the third stage, and the specific working mode and principle thereof are also as described above, which is well described herein.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of El Displays (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

一种像素电路（70），包括：发光二极管；驱动晶体管；第一晶体管，其连接在一个数据线及该驱动晶体管之间，并且其栅极连接至一个第一扫描线；第二晶体管，其连接在一个第一电源线及该驱动晶体管之间，并且其栅极连接至一个第二扫描线；第三晶体管，其连接在该驱动晶体管的栅极与该第二晶体管之间，并且其栅极连接至一个第三扫描线；及驱动电容，其连接在该驱动晶体管的栅极及该第一电源线之间；其中，该驱动晶体管还通过该发光二级管连接至一个第二电源线。如此，流过发光元件的电流只与数据线提供的数据信号有关，从而减小了阈值电压的变化对流过发光元件的电流影响。还提供一种显示面板（8）及像素驱动方法。

Description

像素电路及其驱动方法、显示面板 技术领域
本发明涉及发光显示面板，尤其涉及能够补偿阈值电压变化的像素电路、其驱动方法以及具有该像素电路的显示面板。
背景技术
有机电致发光二极管(Organic Light Emitting Diode，OLED)作为一种电流型发光器件已越来越多地被应用于高性能有机发光显示面板中。请结合图1，现有的OLED显示面板像素电路包括驱动晶体管(Transistor)MD、起开关作用的晶体管M1、一个电容CST以及一个机发光器件，即2T1C。其中，有机发光器件包括一个有机发光二极管DOLED以及一个其自身的感应电容COLED。晶体管M1连接至数据信号VDATA并受扫描信号VSCAN控制，驱动晶体管MD连接至像素电源VDD并通过晶体管M1也连接至数据信号VDATA，电容CST两端分别连接像素电源VDD以及晶体管M1及驱动晶体管MD之间的节点A，有机发光二极管DOLED以及感应电容COLED并联在晶体管MD与外部电源VSS之间。其中，外部电源VSS的电压低于像素电源VDD的电压，例如可以是地电压。当晶体管M1的栅极响应到扫描信号VSCAN开启晶体管M1时，数据信号VDATA就开始对电容CST进行充电，随后电容CST中的电压施加到驱动晶体管MD的栅极，从而打开驱动晶体管MD，使得电流流过有机发光器件进行发光。
通过驱动晶体管MD向有机发光器件提供的电流通过以下公式计算：
IOLED＝1/2*β(VGS-VTH)2---公式1
其中，IOLED是流过有机发光器件的电流，VGS是驱动晶体管MD的栅 极和源极之间施加的电压，VGS由CST两端电压决定，VTH是驱动晶体管MD的阈值电压，β是驱动晶体管MD的增益因子，由器件尺寸及半导体载流子迁移率决定。从公式1可以看出，流过有机发光器件的电流会受到驱动晶体管MD的阈值电压的影响。由于生产过程中有机发光显示面板中的每一个晶体管的阈值电压和电子迁移率均不相同，这就导致了即使给予相同的VGS，电路中产生的电流IOLED也仍然会有差异，从而造成亮度不均。
发明内容
有鉴于此，本发明的一个实施方式提供了一种可使亮度受阀值电压的变化影响较小的像素电路、
一种像素电路，包括：发光二极管；驱动晶体管；第一晶体管，其连接在一个数据线及该驱动晶体管之间，并且其栅极连接至一个第一扫描线；第二晶体管，其连接在一个第一电源线及该驱动晶体管之间，并且其栅极连接至一个第二扫描线；第三晶体管，其连接在该驱动晶体管的栅极与该第二晶体管之间，并且其栅极连接至一个第三扫描线；及驱动电容，其连接在该驱动晶体管的栅极及该第一电源线之间；其中，该驱动晶体管还通过该发光二级管连接至一个第二电源线。
一种显示面板，包括：多个阵列排布的如前段所述的像素电路；扫描驱动单元，用于分别向该第一至第三扫描线提供扫描信号；数据驱动单元，用于向该数据线提供数据信号；第一电源，用于向该第一电源线提供第一电源电压；及第二电源，用于向该第二电源线提供第二电源电压。
一种像素电路的驱动方法，应用于前段所述的像素电路，该驱动晶体管具有一个阈值电压，该驱动方法包括：使该第一至第三及驱动晶体管导通，该驱动电容两端的电势变为该第一电源线提供的第一电压；使该第一、第三及驱动晶体管导通，第二晶体管截止，该数据线通过该第一晶体管向 该驱动晶体管输出一个数据电压，该驱动电容依次通过该第三、驱动及第一晶体管向数据线放电，直至该驱动电容与该驱动晶体管连接一端的电势为该数据电压与该阈值电压之和；及使该第二晶体管导通，第一及第三晶体管截止，该驱动电容驱动该驱动晶体管导通进而使该第一电源线提供的第一电压驱动该发光元件发光。
本发明的像素电路、显示面板及驱动方法中，流过发光元件的电流只与数据线提供的数据信号有关，从而减小了阈值电压的变化对流过发光元件的电流影响。
附图说明
下列附图用于结合具体实施方式详细说明本发明的各个实施方式。应当理解，附图中示意出的各元件并不代表实际的大小及比例关系，仅是为了清楚说明而示意出来的示意图，不应理解成对本发明的限制。
图1是现有像素电路的示意图。
图2是本发明的显示面板的框架示意图。
图3是图1的显示面板的像素电路的示意图。
图4a、4b分别是图3的像素电路的工作时序图及图3的像素电路在该时序图的充电阶段的工作示意图。
图5a、5b分别是时序图及图3的像素电路在该时序图的补偿阶段的工作示意图。
图6a、6b分别是时序图及图3的像素电路在该时序图的发射阶段的工作示意图。
图7a、7b分别是时序图及图3的像素电路在该时序图的放电阶段的工作示意图。
图8是图3的像素电路的驱动晶体管的阈值与通过的电流的变化关系 图。
图9是图2的像素电路的显示面板的像素电路的第二实施方式的示意图。
图10a、10b分别是图9的像素电路的工作时序图及图9的像素电路在该时序图的充电阶段的工作示意图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合多个实施方式及附图，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施方式仅仅用以解释本发明，并不用于限定本发明。
请参照图2，显示面板8包括扫描驱动单元10、数据驱动单元20、发射控制驱动单元30、显示单元40、第一电源50及第二电源60，显示单元40包含多个矩阵排列的像素电路70。扫描驱动单元10、数据驱动单元20、发射控制驱动单元30分别用以向各像素电路70提供扫描信号VSCAN(包括第一扫描信号VSCAN1、第二扫描信号VSCAN2和第三扫描信号VSCAN3)、数据信号VDATA和发射控制信号VEM。第一电源50及第二电源60分别用以向各像素电路70提供第一电压VDD及第二电压VSS。
请再参照图3，本发明第一实施方式的像素电路70具有用于传输第一扫描信号VSCAN1的第一扫描线、用于传输第二扫描信号VSCAN2的第二扫描线、用于传输第三扫描信号VSCAN3的第三扫描线、用于传输第一电压VDD的第一电源线、用于传输第二电压VSS的第二电源线、用于传输数据信号VDATA的数据线、用于传输发射控制信号VEM的发射线。像素电路70还包括：
驱动晶体管TD；
发光二极管DOLED，其一电极连接至该第二电源线；
第一晶体管T1，其控制极连接至该第一扫描线并且其两个受控极分别连接至该数据线及该驱动晶体管TD的一个受控极；
第二晶体管T2，其控制极连接至该第二扫描线并且其两个受控极分别连接至该第一电源线及该驱动晶体管TD的另一受控极；
第三晶体管T3，其控制极连接至该第三扫描线并且其两个受控极分别连接至该驱动晶体管TD的控制极及所述另一受控极；
发射晶体管TE，其控制极连接至该发射线并且其两个受控极分别连接至该驱动晶体管TD所述一个受控极及该发光二极管DOLED的另一电极；
驱动电容CST，其两端分别连接至该驱动晶体管TD的控制极及该第一电源线。
具体地，在下述实施例中，发光元件以有机发光二极管(OLED)为例，但应当理解，本发明并不以此为限，比如，此发光元件也可以是无机发光二极管；且下述实施例中的驱动晶体管TD、第一晶体管T1、第二晶体管T2、第三晶体管T3及发射晶体管TE优选是薄膜场效应晶体管，具体地都是以N型薄膜场效应晶体管，但也不以此为限，也可以是P型或者其它能够实现开关功能的电子器件，比如三极管，并领域技术人员根据下述实施方式的描述可得知其它类型的晶体管是如何工作，因此本发明将不赘述其它类型的晶体管。此时，第二电压VSS的电压值低于第一电压VDD的电压值，比如地电压。
驱动晶体管TD包括一个控制极及两个由该控制极控制而导通或不导通的受控极，其中，控制极即为N型薄膜场效应晶体管TD的栅极G，两个受控极即为其漏极D及源极S，第一至第三晶体管T1、T2、T3及发射晶体管TE同理。第一晶体管T1的漏极D及源极S分别连接至该数据线 及驱动晶体管TD的源极S，而栅极G连接至第一扫描线。第二晶体管T2的漏极D及源极S分别连接第一电源线及驱动晶体管TD的漏极D，而栅极G则连接至该第二扫描线。第三晶体管T3的漏极D及源极S分别连接第二晶体管T2的源极S及驱动晶体管TD的栅极G，而栅极G则连接该第三扫描线。发射晶体管TE的漏极D连接驱动晶体管TD的源极S，源极S通过发光二极管DOLED连接至第二电源线，其中，该发光二极管DOLED的阴极连接至该第二电源线，发射晶体管TE的栅极G连接至该发射线。在本实施方式中，记第一晶体管T1、驱动晶体管TD及发射晶体管TE相互连接的节点为NS，记第二晶体管T2、驱动晶体管TD及第三晶体管T3相互连接的节点为ND，记驱动电容CST、第三晶体管T3及驱动晶体管TD相互连接的节点为NG。
请结合图4a及4b，图3的像素电路70根据图4a所示的时序图运行。在图4a所示的时序图中，像素电路70的每个运行周期可分为四个阶段，在第一阶段，即充电阶段，像素电路70的运行情况如图4b所示。在充电阶段中，节点ND及NG的电压被充电至第一电压VDD的电压。具体地，第一扫描信号VSCAN1及发射控制信号VEM为低电平，第二扫描信号VSCAN2及第三扫描信号VSCAN3为高电平，此时第一晶体管T1及发射晶体管TE截止，而第二晶体管T2及第三晶体管T3导通。此时第一电压VDD通过第二晶体管T2及第三晶体管T3传输到节点NG，即节点NG及ND都被充电至第一电压VDD。此时驱动晶体管TD也截止。在该阶段数据信号VDATA可为低电平。
请结合图5a及5b，在第二阶段，即补偿阶段，节点ND及NG被充电至数据信号VDATA的电压与驱动晶体管TD的阈值电压VTH之和，节点NS被充电至数据信号VDATA的电压。具体地，第二扫描信号VSCAN2及发射控 制信号VEM为低电平，第一扫描信号VSCAN1及第三扫描信号VSCAN3为高电平。由于第一扫描信号VSCAN1及第一电压VDD的电压值与数据信号VDATA的电压差通常大于第一晶体管T1及驱动晶体管TD的阈值电压，因此，第一晶体管T1的VGS大于其VTH而导通，节点NS的电势为数据信号VDATA的电压值，驱动晶体管TD同理也导通，节点ND的电势也为数据信号VDATA的电压值。同理，第三晶体管T3也导通，驱动电容CS与第三晶体管T3连接的一端从而依次通过晶体管T3、TD、T1向数据线释放电量，其电势因此逐渐降低。当节点ND及NG的电势下降到数据信号VDATA的电压与驱动晶体管TD的阈值电压VTH之和(VDATA+VTH)时，驱动晶体管TD的VGS等于其VTH，驱动晶体管TD此时截止。如此，节点ND及NG保持在(VDATA+VTH)，节点NS的电势则等于数据信号VDATA的电压值。
请结合图6a及6b，在第三阶段，即发射阶段，晶体管T2、TD、TE都导通，发光二极管DOLED发光。具体地，像素电路70的在发射阶段的运行情况如图6b所示。在发射阶段中，第二扫描信号VSCAN2及发射控制信号VEM都为高电平，第三扫描信号VSCAN3、及第一扫描信号VSCAN1都低电平，此时第二及发射晶体管T2、TE导通，第一及第三晶体管T1及T3截止。由于没有通路，驱动电容CS的电压保持不变，即节点NG的电势被保持在(VDATA+VTH)，如此，在驱动电容CST所存储的能量的作用下，驱动晶体管TD也导通，第一电压VDD所产生的电流流过发光二极管DOLED以使其发光。通过背景技术里面提到的公式1可知，此时流过发光元件的电流：
IOLED＝1/2*β(VDATA+VTH-VTH)2
＝1/2*β(VDATA)2
从以上公式可看出，在发射阶段流过发光元件的电流只与数据信号VDATA有关，从而减小了阈值电压的变化对流过发光元件的电流影响。如 图8所示，本发明的5T1C结构与传统的2T1C结构相比，在相同的阈值电压VTH的变化下，电流变化明显降低，进而很好的改善显示面板8的亮度的均匀性。
优选地，请结合图7a及7b，还可具有第四阶段，即放电阶段，在该阶段，驱动电容CS向第二电源线放电。具体地，在放电阶段，像素电路70的运行情况如图7b所示，发射控制信号VEM为高电平，第一扫描信号VSCAN1、第二扫描信号VSCAN2及第三扫描信号VSCAN3都低电平。此时发射晶体管TE导通，而由于节点NG的电势被仍保持在(VDATA+VTH)，因此，驱动晶体管TD也导通，第一至第三晶体管T1、T2、T3截止。在原有的电势的作用下，发光二极管DOLED导通，从而使得节点ND及NS的电势被第二电压VSS拉低而逐渐变小。如此，可避免在下个周期的数据电压较低，即数据电压小于节点NS的电压的情况下，在所述下个周期补偿阶段中数据电压写入较慢甚至无法写入的情况，从而提高了响应速度，提升显示效果。
可选地，请结合图9，本发明另一实施方式的像素电路70’与上述实施方式的像素电路70的不同之处在于，省略了发射晶体管TE，如此，驱动晶体管TD直接连接至发光二极管DOLED。像素电路70’的驱动时序图如图10a所示，在充电阶段，节点NS的电压被充电至数据信号VDATA的电压，节点ND及NG的电压被充电至第一电压VDD的电压。具体地，第一扫描信号VSCAN1、第二扫描信号VSCAN2及第三扫描信号VSCAN3都为高电平，此时第一晶体管T1至第三晶体管T3导通，驱动晶体管TD因此也导通。此时第一电压VDD通过第二晶体管T2及第三晶体管T3传输到节点NG，即节点NG及ND都被充电至第一电压VDD。此时第一晶体管T1导通，节点NS的电势为数据信号VDATA的电压。第二阶段，即补偿阶段，节点ND 及NG被充电至(VDATA+VTH)，节点NS被充电至数据信号VDATA的电压。第三阶段，即发射阶段，晶体管T2及TD都导通，发光二极管DOLED发光。在第二及第三阶段，工作原理与具体工作过程与第一方式相同，在此不错赘述。当然，与第一实施方式的时序图相同，像素电路70’也可以在第三阶段后还包括一个放电阶段，其具体工作方式及原理也如上所述，在此不错赘述。
以上所述仅为本发明的较佳实施方式而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (14)

  1. 一种像素电路，包括：
    发光二极管；
    驱动晶体管；
    第一晶体管，其连接在一个数据线及该驱动晶体管之间，并且其栅极连接至一个第一扫描线；
    第二晶体管，其连接在一个第一电源线及该驱动晶体管之间，并且其栅极连接至一个第二扫描线；
    第三晶体管，其连接在该驱动晶体管的栅极与该第二晶体管之间，并且其栅极连接至一个第三扫描线；及
    驱动电容，其连接在该驱动晶体管的栅极及该第一电源线之间；其中，该驱动晶体管还通过该发光二级管连接至一个第二电源线。
  2. 如权利要求1所述的像素电路，其特征在于，该第一晶体管的漏极及源极分别连接该数据线及该驱动晶体管的源极。
  3. 如权利要求1所述的像素电路，其特征在于，该第一晶体管的漏极及源极分别连接该数据线及该驱动晶体管的源极。
  4. 如权利要求1所述的像素电路，其特征在于，该第二晶体管的漏极及源极分别连接该第一电源线及该驱动晶体管的漏极。
  5. 如权利要求1所述的像素电路，其特征在于，该第三晶体管的漏极及源极分别连接该驱动晶体管的漏极及栅极。
  6. 如权利要求1所述的像素电路，其特征在于，该驱动电容的两端分别连接至该驱动晶体管的栅极及该第一电源线。
  7. 如权利要求1所述的像素电路，其特征在于，还包括连接在该驱动晶体管与该发光二极管之间的发射晶体管，并且该发射晶体管的栅极连接至一个发射线。
  8. 如权利要求7所述的像素电路，其特征在于，该发射晶体管的漏极及源极分别连接该驱动晶体管的源极及该发光二极管的阳极，该发光二极管的阴极连接至该第二电源线。
  9. 一种显示面板，包括：
    多个阵列排布的如权利要求1至6任一项所述的像素电路；
    扫描驱动单元，用于分别向该第一至第三扫描线提供扫描信号；
    数据驱动单元，用于向该数据线提供数据信号；
    第一电源，用于向该第一电源线提供第一电源电压；及
    第二电源，用于向该第二电源线提供第二电源电压。
  10. 如权利要求9所述的显示面板，其特征在于，该像素电路还包括连接在该驱动晶体管与该发光二极管之间的发射晶体管，并且该发射晶体管的栅极连接至一个发射线；该显示面板还包括发射控制驱动单元，用于向该发射线提供发射控制信号。
  11. 一种像素电路的驱动方法，应用于如权利要求1至6任一项所述的像素电路，该驱动晶体管具有一个阈值电压，该驱动方法包括：
    使该第一至第三及驱动晶体管导通，该驱动电容两端的电势变为该第一电源线提供的第一电压；
    使该第一、第三及驱动晶体管导通，第二晶体管截止，该数据线通过该第一晶体管向该驱动晶体管输出一个数据电压，该驱动电容依次通过该第三、驱动及第一晶体管向数据线放电，直至该驱动电容与该驱动晶体管 连接一端的电势为该数据电压与该阈值电压之和；及
    使该第二晶体管导通，第一及第三晶体管截止，该驱动电容驱动该驱动晶体管导通进而使该第一电源线提供的第一电压驱动该发光元件发光。
  12. 如权利要求11所述的驱动方法，其特征在于，在该发光元件发光的步骤之后，还包括步骤：使第一至第三晶体管截止，驱动晶体管在驱动电容的驱动下导通，该驱动晶体管与该第一晶体管之间的一个连接节点的电压被拉低。
  13. 一种像素电路的驱动方法，应用于如权利要求7所述的像素电路，该驱动晶体管具有一个阈值电压，该驱动方法包括：
    使该第二及第三晶体管导通，该第一及发射晶体管截止，该电容两端的电势变为该第一电源线提供的第一电压值；
    使该第一、第三及驱动晶体管导通，第二晶体管截止，该数据线通过该第一晶体管向该驱动晶体管输出一个数据电压，该驱动电容依次通过该第三、驱动及第一晶体管向数据线放电，直至该驱动电容与该驱动晶体管连接一端的电势为该数据电压与该阈值电压之和；及
    使该第二晶体管导通，第一及第三晶体管截止，该驱动电容驱动该驱动晶体管导通进而使该第一电源线提供的第一电压驱动该发光元件发光。
  14. 如权利要求12所述的驱动方法，其特征在于，在该发光元件发光的步骤之后，还包括步骤：使第一至第三晶体管截止，驱动晶体管在驱动电容的驱动下导通，该驱动晶体管与该第一晶体管之间的一个连接节点的电压被拉低。
PCT/CN2015/086409 2015-08-07 2015-08-07 像素电路及其驱动方法、显示面板 WO2017024454A1 (zh)

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KR1020187001363A KR20180032560A (ko) 2015-08-07 2015-08-07 화소 회로 및 구동 방법, 디스플레이 패널
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