WO2017015542A1 - Backside stacked die in an integrated circuit (ic) package - Google Patents

Backside stacked die in an integrated circuit (ic) package Download PDF

Info

Publication number
WO2017015542A1
WO2017015542A1 PCT/US2016/043502 US2016043502W WO2017015542A1 WO 2017015542 A1 WO2017015542 A1 WO 2017015542A1 US 2016043502 W US2016043502 W US 2016043502W WO 2017015542 A1 WO2017015542 A1 WO 2017015542A1
Authority
WO
WIPO (PCT)
Prior art keywords
die
integrated circuit
die attach
substrate
mounting area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2016/043502
Other languages
French (fr)
Inventor
Hazel CABALLERO
Fernando Chen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microchip Technology Inc
Original Assignee
Microchip Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Technology Inc filed Critical Microchip Technology Inc
Priority to KR1020177033197A priority Critical patent/KR20180030772A/en
Priority to CN201680033174.5A priority patent/CN107743654A/en
Publication of WO2017015542A1 publication Critical patent/WO2017015542A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/427—Power or ground buses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/834—Interconnections on sidewalls of chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/231—Configurations of stacked chips the stacked chips being on both top and bottom sides of an auxiliary carrier having no electrical connection structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present disclosure relates to semiconductor manufacturing technology, in particular to a manufacturing method for providing multiple electrically active dies in a single IC package, e.g., by providing a backside stacking of one or more dies in an IC package.
  • IC dies may be mounted to a common substrate.
  • the footprint of each die may be important as the size requirements for IC devices are shrinking at the same time processing requirements are increasing. Redesigning a IC die/chip to increase performance and maintain or reduce footprint likely requires a new chip design, tooling a new mask, and/or additional costs and requirements.
  • One embodiment provides an integrated circuit (IC) device comprising: a substrate including a first mounting area and a ground ring, a first integrated circuit die attached to the first mounting area, a die attach paddle mounted onto the ground ring and extending above the first integrated circuit die, and a second integrated circuit die mounted on a second mounting area, wherein the die attach paddle defines the second mounting area above the first integrated circuit die.
  • the second integrated circuit die includes a backside oriented toward the substrate and connected to ground.
  • the IC device further comprises a conductive die attach material joining the die attach paddle to the substrate.
  • the first integrated circuit die and the second integrated circuit die have matching footprints.
  • first integrated circuit die and the second integrated circuit die comprise identical devices. In one embodiment, the first integrated circuit die and the second integrated circuit die comprise 4-channel pulsers.
  • the first mounting area comprises an exposed die attach pad.
  • leads of the first and second integrated circuit dies are connected to the substrate using wirebond.
  • the die attach paddle is attached to the ground ring with a copper clip.
  • Another embodiment provides a method for manufacturing a stacked integrated circuit device, the method comprising: attaching a first die to a substrate having an exposed die attach pad, connecting an external die attach paddle to the substrate, the external die attach paddle extending over the first die, and attaching a second die to the external die attach paddle.
  • the method further includes connecting leads of the first die to leads of the substrate by wire bonding.
  • the method further includes connecting leads of the second die to leads of the substrate by wire bonding. In one embodiment, the method further includes attaching the first and second dies using conductive die attach material.
  • the external die attach paddle provides a backside connection to ground for the second die.
  • connecting an external die attach paddle to the substrate includes using conductive die attach material.
  • the first and second dies comprise matching integrated circuit devices.
  • the first and second dies comprise 4-channel pulsers.
  • the first and second dies have matching footprints.
  • an 8-channel pulser comprising: a substrate including a first mounting area and a ground ring, a first 4-channel pulser attached to the first mounting area, and a die attach paddle mounted onto the ground ring and extending above the first 4- channel pulser, and a second 4-channel pulser mounted on a second mounting area, wherein the die attach paddle defines the second mounting area above the first 4-channel pulser.
  • the 8-channel pulser further includes a backside of the second 4- channel pulser connected to ground through the die attach paddle.
  • Figure 1 is a drawing illustrating a side view of an example integrated circuit device according to teachings of the present disclosure
  • Figure 2 is a flowchart illustrating an example method according to teachings of the present disclosure.
  • a copper clip may be mounted on top of a first die (the bottom die) and then used as a die attach paddle for the top die.
  • FIG. 1 is a drawing illustrating a side view of an example integrated circuit device 10 according to teachings of the present disclosure.
  • Integrated circuit device 10 may include a substrate 20, a first IC die 30, an external die attach paddle 40, and a second IC die 50.
  • substrate 20 may include solder balls 22 and an exposed die attach pad 24.
  • Substrate 20 may comprise any appropriate material (e.g., silicon or other semiconductor).
  • substrate 20 may include features arranged to mate with a socket or other mounting apparatus deployed on a printed circuit board (PCB).
  • PCB printed circuit board
  • Exposed die attach pad 24 may have any features appropriate for mounting an IC die thereon, including exposed leads, a thermal/heat sink pad, etc.
  • substrate 20 may include alternative features for attaching an IC die.
  • the substrate design may include exposed die attach pad 24 with a soldermask mesh design.
  • First IC die 30 may be attached to the substrate 20 (e.g., attached to the exposed die attach pad 24).
  • IC die 30 may comprise a set of electronic circuits on a plate of semiconductor material (e.g., silicon).
  • IC die 30 may be any size, shape, or useful configuration.
  • first IC die 30 may be attached to the substrate with die attach material 32.
  • Die attach material 32 may be a conductive material (e.g., a paste or a film) providing both electrical and mechanical connection between first IC die 30 and exposed die attach pad 24 or the other features of substrate 20.
  • various leads of first IC die 30 may be connected to leads on substrate 20 and/or die attach pad 24 by wire bonding. As shown in Fig.
  • bond wires 34 provide electrical connection between first IC die 30 and leads on substrate 20.
  • IC die 30 may comprise a 4-channel pulser.
  • External die attach paddle 40 may comprise any apparatus or device appropriate for attachment to the substrate 20 and providing a mount for the second IC die 50.
  • external die attach paddle 40 comprises a copper clip.
  • the copper clip is connected to various feature of substrate 20 and attached using die attach material 42 (e.g., conductive paste or film), then the second IC die 50 is placed on the copper clip and attached using die attach material 52 (e.g., conductive paste/film).
  • Substrate 20 may include a ground ring to serve as pad for a copper clip to establish the multi-layer die attach pad.
  • the external die attach paddle 40 provides a second die attach pad allowing a stacked die package.
  • the external die attach paddle 40 provide this additional layer of die attach pad allowing the top die (second IC die 50) to be grounded at its backside.
  • Die attach material 42 attaches the external die attach paddle 40 to the substrate.
  • a conductive die attach material 42 provides a ground connection to both the top and bottom die.
  • Second IC die 50 may be attached to the external die attach paddle 40 (e.g., attached to an exposed die attach pad disposed thereon).
  • IC die 50 may comprise a set of electronic circuits on a plate of semiconductor material (e.g. , silicon).
  • IC die 50 may be any size, shape, or useful configuration.
  • second IC die 50 may be attached to the external die paddle 40 with die attach material 52.
  • Die attach material 52 may be a conductive material (e.g., a paste or a film) providing both electrical and mechanical connection between second IC die 50 and external die attach paddle 40 or the features thereon.
  • various leads of second IC die 50 may be connected to leads on substrate 20 and/or die attach pad 24 by wire bonding. As shown in Fig. 1, bond wires 54 provide electrical connection between second IC die 50 and leads on substrate 20.
  • IC die 50 may comprise a 4-channel pulser.
  • the two IC dies 30, 50 may have similar or identical function and form.
  • Integrated circuit device 10 may provide, for example, two stacked IC dies 30, 50 each comprising a four-channel feature of any type of functionality (e.g., driver, pulser, etc.).
  • the stacked formation incorporating teachings of the present disclosure may provide a IC device 10 with the same footprint as the four-channel device, but with 8-channel function. Instead of designing a completely new integrated circuit or doubling the required footprint, these teachings may be used to integrate two existing integrated circuit dies in a single package and wire them internally to provide for their respective functionality in a single device.
  • a certain integrated circuit device may be currently offered in a 64L QFN 9x9mm package. There may be a demand for the same functionality with twice the number of devices or channels. Rather than employing a new design for the desired device, for example an eight-channel pulser, a double stack of the original IC device may offer two four-channel pulser dies in one package, delivering an eight-channel pulser in a smaller package and without a new IC design.
  • the footprint of the device is not enlarged.
  • the ground connection provided by the external die attach paddle 40 may be required for certain standards and/or applications (e.g., SOI wafers).
  • a side-by-side solution may satisfy the grounding requirement, but the package size will be at least 60% larger compared to the stacked die solution described herein.
  • the multi-layer external die attach paddle 40 allows for an arrangement of multiple dies above each other while still providing ground connection for each die in order to achieve the reduced package size without redesigning the die and/or tooling a new mask set.
  • IC housings incorporating a support structure allowing for placement of an external die attach paddle as shown in Fig. 1.
  • a leadframe design may provide an area onto which such a paddle can be attached.
  • the stack may be extended to more than two semiconductor dies.
  • two U-shaped die attach paddles 40 may be arranged above each other in a 90 degree configuration.
  • first 30 and second 50 integrated circuit dies can be identical. However, other embodiments may integrate two different integrated circuit dies within a single package.
  • the two integrated circuit devices may have different sizes, wherein preferably the smaller die is arranged on top of the larger die.
  • Step 110 may include attaching a first IC die 30 to a substrate 20 having an exposed die attach pad 24.
  • the first IC die 30 may be attached using die attach material 32, e.g., a conductive film and/or paste, as described above.
  • Step 112 may include connecting leads from the first IC die 30 to leads on the substrate. In some embodiments, this may include wire bonding.
  • Step 114 may include connecting an external die attach paddle 40 to the substrate 20.
  • the external die attach paddle 40 may extend over the first die.
  • the external die attach paddle 40 may be attached using die attach material 42, e.g., a conductive film and/or paste, as described above.
  • Step 116 may include attaching a second IC die 50 to the external die attach paddle 40.
  • the second IC die 50 may be attached using die attach material 52, e.g., a conductive paste and/or film.
  • the connection of second IC die 50 to the external die attach paddle 40 may provide a backside connection to ground (on the substrate) for the second IC die 50.
  • Step 118 may include connecting leads from the second IC die 50 to leads of the substrate 20. In some embodiments, this step may include wire bonding.
  • Method 100 may include any finishing processes known in the manufacture of semiconductors and/or IC devices. For example, standard end of line assembly processes such as mold, marking, and singulation may follow Step 118.
  • the first 30 and second die 50 may comprise matching integrated circuit devices.
  • matching IC devices may have similar footprints and/or function, etc.
  • the first and second die are both 4-channel pulsers, providing the function of an 8-channel pulser in the same footprint that previously held a single 4-channel pulser, with the burden of redesigning the IC circuit or retooling the manufacturing process.

Landscapes

  • Die Bonding (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

An integrated circuit (IC) device may include a substrate including a first mounting area and a ground ring, a first integrated circuit die attached to the first mounting area, a die attach paddle mounted onto the ground ring and extending above the first integrated circuit die, and a second integrated circuit die mounted on a second mounting area, wherein the die attach paddle defines the second mounting area above the first integrated circuit die. The second integrated circuit die may have a backside oriented toward the substrate and connected to ground.

Description

BACKSIDE STACKED DIE IN AN INTEGRATED CIRCUIT (IC) PACKAGE
RELATED PATENT APPLICATION This application claims priority to commonly owned U.S. Provisional Patent
Application No. 62/195,670, filed July 22, 2015, the entire contents of which are hereby incorporated by reference herein for all purposes.
TECHNICAL FIELD
The present disclosure relates to semiconductor manufacturing technology, in particular to a manufacturing method for providing multiple electrically active dies in a single IC package, e.g., by providing a backside stacking of one or more dies in an IC package.
BACKGROUND
In semiconductor manufacturing, multiple integrated circuit (IC) dies may be mounted to a common substrate. The footprint of each die may be important as the size requirements for IC devices are shrinking at the same time processing requirements are increasing. Redesigning a IC die/chip to increase performance and maintain or reduce footprint likely requires a new chip design, tooling a new mask, and/or additional costs and requirements.
SUMMARY
One embodiment provides an integrated circuit (IC) device comprising: a substrate including a first mounting area and a ground ring, a first integrated circuit die attached to the first mounting area, a die attach paddle mounted onto the ground ring and extending above the first integrated circuit die, and a second integrated circuit die mounted on a second mounting area, wherein the die attach paddle defines the second mounting area above the first integrated circuit die. In one embodiment, the second integrated circuit die includes a backside oriented toward the substrate and connected to ground.
In one embodiment, the IC device further comprises a conductive die attach material joining the die attach paddle to the substrate. In one embodiment, the first integrated circuit die and the second integrated circuit die have matching footprints.
In one embodiment, the first integrated circuit die and the second integrated circuit die comprise identical devices. In one embodiment, the first integrated circuit die and the second integrated circuit die comprise 4-channel pulsers.
In one embodiment, the first mounting area comprises an exposed die attach pad.
In one embodiment, leads of the first and second integrated circuit dies are connected to the substrate using wirebond. In one embodiment, the die attach paddle is attached to the ground ring with a copper clip.
Another embodiment provides a method for manufacturing a stacked integrated circuit device, the method comprising: attaching a first die to a substrate having an exposed die attach pad, connecting an external die attach paddle to the substrate, the external die attach paddle extending over the first die, and attaching a second die to the external die attach paddle.
In one embodiment, the method further includes connecting leads of the first die to leads of the substrate by wire bonding.
In one embodiment, the method further includes connecting leads of the second die to leads of the substrate by wire bonding. In one embodiment, the method further includes attaching the first and second dies using conductive die attach material.
In one embodiment, the external die attach paddle provides a backside connection to ground for the second die.
In one embodiment, connecting an external die attach paddle to the substrate includes using conductive die attach material. In one embodiment, the first and second dies comprise matching integrated circuit devices.
In one embodiment, the first and second dies comprise 4-channel pulsers.
In one embodiment, the first and second dies have matching footprints. Another embodiment provides an 8-channel pulser comprising: a substrate including a first mounting area and a ground ring, a first 4-channel pulser attached to the first mounting area, and a die attach paddle mounted onto the ground ring and extending above the first 4- channel pulser, and a second 4-channel pulser mounted on a second mounting area, wherein the die attach paddle defines the second mounting area above the first 4-channel pulser. In one embodiment, the 8-channel pulser further includes a backside of the second 4- channel pulser connected to ground through the die attach paddle.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 is a drawing illustrating a side view of an example integrated circuit device according to teachings of the present disclosure; and Figure 2 is a flowchart illustrating an example method according to teachings of the present disclosure.
DETAILED DESCRIPTION
Although stacking IC dies may provide a reduced total footprint, known methods for stacking do not provide a ground connection for the backside of the upper or top die. In some embodiments of the present teaching, a copper clip may be mounted on top of a first die (the bottom die) and then used as a die attach paddle for the top die.
Figure 1 is a drawing illustrating a side view of an example integrated circuit device 10 according to teachings of the present disclosure. Integrated circuit device 10 may include a substrate 20, a first IC die 30, an external die attach paddle 40, and a second IC die 50. In this embodiment, the backside of both first IC die 30 (on the bottom) and second IC die 50 (on the top) are ground connected. As shown, substrate 20 may include solder balls 22 and an exposed die attach pad 24. Substrate 20 may comprise any appropriate material (e.g., silicon or other semiconductor). In some embodiments, substrate 20 may include features arranged to mate with a socket or other mounting apparatus deployed on a printed circuit board (PCB). Exposed die attach pad 24 may have any features appropriate for mounting an IC die thereon, including exposed leads, a thermal/heat sink pad, etc. In some embodiments, substrate 20 may include alternative features for attaching an IC die. The substrate design may include exposed die attach pad 24 with a soldermask mesh design.
First IC die 30 may be attached to the substrate 20 (e.g., attached to the exposed die attach pad 24). IC die 30 may comprise a set of electronic circuits on a plate of semiconductor material (e.g., silicon). IC die 30 may be any size, shape, or useful configuration. In some embodiments, such as that shown in Fig. 1, first IC die 30 may be attached to the substrate with die attach material 32. Die attach material 32 may be a conductive material (e.g., a paste or a film) providing both electrical and mechanical connection between first IC die 30 and exposed die attach pad 24 or the other features of substrate 20. In some embodiments, various leads of first IC die 30 may be connected to leads on substrate 20 and/or die attach pad 24 by wire bonding. As shown in Fig. 1, bond wires 34 provide electrical connection between first IC die 30 and leads on substrate 20. In some embodiments, IC die 30 may comprise a 4-channel pulser. External die attach paddle 40 may comprise any apparatus or device appropriate for attachment to the substrate 20 and providing a mount for the second IC die 50. In some embodiments, external die attach paddle 40 comprises a copper clip. In these embodiments, the copper clip is connected to various feature of substrate 20 and attached using die attach material 42 (e.g., conductive paste or film), then the second IC die 50 is placed on the copper clip and attached using die attach material 52 (e.g., conductive paste/film). Substrate 20 may include a ground ring to serve as pad for a copper clip to establish the multi-layer die attach pad.
As shown in Fig. 1, the external die attach paddle 40 provides a second die attach pad allowing a stacked die package. The external die attach paddle 40 provide this additional layer of die attach pad allowing the top die (second IC die 50) to be grounded at its backside. Die attach material 42 attaches the external die attach paddle 40 to the substrate. In some embodiments, a conductive die attach material 42 provides a ground connection to both the top and bottom die.
Second IC die 50 may be attached to the external die attach paddle 40 (e.g., attached to an exposed die attach pad disposed thereon). IC die 50 may comprise a set of electronic circuits on a plate of semiconductor material (e.g. , silicon). IC die 50 may be any size, shape, or useful configuration. In some embodiments, such as that shown in Fig. 1, second IC die 50 may be attached to the external die paddle 40 with die attach material 52. Die attach material 52 may be a conductive material (e.g., a paste or a film) providing both electrical and mechanical connection between second IC die 50 and external die attach paddle 40 or the features thereon. In some embodiments, various leads of second IC die 50 may be connected to leads on substrate 20 and/or die attach pad 24 by wire bonding. As shown in Fig. 1, bond wires 54 provide electrical connection between second IC die 50 and leads on substrate 20. In some embodiments, IC die 50 may comprise a 4-channel pulser. In some embodiments, the two IC dies 30, 50 may have similar or identical function and form. Integrated circuit device 10 may provide, for example, two stacked IC dies 30, 50 each comprising a four-channel feature of any type of functionality (e.g., driver, pulser, etc.). The stacked formation incorporating teachings of the present disclosure may provide a IC device 10 with the same footprint as the four-channel device, but with 8-channel function. Instead of designing a completely new integrated circuit or doubling the required footprint, these teachings may be used to integrate two existing integrated circuit dies in a single package and wire them internally to provide for their respective functionality in a single device.
For example, a certain integrated circuit device may be currently offered in a 64L QFN 9x9mm package. There may be a demand for the same functionality with twice the number of devices or channels. Rather than employing a new design for the desired device, for example an eight-channel pulser, a double stack of the original IC device may offer two four-channel pulser dies in one package, delivering an eight-channel pulser in a smaller package and without a new IC design.
In a stacked configuration according to the teachings of the present disclosure, the footprint of the device is not enlarged. In addition, the ground connection provided by the external die attach paddle 40 may be required for certain standards and/or applications (e.g., SOI wafers). A side-by-side solution may satisfy the grounding requirement, but the package size will be at least 60% larger compared to the stacked die solution described herein. Thus, in some embodiments, the multi-layer external die attach paddle 40 allows for an arrangement of multiple dies above each other while still providing ground connection for each die in order to achieve the reduced package size without redesigning the die and/or tooling a new mask set.
These teachings can be employed with additional types of IC housings incorporating a support structure allowing for placement of an external die attach paddle as shown in Fig. 1. For example, a leadframe design may provide an area onto which such a paddle can be attached. The stack may be extended to more than two semiconductor dies. In embodiments including a U-shaped die attach paddle, two U-shaped die attach paddles 40 may be arranged above each other in a 90 degree configuration.
As previously noted, the first 30 and second 50 integrated circuit dies can be identical. However, other embodiments may integrate two different integrated circuit dies within a single package. The two integrated circuit devices may have different sizes, wherein preferably the smaller die is arranged on top of the larger die.
Figure 2 is a flowchart illustrating an example method 100 for manufacturing a stacked integrated circuit device according to teachings of the present disclosure. Method 100 may comprise any of the following steps, performed in any suitable order. Step 110 may include attaching a first IC die 30 to a substrate 20 having an exposed die attach pad 24. The first IC die 30 may be attached using die attach material 32, e.g., a conductive film and/or paste, as described above.
Step 112 may include connecting leads from the first IC die 30 to leads on the substrate. In some embodiments, this may include wire bonding. Step 114 may include connecting an external die attach paddle 40 to the substrate 20.
The external die attach paddle 40 may extend over the first die. The external die attach paddle 40 may be attached using die attach material 42, e.g., a conductive film and/or paste, as described above. Step 116 may include attaching a second IC die 50 to the external die attach paddle 40. The second IC die 50 may be attached using die attach material 52, e.g., a conductive paste and/or film. In embodiments including this step, the connection of second IC die 50 to the external die attach paddle 40 may provide a backside connection to ground (on the substrate) for the second IC die 50.
Step 118 may include connecting leads from the second IC die 50 to leads of the substrate 20. In some embodiments, this step may include wire bonding.
Method 100 may include any finishing processes known in the manufacture of semiconductors and/or IC devices. For example, standard end of line assembly processes such as mold, marking, and singulation may follow Step 118.
As described in relation to Fig. 1, the first 30 and second die 50 may comprise matching integrated circuit devices. According to the teachings of the present disclosure, matching IC devices may have similar footprints and/or function, etc. For example, in some embodiments, the first and second die are both 4-channel pulsers, providing the function of an 8-channel pulser in the same footprint that previously held a single 4-channel pulser, with the burden of redesigning the IC circuit or retooling the manufacturing process.

Claims

1. An integrated circuit device comprising:
a substrate including a first mounting area and a ground ring;
a first integrated circuit die attached to the first mounting area;
a die attach paddle mounted onto the ground ring and extending above the first integrated circuit die; and
a second integrated circuit die mounted on a second mounting area;
wherein the die attach paddle defines the second mounting area above the first integrated circuit die.
2. An integrated circuit device according to Claim 1, wherein the second integrated circuit die includes a backside oriented toward the substrate and connected to ground.
3. An integrated circuit device according to Claim 1 or Claim 2, further comprising a conductive die attach material joining the die attach paddle to the substrate.
4. An integrated circuit device according to one of the preceding Claims, wherein the first integrated circuit die and the second integrated circuit die have matching footprints.
5. An integrated circuit device according to one of the preceding Claims, wherein the first integrated circuit die and the second integrated circuit die comprise identical devices.
6. An integrated circuit device according to one of the preceding Claims, wherein the first integrated circuit die and the second integrated circuit die comprise 4-channel pulsers.
7. An integrated circuit device according to one of the preceding Claims, wherein the first mounting area comprises an exposed die attach pad.
8. An integrated circuit device according to one of the preceding Claims, wherein leads of the first and second integrated circuit dies are connected to the substrate using wirebond.
9. An integrated circuit device according to one of the preceding Claims, wherein the die attach paddle is attached to the ground ring with a copper clip.
10. A method for manufacturing a stacked integrated circuit device, the method comprising:
attaching a first die to a substrate having an exposed die attach pad;
connecting an external die attach paddle to the substrate, the external die attach paddle extending over the first die;
attaching a second die to the external die attach paddle.
11. A method according to Claim 10, further comprising connecting leads of the first die to leads of the substrate by wire bonding.
12. A method according to Claim 10 or Claim 11, further comprising connecting leads of the second die to leads of the substrate by wire bonding.
13. A method according to one of Claims 10 - 12, further comprising attaching the first and second dies using conductive die attach material.
14. A method according to one of Claims 10 - 13, wherein the external die attach paddle provides a backside connection to ground for the second die.
15. A method according to one of Claims 10 - 14, wherein connecting an external die attach paddle to the substrate includes using conductive die attach material.
16. A method according to one of Claims 10 - 15, wherein the first and second die comprise matching integrated circuit devices.
17. A method according to one of Claims 10 - 16, wherein the first and second dies comprise 4-channel pulsers.
18. A method according to one of Claims 10 - 17, wherein the first and second dies have matching footprints.
19. An 8-channel pulser, comprising:
a substrate including a first mounting area and a ground ring;
a first 4-channel pulser attached to the first mounting area; and
a die attach paddle mounted onto the ground ring and extending above the first 4- channel pulser; and
a second 4-channel pulser mounted on a second mounting area;
wherein the die attach paddle defines the second mounting area above the first 4- channel pulser.
20. An 8-channel pulser according to Claim 19, further comprising a backside of the second 4-channel pulser connected to ground through the die attach paddle.
PCT/US2016/043502 2015-07-22 2016-07-22 Backside stacked die in an integrated circuit (ic) package Ceased WO2017015542A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
KR1020177033197A KR20180030772A (en) 2015-07-22 2016-07-22 A backside stacked die of an integrated circuit (IC)
CN201680033174.5A CN107743654A (en) 2015-07-22 2016-07-22 Dorsal part stacked die in integrated circuit (IC) encapsulation

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201562195670P 2015-07-22 2015-07-22
US62/195,670 2015-07-22
US15/215,743 2016-07-21
US15/215,743 US20170025388A1 (en) 2015-07-22 2016-07-21 Backside Stacked Die In An Integrated Circuit (IC) Package

Publications (1)

Publication Number Publication Date
WO2017015542A1 true WO2017015542A1 (en) 2017-01-26

Family

ID=56684735

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2016/043502 Ceased WO2017015542A1 (en) 2015-07-22 2016-07-22 Backside stacked die in an integrated circuit (ic) package

Country Status (5)

Country Link
US (1) US20170025388A1 (en)
KR (1) KR20180030772A (en)
CN (1) CN107743654A (en)
TW (1) TW201709470A (en)
WO (1) WO2017015542A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11616048B2 (en) 2019-06-12 2023-03-28 Texas Instruments Incorporated IC package with multiple dies

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030210533A1 (en) * 2002-05-09 2003-11-13 Samsung Electronics Co., Ltd. Multi-chip package having improved heat spread characteristics and method for manufacturing the same
US20040051170A1 (en) * 2002-09-18 2004-03-18 Satoko Kawakami Semiconductor device and method of manufacturing the same
US20040063246A1 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages
US20060118939A1 (en) * 2004-12-03 2006-06-08 Fisher Rayette A Stacked electronics for sensors
US7271470B1 (en) * 2006-05-31 2007-09-18 Infineon Technologies Ag Electronic component having at least two semiconductor power devices
US20080029869A1 (en) * 2006-08-01 2008-02-07 Samsung Electronics Co., Ltd. Vertical stack type multi-chip package having improved grounding performance and lower semiconductor chip reliability
US20080238532A1 (en) * 2007-03-30 2008-10-02 Satoshi Hanazawa Semiconductor integrated circuit device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6737750B1 (en) * 2001-12-07 2004-05-18 Amkor Technology, Inc. Structures for improving heat dissipation in stacked semiconductor packages
TW523894B (en) * 2001-12-24 2003-03-11 Siliconware Precision Industries Co Ltd Semiconductor device and its manufacturing method
US7479407B2 (en) * 2002-11-22 2009-01-20 Freescale Semiconductor, Inc. Digital and RF system and method therefor
TWI235469B (en) * 2003-02-07 2005-07-01 Siliconware Precision Industries Co Ltd Thermally enhanced semiconductor package with EMI shielding
US7205651B2 (en) * 2004-04-16 2007-04-17 St Assembly Test Services Ltd. Thermally enhanced stacked die package and fabrication method
US8569870B1 (en) * 2012-06-25 2013-10-29 Stats Chippac Ltd. Integrated circuit packaging system with shielding spacer and method of manufacture thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030210533A1 (en) * 2002-05-09 2003-11-13 Samsung Electronics Co., Ltd. Multi-chip package having improved heat spread characteristics and method for manufacturing the same
US20040063246A1 (en) * 2002-09-17 2004-04-01 Chippac, Inc. Semiconductor multi-package module having package stacked over die-down flip chip ball grid array package and having wire bond interconnect between stacked packages
US20040051170A1 (en) * 2002-09-18 2004-03-18 Satoko Kawakami Semiconductor device and method of manufacturing the same
US20060118939A1 (en) * 2004-12-03 2006-06-08 Fisher Rayette A Stacked electronics for sensors
US7271470B1 (en) * 2006-05-31 2007-09-18 Infineon Technologies Ag Electronic component having at least two semiconductor power devices
US20080029869A1 (en) * 2006-08-01 2008-02-07 Samsung Electronics Co., Ltd. Vertical stack type multi-chip package having improved grounding performance and lower semiconductor chip reliability
US20080238532A1 (en) * 2007-03-30 2008-10-02 Satoshi Hanazawa Semiconductor integrated circuit device

Also Published As

Publication number Publication date
CN107743654A (en) 2018-02-27
US20170025388A1 (en) 2017-01-26
KR20180030772A (en) 2018-03-26
TW201709470A (en) 2017-03-01

Similar Documents

Publication Publication Date Title
US20240332159A1 (en) Semiconductor package and manufacturing method thereof
US10720406B2 (en) Stacked semiconductor system having interposer of half-etched and molded sheet metal
US9123626B1 (en) Integrated passive flip chip package
CN101350318B (en) Electronic package and electronic device
US9859196B2 (en) Electronic device with periphery contact pads surrounding central contact pads
US6903449B2 (en) Semiconductor component having chip on board leadframe
US11004776B2 (en) Semiconductor device with frame having arms and related methods
US11227818B2 (en) Stacked dies electrically connected to a package substrate by lead terminals
CN110034078B (en) Package embedded structure for semiconductor device and manufacturing method
CN104979323A (en) Quad flat no-lead package and manufacturing method thereof
US8283757B2 (en) Quad flat package with exposed common electrode bars
US20080073763A1 (en) Semiconductor device and method of manufacturing the same
US7768104B2 (en) Apparatus and method for series connection of two die or chips in single electronics package
US20170018487A1 (en) Thermal enhancement for quad flat no lead (qfn) packages
CN115995395A (en) Package with separate lid for heat sink and EMI shielding
US20230068748A1 (en) Leaded semiconductor device package
US20130045572A1 (en) Flexible routing for high current module application
US20170025388A1 (en) Backside Stacked Die In An Integrated Circuit (IC) Package
KR20180062479A (en) Semiconductor package and a method of manufacturing the same
US7282395B2 (en) Method of making exposed pad ball grid array package
TWI757133B (en) Quad flat no-lead package structure
US10796931B2 (en) Manufacturing method of package structure
US20120286409A1 (en) Utilizing a jumper chip in packages with long bonding wires
US20250372493A1 (en) Electronic device with interior and peripheral leads

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16751400

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 20177033197

Country of ref document: KR

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16751400

Country of ref document: EP

Kind code of ref document: A1