WO2016206123A1 - Cmos master and slave sample and hold circuit - Google Patents
Cmos master and slave sample and hold circuit Download PDFInfo
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- WO2016206123A1 WO2016206123A1 PCT/CN2015/082601 CN2015082601W WO2016206123A1 WO 2016206123 A1 WO2016206123 A1 WO 2016206123A1 CN 2015082601 W CN2015082601 W CN 2015082601W WO 2016206123 A1 WO2016206123 A1 WO 2016206123A1
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- nmos transistor
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- hold circuit
- transistor
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/50—Analogue/digital converters with intermediate conversion to time interval
- H03M1/54—Input signal sampled and held with linear return to datum
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- the invention belongs to the field of analog/mixed signal integrated circuits, and in particular relates to a CMOS master-slave sample-and-hold circuit.
- CMOS Complementary Metal Oxide Semiconductor
- CMOS sample-and-hold circuits are widely used in analog-to-digital converter front ends to sample the instantaneous value of an analog signal and hold it for a period of time. During this time, the analog-to-digital converter will process a constant signal, which greatly improves the accuracy and accuracy of the analog-to-digital converter.
- CMOS single-stage sample-and-hold circuit for an analog-to-digital converter front end, comprising an NMOS transistor Ns, a sampling capacitor Cd, an NMOS transistor Ns serving as a sampling switch, and a gate connected to a clock signal CLK, a source
- the pole is connected to the analog signal SIN
- the drain is connected to the upper plate of the sampling capacitor Cd and the signal SOUT is output
- the lower plate of the sampling capacitor Cd is grounded.
- the NMOS transistor Ns when the clock signal CLK is at a high level, the NMOS transistor Ns is turned on, and the upper plate SOUT of the sampling capacitor Cd is connected to the analog signal SIN, and the upper plate SOUT of the sampling capacitor Cd follows the analog signal SIN.
- the clock signal CLK is at a low level, the NMOS transistor Ns is turned off, and the electrical connection between the upper plate SOUT of the sampling capacitor Cd and the analog signal SIN is turned off. Since the sampling capacitor Cd has charge retention capability, the upper plate of the sampling capacitor Cd will sample and maintain the instantaneous value of the analog signal at the falling edge of the clock.
- the sample-and-hold circuit can keep the signal unchanged for half a clock cycle, and is also affected by non-ideal effects such as charge injection and non-linear on-resistance, so it cannot meet the needs of high-speed and high-precision analog-to-digital converters.
- the present invention provides a novel CMOS master-slave sample-and-hold circuit for the prior art CMOS single-stage sample-and-hold circuit that maintains the signal constant for only half a clock cycle.
- a CMOS master-slave sample-and-hold circuit includes:
- An input buffer amplifier adapted to receive and buffer an externally input analog signal and drive the main sample and hold circuit
- a main sample and hold circuit adapted to sample and hold an output signal of the input buffer amplifier and output a first sampling signal
- An interstage buffer amplifier adapted to receive and buffer the first sampled signal and drive the slave sample and hold circuit
- the sample-and-hold circuit is adapted to sample and hold an output signal of the interstage buffer amplifier, and output a second sampling signal, and the second sampling signal is a final output signal of the CMOS master-slave sample-and-hold circuit;
- a clock circuit adapted to receive an external clock signal to generate a first internal clock signal and a second internal clock signal, the first internal clock signal and the second internal clock signal being a pair of non-overlapping clock signals, and the first internal
- the clock signal is used to provide a clock signal to the main sample and hold circuit
- the second internal clock signal is used to provide a clock signal to the sample and hold circuit.
- the clock circuit In the CMOS master-slave sample-and-hold circuit provided by the present invention, the clock circuit generates a pair of non-overlapping first internal clock signals and a second internal clock signal, and the first internal clock signal is used to provide a clock signal to the main sample and hold circuit.
- the second internal clock signal is used to give
- the sample-and-hold circuit provides a clock signal, so that the main sample-and-hold circuit and the hold-sampling circuit maintain a two-stage hold circuit capable of maintaining the signal for the entire clock cycle; and an input buffer amplifier for receiving and buffering the external input.
- an interstage buffer amplifier is inserted between the two stages of sample and hold circuits to isolate the main sample and hold circuit and the sample capacitor from the sample and hold circuit to prevent charge sharing effects.
- the invention is applied to the front end of an analog-to-digital converter, which can greatly improve the performance of the analog-to-digital converter.
- the input buffer amplifier is in the form of a single-ended circuit, including a first NMOS transistor and a second NMOS transistor, the first NMOS transistor is a working transistor, and the gate thereof receives an externally input analog signal, and the source output is buffered.
- An analog signal, the drain is connected to the power supply VCC;
- the second NMOS transistor is a bias transistor, the drain thereof is connected to the source of the first NMOS transistor, the bias current is supplied to the first NMOS transistor, the source is grounded, and the gate is connected A bias voltage.
- main sample-and-hold circuit and the slave sample-and-hold circuit are both in the form of a single-ended circuit and have the same circuit structure, including a sampling switch and a sampling capacitor.
- the lower plate of the sampling capacitor is grounded, and the upper plate is connected to the sampling switch.
- the other end of the sampling switch is connected to the input signal, and the control end of the sampling switch is connected to the internal clock signal, and the upper plate signal of the sampling capacitor is used as the output sampling signal of the master-slave sampling and holding circuit.
- the sampling switch is a bootstrap switch, including a first inverter, a second inverter, a third inverter, a fourth inverter, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor a sixth NMOS transistor, a seventh NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a capacitor, and a main switching transistor; a source of the main switching transistor is connected to an input signal, and a drain is connected to the sampling
- the upper plate of the capacitor is connected to the gates of the sixth NMOS transistor, the seventh NMOS transistor and the third PMOS transistor, and the input end of the first inverter is connected to the internal clock signal, the output terminal and the second inverter are The input end of the third inverter is connected, the output end of the second inverter is connected to the source of the third NMOS transistor, and the third inverter The output end is connected to the input end of the fourth inverter, the
- the interstage buffer amplifier is in the form of a single-ended circuit, and includes an eighth NMOS transistor, a ninth NMOS transistor, a first resistor, and a second resistor, the eighth NMOS transistor being a working transistor, and a gate and a main
- the first sampling signal outputted by the sample-and-hold circuit is connected, the first sampling signal after the buffer is buffered, the source is connected to one end of the first resistor, and the other end of the first resistor is grounded;
- the ninth NMOS transistor is a load transistor The gate is connected to the second bias voltage, the drain is connected to the power source VCC, the source is connected to one end of the second resistor, and the other end of the second resistor is connected to the drain of the eighth NMOS transistor.
- the transconductance of the eighth NMOS transistor and the ninth NMOS transistor are equal, and the resistances of the first resistor and the second resistor are equal.
- the clock circuit includes a first NAND gate, a second NAND gate, a fifth inverter, a sixth inverter, a seventh inverter, and a digital buffer, the fifth inverter and the digital
- the input end of the buffer receives an external clock signal
- the output of the fifth inverter is connected to the first input of the first NAND gate
- the output of the digital buffer and the first input of the second NAND gate End connection the output of the first NAND gate is connected to the input of the sixth inverter and the second input of the second NAND gate
- the output of the second NAND gate and the input of the seventh inverter And connected to the second input end of the first NAND gate
- the output end of the sixth inverter outputs a first internal clock signal
- the output end of the seventh inverter outputs a second internal clock signal.
- the input buffer amplifier is in the form of a differential circuit comprising two single-ended circuits, the two single-ended circuits respectively for processing a positive phase portion and an inverting portion of the differential signal, each single-ended circuit including the first An NMOS transistor and a second NMOS transistor, wherein the first NMOS transistor is a working transistor, a gate thereof receives an externally input analog signal, a source outputs a buffered analog signal, and a drain is connected to the power source VCC; the second NMOS transistor is The bias transistor has a drain connected to the source of the first NMOS transistor, a bias current for the first NMOS transistor, a source grounded, and a gate connected to the first bias voltage.
- each single-ended circuit includes a sampling switch and a sampling capacitor, the lower plate of the sampling capacitor is grounded, the upper plate is connected to one end of the sampling switch, and the other end of the sampling switch is connected to the input signal, and the control end of the sampling switch Connected to the internal clock signal, and the upper plate signal of the sampling capacitor acts as an output sampling signal of the master-slave sample-and-hold circuit.
- the interstage buffer amplifier is in the form of a differential circuit comprising two single-ended circuit forms and a tail current source, and the two single-ended circuits are respectively configured to process the positive phase portion and the inverted phase portion of the differential signal, each single
- the terminal circuit includes an eighth NMOS transistor, a ninth NMOS transistor, a first resistor and a second resistor, wherein the eighth NMOS transistor is a working transistor, and a gate thereof is connected to a first sampling signal output by the main sample-and-hold circuit, and the drain The first sampling signal after the buffer is output, the source is connected to one end of the first resistor, and the other end of the first resistor is grounded via a tail current source; the ninth NMOS transistor is a supporting crystal
- the body tube has a gate connected to the second bias voltage, a drain connected to the power source VCC, a source connected to one end of the second resistor, and the other end of the second resistor connected to the drain of the eighth NMOS transistor.
- FIG. 1 is a schematic structural diagram of a CMOS single-stage sample and hold circuit provided by the prior art.
- FIG. 2 is a timing diagram of a CMOS single-stage sample and hold circuit provided by the prior art.
- FIG. 3 is a block diagram of a single-ended principle of a CMOS master-slave sample-and-hold circuit provided by the present invention.
- FIG. 4 is a timing diagram of a CMOS master-slave sample-and-hold circuit provided by the present invention.
- Figure 5 is a circuit diagram showing the implementation of the input buffer amplifier of Figure 3.
- Figure 6 is a circuit diagram showing the implementation of the master-slave sample-and-hold circuit of Figure 3.
- Figure 7 is a circuit diagram showing the implementation of the sampling switch of Figure 6.
- Figure 8 is a circuit diagram showing the implementation of the interstage buffer amplifier of Figure 3.
- Figure 9 is a circuit diagram showing the implementation of the clock circuit of Figure 3.
- FIG. 10 is a timing chart showing the operation of the clock circuit shown in FIG. 9.
- FIG. 11 is a block diagram of a differential principle of a CMOS master-slave sample-and-hold circuit provided by the present invention.
- Figure 12 is a circuit diagram showing the implementation of the input buffer amplifier of Figure 11.
- Figure 13 is a circuit diagram showing the implementation of the master-slave sample-and-hold circuit of Figure 11;
- Figure 14 is a circuit diagram showing the implementation of the interstage buffer amplifier of Figure 11;
- the present invention provides a CMOS master-slave sample and hold circuit, including:
- the input buffer amplifier 1 is adapted to receive and buffer an externally input analog signal Ain and drive the main sample and hold circuit 2;
- the main sample and hold circuit 2 is adapted to sample and hold the output signal BAin of the input buffer amplifier 1, and output the first sampling signal SS1;
- the interstage buffer amplifier 3 is adapted to receive and buffer the first sampling signal SS1 and drive the slave sample and hold circuit 4;
- the sampling and holding circuit 4 is adapted to sample and hold the output signal BSS1 of the interstage buffer amplifier 3, and output the second sampling signal SS2, and the second sampling signal SS2 is the final output signal of the CMOS master-slave sampling and holding circuit;
- the clock circuit 5 is adapted to receive the external clock signal CK to generate a first internal clock signal CKI1 and a second internal clock signal CKI2, the first internal clock signal CKI1 and the second internal clock signal CKI2 being a pair of non-overlapping clocks
- the signal, and the first internal clock signal CKI1 is used to provide a clock signal to the main sample and hold circuit 2, and the second internal clock signal CKI2 is used to supply a clock signal to the sample and hold circuit 4.
- the clock circuit In the CMOS master-slave sample-and-hold circuit provided by the present invention, the clock circuit generates a pair of non-overlapping first internal clock signals and a second internal clock signal, and the first internal clock signal is used to provide a clock signal to the main sample and hold circuit.
- the second internal clock signal is used to provide a clock signal from the sample-and-hold circuit, so that the main sample-and-hold circuit and the slave-sampling circuit maintain a two-stage hold circuit capable of maintaining the signal for the entire clock cycle; and an input buffer amplifier is also included.
- An analog signal for receiving and buffering external inputs, an interstage buffer amplifier is inserted between the two stages of sample and hold circuits to isolate the sampling capacitors of the main sample and hold circuit and the slave sample and hold circuit to prevent charge sharing effects from occurring.
- the invention is applied to the front end of an analog-to-digital converter, which can greatly improve the performance of the analog-to-digital converter.
- the main sample-and-hold circuit 2 and the slave sample-and-hold circuit 4 are clocked The signal is driven periodically, and each working cycle is divided into two parts: the phase and the sampling phase.
- the tracking phase the output of the main sample-and-hold circuit 2 and the slave sample-and-hold circuit 4 follows its input signal; in the sustain phase, the output signals of the main sample-and-hold circuit 2 and the slave sample-and-hold circuit 4 remain unchanged.
- the main sample and hold circuit 2 When the first internal clock signal CKI1 is at a high level, the main sample and hold circuit 2 is in a tracking phase, when the first internal clock signal CKI1 is at a low level, the main sample and hold circuit 2 is in a hold phase; when the second internal clock signal CKI2 is When the level is high, the slave sample-and-hold circuit 4 is in the tracking phase, and when the second internal clock signal CKI2 is at the low level, the slave sample-and-hold circuit 4 is in the hold phase. Since the first internal clock signal CKI1 and the second internal clock signal CKI2 are a pair of non-overlapping clock signals, the main track hold circuit 2 and the slave track hold circuit 4 are not simultaneously in the tracking phase.
- the first internal clock signal CKI1 and the second internal clock signal CKI2 are both at a low level, and the main sample hold circuit 2 and the slave sample and hold circuit 4 are both in a hold phase.
- the rising edge of the first internal clock signal CKI1 comes, which transitions from a low level to a high level, the main sample and hold circuit 2 enters the tracking phase, and the output of the first sampling signal SS1 follows the analog of the external input.
- the sampled and held circuit 4 samples and holds the first sampled signal SS1 at that moment and enters the hold phase, and the output of the second sampled signal SS2 remains unchanged. Thereafter, under the driving of the first internal clock signal CKI1 and the second internal clock signal CKI2, the main sample-and-hold circuit 2 and the sample-and-hold circuit 4 are superimposed to sample the signal and maintain. And as can be seen from FIG. 4, the second sampling signal SS2 output from the sample and hold circuit 4 remains unchanged throughout the entire clock cycle.
- all of the signals and modules in Figure 3 are in the form of single-ended signals or single-ended circuits.
- FIG. 5 shows a circuit diagram of the input buffer amplifier 1 of FIG. 3 implemented in a single-ended circuit form.
- the input buffer amplifier 1 includes a first NMOS transistor N1 and a second NMOS transistor N2, the first NMOS.
- the transistor N1 is a working transistor, the gate thereof receives an externally input analog signal Ain, the source output buffered analog signal BAin, and the drain is connected to the power supply VCC;
- the second NMOS transistor N2 is a bias transistor, and its drain is connected
- the source of an NMOS transistor N1 supplies a bias current to the first NMOS transistor N1, the source is grounded, and the gate is coupled to the first bias voltage BIAS1.
- the first bias voltage BIAS1 is a voltage signal, which can be generated by a bias signal generating circuit in the chip, and the size of the first bias voltage BIAS1 is changed, and the second NMOS transistor N2 can be adjusted to be supplied to the first NMOS transistor.
- the main sample-and-hold circuit 2 and the slave sample-and-hold circuit 4 have the same circuit structure.
- Their single-ended circuit implementation forms a sampling switch SW and a sampling capacitor Cs, and the lower pole of the sampling capacitor Cs.
- the board is grounded, the upper board is connected to one end of the sampling switch SW, the other end of the sampling switch SW is connected to the input signal VIN, the control end of the sampling switch SW is connected to the internal clock signal CKI, and the plate signal of the sampling capacitor Cs is used as the master.
- the output sample signal SS of the sample and hold circuit is used as the master.
- the input signal connected to the other end of the sampling switch SW is BAin, the control end of the sampling switch SW is connected to the internal clock signal CKI1, and the sampling capacitor Cs is on the upper plate.
- the signal is used as the output sampling signal SS1 of the main sample and hold circuit 2; in the slave sample and hold circuit 4, the input signal connected to the other end of the sampling switch SW is BSS1, and the control end of the sampling switch SW is connected to the internal clock signal CKI2.
- the plate signal on the sampling capacitor Cs is used as the output sampling signal SS2 from the sample and hold circuit 4.
- the sampling switch SW is closed, and the input signal VIN is connected with the upper plate SS of the sampling capacitor Cs.
- the sampling plate Cs upper plate SS tracks the input signal VIN; when the clock signal When CKI is low, the sampling switch SW is turned off, and the SS signal of the upper plate of the sampling capacitor Cs remains unchanged.
- the sampling switch SW is a bootstrap switch, including a first inverter T1, a second inverter T2, a third inverter T3, and a fourth inverter T4.
- the input end of the second inverter T2 is a bootstrap switch, including
- the gate of the first PMOS transistor P1 is connected to the drains of the second PMOS transistor P2, the fifth NMOS transistor N5 and the seventh NMOS transistor N7, and the upper plate of the capacitor Ca is connected to the source of the first PMOS transistor P1 and the third
- the drain of the PMOS transistor P3, the source of the third PMOS transistor P3 is connected to the power source VCC, and the lower plate of the capacitor Ca is connected.
- the source of the switching transistor N0 is connected.
- the working principle of the bootstrap switch is as follows:
- the second inverter T2 When the clock signal CKI is low, the second inverter T2 outputs a low level, the third NMOS transistor N3 is turned on, the gate of the main switching transistor N0 is pulled low, the main switching transistor N0 is turned off, and the source thereof is turned off. Electrical connection between the gates. Due to the signal holding function of the sampling capacitor Cs in FIG. 6, the signal SS at the drain of the main switching transistor N0 is sampled and held; meanwhile, the gate potential of the sixth NMOS transistor N6 is pulled low, and the sixth NMOS transistor N6 is turned off.
- the electrical connection between the lower plate of the capacitor Ca and the input signal VIN is disconnected; at the same time, the gate potential of the third PMOS transistor P3 is pulled low, the third PMOS transistor P3 is turned on, and the upper plate of the capacitor Ca is connected to the power supply VCC.
- the gate of the seventh NMOS transistor N7 is pulled low, and the seventh NMOS transistor N7 is turned off and partially turned off (because the lower plate of the capacitor Ca is connected to the gate of the first PMOS transistor P1 through N7 and N5, the N7 cutoff is only partially broken.
- the electrical connection between the gate of the first PMOS transistor P1 and the lower plate of the capacitor Ca is only completely disconnected when N5 is also turned off.
- the third inverter T3 outputs a low level, the gate of the fifth NMOS transistor N5 is at a low level, and the fifth NMOS transistor N5 is turned off, further completely turning off the gate of the first PMOS transistor P1 and the lower pole of the capacitor Ca. Electrical connection between boards.
- the gate of the second PMOS transistor P2 is at a low level, the second PMOS transistor P2 is turned on, the gate of the first PMOS transistor P1 is connected to the power source VCC, the first PMOS transistor is turned off, and the upper plate and the main electrode of the capacitor Ca are disconnected. Electrical connection between the gates of the switching transistor N0.
- the output of the fourth inverter T4 is at a high level
- the gate of the fourth NMOS transistor N4 is at a high level
- the fourth NMOS transistor N4 is turned on, connecting the lower plate of the capacitor Ca to the ground gnd.
- the upper plate of the capacitor Ca is connected to the power source VCC through the third PMOS transistor P3, and the lower plate is connected to the ground through the fourth NMOS transistor N4, and the power source VCC pair
- the capacitor Ca is charged until the voltage difference across the capacitor reaches the supply voltage VCC.
- the output of the second inverter T2 is at a high level, and the third NMOS transistor N3 is turned off, turning off the electrical connection between the source and the drain.
- the third inverter T3 outputs a high level, the second PMOS transistor P2 is turned off, and the electrical connection between the gate of the first PMOS transistor P1 and the power source VCC is turned off.
- the fifth NMOS transistor N5 is turned on to connect the gate of the first PMOS transistor P1 to the lower plate of the capacitor Ca.
- the voltage difference VCC between the upper and lower plates of the capacitor Ca is applied between the source and the gate of the first PMOS transistor P1, and the first PMOS transistor P1 is turned on, thereby connecting the upper plate of the capacitor Ca to the main switching transistor N0.
- the gate thus, the voltage difference VCC between the upper and lower plates of the capacitor Ca is applied between the gate and the source of the seventh NMOS transistor N7, and the seventh NMOS transistor N7 is turned on, so that the gate of the first PMOS transistor P1 is further sufficiently connected. Go to the lower plate of capacitor Ca.
- the output of the fourth inverter T4 is at a low level, and the fourth NMOS transistor N4 is turned off, and the electrical connection between the lower plate of the capacitor Ca and the ground gnd is broken.
- the voltage difference VCC of the upper and lower plates of the capacitor Ca is applied between the gate and the source of the sixth NMOS transistor, and the sixth NMOS transistor is turned on, thereby connecting the lower plate of the capacitor Ca to the source of the main switching transistor N0. pole.
- the voltage difference VCC between the upper and lower plates of the capacitor Ca is applied between the gate and the source of the main switching transistor N0, and the main switching transistor N0 is turned on, thereby connecting the input signal VIN and the output signal SS. Due to the signal holding function of the capacitor Ca, when the input signal VIN changes, the voltage difference of VCC is always maintained between the gate and the source of the main switching transistor N0.
- the on-resistance of the main switching transistor N0 is:
- ⁇ n is the electron mobility
- C ox is the gate capacitance of the MOS transistor per unit area
- W and L are the gate width and the gate length of the main switching transistor N0, respectively
- V g and V s are the gates of the main switching transistor N0, respectively.
- Source potential V th is the threshold voltage of the MOS transistor;
- V g -V s VCC (2)
- the sampling switch SW of the present invention adopts a specially designed bootstrap switch, which greatly improves the linearity of the sampling switch SW.
- the interstage buffer amplifier 3 adopts a single-ended circuit form, which includes an eighth NMOS transistor N8, a ninth NMOS transistor N9, a first resistor R1, and a second resistor R2.
- the eighth NMOS transistor N8 is a working transistor, the gate thereof is connected to the first sampling signal SS1 outputted by the main sample-and-hold circuit 2, the drain outputs the buffered first sampling signal BSS1, and the source is connected to the first resistor R1.
- One end of the first resistor R1 is grounded;
- the ninth NMOS transistor N9 is a load transistor, the gate is connected to the second bias voltage BIAS2, the drain is connected to the power source VCC, and the source is connected to the second resistor R2.
- the second bias voltage BIAS2 is a voltage signal, which can be generated by an on-chip bias generating unit.
- the gain of the interstage buffer amplifier 3 can be expressed as:
- g m8 and g m9 are transconductances of the eighth NMOS transistor N8 and the ninth NMOS transistor N9, respectively; as a specific embodiment, the eighth NMOS transistor N8 and the ninth NMOS transistor N9 have the same size. That is, the transconductance of the eighth NMOS transistor N8 and the ninth NMOS transistor N9 is equal, so
- the clock circuit 5 includes a first NAND gate NAND1, a second NAND gate NAND2, a fifth inverter T5, a sixth inverter T6, and a seventh inversion.
- the input terminal of the fifth inverter T5 and the digital buffer B1 receives the external clock signal CK, the output of the fifth inverter T5 and the first input of the first NAND gate NAND1 End connection, the output of the digital buffer B1 is connected to the first input of the second NAND gate NAND2, the output of the first NAND gate NAND1 and the input of the sixth inverter T6 and the second NAND gate NAND2
- the second input terminal is connected, the output terminal of the second NAND gate NAND2 is connected to the input terminal of the seventh inverter T7 and the second input terminal of the first NAND gate NAND1, and the output terminal of the sixth inverter T6 is output.
- the first internal clock signal CKI1 the output of the seventh inverter T7 outputs a second internal clock signal CKI2.
- ⁇ gate the working principle of the clock circuit 5 is as follows:
- the external clock signal CK is at a low level (ie, ground), at which time the output of the digital buffer B1 is at a low level, and the output of the second NAND gate NAND2 is at a high level;
- the output of the fifth inverter T5 is at a high level, and the output of the first NAND gate NAND1 is at a low level.
- the external clock signal CK changes from a low level to a high level (ie, the power supply voltage VCC), and the output of the fifth inverter T5 goes from a high voltage after a gate delay time ⁇ gate
- the output of the first NAND gate NAND1 changes from a low level to a high level
- a gate delay time the output of the second NAND gate NAND2 Go from high to low.
- the falling edge of the external clock signal CK comes, and the external clock signal CK changes from a high level to a low level.
- the output of the digital buffer B1 changes from a high level to a low level.
- the output of the second NAND gate NAND2 changes from a low level to a high level, and after a gate delay, the output of the first NAND gate NAND1 changes from a high level to a low level.
- the output changes from a high level to a low level; whenever the falling edge of the external clock signal CK comes, the output of the second NAND gate NAND2 is changed from a low level to a high level, and after a gate delay,
- the output of the first NAND gate NAND1 changes from a high level to a low level. That is, the output of the first NAND gate NAND1 and the output of the second NAND gate NAND2 have a pulse overlap time of a gate delay time; when the sixth inverter T6 and the seventh inverter T7 are inverted
- the obtained first internal clock signal CKI1 and the second internal clock signal CKI2 are non-overlapping clocks, and the non-overlap time is one gate delay time.
- the present invention can also be implemented in the form of a differential circuit, that is, part of the signals and modules in FIG. 3 will be in the form of differential signals and differential modules.
- the present invention redraws the principle block diagram of the differential form implementation.
- the input buffer amplifier 1, the main sample and hold circuit 2, the interstage buffer amplifier 3, and the main sample and hold circuit 4 all employ a differential circuit.
- the input buffer amplifier 2 adopts a differential circuit form, which includes two single-ended circuit form input buffer amplifiers as shown in FIG. 5, and two single-ended circuits respectively for processing differentials. a positive phase portion and an inverting portion of the signal, each single-ended circuit comprising a first NMOS transistor N1 and a second NMOS transistor N2, the first NMOS transistor N1 being a working transistor, the gate of which receives an externally input analog signal Ain+ And Ain-, the source signal buffered analog signals Bain- and Bain+, leak
- the second NMOS transistor N2 is a bias transistor, the drain of which is connected to the source of the first NMOS transistor N1, the bias current is supplied to the first NMOS transistor N1, the source is grounded to gnd, and the gate is connected.
- the first bias voltage BIAS1 is a voltage signal, which can be generated by a bias signal generating circuit in the chip, and the size of the first bias voltage BIAS1 is changed, and the second NMOS transistor N2 can be adjusted to be supplied to the first NMOS transistor. The magnitude of the bias current of N1.
- the main sample-and-hold circuit 2 and the slave sample-and-hold circuit 4 are both in the form of a differential circuit and have the same circuit structure, including two single-ended circuit forms as shown in FIG. a sample-and-hold circuit, two single-ended circuits for respectively processing a positive phase portion and an inverting portion of the differential signal, each single-ended circuit comprising a sampling switch SW and a sampling capacitor Cs, the lower plate of the sampling capacitor Cs being grounded, The upper plate is connected to one end of the sampling switch SW, the other end of the sampling switch is connected to the input signals VIN+ and VIN-, the control end of the sampling switch SW is connected to the internal clock signal CKI, and the sampling signals Cs are on the plate signals SS+ and SS- As the output sampling signal of the master-slave sample-and-hold circuit.
- the input signals connected to the other end of the sampling switch SW are Bain+ and Bain-
- the control end of the sampling switch SW is connected to the internal clock signal CKI1
- the sampling capacitor Cs The upper plate signal is used as the output sampling signals SS1+ and SS1 of the main sample and hold circuit 2
- the input signals connected to the other end of the sampling switch SW are BSS1+ and BSS1-
- the sampling switch SW The control terminal is connected to the internal clock signal CKI2, and the plate signal on the sampling capacitor Cs is used as the output sampling signals SS2+ and SS2- from the sample and hold circuit 4.
- the sampling switch SW is closed, and the input signals VIN+ and VIN- are connected with the upper plates SS+ and SS- of the sampling capacitor Cs. At this time, the sampling capacitor Cs is the upper plate SS tracking input. Signals VIN+ and VIN-; When the clock signal CKI is low, the sampling switch SW is turned off, and the SS signal of the upper plate of the sampling capacitor Cs remains unchanged.
- the interstage buffer amplifier 3 is in the form of a differential circuit including two single-ended circuit-level inter-stage buffer amplifiers and a tail current source U1 as shown in FIG.
- the single-ended circuit is respectively configured to process the positive phase portion and the inverting portion of the differential signal, and each single-ended circuit includes an eighth NMOS transistor N8, a ninth NMOS transistor N9, a first resistor R1, and a second resistor R2.
- the eighth NMOS transistor N8 is a working transistor, the gate thereof is connected to the first sampling signals SS1+ and SS1- output from the main sample-and-hold circuit 2, and the drain-sampling first sampling signals BSS1- and BSS1+ are connected to the source.
- the ninth NMOS transistor N9 is a load transistor, the gate is connected to the second bias voltage BIAS2, and the drain is connected to the power source VCC The source is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the drain of the eighth NMOS transistor N8.
- the first resistor R1 is used as a degeneration resistor for increasing the linearity of the interstage buffer amplifier 3.
- the second bias voltage BIAS2 is a voltage signal, which can be generated by an on-chip bias generating unit.
- the single-ended equivalent circuit of the differential buffer type interstage buffer amplifier shown in Fig. 14 is the same as that of Fig. 8, so the differential gain is also 1.
- the output common mode level of the differential buffer type interstage buffer amplifier shown in Figure 14 is:
- I is the current supplied by the tail current source U1
- R is the resistance of the second resistor R2.
- the invention provides a CMOS master-slave sample-and-hold circuit, comprising a main sample-and-hold circuit and a slave-sampling circuit, a two-stage sample-and-hold circuit capable of maintaining a signal constant throughout a clock cycle; the input buffer amplifier is used for Receiving and buffering an analog signal; the interstage buffer amplifier is inserted between the master-slave two-stage sample-and-hold circuit for isolating the sampling capacitor of the main sample-and-hold circuit and the slave sample-and-hold circuit to prevent charge sharing effects from occurring; sampling of the present invention
- the switch uses a specially designed bootstrap switch, which greatly improves the sampling switch Linearity.
- the differential implementation form of the present invention can minimize the influence of the MOS switch charge injection effect on the circuit performance; in addition, the differential implementation can generate a common mode signal inside the master-slave sample-and-hold circuit, and the common mode signal is not input. Signal impact.
- Applying the CMOS master-slave sample-and-hold circuit provided by the present invention to the front end of the analog-to-digital converter can greatly improve the performance of the analog-to-digital converter.
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Abstract
Description
Claims (10)
- 一种CMOS主从式采样保持电路,其特征在于,包括:A CMOS master-slave sample and hold circuit, comprising:输入缓冲放大器,适于接收和缓冲外部输入的模拟信号,并驱动主采样保持电路;An input buffer amplifier adapted to receive and buffer an externally input analog signal and drive the main sample and hold circuit;主采样保持电路,适于采样保持输入缓冲放大器的输出信号,并输出第一采样信号;a main sample and hold circuit adapted to sample and hold an output signal of the input buffer amplifier and output a first sampling signal;级间缓冲放大器,适于接收和缓冲第一采样信号,并驱动从采样保持电路;An interstage buffer amplifier adapted to receive and buffer the first sampled signal and drive the slave sample and hold circuit;从采样保持电路,适于采样保持级间缓冲放大器的输出信号,并输出第二采样信号,且第二采样信号为所述CMOS主从式采样保持电路的最终输出信号;The sample-and-hold circuit is adapted to sample and hold an output signal of the interstage buffer amplifier, and output a second sampling signal, and the second sampling signal is a final output signal of the CMOS master-slave sample-and-hold circuit;时钟电路,适于接收外部时钟信号,产生第一内部时钟信号和第二内部时钟信号,所述第一内部时钟信号和第二内部时钟信号为一对非交叠的时钟信号,且第一内部时钟信号用于给主采样保持电路提供时钟信号,第二内部时钟信号用于给从采样保持电路提供时钟信号。a clock circuit adapted to receive an external clock signal to generate a first internal clock signal and a second internal clock signal, the first internal clock signal and the second internal clock signal being a pair of non-overlapping clock signals, and the first internal The clock signal is used to provide a clock signal to the main sample and hold circuit, and the second internal clock signal is used to provide a clock signal to the sample and hold circuit.
- 根据权利要求1所述的CMOS主从式采样保持电路,其特征在于,所述输入缓冲放大器采用单端电路形式,包括第一NMOS晶体管和第二NMOS晶体管,所述第一NMOS晶体管为工作晶体管,其栅极接收外部输入的模拟信号,源极输出缓冲后的模拟信号,漏极连接电源VCC;所述第二NMOS晶体管为偏置晶体管,其漏极连接第一NMOS晶体管的源极,为第一NMOS晶体管提供偏置电流,源极接地,栅极连接第一偏置电压。The CMOS master-slave sample-and-hold circuit according to claim 1, wherein said input buffer amplifier is in the form of a single-ended circuit, comprising a first NMOS transistor and a second NMOS transistor, said first NMOS transistor being a working transistor The gate receives an externally input analog signal, the source outputs the buffered analog signal, and the drain is connected to the power supply VCC; the second NMOS transistor is a bias transistor whose drain is connected to the source of the first NMOS transistor, The first NMOS transistor provides a bias current, the source is grounded, and the gate is coupled to the first bias voltage.
- 根据权利要求1所述的CMOS主从式采样保持电路,其特征在于,所述主采样保持电路和从采样保持电路均采用单端电路形式并具有相同的电路结构,包括采样开关和采样电容,所述采样电容的下极板接地,上极板连接采样开关的一端,采样开关的另一端连接输入 信号,采样开关的控制端与内部时钟信号连接,且所述采样电容上极板信号作为主从采样保持电路的输出采样信号。The CMOS master-slave sample-and-hold circuit according to claim 1, wherein the main sample-and-hold circuit and the slave sample-and-hold circuit both adopt a single-ended circuit form and have the same circuit structure, including a sampling switch and a sampling capacitor. The lower plate of the sampling capacitor is grounded, the upper plate is connected to one end of the sampling switch, and the other end of the sampling switch is connected to the input. The signal, the control end of the sampling switch is connected to the internal clock signal, and the upper plate signal of the sampling capacitor is used as the output sampling signal of the master-slave sampling and holding circuit.
- 根据权利要求3所述的CMOS主从式采样保持电路,其特征在于,所述采样开关为自举开关,包括第一反相器、第二反相器、第三反相器、第四反相器、第三NMOS晶体管、第四NMOS晶体管、第五NMOS晶体管、第六NMOS晶体管、第七NMOS晶体管、第一PMOS晶体管、第二PMOS晶体管、第三PMOS晶体管、电容器和主开关晶体管;所述主开关晶体管的源极连接输入信号,漏极连接所述采样电容的上极板,栅极同时连接第六NMOS晶体管、第七NMOS晶体管和第三PMOS晶体管的栅极,第一反相器的输入端连接内部时钟信号,输出端与第二反相器和第三反相器的输入端连接,第二反相器的输出端连接第三NMOS晶体管的源极,第三反相器的输出端连接第四反相器的输入端、第二PMOS晶体管和第五NMOS晶体管的栅极,第四反相器的输出端连接第四NMOS晶体管的栅极,第一反相器、第二反相器、第三反相器和第四反相器为CMOS静态逻辑门电路,由电源VCC供电,第三NMOS晶体管的栅极接电源VCC,漏极连接主开关晶体管的栅极和第一PMOS晶体管的漏极,第一PMOS晶体管的栅极连接第二PMOS晶体管、第五NMOS晶体管和第七NMOS晶体管的漏极,电容器的上极板连接第一PMOS晶体管的源极和第三PMOS晶体管的漏极,第三PMOS晶体管的源极连接电源VCC,电容器的下极板连接第五NMOS晶体管和第七NMOS晶体管的源极以及第四NMOS晶体管和第六NMOS晶体管的漏极,第四NMOS晶体管的源极接地,第六NMOS晶体管的源极与主开关晶体管的源极连接。The CMOS master-slave sample-and-hold circuit according to claim 3, wherein the sampling switch is a bootstrap switch, including a first inverter, a second inverter, a third inverter, and a fourth reverse Phase comparator, third NMOS transistor, fourth NMOS transistor, fifth NMOS transistor, sixth NMOS transistor, seventh NMOS transistor, first PMOS transistor, second PMOS transistor, third PMOS transistor, capacitor, and main switching transistor; The source of the main switching transistor is connected to the input signal, the drain is connected to the upper plate of the sampling capacitor, and the gate is connected to the gates of the sixth NMOS transistor, the seventh NMOS transistor and the third PMOS transistor, the first inverter The input end is connected to the internal clock signal, the output end is connected to the input ends of the second inverter and the third inverter, the output end of the second inverter is connected to the source of the third NMOS transistor, and the third inverter is The output terminal is connected to the input end of the fourth inverter, the gates of the second PMOS transistor and the fifth NMOS transistor, and the output end of the fourth inverter is connected to the gate of the fourth NMOS transistor, the first inverter and the second Inverter, third The phase converter and the fourth inverter are CMOS static logic gate circuits, which are powered by a power supply VCC, the gate of the third NMOS transistor is connected to the power supply VCC, and the drain is connected to the gate of the main switching transistor and the drain of the first PMOS transistor, The gate of a PMOS transistor is connected to the drains of the second PMOS transistor, the fifth NMOS transistor and the seventh NMOS transistor, and the upper plate of the capacitor is connected to the source of the first PMOS transistor and the drain of the third PMOS transistor, the third PMOS The source of the transistor is connected to the power source VCC, the lower plate of the capacitor is connected to the source of the fifth NMOS transistor and the seventh NMOS transistor, and the drains of the fourth NMOS transistor and the sixth NMOS transistor, the source of the fourth NMOS transistor is grounded, The source of the six NMOS transistor is connected to the source of the main switching transistor.
- 根据权利要求1所述的CMOS主从式采样保持电路,其特征在于,所述级间缓冲放大器采用单端电路形式,包括第八NMOS晶 体管、第九NMOS晶体管、第一电阻器和第二电阻器,所述第八NMOS晶体管为工作晶体管,其栅极与主采样保持电路输出的第一采样信号连接,漏极输出缓冲后的第一采样信号,源极连接第一电阻器的一端,第一电阻器的另一端接地;所述第九NMOS晶体管为负载晶体管,其栅极连接第二偏置电压,漏极连接电源VCC,源极连接第二电阻器的一端,第二电阻器的另一端与第八NMOS晶体管的漏极连接。The CMOS master-slave sample-and-hold circuit of claim 1 wherein said interstage buffer amplifier is in the form of a single-ended circuit comprising an eighth NMOS transistor a body tube, a ninth NMOS transistor, a first resistor and a second resistor, the eighth NMOS transistor being a working transistor, the gate of which is connected to the first sampling signal output by the main sample-and-hold circuit, and the drain output is buffered a first sampling signal, the source is connected to one end of the first resistor, and the other end of the first resistor is grounded; the ninth NMOS transistor is a load transistor, the gate is connected to the second bias voltage, and the drain is connected to the power source VCC. The source is connected to one end of the second resistor, and the other end of the second resistor is connected to the drain of the eighth NMOS transistor.
- 根据权利要求5所述的CMOS主从式采样保持电路,其特征在于,所述第八NMOS晶体管和第九NMOS晶体管的跨导相等,且所述第一电阻器和第二电阻器的阻值相等。The CMOS master-slave sample-and-hold circuit according to claim 5, wherein a transconductance of said eighth NMOS transistor and said ninth NMOS transistor are equal, and resistance values of said first resistor and said second resistor equal.
- 根据权利要求1所述的CMOS主从式采样保持电路,其特征在于,所述时钟电路包括第一与非门、第二与非门、第五反相器、第六反相器、第七反相器和数字缓冲器,所述第五反相器和数字缓冲器的输入端接收外部时钟信号,第五反相器的输出端与第一与非门的第一输入端连接,数字缓冲器的输出端与第二与非门的第一输入端连接,第一与非门的输出端与第六反相器的输入端和第二与非门的第二输入端连接,第二与非门的输出端与第七反相器的输入端和第一与非门的第二输入端连接,第六反相器的输出端输出第一内部时钟信号,第七反相器的输出端输出第二内部时钟信号。The CMOS master-slave sample-and-hold circuit according to claim 1, wherein said clock circuit comprises a first NAND gate, a second NAND gate, a fifth inverter, a sixth inverter, and a seventh An inverter and a digital buffer, the input of the fifth inverter and the digital buffer receives an external clock signal, and the output of the fifth inverter is connected to the first input of the first NAND gate, the digital buffer The output end of the device is connected to the first input end of the second NAND gate, and the output end of the first NAND gate is connected to the input end of the sixth inverter and the second input end of the second NAND gate, the second The output end of the NOT gate is connected to the input end of the seventh inverter and the second input end of the first NAND gate, and the output end of the sixth inverter outputs a first internal clock signal, and the output end of the seventh inverter The second internal clock signal is output.
- 根据权利要求1所述的CMOS主从式采样保持电路,其特征在于,所述输入缓冲放大器采用差分电路形式,其包括两个单端电路形式,两个单端电路分别用于处理差分信号中的正相部分和反相部分,每个单端电路包括第一NMOS晶体管和第二NMOS晶体管,所述第一NMOS晶体管为工作晶体管,其栅极接收外部输入的模拟信号,源极输出缓冲后的模拟信号,漏极连接电源VCC;所述第二NMOS晶体管为偏置晶体管,其漏极连接第一NMOS晶体管的源极,为第一NMOS晶体管提供偏置电流,源极接地,栅极连接第一偏置 电压。The CMOS master-slave sample-and-hold circuit according to claim 1, wherein said input buffer amplifier is in the form of a differential circuit comprising two single-ended circuits, and two single-ended circuits are respectively used for processing differential signals. a positive phase portion and an inverting portion, each single-ended circuit comprising a first NMOS transistor and a second NMOS transistor, the first NMOS transistor being a working transistor, the gate receiving an externally input analog signal, and the source output buffered Analog signal, the drain is connected to the power supply VCC; the second NMOS transistor is a bias transistor, the drain is connected to the source of the first NMOS transistor, the bias current is supplied to the first NMOS transistor, the source is grounded, and the gate is connected First offset Voltage.
- 根据权利要求1所述的CMOS主从式采样保持电路,其特征在于,所述主采样保持电路和从采样保持电路均采用差分电路形式并具有相同的电路结构,其包括两个单端电路形式,两个单端电路分别用于处理差分信号中的正相部分和反相部分,每个单端电路包括采样开关和采样电容,所述采样电容的下极板接地,上极板连接采样开关的一端,采样开关的另一端连接输入信号,采样开关的控制端与内部时钟信号连接,且所述采样电容上极板信号作为主从采样保持电路的输出采样信号。The CMOS master-slave sample-and-hold circuit according to claim 1, wherein said main sample-and-hold circuit and the slave sample-and-hold circuit both adopt a differential circuit form and have the same circuit structure, and include two single-ended circuit forms. Two single-ended circuits are respectively used for processing the positive phase portion and the inverted phase portion of the differential signal. Each single-ended circuit includes a sampling switch and a sampling capacitor. The lower plate of the sampling capacitor is grounded, and the upper plate is connected to the sampling switch. At one end, the other end of the sampling switch is connected to the input signal, the control end of the sampling switch is connected to the internal clock signal, and the upper plate signal of the sampling capacitor is used as the output sampling signal of the master-slave sampling and holding circuit.
- 根据权利要求1所述的CMOS主从式采样保持电路,其特征在于,所述级间缓冲放大器采用差分电路形式,其包括两个单端电路形式和尾电流源,两个单端电路分别用于处理差分信号中的正相部分和反相部分,每个单端电路包括第八NMOS晶体管、第九NMOS晶体管、第一电阻器和第二电阻器,所述第八NMOS晶体管为工作晶体管,其栅极与主采样保持电路输出的第一采样信号连接,漏极输出缓冲后的第一采样信号,源极连接第一电阻器的一端,第一电阻器的另一端经尾电流源接地;所述第九NMOS晶体管为负载晶体管,其栅极连接第二偏置电压,漏极连接电源VCC,源极连接第二电阻器的一端,第二电阻器的另一端与第八NMOS晶体管的漏极连接。 The CMOS master-slave sample-and-hold circuit according to claim 1, wherein said interstage buffer amplifier is in the form of a differential circuit comprising two single-ended circuit forms and a tail current source, and two single-ended circuits are respectively used. Processing a positive phase portion and an inverting portion of the differential signal, each single-ended circuit comprising an eighth NMOS transistor, a ninth NMOS transistor, a first resistor, and a second resistor, the eighth NMOS transistor being a working transistor, The gate is connected to the first sampling signal outputted by the main sample-and-hold circuit, the drain outputs the buffered first sampling signal, the source is connected to one end of the first resistor, and the other end of the first resistor is grounded via the tail current source; The ninth NMOS transistor is a load transistor, the gate thereof is connected to the second bias voltage, the drain is connected to the power source VCC, the source is connected to one end of the second resistor, and the other end of the second resistor is connected to the drain of the eighth NMOS transistor. Extremely connected.
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