WO2016194083A1 - Ultrasonice probe and ultrasonic diagnostic apparatus using same - Google Patents

Ultrasonice probe and ultrasonic diagnostic apparatus using same Download PDF

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WO2016194083A1
WO2016194083A1 PCT/JP2015/065670 JP2015065670W WO2016194083A1 WO 2016194083 A1 WO2016194083 A1 WO 2016194083A1 JP 2015065670 W JP2015065670 W JP 2015065670W WO 2016194083 A1 WO2016194083 A1 WO 2016194083A1
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circuit
control
signal
control line
line
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PCT/JP2015/065670
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French (fr)
Japanese (ja)
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秀男 坂井
勇作 勝部
五十嵐 豊
琢真 西元
今川 健吾
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株式会社日立製作所
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    • AHUMAN NECESSITIES
    • A61MEDICAL OR VETERINARY SCIENCE; HYGIENE
    • A61BDIAGNOSIS; SURGERY; IDENTIFICATION
    • A61B8/00Diagnosis using ultrasonic, sonic or infrasonic waves
    • A61B8/13Tomography
    • A61B8/14Echo-tomography

Abstract

An ultrasonic probe which includes multiple transducers arranged in an array and multiple element circuits that correspond to each of the multiple transducers and drive the multiple transducers, the ultrasonic probe having a first set of control lines connected to the multiple element circuits, a second control line commonly connected to the multiple element circuits, and a control circuit to which the first set of control lines and the second control line are connected. Each of the element circuits is configured from: a transmission reception circuit connected to the first set of control lines; an individual control circuit that controls the transmission reception circuit; and a branch line that branches off of a corresponding control line of the first set of control lines and is connected to the individual control circuit. The individual control circuit is connected to the branch line and the second control line. The individual control circuit switches the transmission reception circuit on and off individually on the basis of a signal from the branch line and a signal from the second control line.

Description

Ultrasonic probe and ultrasonic diagnostic apparatus using the same

The present invention relates to an ultrasonic diagnostic apparatus ultrasound probe and using the same.

Patent Document 1, a vibrator arranged in an array, the control circuit of the oscillator, by connecting one to one, the switching of the vibrator arranged in an array, so as to be controlled for each transducer configuration ultrasound diagnostic apparatus for 2D array probe is disclosed.

Patent Document 2, is connected with the vibrator one-to-one, the transceiver circuit for transmitting and receiving ultrasonic waves, the common control vertical or transceiver unit located on the horizontal line in one control line per line how to have been disclosed.

JP-5-146444 discloses JP 2005-304692 JP

Through the semiconductor fabrication and vibrator when mounting the 2D array IC, between transducers adjacent a defect of internal contamination and the like are electrically shorted, or the output power or the like of the transmission circuit for driving a vibrator and there is a possibility that like to be a short circuit occurs. When driving the vibrator in this state, by an excessive current flows from the output of the transmitter circuit, the power consumption increases. As a result, heat generation of the ultrasonic probe is increased. Generally medical ultrasound probe is controlled from the ultrasonic diagnostic apparatus to stop at the preset temperature in order not to burn the patient. Therefore, heat generation is increased by increased power consumption, since the immediately such would stop trouble occurs, necessary to select the ultrasound probe as a defective product is produced. On the other hand, by stopping the transmission circuit affected by contamination, etc., it is possible to prevent the excessive current from flowing from the output of the transmitting circuit by the short circuit between the oscillator. In addition, since the receiving circuit can not even correctly ultrasonic receiver, it is possible to reduce unnecessary power consumption by turning off.

The present inventors have examined, the power on and off individually each transmission circuits arranged in a 2D array IC is, in Patent Document 1, the switch is required for the number of transducers. Control lines for controlling the switching from the switching controller with it also required. Therefore, the more increase in the number of transducers and reception circuit, for also increases control line for controlling the switch and the switch, when the vibrator is composed of N × M (N rows × M columns) number, the control switch and switch the number of control lines is also N × M, and the that the large wiring area in a 2D array IC of increase becomes a challenge to.

In Patent Document 2, when the vibrator is composed of N × M (N rows × M columns) number, to become a N + M (N rows + M column), even if many numbers transducers, the number of control lines is almost Will not Increase. However, when stopping the transmission circuit defective, since the common control transmission circuit on the same line, if a short circuit or the like defect is caused between the transmitting circuit and the transmitting circuit outputs the vibrator, there is a defect since thereby transmitting circuit good also stopped simultaneously present on the line, is not ultrasonic waves output from a number of transducers may not be obtained quality of a desired ultrasound image.

The present invention solves these problems, it is possible to perform the individual control of the transmission circuit in a small area and provide an ultrasonic probe capable yield improvement of a 2D array IC by turning off the transmitter circuit becomes defective an object of the present invention is to.

The invention has included a plurality of means for solving the above problems, if the 1 example, a plurality of transducers arranged in an array, corresponding to each of the plurality of transducers, the plurality an ultrasonic probe comprising a plurality of element circuit for driving the vibrator, a first control line group connected to said plurality of element circuits, the second being connected in common to said plurality of element circuits a control line, the control circuit the first group of control lines a second control line is connected, wherein the respective element circuit includes a transmitting and receiving circuit connected to said first control line group When the individual control circuit for controlling the transmission and reception circuit, the first branches from the corresponding control lines of the control line group, is composed of a branch line to the connected to the individual control circuit, the individual control circuit , which is connected to the branch line and the second control line, the Another control circuit may include a signal from the branch line, based on a signal from the second control line, and switches the individual on-off of the transmission and reception circuit.

Further, if the other one example comprises a plurality of transducers arranged in an array, corresponding to each of the plurality of transducers, and a plurality of element circuit for driving the plurality of transducers super a sonic probe, the vertical control line group connected to said plurality of element circuits, a horizontal control line group connected to said plurality of element circuits, the second being connected in common to said plurality of element circuits a control line, and a control circuit for the said vertical control line group and the transverse control line group second control lines are connected, each of said element circuit, the vertical control line group and lateral group of control lines a transceiver circuit connected to a separate control circuit for controlling the transmission and reception circuit, branched from a corresponding control line of the vertical control line group, wherein the first branch line connected to the individual control circuit, the horizontal branches from a corresponding control line of the control line group, the individual control circuit A second branch line connected, consists, the individual control circuit, the first branch line, is connected to the second branch line and the second control line, the individual control circuit, said a signal from the first branch line and said second branch line, based on a signal from the second control line, and switches the individual on-off of the transmission and reception circuit.

According to the present invention, it can be performed individually control of the transmission circuit in a small area. Also, improvement in yield 2D array IC is made possible by turning off the transmitter circuit becomes defective.

Other problems above, configurations, and effects will be apparent from the following description of embodiments.

Is a diagram showing an ultrasonic diagnostic apparatus according to the first embodiment of the present invention. Is a diagram illustrating a 2D array IC in FIG. Is a diagram illustrating the connection configuration and control line of the element circuit of the first embodiment of the present invention. It is a diagram showing a circuit example of the individual control circuit of FIG. It is a truth table of the individual control circuit shown in FIG. It is a circuit diagram for explaining a first embodiment of the present invention. Is a timing chart illustrating a circuit operation of FIG. Is a diagram illustrating the connection configuration and control line of the element circuit of the second embodiment of the present invention. It is a diagram showing a circuit example of the individual control circuit of FIG. It is a diagram showing a circuit of the second embodiment of the present invention. It is a truth table of the individual control circuit shown in FIG. 10. Is a timing chart illustrating a circuit operation of FIG. 10. It is a diagram showing a circuit of the third embodiment of the present invention. Is a timing chart illustrating a circuit operation of FIG. 13.

Hereinafter, the embodiments of the present invention will be described with reference to the drawings. Incidentally, omitted in the drawings for explaining the embodiments, same same name elements having the function, by reference numeral, the repeated description thereof.

Figure 1 is a diagram showing an ultrasonic diagnostic apparatus according to the first embodiment of the present invention. As shown in FIG. 1, the ultrasonic diagnostic apparatus has an apparatus body 11, and an ultrasonic probe 12.

Apparatus main body 11 includes, inside its housing, for example, to process an HDD (Hard Disk Drive) and storing a CPU (Central Processor Unit), a program or the like executed by the CPU for controlling the entire of the ultrasonic diagnostic apparatus data a storage device, such as a temporary storage to RAM a communication IF for communicating with the external device (IF: InterFace) and a device. The device body 11 has its inside casing, for example, has a variety of power supply circuits, and an image processing circuit for image processing the signals from the ultrasound probe. The device main body 11 has, for example, an input device such as a keyboard and a mouse, an output device such as a liquid crystal display device. The input device may be, for example, a touch panel provided on the liquid crystal display device. Apparatus main body 11, the attached casters or the like to the bottom surface, which is on the floor surface and freely movable structure.

The ultrasonic probe 12 includes a 2D (Dimension) array transducer 12a, and a 2D array IC (Integrated Circuit) 12b. 2D array transducer 12a is in the plane of the side in contact with the human body of the ultrasonic probe 12 has a plurality of transducers for emitting ultrasonic. A plurality of transducers of 2D array transducer 12a are arranged in a two-dimensional (planar). 2D array IC12b is so as to face the 2D array transducer 12a, has a plurality of circuits for driving the transducers of 2D array transducer 12a. A plurality of circuits of a 2D array IC12b are arranged two-dimensionally. A plurality of circuits of a 2D array IC12b are provided corresponding to the plurality of transducers of the 2D array transducer 12a. For example, one circuit of the 2D array IC12b is electrically connected to the one vibrator of 2D array transducer 12a.

Figure 2 is a diagram illustrating the configuration of the 2D array IC 12b. 2D array IC12b includes a plurality of element circuits 31, the control circuit 23. Element circuit 31 and the control circuit 23 is formed, for example, into a single IC substrate. In Figure 2, four on the IC substrate (element circuits 31a, 31b, 31c, 31d) element circuit 31 is formed. Further, in FIG. 2, one control circuit 23 is formed on an IC substrate.

The control circuit 23 includes an IF circuit for communicating with the device body 11. Further, the control circuit 23 based on an instruction from the apparatus main body 11, and a control circuit for controlling a plurality of element circuits 31. Further, the control circuit 23 and the vertical delay control line 25 for controlling a plurality of element circuits 31, and a switching control line 26.

Each element circuit 31 includes a vertical delay control line 25 is connected to the switching control line 26. A plurality of transducers of 2D array transducer 12a is miniaturized in response to a request image quality, the number is increasing. Along with this, the number of element circuit 31, for example, up to about 10,000. Therefore, reduction in size and power consumption of the device circuit 31 is important. In FIG. 2, to simplify the illustration, an example of two × 2 pieces of element circuit 31.

Figure 3 is a diagram showing the connection structure between the control line of the element circuits. Element circuit 31 includes a transceiver circuit 32, and a dedicated control circuit 36, an individual control line 37, and a branch line 38. Transceiver circuit 32 includes a delay control circuit 33, a transmitting circuit 34, a reception circuit 35. In Figure 3, there is shown a configuration example of the element circuit 31a of FIG. Note that FIG. 3 is connected to the device circuitry 31 also shows transducer 41 of the 2D array transducer 12a.

Delay control circuit 33 through the control circuit 23 under the control of the apparatus main body 11, depending on the value of the vertical delay control line 25, the output timing of the driving signal for driving the vibrator 41 output from the transmitting circuit 34 to control. For example, the delay control circuit 33, so as to scan a plurality of ultrasonic focal point that is output from a plurality of transducers of 2D array transducer 12a (point ultrasonic overlap), driving the transmitting circuit 34 outputs controlled by the vertical delay control line 25 the output timing of the signal. The delay control circuit 33, for example, a plurality of reflected waves received by the plurality of transducers of the 2D array transducer 12a, such that the proper image of the target is obtained, the output timing of the signal input from the receiving circuit 35 It was controlled by the vertical delay control line 25, and outputs to the control circuit 23. Control circuit, not shown by adding the signals output from the element circuit 31, and transmits to the apparatus main body 11 through the buffer. Thus, the device body 11 is capable of displaying a signal received from the delay control circuit 33 to the image processing, the output device images of the target.

Transmitting circuit 34 amplifies the signal output from the delay control circuit 33 outputs a drive signal for driving the vibrator 41.

Receiving circuit 35 amplifies the signal received by the transducer 41, and outputs the delay control circuit 33.

Individual control circuit 36 ​​includes a switching control line 26 which is output from the control circuit 22 or control circuit 23, branch line 38 branching off the delay control line 25 is input to the delay control circuit 33 is input.

Figure 4 is a diagram showing a structure of individual control circuit 36 ​​included in the circuit of FIG. Individual control circuit 36 ​​has a memory circuit 51, the determination circuit 53, an inverter 52, an internal control line 39.

Storage circuit 51 includes a branch line 38, receives the signal from the switching control line 26, and outputs a signal to the internal control line 39. Storage circuit 51, in response to an input signal from the switch control line 26, or hold the value of the output signal to the internal control line 39 switches whether to output a signal corresponding to the branch line 38.

Inverter 52 receives a signal from the switching control line 26, and outputs a signal corresponding to an input signal to the determination circuit 53.

Judging circuit 53 receives the signal from the memory circuit 51 and the inverter 52, and outputs a signal corresponding to an input signal to the individual control lines 37.

It shows a truth table of the individual control circuit 36 ​​in FIG. 5.
Storage circuit 51, when the signal of the switching control line 26 is "1 state", and outputs the state of the signal of the branch line 38 to the internal control line 39. Storage circuit 51, when the switching control line 26 is "0 state", and holds the signal output to the internal control line 39 immediately before the switch control line is switched to "0 state".
Judging circuit 53, only when the signal of the switching control line 26 is "0 state", the state of the signal of the internal control line 39, and outputs to the individual control lines 37.
As described above, the individual control circuit 36 ​​in accordance with the value of the branch line 38 and the switching control line 25, it is possible to switch on and off the transceiver circuit 32.

6 element circuit 31, when it is the N placed on the vertical line, element circuit 31 and a vertical delay control line 25 is a block diagram showing a connection example of the switching control line 26. The block of Figure 6, 2D array IC is constructed by arranging a plurality laterally.

In Figure 6, and a control circuit 23, a vertical delay control line 25, a switching control line 26 has an element circuits 31a ~ 31N, each element circuit 31 includes a transceiver circuit 32 to the individual control circuit 36.

Vertical delay control line 25 is composed of S [0] from the signal line S of the N-bit [N-1], is connected to the transmission and reception circuit 32 of the element circuits 31a ~ 31N. Switching control line 26 is connected in common to the individual control circuit 36 ​​of the element circuits 31a ~ 31N.

Branch line 38a to be inputted to the individual control circuit 36a is branched from the line of S [N-1] of the vertical delay control line 25. Branch line 38b to be input to the individual control circuit 36b branches from the line of S [N-2] of the vertical delay control line 25. Branch lines 38c ~ 38N that similarly inputted to the individual control circuits 36c ~ 36N is, S [N-3] of the vertical delay control line 25 branches respectively from ~ S [0]. That is, the individual control circuits 36 of each element circuit 31 disposed in a vertical line, the branch line 38 branching off at different line from a plurality of vertical delay control line is input.

Line shape element circuit in FIG. 7 shows a time chart of the operation when the is located. The ultrasonic probe 12 includes a reception period for transmitting and receiving ultrasonic waves, with an idle period of not performing transmission and reception. Internal control lines 39a ~ 39c shows the individual control circuits 36a ~ signal waveform of the internal control line 39 each in 36c of Fig. Hereinafter, with reference to FIG. 7, a specific operation of the idle period and the reception period of the 2D array IC.

In idle period 1, since the switching control line 26 is "1 state", the individual control lines 37 becomes "0 state", and the total transmission and reception circuit 32 is powered off.

For vertical delay control line 25S [N-1] is "1 state", the internal control line 39a becomes "1 state". For vertical delay control line 25S [N-2] is "0 state", the internal control lines 39b becomes "0 state". For vertical delay control line 25S [N-3] is "1 state", the internal control line 39c is "1 state". All individual control lines 37, regardless of the signal state of the internal control line 39, during the idle period, since the "0 state", all of the transmitting and receiving circuit 32 is powered off.

Next, transmission and reception period 1, the switching control line 26 is "0 state", and the vertical delay control line 25 is input signal for the delay control. The value of the internal control line 39 to hold the signal value set when the switching control line 26 is "1 state". Accordingly, without being affected by the vertical delay control line 25, the internal control lines 39a, 39c holds the "1 state", the internal control line 39b holds the "0 state". Individual control lines 37a, the value of 37c is "1 state", and transmission and reception circuit 32a, 32c are powered on and amplifies the input signal to the transmission circuit delayed according to the delay control, to drive the transducer. Since the value of the individual control lines 37b is a "0 state", the transmission and reception circuit 32b will remain powered off and does not transmit and receive circuit drives the vibrator.

Then, the idle period 2, because the switching control line 26 is "1 state", the entire transceiver circuit 32 is powered off. Further, since the vertical delay control line 25S [N-1] is "0 state", the internal control line 39a is changed to "0 state" from the "1 state". For vertical delay control line 25S [N-2] is "1 state", the internal control line 39b is changed to "1 state" from the "0 state". For vertical delay control line 25S [N-3] is "1 state", the internal control line 39c continues the "1 state".

Next, transmission and reception periods in the second switching control line 26 is "0 state", and the vertical delay control line 25 is input a signal for performing the delay control. The value of the internal control line 39 to hold the signal value set when the switching control line 26 is "1 state". Each individual control lines 37 in accordance with the signal state of the internal control line 39 becomes "0 state" or "1 state". Reception circuit 32, to power on and off according to a signal state of the individual control lines 37.

For example, in the case of FIG. 6, the branch line 38a that is input to the individual control circuit 36a of the element circuit 31a is branched from the control line 25S [N-1]. The branch line 38b which is input to the individual control circuit 36b of the element circuit 31b is branched from the control line 25S [N-2]. The branch line 38N input to the individual control circuit 36N of the element circuit 31N is branched from the control line 25S [0], that all the branch lines 38 is different from the control line 25 is branched It can be seen.

Is one branch line 38 of the control line of the individual control circuit 36 ​​is a control line which branches from the vertical delay control line 25 for transmitting and receiving circuit 32. Branch line 38 is branched from the vertical delay control line 25 in the device circuit 31, for connection to a separate control circuit 36, it is easy maneuverability. Using conventional methods of Patent Document 2, when laid the control line of the individual control circuits, and the longitudinal direction of the control line, two transverse control line is required for each one of the individual control circuits. Than this, the method of Patent Document 2, it is necessary wiring area of ​​a total of two duty. Next, consider a control line area for laid in the present invention to the individual control circuits. For example, when it is assumed the wiring length of the branch line to be 1/4 of the element circuit length, when laid in the process of this invention, the switching control line 26 branching lines is 1/4 duty, the common control line 1 duty is required. Than this, in the method of the present invention, the wiring area of ​​the total 1.25 duty. A wiring area of ​​the present invention, when comparing the wiring area of ​​the Patent Document 2, the present invention can reduce the wiring area of ​​37.5% from the patent document 2.

Also, since the branched from different control line 25, as shown in FIG. 7, during the idle period, signals of different "1 state" or "0 state", to each of the storage circuits 39, individually simultaneous input it is possible to. Therefore, compared with a method of rewriting each memory circuit 39 sequentially, it is possible shorten the idle period.

In this way, by using the present invention method, it is possible to wiring control lines in space saving, that each transceiver circuit with a small area to realize an ultrasonic probe including a power on-off capable 2D array IC individually it is possible.

Further, to each of the memory circuit 39, it is possible to simultaneously enter different signals, compared to the method of rewriting each memory circuit 39 sequentially, it is possible shorten the idle period.

According to this embodiment, by using the delay control line group for supplying a signal for controlling the output timing of the transducer drive signal, it holds information on the individual control circuit with the idle period, by using this information to send and receive periods transceiver it is possible to switch the individual power-on power-off of the circuit, it is possible to perform the individual control of the transmission circuit in a small area, possible to improve yield of a 2D array IC by turning off the transmitter circuit becomes defective can.

In Example 2, as compared to the number of vertical delay control lines 25 which are laid in a vertical column, the number of vertical element circuit 31 disposed in the line of the control example will be described of a case often.

Figure 8 is a diagram showing a connection configuration as the control line of the element circuits. Compared to the configuration of FIG. 3, a configuration in which the horizontal delay control line 24 is newly wired to the delay control circuit 33. Horizontal delay control line 24 is connected to a separate control circuit 36 ​​by a branch line 40.

Figure 9 is a diagram showing the configuration of an individual control circuit 36 ​​included in the circuit of FIG. Compared to the configuration of FIG. 4, a decision circuit 54, branch line 40 is added.
Judging circuit 54 receives the signal from the branch line 40 and the switching control line 26, and outputs a signal to the memory circuit 51.
Storage circuit 51 includes a branch line 38, receives the signal from the determination circuit 54, and outputs a signal to the internal control line 39. Storage circuit 51, in response to an input signal from the determination circuit 54, or hold the value of the output signal to the internal control line 39 switches whether to output a signal corresponding to the branch line 38.
Inverter 52 receives the signal from the control line 26, to the determination circuit 53, and outputs a signal corresponding to the input signal.
Judging circuit 53 receives the signal from the memory circuit 51 and the inverter 52, and outputs a signal corresponding to an input signal to the individual control lines 37.

It shows a circuit example of a 2D array IC for controlling the device circuit 31 arranged in an array in FIG.
In 2D array IC in FIG. 10, with respect to FIG. 6, it is characterized in that the horizontal delay control lines 24a ~ 24d which are wired in the horizontal direction is added.

The following describes the structure of FIG. 10.
2D array IC shown in FIG. 10, an array with eight element circuit 31 arranged in (vertical 4 × horizontal 2), the horizontal delay control line 24 and the vertical delay control lines to the delay control the transmission and reception circuit 32 of the device circuit 31 25, a control circuit 22 for controlling the signal input to the horizontal delay control line 24 and the vertical delay control line 25. Further, a switching control line 26 which is connected to each individual control circuit 36. Element circuit 31 includes a transceiver circuit 32, an individual control circuit 36.

The control circuit 22, the horizontal delay control line 24a, 24b, 24c, is connected to 24d. The control circuit 22, the horizontal delay control line 24a, 24b, 24c, to 24d, a signal of "1 state" or "0 state", entered individually.
Horizontal delay control line 24a is transmitting and receiving circuit 32a, and 32b, are connected to the individual control circuits 36a, 36b.
Horizontal delay control line 24b includes a transmitting and receiving circuit 32c, and 32d, is connected to a separate control circuit 36c, 36d.
Horizontal delay control line 24c includes a transmitting and receiving circuit 32e, and 32f, are connected individually control circuit 36e, to 36f.
Horizontal delay control line 24d is transmitting and receiving circuit 32g, and 32h, are connected individually control circuit 36 ​​g, to 36h.

The control circuit 23, the vertical delay control lines 25a, 25b, are connected 25c, 25d and. The control circuit 23, the vertical delay control line 25a, 25b, 25c, to 25d, a signal of "1 state" or "0 state", entered individually.
Vertical delay control line 25a is transmitting and receiving circuit 32a, 32c, 32e, and 32g, and is connected to the individual control circuits 36a, 36e.
Vertical delay control line 25b includes a transmitting and receiving circuit 32a, 32c, 32e, and 32g, and is connected to the individual control circuit 36c, 36 g.
Vertical delay control line 25c includes a transmitting and receiving circuit 32 b, 32d, 32f, and 32h, are connected to the individual control circuits 36b, 36f.
Vertical delay control line 25d is transmitting and receiving circuit 32 b, 32d, 32f, and 32h, it is connected to the individual control circuit 36d, 36h.

The control circuit 23 is connected to the switching control line 26. Switching control line 26, each element circuit 31 has, connected to the individual control circuit 36. The control circuit 23, the switching control line 26, and inputs the signal of "1 state" or "0 state".

Individual control circuit 36, during the idle period, the switch control line 26, a horizontal delay control line 24, in response to the input signal of the vertical delay control line 25, a signal of "1 state" or "0 state" transceiver circuit and outputs it to the 32.

11, the switching control line 25, a horizontal delay control line 24 (branch line 40), the input signal of the branch line 38, as the truth table the relationship between the output signal of the individual control lines 37 and the internal control line 39 show.

Write timing to the storage circuit 51, the switching control line 26, is controlled by the horizontal delay control line 24. During the writing period, the signal state of the branch line 38 is written in the memory circuit 51. Write time out, a signal branch line 38 is not written to the memory circuit 51 holds a signal state that has been written just before.

Signal output to the transceiver circuit 32 is controlled by the switching control line 26. Switching control line 26, as transmission and reception circuit 32 does not operate during the idle period, it controls the signal of the individual control lines 37 to the "0 state". On the other hand, during the reception period, a signal storage circuit 51 is holding, so as to output to the transceiver circuit 32 is controlled by the switching control line 26.
For example, when both the switching control line 26 and the lateral delay control line 24 of the signal is "1 state", the memory circuit 51 becomes the writing period. Storage circuit 51, the signal state of the branch line 38, and stores "0 state" or "1 state", and outputs a signal state stored to internal control lines 39.

When the switching control line 26 is "1 state", the horizontal delay control line 24 is "0 state", the outer writing period to the storage circuit 51. Storage circuit 51, regardless of the state of the branch line 38, to hold the state of the previously stored, and outputs a signal that is stored in the internal control line 39.

When the switching control line 26 is "0 state", regardless of the state of the horizontal delay control line 24 and branch line 38 becomes the writing period outside to the storage circuit 51, and outputs the state of the internal control line 39 to the transmitting and receiving circuit 32 . For example, when the signal of the individual control lines 37 is "1 state", the transmission and reception circuit 32 is power-on, when the signal of the individual control lines 37 is "0 state", the transmission and reception circuit 32 powers off.

Figure 12 shows a timing chart of a 2D array IC shown in FIG. 10.
Hereinafter, a specific operation example of a 2D array IC in FIG. 10 will be described with reference to FIG. 12.

In idle period 11, since the switching control line 26 is "1 state", the entire element circuit is a state of power-off, the signal output are not.
Horizontal delay control lines 24a, 24b and for vertical delay control line 25a and 25c is "1 state", the horizontal delay control line 24a and the vertical delay control line 25a is the output of the connected individual control circuit 36a individually control line 37a When the horizontal delay control line 24b and the "1 state" at the individual control lines 37b transmit and receive periods 11 which is the output of the vertical delay control line 25c is connected to the individual control circuit 36b, and the other individual control lines 37c, 37d It becomes "0 state".

In idle period 12, since the switching control line 26 is "1 state", the entire element circuit is a state of power-off, the signal output are not. Further, since the horizontal delay control line 24a, 24b is switched to "0 state", individual control lines 37a, 37b, 37c, the value of 37d is maintained.
For horizontal delay control lines 24c, 24d and vertical delay control lines 25b and 25c is "1 state", the horizontal delay control line 24d and vertical delay control line 25b is the output of the connected individual control circuit 36g individual control lines 37g When "1 state" and in the individual control lines 37f transmit and receive periods 11 transverse delay control line 24c and vertical delay control line 25c is the output of the connected individual control circuit 36f, the other individual control line 37e, 37h It becomes "0 state".

In reception period 11, since the switching control line 26 becomes "0 state", writing to the memory circuit 51 becomes impossible, the memory to which the signal of the memory circuit 51 is output to the transceiver circuit 32. In response to the output signal to the reception circuit 32, transmission and reception circuit is a power on-off state.

METHOD example, the number of vertical delay control line which is laid in the element circuits on one line of a vertical is less than the number of elements circuitry present in one line on a certain vertical, as described in Example 1 in all the branch lines 38, can not be created by branching from different control lines, it is not possible to power on or power off individually each transceiver circuit 32.

In this embodiment, for connecting both laterally and laid the horizontal delay control line and vertically to laid the vertical delay control lines to the individual control circuits, cloth vertical element circuits on one line the number of lines have been vertical delay control lines, even less than the number of elements circuitry present in one line on a certain vertical, you are possible to power on or power off the transceiver circuit individually.

Therefore, in the longitudinal and transverse directions, the case of a 2D array IC delay control line is laid, individually control circuit a signal line required for the input of 36, the delay control line which is laid in the longitudinal and transverse directions since branching to be used from a small wiring area, it is possible to realize a power-on and off individually transceiver circuit.

13, included in the circuit of FIG. 8, the delay control circuit 33, transmitting circuit 34, showing a specific example of connection of the individual control circuits 36. Figure 13 is compared with FIG. 8 describes the internal configuration of the transmitting circuit 34. Further, the output of the transmitting circuit 34, and an additional resistor R1 and a switch SW1. For example, transmitting circuit 34, a decision circuit 61, a positive level shifter 63, a negative level shifter 64, the positive driver 65 is a circuit having a negative driver 66.

A delay control circuit 33 receiving circuit 35, a horizontal delay control line 24, in response to the signal inputted from the vertical delay control line 25, to the determination circuit 61 a signal inp "1 state" or "0 state", the signal inn "1 state" or "0 state" to the determination circuit 62, respectively output.

Individual control circuit 36 ​​includes a horizontal delay control line 24, the branch line 38, in response to the signal inputted from the switching control line 26, signals through individual control lines 37 "1 state" or "0 state", decision circuits 61 and 62, and outputs it to SW1. For example, the configuration of the individual control circuit 36 ​​is the circuit of FIG.

Judging circuit 61, as an input, is connected to a separate control line 37 and the signal inp, a circuit connected to a positive level shifter 63 as output. Judging circuit 61, the individual control lines 37, in accordance with an input signal of the signal inp, and outputs a signal of "1 state" or "0 state" to a positive level shifter 63. For example, individual control line 37 only when both the signal inp is "1 state", and outputs a signal of "1 state" to a positive level shifter 63.

Positive level shifter 63, as an input, is connected to the determination circuit 61, as an output, a circuit connected to the positive driver 65. Positive level shifter 63, the input from the decision circuit 61 the signal is a circuit for shifting the level of the high-pressure signal. Level shifted signal to the high-voltage signal is output to the positive driver 65.

Positive driver 65, as an input, is connected to a positive level shifter 63, as an output, the transducer 41, a resistor R1, and is connected to the receiving circuit 35. From the positive driver 65, and outputs a signal having a positive amplitude which is amplified to the transducer 41.

Judging circuit 62, as an input, is connected to a separate control line 37 and the signal inn, is a circuit which is connected to a negative level shifter 64 as output. Judging circuit 62, the individual control lines 37, in accordance with an input signal of the signal inn, and outputs a signal of "1 state" or "0 state" to the negative level shifter 64. For example, individual control line 37 only when both the signal inn is "1 state", and outputs a signal of "1 state" to the negative level shifter 64.

Negative level shifter 64, as an input, is connected to the determination circuit 62, as an output, a circuit connected to the negative driver 66. Negative level shifter 64, the input from the decision circuit 62 the signal is a circuit for shifting the level of the high-pressure signal. Level shifted signal to the high-voltage signal is output to the negative of the driver 66.

Negative driver 66, as an input, is connected to a negative level shifter 64, as an output, the transducer 41, a resistor R1, and is connected to the receiving circuit 35. From a negative driver 66, and outputs a signal having a negative amplitude which is amplified to the transducer 41.

One terminal of the resistor R1 has a positive driver 65, a negative driver 66 is connected vibrator 41, to the receiving circuit 35. The other terminal of the resistor R1 is connected to the switch SW1. Resistor R1 is installed to send accumulated in the output OUT charges to GND.
Switch SW1 is controlled by a separate control line 37, a resistor R1, and is connected to GND. When there is an input to the switch SW1 (if the signal of individual control lines 37 "1 state" is input to the switch SW1), the resistor R1 and the GND between conducts. When there is no input to the switch SW1 (if the signal of individual control lines 37 of the "0 state" is input to the switch SW1), the resistor R1 and the GND between becomes an open state. By opening the switch SW1, for example, a driver 65, 66, mistakenly during the vibrator 41, even such as a power line had been connected, it is possible to suppress the current passing through the resistor R1.

Since circuit operation described shows a timing chart of FIG. 13 in FIG. 14.

Judging circuit 61, when the input signal from the signal inp and individual control lines 37 is "1 state" only, and outputs a signal of "1 state" to a positive level shifter 63, the input from the signal inp and individual control lines 37 when either signal, or both are "0 state", and outputs a signal of "0 state" to a positive level shifter 63.

Judging circuit 62, when the input signal from the signal inp and individual control lines 37 is "1 state" only, and outputs a signal of "1 state" to the level shifter 64, the signal inn and the input signal from the individual control lines 37 when either, or both of "0 state", and outputs a signal of "0 state" to the level shifter 64.

In reception period 21 shown in FIG. 14, the signal of the individual control signal 37 is "1 state". At this time, the positive pulse signal is "1 state" from the signal inp is, is input to the determination circuit 61, a positively amplified pulse waveform, the positive driver 65, the signal of the output OUT is output .

Positive pulse signal is "1 state" from the signal inn is is input to the determination circuit 62, a pulse waveform which has been amplified in the negative, the negative of the driver 66, the signal of the output OUT is output.
Since the signal of the individual control signal 37 is "1 state", SW1 is conductive. Therefore, the signal inn, negative charge of the output OUT section charges accumulated shifts to GND through a resistor R1 and SW1, the voltage of the output OUT returns to 0V.

During idle periods 21, writes "0 state" to the memory circuit 51 of the individual control circuit 36, and was controlled so that the signal of the individual control lines 37 becomes "0 state" transmission and reception periods 22.

In reception period 22, the signal of the individual control signal 37 is "0 state". At this time, signal inp, from the signal inn, a positive pulse signal, entering into the determination circuit 61, a signal of "1 state" from the determination circuit is not output, the signal of "0 state", the level shifter is output to the 63 and 64. When the signal of "0 state" is input, since the level shifter 63, 64 is not operated, the voltage of the output OUT section, remains at 0V.

Thus, the state of the individual control lines 37 of the signal, it is possible to drive / stop the transmitting circuit 34. Further, even when the power and is mis-wired to the output OUT of the transmitting circuit 34, by opening the SW1, the leakage current can be suppressed.

Above, in the example shown in the present invention, although using a vertical delay control line 25 to the input of the individual control circuits 36 it is not limited thereto. That is, even if the signal value is changed during the idle period of the transmitting and receiving circuit 32 is powered off, it is possible if control line substitute that does not affect the output of the transmitting and receiving circuit 32. For example, if there is a variable gain amplifier in the transceiver circuit may utilize current control line for controlling the control lines and the amount of current to perform the gain control.
The value of the switching control line 26 and receive circuit power off if "1 state", was to follow the output of the individual control circuits 36 set in if "0 state", "1 state", the present invention is not limited thereto . For example, transmission and reception circuit 32 if the value of the switching control line 26 is "0 state" power off, to follow the output of the individual control circuits 36 set in if "1 state", "0 state", constitute the reception circuit 32 and it may be.

11: apparatus main body 12: an ultrasonic probe 12a: 2D array transducer 12b: 2D array IC
22: Control circuit 24: Side delay control line 25: Vertical delay control line 26: the switching control line 31: element circuit 32: reception circuit 33: delay control circuit 34: wave transmission circuit 35: reception circuit 36: individual control circuit 37: individual control lines 38: the branch line 39: internal control lines 40: the branch line 41: vibrator 51: storage circuit 52: inverter 53: judging circuits 61 and 62: the determination circuit 63: positive level shifter 64: negative the level shifter 65: positive driver 66: negative driver

Claims (15)

  1. A plurality of transducers arranged in an array, corresponding to each of the plurality of transducers, an ultrasonic probe comprising a plurality of element circuit for driving the plurality of transducers,
    A first control line group connected to said plurality of element circuits,
    A second control line connected in common to said plurality of element circuits,
    And a control circuit for the second control line and the first control line group is connected,
    Wherein each element circuit,
    A transceiver circuit connected to said first control line group,
    And individual control circuit for controlling the transmission and reception circuit,
    Branches from a corresponding control line of said first group of control lines, and branch lines the are connected to a separate control circuit,
    It is composed of,
    The individual control circuit is connected to the second control line and the branch line,
    The individual control circuit, a signal from the branch line, on the basis of the signal from the second control line, the ultrasound probe, characterized by switching the individual on-off of the transmission and reception circuit.
  2. The ultrasonic probe according to claim 1,
    The individual control circuit, a memory circuit,
    The individual control circuit, the value of the branch line stored in the storage circuit with the idle period, the ultrasound probe and outputs the value stored in the reception time periods as a switching signal on and off.
  3. The ultrasonic probe according to claim 1,
    The transceiver circuit,
    The signal from the first control line group are inputted, a delay control circuit for controlling the output timing of the drive signal transmitting circuit outputs,
    A transmitting circuit for outputting a drive signal of the vibrator,
    A receiving circuit for amplifying and receiving a signal from the oscillator,
    Ultrasound probe, characterized in that it comprises a.
  4. The ultrasonic probe according to claim 1,
    Said plurality of element circuits and the control circuit, the ultrasonic probe is characterized in that it is formed on a single IC substrate.
  5. The ultrasonic probe according to claim 1,
    The first group of control lines is the delay control line, the ultrasound probe, wherein the second control line is a switch control line.
  6. The ultrasonic probe according to claim 1,
    The transceiver circuit includes a power-on or power-off state in response to the second signal input from the control line,
    When the power-on state, and drives the vibrator in response to a signal from the first control line group,
    When the power-off state, without driving the vibrator,
    Ultrasound probe, characterized in that.
  7. The ultrasonic probe according to claim 1,
    The individual control circuit includes a memory circuit, and an inverter circuit, the determination circuit,
    The memory circuit receives as input said second control line and the branch line, and outputs a signal to the decision circuit,
    The inverter circuit receives as input said second control line, and outputs a signal to the decision circuit,
    The decision circuit, said storage circuit, and inputs the signal from the inverter circuit, and outputs a signal to the transceiver circuit,
    Ultrasound probe, characterized in that.
  8. The ultrasonic probe according to claim 1,
    The individual control circuit, in response to an input signal from the second control line, or hold the value of the individual output signals of said first group of control lines, switching between the outputs the held signal, that ultrasonic probe according to claim.
  9. The ultrasonic probe according to claim 1,
    The branch line is branched from the first group of control lines in the device circuit,
    Ultrasound probe, characterized in that.
  10. A plurality of transducers arranged in an array, corresponding to each of the plurality of transducers, an ultrasonic probe comprising a plurality of element circuit for driving the plurality of transducers,
    A vertical control line group connected to said plurality of element circuits,
    A horizontal control line group connected to said plurality of element circuits,
    A second control line connected in common to said plurality of element circuits,
    And a control circuit wherein said a vertical control line group and the transverse control line group second control line is connected,
    Wherein each element circuit,
    A transceiver circuit connected to the vertical control line group and lateral group of control lines,
    And individual control circuit for controlling the transmission and reception circuit,
    Branches from a corresponding control line of the vertical control line group, a first branch line connected to the individual control circuit,
    Branches from a corresponding control line of the transverse control line group, and a second branch line connected to the individual control circuit,
    It is composed of,
    The individual control circuit, the first branch line, is connected to the second branch line and the second control line,
    The individual control circuit comprises a signal from the first branch line and said second branch line, based on a signal from the second control line, to switch the individual on-off of the transceiver circuit ultrasonic probe according to claim.
  11. The ultrasonic probe according to claim 10,
    The individual control circuit, a memory circuit,
    The individual control circuit, characterized in that the value of the first branch line or the second branch line stored in the storage circuit with the idle period, and outputs the value stored in the reception time periods as a switching signal on and off an ultrasonic probe to be.
  12. The ultrasonic probe according to claim 10,
    The individual control circuit includes a memory circuit, an inverter circuit, a first judgment circuit, the second decision circuit,
    It said second judgment circuit inputs the second control line and the second branch line, and outputs a signal to the memory circuit,
    The memory circuit receives the output of said first branch line and the second judging circuit outputs a signal to the first determination circuit,
    The inverter circuit receives as input said second control line, and outputs the signal to the first determination circuit,
    The first decision circuit, said storage circuit, and inputs the signal from the inverter circuit, and outputs a signal to the transceiver circuit,
    Ultrasound probe, characterized in that.
  13. The ultrasonic probe according to claim 10,
    The transceiver circuit,
    The signal from the vertical control line group and lateral group of control lines is input, a delay control circuit for controlling the output timing of the drive signal transmitting circuit outputs,
    A transmitting circuit for outputting a drive signal of the vibrator,
    A receiving circuit for amplifying and receiving a signal from the oscillator,
    Ultrasound probe, characterized in that it comprises a.
  14. The ultrasonic probe according to claim 10,
    The output side of the transceiver circuit, a switching circuit connected to ground through a resistor is provided, the ultrasound probe, characterized in that the on-off the switching circuit in response to the output of the individual control circuits.
  15. An ultrasonic probe according to any one of claims 1 to 14,
    A control device for controlling the entire ultrasonic diagnostic apparatus, an input apparatus, an apparatus body having an output device, an ultrasonic diagnostic apparatus comprising a.
PCT/JP2015/065670 2015-05-29 2015-05-29 Ultrasonice probe and ultrasonic diagnostic apparatus using same WO2016194083A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP2015/065670 WO2016194083A1 (en) 2015-05-29 2015-05-29 Ultrasonice probe and ultrasonic diagnostic apparatus using same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2015/065670 WO2016194083A1 (en) 2015-05-29 2015-05-29 Ultrasonice probe and ultrasonic diagnostic apparatus using same

Publications (1)

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WO2016194083A1 true true WO2016194083A1 (en) 2016-12-08

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005040376A (en) * 2003-07-23 2005-02-17 Aloka Co Ltd Two-dimensional array ultrasonic probe
JP2006122659A (en) * 2004-10-29 2006-05-18 General Electric Co <Ge> Method and device for controlling scanning of mosaic sensor array
JP2010142639A (en) * 2008-12-17 2010-07-01 General Electric Co <Ge> System and method for operating two-dimensional transducer array

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005040376A (en) * 2003-07-23 2005-02-17 Aloka Co Ltd Two-dimensional array ultrasonic probe
JP2006122659A (en) * 2004-10-29 2006-05-18 General Electric Co <Ge> Method and device for controlling scanning of mosaic sensor array
JP2010142639A (en) * 2008-12-17 2010-07-01 General Electric Co <Ge> System and method for operating two-dimensional transducer array

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