WO2016181261A1 - Dispositif d'affichage, module d'affichage et dispositif électronique - Google Patents

Dispositif d'affichage, module d'affichage et dispositif électronique Download PDF

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Publication number
WO2016181261A1
WO2016181261A1 PCT/IB2016/052556 IB2016052556W WO2016181261A1 WO 2016181261 A1 WO2016181261 A1 WO 2016181261A1 IB 2016052556 W IB2016052556 W IB 2016052556W WO 2016181261 A1 WO2016181261 A1 WO 2016181261A1
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Prior art keywords
transistor
film
semiconductor film
oxide semiconductor
insulating film
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PCT/IB2016/052556
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English (en)
Japanese (ja)
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豊高耕平
肥塚純一
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株式会社半導体エネルギー研究所
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Priority to JP2017517444A priority Critical patent/JPWO2016181261A1/ja
Publication of WO2016181261A1 publication Critical patent/WO2016181261A1/fr

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • One embodiment of the present invention relates to a display device, a display module, and an electronic device.
  • one embodiment of the present invention is not limited to the above technical field.
  • the technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method.
  • this invention relates to a process, a machine, a manufacture, or a composition (composition of matter).
  • one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, and a driving method thereof.
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • a semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are one embodiment of the semiconductor device.
  • An imaging device, a display device, a liquid crystal display device, a light emitting device, an electro-optical device, a power generation device (including a thin film solar cell, an organic thin film solar cell, and the like) and an electronic device may include a semiconductor device.
  • a technique for forming a transistor also referred to as a field effect transistor (FET) or a thin film transistor (TFT)) using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention.
  • the transistor is widely applied to an electronic device such as an integrated circuit (IC) or a display device.
  • IC integrated circuit
  • a semiconductor material typified by silicon is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.
  • the transistor is used in a display device such as an active matrix organic electroluminescence (EL) display.
  • a display device such as an active matrix organic electroluminescence (EL) display.
  • Each pixel of the display device is provided with a transistor for driving the organic EL element.
  • the threshold voltage of the transistor varies depending on the manufacturing process, the display quality of the display is lowered.
  • Patent Document 1 a light emitting device in which a pixel is provided with a circuit that corrects threshold variation is disclosed (Patent Document 1).
  • a transistor using an oxide semiconductor film as an active layer As a transistor using an oxide semiconductor film as an active layer, a transistor having a structure in which a gate electrode and a source electrode and a gate electrode and a drain electrode partially overlap with each other is often manufactured.
  • parasitic capacitance is generated between the gate electrode and the source electrode and between the gate electrode and the drain electrode.
  • the parasitic capacitance increases the load capacitance of the scanning line and the data line, which hinders the production of a high-definition panel that requires a high frequency.
  • it is effective to provide a circuit for correcting variations in the threshold voltage of the transistor that drives the organic EL element in the pixel of the organic EL display.
  • the parasitic capacitance is large, the correction accuracy is reduced.
  • the electrical characteristics of the region where the semiconductor film does not overlap with the gate electrode and the source electrode, or the region where the semiconductor film does not overlap with the gate electrode and the drain electrode since it is difficult to reduce the resistance, the field-effect mobility or current driving capability of the transistor may be reduced.
  • an object of one embodiment of the present invention is to provide a display device with high display quality. Another object of one embodiment of the present invention is to provide a high-speed display device. Another object of one embodiment of the present invention is to provide a high-definition display device. Another object of one embodiment of the present invention is to provide a display device with low power consumption. Another object of one embodiment of the present invention is to provide a novel display device.
  • One embodiment of the present invention is a display device including a driving transistor, a switching transistor, a light-emitting element, a capacitor, and a current supply line.
  • One of the source and the drain of the driving transistor is electrically connected to the light emitting element, and the other of the source and the drain is electrically connected to the current supply line.
  • the driving transistor is a first transistor
  • the switching transistor is a second transistor.
  • the first transistor and the second transistor each include a first gate electrode, a first gate insulating film, a semiconductor film, a source electrode, and a drain electrode, and the semiconductor film is electrically connected to the source electrode.
  • the semiconductor film is electrically connected to the drain electrode, and the first gate insulating film is provided between the semiconductor film and the first gate electrode.
  • the semiconductor film has a region overlapping with the first gate electrode, the semiconductor film overlaps with the source electrode in part of the region, and the drain electrode in another part of the region. Overlap.
  • the semiconductor film has a region overlapping with the first gate electrode, and the semiconductor film does not overlap with the source electrode in the region and does not overlap with the drain electrode in the region.
  • the semiconductor device includes a plurality of switching transistors, and at least one of the switching transistors is a second transistor.
  • the switching transistors are all second transistors.
  • the display device includes a scanning line and a data line, one of the switching transistors is a selection transistor, and the gate of the selection transistor is electrically connected to the scanning line.
  • One of the source and the drain of the selection transistor is preferably electrically connected to the data line, and the selection transistor is preferably a second transistor.
  • the first transistor includes a second gate electrode and a second gate insulating film.
  • the second gate insulating film includes a semiconductor film and a second gate electrode.
  • the semiconductor film is provided between the first gate electrode and the second gate electrode, and is a unit in a capacitor element formed of the first gate electrode, the first gate insulating film, and the semiconductor film.
  • the capacitance per area is preferably larger than the capacitor formed by the second gate electrode, the second gate insulating film, and the semiconductor film.
  • the second transistor includes a second gate electrode and a second gate insulating film.
  • the second gate insulating film includes a semiconductor film and a second gate.
  • the semiconductor film is provided between the first gate electrode and the second gate electrode, and is formed of the first gate electrode, the first gate insulating film, and the semiconductor film. It is preferable that the capacitance per unit area is larger than that of the capacitor formed by the second gate electrode, the second gate insulating film, and the semiconductor film.
  • the semiconductor film includes a second region that overlaps with the second gate electrode, the semiconductor film does not overlap with the source electrode in the second region, and It is preferable that the drain electrode does not overlap with the second region.
  • the semiconductor film is an oxide semiconductor film
  • the oxide semiconductor film includes a first oxide semiconductor film on the gate electrode side and a second oxide on the first oxide semiconductor film.
  • the first oxide semiconductor film has an In atomic ratio of M (M represents Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).
  • the second oxide semiconductor film preferably has a smaller atomic ratio of In than the first oxide semiconductor film.
  • the oxide semiconductor film preferably includes In, M, and Zn, and M is Ga.
  • the oxide semiconductor film preferably includes a crystal part, and the crystal part preferably includes a portion where the c-axis of the crystal part is parallel to the normal vector of the formation surface of the oxide semiconductor film.
  • the first oxide semiconductor film preferably includes a portion where the ratio of crystal parts is higher than that of the second oxide semiconductor film.
  • the first oxide semiconductor film preferably includes a portion with a lower hydrogen concentration than the second oxide semiconductor film.
  • a light emitting element is an organic electroluminescent element.
  • the display device includes a scan line and a data line. In a region where the scan line and the data line intersect, the display device includes a first transistor or a second line between the scan line and the data line.
  • a structure having an insulating film thicker than the first gate insulating film or the second gate insulating film of the transistor may be employed.
  • Another embodiment of the present invention is a display module including the display device and a touch sensor.
  • Another embodiment of the present invention is an electronic device including the pixel described in any one of the above structures, the display device, or the display module, and an operation key or a battery.
  • a display device with high display quality can be provided according to one embodiment of the present invention.
  • a high-speed display device can be provided.
  • a high-definition display device can be provided.
  • a display device with low power consumption can be provided.
  • a novel display device can be provided.
  • the circuit diagram of a pixel. Pixel timing chart The figure which shows typically operation
  • the circuit diagram of a pixel. Pixel timing chart The figure which shows typically operation
  • Pixel timing chart The figure which shows typically operation
  • 4A and 4B are a top view and cross-sectional views illustrating one embodiment of a transistor.
  • 4A and 4B are a top view and cross-sectional views illustrating one embodiment of a transistor.
  • 4A and 4B are a top view and cross-sectional views illustrating one embodiment of a transistor.
  • 4A and 4B are a top view and cross-sectional views illustrating one embodiment of a transistor.
  • 4A and 4B are a top view and cross-sectional views illustrating one embodiment of a transistor.
  • 4A and 4B are a top view and cross-sectional views illustrating one embodiment of a transistor.
  • 4A and 4B are a top view and cross-sectional views illustrating one embodiment of a transistor.
  • 4A and 4B are a top view and cross-sectional views illustrating one embodiment of a transistor.
  • 4A and 4B are a top view and cross-sectional views illustrating one embodiment of a transistor.
  • 10 is a cross-sectional view illustrating an example of a manufacturing process of a transistor.
  • 10 is a cross-sectional view illustrating an example of a manufacturing process of a transistor.
  • 10 is a cross-sectional view illustrating an example of a manufacturing process of a transistor.
  • 10 is a cross-sectional view illustrating an example of a manufacturing process of a transistor.
  • 10 is a cross-sectional view illustrating an example of a manufacturing process of a transistor.
  • FIGS. Sectional TEM image of CAAC-OS, planar TEM image and image analysis image thereof.
  • FIG. 6 shows changes in crystal parts of an In—Ga—Zn oxide due to electron irradiation.
  • 8A and 8B illustrate a method for forming a CAAC-OS.
  • FIG. 6 illustrates a crystal of InMZnO 4 .
  • 8A and 8B illustrate a method for forming a CAAC-OS.
  • FIG. 8A and 8B illustrate a method for forming a CAAC-OS.
  • 8A and 8B illustrate a method for forming an nc-OS.
  • FIG. 14 is a top view illustrating one embodiment of a display device.
  • FIG. 14 is a cross-sectional view illustrating one embodiment of a display device.
  • FIG. 10 is a block diagram and a circuit diagram illustrating a display device.
  • 4A and 4B are a top view and cross-sectional views illustrating one embodiment of a transistor.
  • the figure explaining a display module. 10A and 10B each illustrate an electronic device.
  • 10A and 10B each illustrate an electronic device.
  • the circuit diagram of a pixel. The circuit diagram of a pixel.
  • the circuit diagram of a pixel The circuit diagram of a pixel.
  • the circuit diagram of a pixel. The circuit diagram of a pixel.
  • the circuit diagram of a pixel. The circuit diagram of a pixel.
  • the circuit diagram of a pixel. The circuit diagram of a pixel.
  • the circuit diagram of a pixel. The circuit diagram of a pixel.
  • the circuit diagram of a pixel. The circuit diagram of a pixel. 4A and 4B are a top view and cross-sectional views illustrating one embodiment of a transistor.
  • 4A and 4B are a top view and cross-sectional views illustrating one embodiment of a transistor.
  • a transistor is an element having at least three terminals including a gate, a drain, and a source.
  • a channel region is provided between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and a current flows through the drain, channel region, and source. It is something that can be done.
  • a channel region refers to a region through which a current mainly flows.
  • the functions of the source and drain may be switched when transistors with different polarities are used or when the direction of current changes during circuit operation. Therefore, in this specification and the like, the terms source and drain can be used interchangeably.
  • source and drain of a transistor interchange with each other depending on the channel type of the transistor and the level of potential applied to each terminal.
  • a terminal to which a low potential is applied is called a source
  • a terminal to which a high potential is applied is called a drain
  • a terminal to which a high potential is applied is called a source.
  • the connection relationship between transistors may be described on the assumption that the source and the drain are fixed. However, the names of the source and the drain are actually switched according to the above-described potential relationship. .
  • “electrically connected” includes a case of being connected via “something having an electric action”.
  • the “thing having some electric action” is not particularly limited as long as it can exchange electric signals between connection targets.
  • “thing having some electric action” includes electrodes, wiring, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.
  • a silicon oxynitride film refers to a film having a higher oxygen content than nitrogen as the composition, and a silicon nitride oxide film has a nitrogen content as compared to oxygen as a composition. Refers to membranes with a lot of
  • parallel means a state in which two straight lines are arranged at an angle of ⁇ 10 ° to 10 °. Therefore, the case of ⁇ 5 ° to 5 ° is also included.
  • Very refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included.
  • the terms “film” and “layer” can be interchanged with each other depending on circumstances or circumstances.
  • the term “conductive layer” may be changed to the term “conductive film”.
  • the term “insulating film” may be changed to the term “insulating layer” in some cases.
  • the pixel includes a driving transistor, a switching transistor, a capacitor element, and a light emitting element.
  • the display device has a current supply line.
  • one of the source and the drain of the driving transistor is electrically connected to the light emitting element, and the other of the source and the drain of the driving transistor is electrically connected to the current supply line.
  • the driving transistor is a first transistor, and the switching transistor is a second transistor.
  • the first transistor and the second transistor each include a first gate electrode, a first insulating film, a semiconductor film, a source electrode, and a drain electrode.
  • the semiconductor film is electrically connected to the source electrode.
  • the semiconductor film is electrically connected to the drain electrode.
  • the first gate insulating film is provided between the semiconductor film and the first gate electrode.
  • the semiconductor film has a region overlapping with the first gate electrode, overlaps with the source electrode in part of the region, and overlaps with the drain electrode in another part of the region.
  • the semiconductor film has a region overlapping with the first gate electrode, does not overlap with the source bipolar electrode in the region, and does not overlap with the drain electrode in the region.
  • the display device When the display device includes a plurality of switching transistors, at least one of the switching transistors is a second transistor. In the case where the display device includes a plurality of switching transistors, it is preferable that all of the switching transistors are second transistors.
  • the display device includes a scan line and a data line.
  • One of the switching transistors is a selection transistor, the gate of the selection transistor is electrically connected to the scan line, and one of the source and the drain is It is preferable that the selection transistor is a second transistor electrically connected to the data line.
  • a structure in which a semiconductor film has a region overlapping with a first gate electrode, overlaps with a source electrode in part of the region, and overlaps with a drain electrode in another part of the region is Lov. Structure.
  • a transistor having the Lov structure is referred to as a Lov transistor. Therefore, the first transistor is a Lov transistor.
  • a structure in which the semiconductor film has a region overlapping with the first gate electrode, does not overlap with the source electrode in the region, and does not overlap with the drain electrode in the region is referred to as a Loff structure.
  • a transistor having a Loff structure is referred to as a Loff type transistor. Therefore, the second transistor is a Loff type transistor. Note that in this specification, a region that does not overlap with the first gate electrode, the source electrode, and the drain electrode in the semiconductor film is referred to as a Loff region.
  • the first transistor and the second transistor may have two gate electrodes.
  • the first transistor and the second transistor each include a first gate electrode, a first insulating film, a second gate electrode, a second insulating film, a semiconductor film, a source electrode, and a drain electrode.
  • the semiconductor film is electrically connected to the source electrode.
  • the semiconductor film is electrically connected to the drain electrode.
  • the first gate insulating film is provided between the semiconductor film and the first gate electrode.
  • the second gate insulating film is provided between the semiconductor film and the second gate electrode.
  • the semiconductor film is provided between the first gate electrode and the second gate electrode.
  • the semiconductor film in a structure having two gate electrodes, has a region overlapping with the first gate electrode, overlaps with the source electrode in part of the region, and is another part of the region.
  • a structure overlapping with the drain electrode in the portion is a Lov transistor.
  • the semiconductor film in the structure having two gate electrodes, has a region overlapping with the first gate electrode, does not overlap with the source electrode in the region, and does not overlap with the source electrode.
  • a structure that does not overlap with the transistor is a Loff type transistor.
  • the semiconductor film has a second region that overlaps with the second gate electrode, and overlaps with the source electrode in part of the second region, or part of the second region.
  • the structure may overlap with the drain electrode in FIG. Note that in the Loff transistor having two gate electrodes, the semiconductor film has a second region overlapping with the second gate electrode, does not overlap with the source electrode in the second region, and It is preferable that it does not overlap with the drain electrode in the region 2.
  • a gate electrode having a larger capacity per unit area in a capacitor formed of a gate electrode, a gate insulating film, and a semiconductor film is referred to as the first gate electrode. It is called a gate electrode.
  • a gate electrode facing the first gate electrode with the semiconductor film interposed therebetween is called a second gate electrode.
  • the semiconductor film functions as an electrode of a capacitor because the carrier concentration is increased by a voltage applied to the gate electrode. Therefore, the gate electrode, the gate insulating film, and the semiconductor film can be regarded as a capacitor element using the gate electrode and the semiconductor film as electrodes and the gate insulating film as an insulator.
  • the capacitance of the capacitor formed by the gate electrode, the gate insulating film, and the semiconductor film may be referred to as a gate oxide film capacitance or a gate capacitance.
  • the switching transistor or the selection transistor has a Loff structure with little parasitic capacitance, so that a load caused by driving is reduced.
  • a high-definition panel can be manufactured.
  • the panel can be driven at high speed.
  • the selection transistor when the display device is driven, after data is written to the capacitor element, when the selection transistor is turned off, the charge stored in the parasitic capacitance of the transistor flows to the capacitor element, and the data voltage stored in the capacitor element May decrease. In this case, it is necessary to increase the data voltage in advance in consideration of the decrease in voltage, but if the data voltage increases, the power consumption of the entire display device increases.
  • the selection transistor has a Loff structure with little parasitic capacitance, an increase in power consumption due to an increase in data voltage can be reduced.
  • the driving transistor supplies current to the light emitting element, if the threshold voltage of the driving transistor varies, the display quality is deteriorated. Therefore, a circuit and a driving method for correcting the variation in threshold value are required.
  • the correction accuracy of a circuit also referred to as a threshold correction circuit
  • the correction accuracy of a circuit for correcting a threshold provided in a pixel may be reduced due to a parasitic capacitance of a selection transistor or a switching transistor. At this time, by using a Loff type transistor with a small parasitic capacitance as the switching transistor or the selection transistor, it is possible to improve the accuracy of correcting the threshold variation.
  • the Loff region in the Loff transistor often has a high resistance when a process for reducing the resistance is not performed.
  • This high-resistance Loff region decreases the field-effect mobility or current driving capability of the Loff-type transistor.
  • the resistance since the range of the Loff region varies during the manufacturing process, the resistance also varies, and as a result, the degree to which the field-effect mobility or the current driving capability is decreased may vary.
  • the luminance of the light emitting element changes depending on the current supplied by the driving transistor. Therefore, the drive transistor is required to have high field effect mobility or current driving capability and good uniformity of field effect mobility or current driving capability. Therefore, in this configuration, a Lov transistor is used as the drive transistor.
  • the Lov transistor has a parasitic capacitance, it does not have a Loff region between the source and drain electrodes and the active region of the semiconductor film, so that there is no reduction in field effect mobility or current driving capability due to the Loff region. Therefore, the Lov transistor has high field effect mobility or current driving capability, and also has good field effect mobility or current driving capability.
  • a high-definition and high-speed display device can be manufactured.
  • a pixel can have various circuit configurations depending on its function.
  • the configuration of the five pixels of the present invention will be described below.
  • an example of a driving method for correcting the above-described threshold variation of the driving transistor will be described.
  • FIG. 1 shows an example of a circuit diagram of the pixel 10.
  • the pixel 10 includes a transistor 11, transistors 21 to 25, a capacitor element 12, and a light emitting element 14.
  • the transistor 11 is a driving transistor
  • the transistor 21 is a selection transistor
  • the transistors 22 to 25 are switching transistors.
  • the wirings 26 to 28 function as scan lines or gate lines.
  • the wiring SL has a function as a data line.
  • the wiring VL functions as a current supply line.
  • the wiring CL has a function as a cathode line.
  • the wiring ML has a function as a monitor line.
  • One of a source and a drain of the transistor 11 is electrically connected to the light-emitting element 14 with the transistor 24 interposed therebetween, and the other of the source and the drain is electrically connected to a wiring VL that functions as a current supply line.
  • the gate of the transistor 21 is electrically connected to the wiring 26 functioning as a scanning line, and one of the source and the drain is electrically connected to the wiring SL functioning as a data line.
  • the transistor 11 as a driving transistor is a Lov type transistor. Further, the transistor 21 which is a selection transistor and the transistors 22 to 25 which are switching transistors are all Loff type transistors. In FIG. 1, “Loff” is written for the Loff type transistor, and “Lov” is written for the Lov type transistor.
  • the potential of the pixel electrode of the light emitting element 14 is controlled according to the image signal Sig input to the pixel 10. Further, the luminance of the light emitting element 14 is determined by a potential difference between the pixel electrode and the common electrode.
  • the light-emitting element 14 when an organic electroluminescence element is used as the light-emitting element 14, one of the anode and the cathode functions as a pixel electrode, and the other functions as a common electrode.
  • FIG. 1 illustrates the configuration of the pixel 10 using the anode of the light emitting element 14 as a pixel electrode and the cathode of the light emitting element 14 as a common electrode. Note that the light-emitting element 14 has an equivalent function in other configuration examples.
  • the transistor 21 has a function of controlling a conduction state between the wiring SL and one of the pair of electrodes of the capacitor 12.
  • the other of the pair of electrodes of the capacitor 12 is connected to one of the source and the drain of the transistor 11.
  • the transistor 22 has a function of controlling a conduction state between the wiring 29 and the gate of the transistor 11.
  • the transistor 23 has a function of controlling a conduction state between one of the pair of electrodes of the capacitor 12 and the gate of the transistor 11.
  • the transistor 24 has a function of controlling a conduction state between one of the source and the drain of the transistor 11 and the anode of the light-emitting element 14.
  • the transistor 25 has a function of controlling electrical continuity between one of the source and the drain of the transistor 11 and the wiring ML.
  • the other of the source and the drain of the transistor 11 is connected to the wiring VL.
  • the transistor 21 is turned on or off according to the potential of the wiring 26 connected to the gate of the transistor 21.
  • Selection of ON or OFF in the transistor 22 is performed according to the potential of the wiring 26 connected to the gate of the transistor 22.
  • Selection of ON or OFF in the transistor 23 is performed according to the potential of the wiring 27 connected to the gate of the transistor 23.
  • Selection of ON or OFF in the transistor 24 is performed according to the potential of the wiring 27 connected to the gate of the transistor 24.
  • Selection of ON or OFF in the transistor 25 is performed according to the potential of the wiring 28 connected to the gate of the transistor 25.
  • FIG. 2 illustrates a timing chart of the potentials of the wiring 26, the wiring 27, and the wiring 28 connected to the pixel 10 illustrated in FIG. 1 and the potential of the image signal Sig supplied to the wiring SL.
  • the timing chart illustrated in FIG. 2 illustrates the case where all the transistors included in the pixel 10 illustrated in FIG. 1 are n-channel transistors. 3 to 5 schematically illustrate the operation of the pixel 10 in each period. However, in FIGS. 3 to 5, transistors other than the transistor 11 are illustrated as switches for easy understanding of the operation of the pixel 10.
  • a low-level potential is applied to the wiring 26
  • a high-level potential is applied to the wiring 27, and a high-level potential is applied to the wiring 28.
  • the transistor 23, the transistor 24, and the transistor 25 are turned on, and the transistor 21 and the transistor 22 are turned off.
  • the transistor 24 and the transistor 25 are turned on, the potential V0 of the wiring ML is supplied to one of a source and a drain of the transistor 11 and the other of the pair of electrodes of the capacitor 12 (illustrated as a node A).
  • the potential Vano is applied to the wiring VL, and the potential Vcat is applied to the wiring CL.
  • the potential Vano is preferably higher than the potential obtained by adding the threshold voltage Vthe of the light emitting element 14 to the potential V0.
  • the potential V0 is desirably lower than a potential obtained by adding the threshold voltage Vthe of the light emitting element 14 to the potential Vcat.
  • a high-level potential is applied to the wiring 26
  • a low-level potential is applied to the wiring 27, and a low-level potential is applied to the wiring 28. Accordingly, as illustrated in FIG. 3B, the transistor 21 and the transistor 22 are turned on, and the transistor 23, the transistor 24, and the transistor 25 are turned off.
  • the potential applied to the wiring 26 is preferably switched from the high level to the low level after the potential applied to the wiring 26 is switched from the low level to the high level.
  • the potential Vano is applied to the wiring VL, and the potential Vcat is applied to the wiring CL.
  • the wiring SL is supplied with the potential Vdata of the image signal Sig, and the wiring 29 is supplied with the potential V1.
  • the potential V1 is preferably higher than the potential obtained by adding the threshold voltage Vth of the transistor 11 to the potential V0 and lower than the potential obtained by adding the threshold voltage Vth of the transistor 11 to the potential Vano.
  • the light emitting element 14 does not emit light as long as the transistor 24 is off. Therefore, the range of values that can be set as the potential V0 can be widened, and the range of values that can be taken as V1-V0 can also be widened. Accordingly, since the degree of freedom in setting the value of V1-V0 is increased, even when the time required for acquiring the threshold voltage of the transistor 11 is shortened or when the acquisition period of the threshold voltage is limited, the transistor 11 can be accurately set. The threshold voltage can be acquired.
  • one of the pair of electrodes of the capacitor 12 (illustrated as a node C) is supplied with the potential Vdata of the image signal Sig supplied to the wiring SL through the transistor 21.
  • a low-level potential is applied to the wiring 26
  • a high-level potential is applied to the wiring 27, and a low-level potential is applied to the wiring 28. Accordingly, as illustrated in FIG. 4A, the transistor 23 and the transistor 24 are turned on, and the transistor 21, the transistor 22, and the transistor 25 are turned off.
  • the potential applied to the wiring 27 be switched from a low level to a high level after the potential applied to the wiring 26 is switched from a high level to a low level.
  • the potential Vano is applied to the wiring VL
  • the potential Vcat is applied to the wiring CL.
  • the potential Vdata is applied to the node B, so that the gate-source voltage of the transistor 11 becomes Vdata ⁇ V1 + Vth. Therefore, the gate-source voltage of the transistor 11 can be set to a value with the threshold voltage Vth taken into account.
  • variation in the threshold voltage Vth of the transistor 11 can be corrected. Therefore, variation in the current value supplied to the light emitting element 14 can be suppressed, and luminance unevenness of the display device can be reduced.
  • the transistors 21 to 25 have parasitic capacitance
  • the transistors 21 to 25 are changed from on to off or from off to on, the charge accumulated in the parasitic capacitance is discharged or the charge to the parasitic capacitance is discharged. Accumulation occurs.
  • the voltage applied to the capacitor 12 or the gate-source voltage of the transistor 11 may deviate from the value shown in the description of the driving method of this configuration example.
  • the transistor 21 since the transistor 21 is on in the period t12, electric charge is accumulated in the parasitic capacitance of the transistor 21. However, in the next period t13, since the transistor 21 is turned off, the charge stored in the parasitic capacitance is released. Similarly, when the transition from the period t12 to the period t13 occurs, the transistor 22 changes from on to off, so that charge is discharged from the parasitic capacitance of the transistor 22. On the other hand, the transistor 23 and the transistor 24 change from off to on when moving from the period t12 to the period t13, and thus charge accumulation in the parasitic capacitance occurs. Due to the discharge or accumulation of these charges, the voltage applied to the capacitor 12 or the gate-source voltage of the transistor 11 deviates from the value shown in the driving method of this configuration example.
  • the above deviation affects the correction of the threshold voltage variation of the transistor 11.
  • the transistors 21 to 25 included in the pixel 10 are Loff type transistors with little parasitic capacitance, so that the threshold voltage variation can be corrected with high accuracy.
  • the influence of variations in the threshold voltage of the transistor 24 on the current value supplied to the light-emitting element 14 can be reduced.
  • a high-level potential is applied to the gate of the transistor 24, the resistance between the source and the drain of the transistor 24 varies due to variations in the threshold voltage of the transistor 24.
  • the resistance between the source and drain of the transistor 24 is sufficiently higher than that of the light emitting element 14 or the like regardless of the threshold voltage Vth. Get smaller. Therefore, the influence of the variation in the threshold voltage of the transistor 24 on the current value of the light emitting element 14 is reduced.
  • the transistor 24 is turned on and off by making the high level potential applied to the wiring 27 sufficiently larger than the threshold voltage of the transistor 24 and making the low level potential applied to the wiring 27 sufficiently smaller than the threshold voltage of the transistor 24. Can be reliably switched.
  • a low-level potential is applied to the wiring 26
  • a low-level potential is applied to the wiring 27, and a high-level potential is applied to the wiring 28. Accordingly, as illustrated in FIG. 4B, the transistor 25 is turned on, and the transistor 21, the transistor 22, the transistor 23, and the transistor 24 are turned off.
  • the potential Vano is applied to the wiring VL, and the wiring ML is connected to the monitor circuit.
  • the drain current Id of the transistor 11 flows to the wiring ML not through the light emitting element 14 but through the transistor 25.
  • the monitor circuit generates a signal including the value of the drain current Id as information, using the drain current Id flowing through the wiring ML.
  • the drain current Id has a magnitude depending on the field effect mobility of the transistor 11 and the size (channel length, channel width) of the transistor 11.
  • the value of the potential Vdata of the image signal Sig supplied to the pixel 10 can be corrected using the signal. That is, the influence of variations in the field effect mobility of the transistor 11 can be reduced.
  • the transistor 24 changes from on to off, and the transistor 25 changes from off to on.
  • charge discharge from the parasitic capacitance of the transistor 24 and charge accumulation in the transistor 25 occur.
  • the potential of the node A changes, and the voltage applied to the capacitor 12 or the gate-source voltage of the transistor 11 may change.
  • the correction of the potential Vdata of the image signal Sig is shifted.
  • the transistors 24 and 25 are Loff type transistors with a small parasitic capacitance, and thus correction deviation can be reduced.
  • the operation in the period t14 may be performed after the operations in the periods t11 to t13 are repeated a plurality of times.
  • the image signal corresponding to the minimum gradation value 0 is written in the pixels 10 in the row in which the operation is performed, so that the light-emitting elements 14 are made to emit no light.
  • the operation in the period t14 may be performed in the pixels 10 in the next row.
  • the transistor 11 not only the characteristics of the transistor 11 but also the characteristics of the light emitting element 14 may be monitored.
  • An example of the operation in that case is shown in FIG.
  • the electric current of the light emitting element 14 can be taken out.
  • the transistor 25 can be monitored accurately by making it a Loff type transistor.
  • the transistor 11 is a driving transistor
  • the transistor 21 is a selection transistor
  • the transistors 22 to 25 are switching transistors.
  • the transistor 11 as a driving transistor is a Lov type transistor.
  • the transistor 21 and the switching transistor that are selection transistors are Loff type transistors.
  • the transistor 24 and the transistor 25 are Lov transistors.
  • “Loff” is written for the Loff type transistor
  • “Lov” is written for the Lov type transistor.
  • the transistor 24 may require high field effect mobility or current driving capability. Therefore, when the transistor 24 is a Lov transistor, a high-definition panel or a large panel can be manufactured.
  • the transistors 21 to 23 are Loff type transistors, it is possible to reduce the load capacitance of the wiring, improve the accuracy of threshold variation correction, and the like.
  • FIGS. 1 Another modification of the pixel 10 shown in FIG. 1 is shown in FIGS.
  • the transistor in the pixel 10 may have a dual gate structure having two gate electrodes.
  • the semiconductor film is provided between one of the gate electrodes of the transistor and the other of the gate electrodes of the transistor.
  • one electrode of the dual gate structure may be referred to as a first gate electrode or a second gate electrode.
  • the other electrode of the dual gate structure is the first gate electrode or the second gate electrode which is not one electrode of the dual gate structure.
  • FIG. 50 illustrates a pixel 10_3 in which the transistor in the pixel 10 has a dual-gate structure, and one of the gates of the transistor and the other of the gates of the transistor are electrically connected.
  • the transistor in the pixel 10 has a dual gate structure, one of the transistor gates is connected in the same manner as the gate of the transistor in the pixel 10, and the other gate of the transistor is connected to the source or drain of the transistor.
  • One or the other of the source and the drain of the transistor is electrically connected to the pixel 10_4.
  • the other of the gates of the transistors may be electrically connected to a terminal opposite to the source or the drain illustrated in FIG. In other words, a structure in which the terminal electrically connected to the other of the gates of the transistors in FIG. 51 is electrically connected to the drain if the source is the source may be used.
  • the transistor in the pixel 10 has a dual gate structure, one of the gates of the transistor is connected in the same manner as the gate of the transistor in the pixel 10, and the other gate of the transistor is electrically connected to the wiring.
  • a pixel 10_5 having the above structure is shown. 52, the other gate of the transistor 11 is electrically connected to the wiring 11L, the other gate of the transistor 21 is electrically connected to the wiring 21L, and the other gate of the transistor 22 is electrically connected to the wiring 22L.
  • the other gate of the transistor 23 is electrically connected to the wiring 23L, the other gate of the transistor 24 is electrically connected to the wiring 24L, and the other gate of the transistor 25 is electrically connected to the wiring 25L.
  • the wiring 11L and the wirings 21L to 25L may be electrically connected to any other wiring.
  • the wiring 11L and the wirings 21L to 25L may be partially or entirely electrically connected to each other.
  • the structure of the transistor in the pixel illustrated in FIGS. 1 and 50 to 52 may be replaced for each transistor.
  • the transistor in the pixel 10_2 illustrated in FIG. 6 can also have a dual gate structure.
  • the connection between the two gates can be the same as that of the transistor in FIGS.
  • FIG. 7 shows another example of a circuit diagram of the pixel 10A.
  • the pixel 10 ⁇ / b> A includes a transistor 11, transistors 31 to 34, a capacitor element 12, and a light emitting element 14.
  • the transistor 11 is a driving transistor
  • the transistor 31 is a selection transistor
  • the transistors 32 to 34 are switching transistors.
  • the wirings 36 to 38 function as scan lines or gate lines.
  • the wiring SL has a function as a data line.
  • the wiring VL functions as a current supply line.
  • the wiring CL has a function as a cathode line.
  • One of the source and the drain of the transistor 11 is electrically connected to the light-emitting element 14, and the other of the source and the drain of the transistor 11 is electrically connected to a wiring VL that functions as a current supply line.
  • the gate of the transistor 31 is electrically connected to the wiring 36 functioning as a scan line, and one of the source and the drain of the transistor 31 is electrically connected to the wiring SL functioning as a data line.
  • the transistor 11 as a driving transistor is a Lov type transistor.
  • the transistor 31 which is a selection transistor and the transistors 32 to 34 which are switching transistors are all Loff type transistors.
  • “Loff” is written for the Loff type transistor
  • “Lov” is written for the Lov type transistor.
  • the transistor 31 has a function of controlling a conduction state between the wiring SL and one of the pair of electrodes of the capacitor 12.
  • the other of the pair of electrodes of the capacitor 12 is connected to one of the source and the drain of the transistor 11.
  • the transistor 32 has a function of controlling a conduction state between the wiring 39 and the gate of the transistor 11.
  • the transistor 33 has a function of controlling a conduction state between one of the pair of electrodes of the capacitor 12 and the gate of the transistor 11.
  • the transistor 34 has a function of controlling a conduction state between one of the source and the drain of the transistor 11 and the anode of the light-emitting element 14.
  • the other of the source and the drain of the transistor 11 is connected to the wiring VL.
  • the selection of ON or OFF in the transistor 31 is determined by the potential of the wiring 36 connected to the gate of the transistor 31.
  • the on / off selection of the transistor 32 is determined by the potential of the wiring 36 connected to the gate of the transistor 32.
  • Selection of ON or OFF in the transistor 33 is determined by the potential of the wiring 37 connected to the gate of the transistor 33.
  • the on / off selection of the transistor 34 is determined by the potential of the wiring 38 connected to the gate of the transistor 34.
  • FIG. 8 illustrates the potential of the wirings 36 to 38 connected to the pixel 10 ⁇ / b> A illustrated in FIG. 7 and the potential Vdata supplied to the wiring SL with a timing chart. Note that the timing chart illustrated in FIG. 8 illustrates the case where the transistor 11 and the transistors 31 to 34 are n-channel transistors.
  • FIG. 9 schematically shows the operation of the pixel 10A in each period. However, in FIG. 9, transistors other than the transistor 11 are illustrated as switches for easy understanding of the operation of the pixel 10 ⁇ / b> A.
  • a low-level potential is applied to the wiring 36
  • a low-level potential is applied to the wiring 37
  • a high-level potential is applied to the wiring 38. Accordingly, as illustrated in FIG. 9A, the transistor 34 is turned on, and the transistor 11 and the transistors 31 to 33 are turned off.
  • the potential Vano is applied to the wiring VL, and the potential Vcat is applied to the wiring CL.
  • the potential Vano is higher than the potential obtained by adding the threshold voltage Vthe of the light emitting element 14 to the potential Vcat. In the description of this configuration example, it is assumed that the threshold voltage Vthe of the light emitting element 14 is zero.
  • one of the source and the drain of the transistor 11 (illustrated as the node A) becomes a potential obtained by adding the threshold voltage VLhe of the light-emitting element 14 to the potential Vcat.
  • the threshold voltage Vthe since it is assumed that the threshold voltage Vthe is 0, the potential of the node A is the potential Vcat.
  • a high level potential is applied to the wiring 36, a low level potential is applied to the wiring 37, and a low level potential is applied to the wiring 38. Accordingly, the transistor 31 and the transistor 32 are turned on, and the transistor 33 and the transistor 34 are turned off.
  • the potential applied to the wiring 36 is preferably switched from a low level to a high level before the potential applied to the wiring 38 is switched from a high level to a low level.
  • the potential variation at the node A can be reduced by switching the potential applied to the wiring 36.
  • the potential Vano is applied to the wiring VL, and the potential Vcat is applied to the wiring CL.
  • the wiring 39 is supplied with the potential V2, and the wiring SL is supplied with the potential Vdata of the image signal Sig.
  • the potential V2 is preferably higher than the potential obtained by adding the threshold voltage Vth of the transistor 11 and the threshold voltage Vthe of the light-emitting element 14 to the potential Vcat and lower than the potential obtained by adding the threshold voltage Vth of the transistor 11 to the potential Vano.
  • the potential V2 is applied to the gate (illustrated as the node B) of the transistor 11, so that the transistor 11 is turned on. Therefore, the charge of the capacitor 12 is released through the transistor 11, and the potential of the node A, which is the potential Vcat, starts to increase. Finally, when the potential of the node AM becomes the potential V2-Vth, that is, when the gate-source voltage of the transistor 11 decreases to the threshold voltage Vth, the transistor 11 is turned off.
  • a potential Vdata is applied to one electrode (illustrated as a node C) of the capacitor 12.
  • a low level potential is applied to the wiring 36, a high level potential is applied to the wiring 37, and a high level potential is applied to the wiring 38. Accordingly, the transistor 33 and the transistor 34 are turned on, and the transistor 31 and the transistor 32 are turned off.
  • the potential applied to the wiring 37 and the wiring 38 be switched from the low level to the high level after the potential applied to the wiring 36 is switched from the high level to the low level.
  • the potential Vano is applied to the wiring VL
  • the potential Vcat is applied to the wiring CL.
  • FIG. 9C illustrates the operation of the pixel 10A in the period t23.
  • the gate-source voltage of the transistor 11 is Vdata ⁇ V2 + Vth. Therefore, the gate-source voltage of the transistor 11 can be set to a value with the threshold voltage Vth taken into account.
  • the transistors 31 to 34 have parasitic capacitance
  • the charge accumulated in the parasitic capacitance is discharged or the charge to the parasitic capacitance is reduced. Since accumulation occurs, charge may flow to one or the other electrode of the capacitor 12 or the gate of the transistor 11. As a result, the voltage applied to the capacitor 12 or the gate-source voltage of the transistor 11 deviates from the value shown in the driving method of this configuration example.
  • the transistor 31 since the transistor 31 is on in the period t22, electric charge is accumulated in the parasitic capacitance of the transistor 31. Next, in the period t23, the transistor 31 is turned off, so that the charge stored in the parasitic capacitance is released. Similarly, when moving from the period t22 to the period t23, the transistor 32 changes from on to off, and thus charge is discharged from the parasitic capacitance of the transistor 32. On the other hand, since the transistor 33 and the transistor 34 change from off to on, charge is accumulated in the parasitic capacitance.
  • the transistors 31 to 34 included in the pixel 10A are Loff type transistors with little parasitic capacitance, so that the threshold voltage variation can be corrected with high accuracy.
  • the transistor 11 is a driving transistor
  • the transistor 31 is a selection transistor
  • the transistors 32 to 34 are switching transistors.
  • the transistor 11 as a driving transistor is a Lov type transistor.
  • the transistor 31 and the switching transistor which are selection transistors are Loff type transistors.
  • the transistor 34 is a Lov transistor. In FIG. 10, “Loff” is written for the Loff type transistor, and “Lov” is written for the Lov type transistor.
  • the transistor 34 may be required to have high field effect mobility or current driving capability. Therefore, when the transistor 34 is a Lov transistor, a high-definition panel or a large panel can be manufactured.
  • the transistors 31 to 33 are Loff type transistors, the load capacitance of the wiring is reduced, the accuracy of threshold variation correction is improved, and the like.
  • FIGS. 7 Another modification of the pixel 10A shown in FIG. 7 is shown in FIGS.
  • the transistor in the pixel 10A may have a dual gate structure having two gate electrodes.
  • the semiconductor film is provided between one of the gate electrodes of the transistor and the other of the gate electrodes of the transistor.
  • FIG. 53 shows a pixel 10A_3 in which the transistor in the pixel 10A has a dual gate structure, and one of the gates of the transistor is electrically connected to the other of the gates of the transistor.
  • the transistor in the pixel 10A has a dual gate structure, one of the transistor gates is connected in the same manner as the gate of the transistor in the pixel 10A, and the other gate of the transistor is connected to the source or drain of the transistor.
  • One pixel or the pixel 10A_4 electrically connected to the other of the source and the drain of the transistor is illustrated.
  • the other of the gates of the transistors may be electrically connected to a terminal opposite to the source or the drain illustrated in FIG. In other words, a structure in which the terminal electrically connected to the other of the gates of the transistors in FIG. 54 is electrically connected to the drain if the source is the source may be used.
  • the transistor in the pixel 10A has a dual gate structure, one of the gates of the transistor is connected in the same manner as the gate of the transistor in the pixel 10A, and the other gate of the transistor is electrically connected to the wiring.
  • a pixel 10A_5 having the above-described configuration is shown. 55, the other gate of the transistor 11 is electrically connected to the wiring 11L, the other gate of the transistor 31 is electrically connected to the wiring 31L, and the other gate of the transistor 32 is electrically connected to the wiring 32L.
  • the other gate of the transistor 33 is electrically connected to the wiring 33L, and the other gate of the transistor 34 is electrically connected to the wiring 34L.
  • the wiring 11L and the wirings 31L to 34L may be electrically connected to any other wiring.
  • the wiring 11L and the wirings 31L to 34L may be partially or entirely electrically connected to each other.
  • the structure of the transistor in the pixel illustrated in FIGS. 7 and 53 to 55 may be replaced for each transistor.
  • the transistor in the pixel 10A_2 illustrated in FIG. 10 can have a dual gate structure.
  • the connection between the two gates can be the same as, for example, the transistors in FIGS.
  • FIG. 11 shows an example of a circuit diagram of the pixel 10B.
  • the pixel 10 ⁇ / b> B includes a transistor 11, transistors 41 to 45, a capacitor element 12, a capacitor element 13, and a light emitting element 14.
  • the transistor 11 is a driving transistor
  • the transistor 41 is a selection transistor
  • the transistors 42 to 45 are switching transistors.
  • the wirings 46 to 49 function as scan lines or gate lines.
  • the wiring SL has a function as a data line.
  • the wiring VL functions as a current supply line.
  • the wiring CL has a function as a cathode line.
  • the wiring ML has a function as a monitor line.
  • One of a source and a drain of the transistor 11 is electrically connected to the light-emitting element 14, and the other of the source and the drain is electrically connected to a wiring VL that functions as a current supply line.
  • the gate of the transistor 41 is electrically connected to the wiring 48 functioning as a scan line, and one of the source and the drain is electrically connected to the wiring SL functioning as a data line.
  • the transistor 11 as a driving transistor is a Lov type transistor. Further, the transistor 41 which is a selection transistor and the transistors 42 to 45 which are switching transistors are all Loff type transistors. In FIG. 11, “Loff” is written for the Loff type transistor, and “Lov” is written for the Lov type transistor.
  • the transistor 41 has a function of controlling a conduction state between the wiring SL and one of the pair of electrodes of the capacitor 12.
  • the other of the pair of electrodes of the capacitor 12 is connected to the gate of the transistor 11.
  • the transistor 42 has a function of controlling a conduction state between the wiring 50 and the gate of the transistor 11.
  • the transistor 43 has a function of controlling a conduction state between one of the pair of electrodes of the capacitor 12 and one of the source and the drain of the transistor 11.
  • the transistor 44 has a function of controlling a conduction state between one of the source and the drain of the transistor 11 and the anode of the light-emitting element 14.
  • the transistor 45 has a function of controlling electrical continuity between one of the source and the drain of the transistor 11 and the wiring ML.
  • the other of the source and the drain of the transistor 11 is connected to the wiring VL.
  • One of the pair of electrodes included in the capacitor 13 is connected to one of the pair of electrodes of the capacitor 12, and the other is connected to one of the source and the drain of the transistor 11.
  • the transistor 41 is turned on or off according to the potential of the wiring 48 connected to the gate of the transistor 41.
  • the transistor 42 is turned on or off according to the potential of the wiring 47 connected to the gate of the transistor 42.
  • Selection of ON or OFF in the transistor 43 is performed according to the potential of the wiring 47 connected to the gate of the transistor 43.
  • Selection of ON or OFF in the transistor 44 is performed in accordance with the potential of the wiring 49 connected to the gate of the transistor 44.
  • the transistor 45 is turned on or off according to the potential of the wiring 46 connected to the gate of the transistor 45.
  • FIG. 12 illustrates a timing chart of the potentials of the wirings 46 to 49 connected to the pixel 10B illustrated in FIG. 11 and the potential of the image signal Sig supplied to the wiring SL.
  • the timing chart illustrated in FIG. 12 illustrates the case where all the transistors included in the pixel 10B illustrated in FIG. 11 are n-channel transistors. 13 to 15 schematically show the operation of the pixel 10B in each period. However, in FIGS. 13 to 15, transistors other than the transistor 11 are illustrated as switches for easy understanding of the operation of the pixel 10 ⁇ / b> B.
  • a high-level potential is applied to the wiring 46, a high-level potential is applied to the wiring 47, a low-level potential is applied to the wiring 48, and a low-level potential is applied to the wiring 49.
  • the transistor 42, the transistor 43, and the transistor 45 are turned on, and the transistor 41 and the transistor 44 are turned off.
  • the potential Vi2 of the wiring 50 is supplied to the gate (illustrated as the node B) of the transistor 11, and the potential Vi1 of the wiring ML is applied to one of the source and the drain of the transistor 11 (illustrated as the node A). Is given.
  • the potential Vano is applied to the wiring VL
  • the potential Vcat is applied to the wiring CL.
  • the potential Vi1 is preferably lower than a potential obtained by adding the threshold voltage Vthe of the light-emitting element 14 to the potential Vcat.
  • the potential Vi2 is preferably higher than the potential obtained by adding the threshold voltage Vth of the transistor 11 to the potential Vi1. Therefore, the gate-source voltage of the transistor 11 is Vi2-Vi1, and the transistor 11 is turned on.
  • the potential Vi2 is preferably lower than the potential obtained by adding the threshold voltage Vth of the transistor 11 to the potential Vano of the wiring VL.
  • a low level potential is applied to the wiring 46, a high level potential is applied to the wiring 47, a low level potential is applied to the wiring 48, and a low level potential is applied to the wiring 49. Accordingly, as illustrated in FIG. 13B, the transistor 42 and the transistor 43 are turned on, and the transistor 41, the transistor 44, and the transistor 45 are turned off. Through the above operation, the potential Vi ⁇ b> 2 is held at the gate of the transistor 11. Further, the potential Vano is applied to the wiring VL, and the potential Vcat is applied to the wiring CL.
  • the charge of the capacitor 12 is released through the transistor 11 which is on, and the potential of the node A, which is the potential Vi1, starts to increase. Finally, when the potential of the node A converges to Vi2-Vth and the gate-source voltage of the transistor 11 converges to the threshold voltage Vth, the transistor 11 is turned off.
  • the light-emitting element 14 does not emit light as long as the transistor 44 is off. Therefore, the range of values that can be set as the potential Vi1 can be increased, and the range of values that can be taken as Vi2-Vi1 can also be increased. Accordingly, the degree of freedom in setting the value of Vi2-Vi1 is increased, so that even when the time required for acquiring the threshold voltage of the transistor 11 is shortened or when the acquisition period of the threshold voltage is limited, the transistor 11 can be accurately set. The threshold voltage can be acquired.
  • a high level potential is applied to the wiring 46, a low level potential is applied to the wiring 47, a high level potential is applied to the wiring 48, and a low level potential is applied to the wiring 49.
  • the transistor 41 and the transistor 45 are turned on, and the transistor 42, the transistor 43, and the transistor 44 are turned off.
  • a potential Vdata of the image signal Sig is applied to the wiring SL, and the potential Vdata is applied to one of a pair of electrodes of the capacitor 12 (illustrated as a node C) through the transistor 41.
  • the transistor 42 Since the transistor 42 is off, the node B is in a floating state. Further, since the threshold voltage Vth is held in the capacitor 12, when the potential Vdata is applied to one of the pair of electrodes (node C) of the capacitor 12, the capacitance 12 The potential of the node B connected to the other of the pair of electrodes is Vdata + Vth. Further, the potential Vi1 of the wiring ML is supplied to the node A through the transistor 45. Therefore, the voltage Vdata ⁇ Vi1 is applied to the capacitor 13, and the gate-source voltage of the transistor 11 is Vth + Vdata ⁇ Vi1.
  • the potential applied to the wiring 47 is preferably switched from the low level to the high level after the potential applied to the wiring 47 is switched from the high level to the low level.
  • a low level potential is applied to the wiring 46
  • a low level potential is applied to the wiring 47
  • a low level potential is applied to the wiring 48
  • a high level potential is applied to the wiring 49. Accordingly, as illustrated in FIG. 14B, the transistor 44 is turned on, and the transistor 41, the transistor 42, the transistor 43, and the transistor 45 are turned off.
  • the potential Vano is applied to the wiring VL
  • the potential Vcat is applied to the wiring CL.
  • the threshold voltage Vth is held in the capacitor 12
  • the voltage Vdata ⁇ Vi1 is held in the capacitor 13
  • the gate-source voltage of the transistor 11 becomes Vdata + Vth ⁇ Vi1.
  • the anode of the light emitting element 14 becomes the potential Vel
  • the potential of the node B becomes the potential Vdata + Vth + Vel ⁇ Vi1.
  • the potential Vel is a potential that is set when a current is passed through the light emitting element 14 through the transistor 11. Specifically, it is set to a potential between the potential Vano and the potential Vcat.
  • the gate-source voltage of the transistor 11 can be set to a value with the threshold voltage Vth taken into account.
  • variation in the threshold voltage Vth of the transistor 11 can be suppressed. Therefore, variation in the current value supplied to the light-emitting element 14 can be suppressed, and uneven luminance in the display device can be reduced.
  • the transistors 41 to 45 have parasitic capacitance
  • the charge accumulated in the parasitic capacitance is discharged or the charge to the parasitic capacitance is discharged. Accumulation occurs.
  • the voltage applied to the capacitive element 12 or the capacitive element 13 or the gate-source voltage of the transistor 11 may deviate from the value shown in the driving method of this configuration example.
  • the transistor 41 is off, so that no charge is accumulated in the parasitic capacitance of the transistor 41.
  • the transistor 41 is turned on, so that charge is stored in the parasitic capacitance.
  • the transistor 45 changes from off to on, and charge accumulation in the parasitic capacitance of the transistor 45 occurs.
  • the transistor 43 and the transistor 44 change from on to off.
  • the transistor 41 and the transistor 45 change from on to off. Further, the transistor 44 changes from off to on.
  • the transistors 41 to 45 included in the pixel 10B are Loff type transistors with little parasitic capacitance, so that the threshold voltage variation can be corrected with high accuracy.
  • the influence of variations in threshold voltage of the transistor 44 on the current value supplied to the light-emitting element 14 can be reduced.
  • a high-level potential is applied to the gate of the transistor 44
  • the resistance between the source and the drain of the transistor 44 varies due to variations in the threshold voltage of the transistor 44.
  • the transistor 44 is turned on and off by setting the high level potential applied to the wiring 49 sufficiently higher than the threshold voltage of the transistor 44 and setting the low level potential applied to the wiring 49 sufficiently lower than the threshold voltage of the transistor 44. Can be reliably switched.
  • a high level potential is applied to the wiring 46, a low level potential is applied to the wiring 47, a low level potential is applied to the wiring 48, and a low level potential is applied to the wiring 49. Accordingly, as shown in FIG. 15, the transistor 45 is turned on, and the transistor 41, the transistor 42, the transistor 43, and the transistor 44 are turned off.
  • the potential Vano is applied to the wiring VL, and the wiring ML is connected to the monitor circuit.
  • the drain current Id of the transistor 11 flows to the wiring ML not through the light emitting element 14 but through the transistor 45.
  • the monitor circuit generates a signal including the value of the drain current Id as information, using the drain current Id flowing through the wiring ML.
  • the value of the potential Vdata of the image signal Sig supplied to the pixel 10B can be corrected using the signal.
  • the transistor 44 changes from on to off, and the transistor 45 changes from off to on.
  • charge discharge from the parasitic capacitance of the transistor 44 and charge accumulation in the transistor 45 occur.
  • the potential of the node A changes, and the voltage applied to the capacitor 12 or the capacitor 13 or the gate-source voltage of the transistor 11 may change.
  • the correction of the potential Vdata of the image signal Sig is shifted.
  • the transistors 44 and 45 are Loff type transistors with a small parasitic capacitance, so that the correction deviation can be reduced.
  • the operation in the period t35 may be performed after the operations in the periods t31 to t34 are repeated a plurality of times.
  • an image signal corresponding to the minimum gradation value 0 is written in the pixel 10B in the row in which the operation is performed, so that the light-emitting elements 14 are not emitting light.
  • the operation in the period t34 may be performed in the pixel 10B of the next row.
  • the transistor 11 is a driving transistor
  • the transistor 41 is a selection transistor
  • the transistors 42 to 45 are switching transistors.
  • the transistor 11 as a driving transistor is a Lov type transistor.
  • the transistor 41 and the switching transistor which are selection transistors the transistor 42 and the transistor 43 are Loff type transistors.
  • the transistor 44 and the transistor 45 are Lov transistors. In FIG. 16, “Loff” is written for the Loff type transistor, and “Lov” is written for the Lov type transistor.
  • the transistor 44 may be required to have high field effect mobility or current driving capability. Therefore, when the transistor 44 is a Lov transistor, a high-definition panel or a large panel can be manufactured. On the other hand, when the transistors 41 to 43 are Loff transistors, the load capacitance of the wiring is reduced and the accuracy of the threshold variation correcting circuit is improved.
  • FIGS. 10B Another modification of the pixel 10B shown in FIG. 11 is shown in FIGS.
  • the transistor in the pixel 10B may have a dual gate structure having two gate electrodes.
  • the semiconductor film is provided between one of the gate electrodes of the transistor and the other of the gate electrodes of the transistor.
  • FIG. 56 shows a pixel 10B_3 in which the transistor in the pixel 10B has a dual gate structure, and one of the gates of the transistor and the other of the gates of the transistor are electrically connected.
  • the transistor in the pixel 10B has a dual gate structure, one of the transistor gates is connected in the same manner as the gate of the transistor in the pixel 10B, and the other gate of the transistor is connected to the source or drain of the transistor.
  • One pixel or the pixel 10B_4 electrically connected to the other of the source and the drain of the transistor is illustrated.
  • the other of the gates of the transistors may be electrically connected to a terminal opposite to the source or the drain illustrated in FIG. In other words, a structure in which the terminal electrically connected to the other of the gates of the transistors in FIG. 57 is electrically connected to the drain if the source is the source may be used.
  • the transistor in the pixel 10B has a dual gate structure, one of the gates of the transistor is connected in the same manner as the gate of the transistor in the pixel 10B, and the other gate of the transistor is electrically connected to the wiring.
  • a pixel 10B_5 having the above-described configuration is shown.
  • the other gate of the transistor 11 is electrically connected to the wiring 11L
  • the other gate of the transistor 41 is electrically connected to the wiring 41L
  • the other gate of the transistor 42 is electrically connected to the wiring 42L.
  • the other gate of the transistor 43 is electrically connected to the wiring 43L
  • the other gate of the transistor 44 is electrically connected to the wiring 44L
  • the other gate of the transistor 45 is electrically connected to the wiring 45L.
  • the wiring 11L and the wirings 41L to 45L may be electrically connected to any other wiring.
  • the wiring 11L and the wirings 41L to 45L may be partially or entirely electrically connected to each other.
  • the structure of the transistor in the pixel illustrated in FIGS. 11 and 56 to 58 may be replaced for each transistor.
  • the transistor in the pixel 10B_2 illustrated in FIG. 16 can have a dual-gate structure.
  • the connection between the two gates can be the same as, for example, the transistors in FIGS.
  • FIG. 17 shows an example of a circuit diagram of the pixel 10C.
  • a pixel 10 ⁇ / b> C illustrated in FIG. 17 includes a transistor 61, a transistor 62, a transistor 11, a capacitor 12, and a light-emitting element 14.
  • the transistor 11 is a drive transistor
  • the transistor 61 is a selection transistor
  • the transistor 62 is a switching transistor.
  • the wiring 66 and the wiring 67 have a function as a scanning line or a gate line.
  • the wiring SL has a function as a data line.
  • the wiring VL functions as a current supply line.
  • the wiring CL has a function as a cathode line.
  • the wiring ML has a function as a monitor line.
  • One of a source and a drain of the transistor 11 is electrically connected to the light-emitting element 14, and the other of the source and the drain is electrically connected to a wiring VL that functions as a current supply line.
  • the gate of the transistor 61 is electrically connected to the wiring 66 functioning as a scan line, and one of the source and the drain is electrically connected to the wiring SL functioning as a data line.
  • the transistor 11 as a driving transistor is a Lov type transistor.
  • the transistor 61 as a selection transistor and the transistor 62 as a switching transistor are Loff type transistors.
  • “Loff” is written for the Loff type transistor
  • “Lov” is written for the Lov type transistor.
  • the transistor 61 has a function of controlling electrical continuity between the wiring SL and the gate of the transistor 11.
  • one of a source and a drain is electrically connected to the anode of the light-emitting element 14, and the other of the source and the drain is electrically connected to the wiring VL.
  • the transistor 62 has a function of controlling a conduction state between the wiring ML and one of the source and the drain of the transistor 11.
  • One of the pair of electrodes of the capacitor 12 is electrically connected to the gate of the transistor 11, and the other is electrically connected to the anode of the light-emitting element 14.
  • the transistor 61 is turned on or off in accordance with the potential of the wiring 66 electrically connected to the gate of the transistor 61.
  • the transistor 62 is switched in accordance with the potential of the wiring 67 electrically connected to the gate of the transistor 62.
  • the transistors 61 and 62 are Loff type transistors, parasitic capacitance is reduced, so that the capacitive load on the wiring is reduced. Therefore, for example, a high-definition panel can be manufactured and the panel can be driven at high speed.
  • the drain current of the transistor 11 can be supplied to the monitor circuit through the wiring ML.
  • the monitor circuit generates a signal including the value of the drain current as information, using the drain current flowing through the wiring ML. Further, the value of the potential Vdata of the image signal Sig supplied to the pixel 10C can be corrected using the signal.
  • the parasitic capacitance of the transistor is reduced, so that the correction accuracy is improved.
  • the variation in the threshold voltage and the field effect mobility of the transistor 11 can be corrected.
  • the transistor 62 when the transistor 62 is turned off, the structure is the same as that of the pixel shown in the pixel structure example 5, and thus the same driving method can be used.
  • the transistor 62 may be turned on.
  • the potential of the terminal of the transistor 11 connected to the light-emitting element 14 when the potential of the terminal is initialized, the potential of the terminal can be initialized by turning on the transistor 62 and applying the potential of the wiring ML. In this case, it is not necessary to change the potential of the wiring VL at the time of initialization.
  • the driving method described in the pixel configuration example 5 or a driving method using the driving method is used, by using a Loff type transistor as the transistor 61, the parasitic capacitance of the transistor is reduced, so that the correction accuracy is improved. To do.
  • FIGS. 17 Another modification of the pixel 10C shown in FIG. 17 is shown in FIGS.
  • the transistor in the pixel 10C may have a dual gate structure having two gate electrodes.
  • the semiconductor film is provided between one of the gate electrodes of the transistor and the other of the gate electrodes of the transistor.
  • FIG. 59A illustrates a pixel 10C_3 in which the transistor in the pixel 10C has a dual-gate structure, and one of the gates of the transistor and the other of the gates of the transistor are electrically connected.
  • the transistor in the pixel 10C has a dual gate structure, one of the gates of the transistors is connected in the same manner as the gate of the transistor in the pixel 10C, and the other gate of the transistor is connected to the source of the transistor.
  • the pixel 10C_4 is electrically connected to one of the drains or the other of the source and the drain of the transistor.
  • the other of the gates of the transistors may be electrically connected to a terminal opposite to the source or the drain illustrated in FIG.
  • a structure in which the terminal electrically connected to the other of the gates of the transistors in FIG. 59B is electrically connected to the drain if it is a source and to the source if it is a drain may be employed.
  • the transistor in the pixel 10C has a dual gate structure, one of the gates of the transistor is connected in the same manner as the gate of the transistor in the pixel 10C, and the other gate of the transistor is electrically connected to the wiring.
  • a pixel 10C_5 having the above-described configuration is shown. 60, the other gate of the transistor 11 is electrically connected to the wiring 11L, the other gate of the transistor 61 is electrically connected to the wiring 61L, and the other gate of the transistor 62 is electrically connected to the wiring 62L. is doing.
  • the wiring 11L, the wiring 61L, and the wiring 62L may be electrically connected to any other wiring. Further, the wiring 11L, the wiring 61L, and the wiring 62L may be partially or entirely electrically connected to each other.
  • the structure of the transistor in the pixel illustrated in FIGS. 17 and 59 to 60 may be replaced for each transistor.
  • FIG. 18 illustrates a configuration example of the pixel 10D of the display device which is one embodiment of the present invention.
  • the pixel 10 ⁇ / b> D includes a transistor 11, a transistor 71, a capacitor 12, and a light emitting element 14.
  • the transistor 11 is a drive transistor
  • the transistor 71 is a selection transistor
  • One of a source and a drain of the transistor 11 is electrically connected to the light-emitting element 14, and the other of the source and the drain is electrically connected to a wiring VL that functions as a current supply line.
  • the gate of the transistor 71 is electrically connected to the wiring 76 functioning as a scan line, and one of the source and the drain is electrically connected to the wiring SL functioning as a data line.
  • the transistor 11 as a driving transistor is a Lov type transistor.
  • the transistor 71 which is a selection transistor is a Loff type transistor. Note that in FIG. 18A, “Loff” is written for a Loff transistor and “Lov” is written for a Lov transistor.
  • a node between the transistor 11 and the 11 light-emitting element 14 is illustrated as a node A.
  • the gate of the transistor 11 is illustrated as a node B.
  • a gate of the transistor 71 is connected to the wiring 76.
  • One of a source and a drain of the transistor 71 is connected to the wiring SL.
  • the other of the source and the drain of the transistor 71 is connected to the node B.
  • the wiring 76 is a wiring having a function of giving (or transmitting) a signal for controlling on or off of the transistor 71 functioning as a switch.
  • the wiring 76 is on at an H level and off at an L level.
  • the wiring SL is a wiring having a function of giving (or transmitting) an initialization potential in the initialization period and the threshold voltage acquisition period.
  • the wiring SL is a wiring having a function of supplying (or transmitting) a video signal (or video signal voltage, data voltage, or the like) to the pixel 10D in the video signal writing period and the field effect mobility correction period. is there.
  • the video signal is a voltage for causing the light emitting element 14 to emit light with a desired gradation value.
  • the video signal may be represented by VIN .
  • the initialization potential applied to the wiring SL is a potential having a function for initializing the potential of one electrode of the capacitor 12.
  • the potential when the potential of the wiring SL is at the L level can be set as the initialization potential.
  • the gate of the transistor 11 is connected to the node B.
  • One of the source and the drain of the transistor 11 is connected to the node A.
  • the other of the source and the drain of the transistor 11 is connected to the wiring VL.
  • the transistor 71 and the transistor 11 are described as being n-channel type. In the following description, as an example, it represents the threshold voltage of the transistor 11 as a V TH.
  • the wiring VL is, for example, a wiring having a function of providing an initialization potential for initializing the potential of the other electrode of the capacitor 12 in the initialization period.
  • the wiring VL has a function of supplying a potential for allowing a current to flow according to the gate-source voltage (V GS ) of the transistor 11 in the threshold voltage acquisition period, the video signal writing period, the field effect mobility correction period, and the light emission period. Wiring.
  • the initialization potential applied to the wiring VL is a potential for initializing the potential of the other electrode of the capacitor 12.
  • the potential when the potential of the wiring VL is at the L level can be set as the initialization potential.
  • the potential for supplying current to the wiring VL in accordance with V GS of the transistor 11 is such that the voltage held at the electrodes at both ends of the capacitor 12 is the threshold voltage of the transistor 11. This is a potential for correcting the mobility and for causing the light emitting element 14 to emit light.
  • the potential when the potential of the wiring VL is at the H level can be set to a potential for allowing a current to flow according to V GS of the transistor 11.
  • the wiring 76 has a function as a scanning line. It can also be said that the wiring SL has a function as a data line. It can also be said that the wiring VL functions as a current supply line. In addition, the wiring CL has a function as a cathode line.
  • One electrode of the capacitor 12 is connected to the node B.
  • the other electrode of the capacitor 12 is connected to the node A.
  • One electrode of the light emitting element 14 is connected to the node A.
  • the other electrode of the light emitting element 14 is connected to the wiring CL.
  • FIG. 18B shows a timing chart for explaining the operation of the pixel 10D.
  • the timing chart in FIG. 18B is divided into a light emission period t51, an initialization period t52, a threshold voltage acquisition period t53, a video signal writing period, and a field effect mobility correction period t54.
  • the timing chart in FIG. 18B illustrates an example of changes in potentials of the wiring VL, the wiring SL, the node A, the node B, and the wiring 76.
  • the threshold voltage V TH of the transistor 11 the video signal voltage V IN , and the field effect mobility correction voltage ⁇ V of the transistor 11 are illustrated.
  • the wiring 76 is set to an H level, and the potential of the wiring SL is set as an initialization potential.
  • the potential of the wiring SL is transmitted to the node B, and the potential of the node B is decreased. Further, the potential at the node A also decreases.
  • the initialization period t52 an operation for initializing the voltage held in the node A is performed.
  • the potential of the wiring VL is set as an initialization potential.
  • a current flows through the transistor 11 and the potential of the node A further decreases.
  • the potentials at both ends of the capacitive element 12 are initialized.
  • the initialization period t52 is completed.
  • the potential of the wiring VL is set to a potential for allowing current to flow in accordance with V GS of the transistor 11. As the potential of the wiring VL increases, a current flows through the transistor 11 and the potential of the node A increases. That is, the charge accumulated in the capacitive element 12 is discharged.
  • the wiring 76 is at an H level, that is, the transistor 71 is on, the potential of the node B does not change.
  • the potential of the node A increases, the current flowing through the transistor 11 decreases as V GS of the transistor 11 becomes V TH, and the current stops. That is, the potential of the node A is a potential that is lower than the potential of the node B by V TH . That is, V TH of the transistor 11 can be acquired.
  • the wiring 76 is at an H level, that is, the transistor 71 is turned on, and the wiring SL is set to VIN .
  • the potential at node B changes to VIN .
  • the voltage across the capacitor 12 acts so that V IN is added to V TH .
  • the potential of the node A rises by ⁇ V because a current flows through the transistor 11 and charges are accumulated in the parasitic capacitance of the light emitting element 14. That is, the voltage across the capacitor 12 is V IN + V TH ⁇ V.
  • the change ⁇ V in the potential of the node A increases as the current flowing through the transistor 11 increases.
  • the magnitude of the current flowing through the transistor 11 is proportional to the field effect mobility of the transistor 11. Therefore, by changing the potential of the node A, it is possible to suppress the influence of variations in the field effect mobility of the transistor 102 of each pixel.
  • the field effect mobility may not be corrected in the video signal writing period and the field effect mobility correction period t54. In this case, it is not necessary to increase the potential of the node A through the transistor 11. Therefore, since the period during which the potential of the node A is raised can be omitted, unintentional light emission of the light-emitting element 14 can be suppressed.
  • the potential of the wiring VL does not need to be a potential for flowing current in accordance with V GS of the transistor 11.
  • the potential of the wiring VL be a potential that does not increase the potential of the node A, for example, the same potential as or lower than that of the wiring CL.
  • Such a configuration can be realized, for example, by providing a switch between the transistor 11 and the wiring VL and turning off the switch during the video signal writing period. With this structure, unintentional light emission of the light-emitting element can be suppressed when a video signal is written.
  • the wiring 76 is set at the L level, that is, the transistor 71 is turned off.
  • Node B becomes electrically floating. Since a current flows through the transistor 11 following the previous period, the potential of the node A is increased. Since the node B is in an electrically floating state, the potential of the node B increases as the potential of the node A increases while the voltage across the capacitor 12 is kept at V IN + V TH ⁇ V. Therefore, a current corresponding to the magnitudes of V TH and ⁇ V flows through the light emitting element 14. That is, the current flowing through the light emitting element 14 can reduce the influence of variations in V TH and ⁇ V.
  • the current flowing through the light-emitting element 14 can have a magnitude that includes the threshold voltage of the transistor 11 and the field-effect mobility of the transistor 11. By doing so, it is possible to reduce the influence of variation in the electrical characteristics of the transistor and suppress variation in luminance of the light-emitting element for each pixel.
  • the transistor 71 has a parasitic capacitance
  • the charge accumulated in the parasitic capacitance is released or the charge is accumulated in the parasitic capacitance when the transistor 71 is changed from on to off or from off to on.
  • the current flows through one or the other electrode of 12 or the gate of the transistor 11.
  • the voltage applied to the capacitive element 12 or the gate-source voltage of the transistor 11 may deviate from the value shown in the driving method of this configuration example. This deviation affects the threshold correction.
  • the transistor 71 is a Loff type transistor, and since the parasitic capacitance is small, the influence on threshold correction is small.
  • the transistor 71 is a Loff type transistor, the parasitic capacitance is reduced, so that the capacitive load on the wiring is reduced. Therefore, for example, a high-definition panel can be manufactured and the panel can be driven at high speed.
  • FIGS. 10D Another modification of the pixel 10D shown in FIG. 18 is shown in FIGS.
  • the transistor in the pixel 10D may have a dual gate structure having two gate electrodes.
  • the semiconductor film is provided between one of the gate electrodes of the transistor and the other of the gate electrodes of the transistor.
  • FIG. 61A illustrates a pixel 10D_3 in which a transistor in the pixel 10D has a dual gate structure, and one of the gates of the transistor and the other of the gates of the transistor are electrically connected.
  • the transistor in the pixel 10D has a dual gate structure, one of the transistor gates is connected in the same manner as the gate of the transistor in the pixel 10D, and the other gate of the transistor is connected to the source of the transistor.
  • the pixel 10D_4 which is electrically connected to one of the drains or the other of the source and the drain of the transistor is illustrated.
  • the other of the gates of the transistors may be electrically connected to a terminal opposite to the source or the drain illustrated in FIG.
  • a structure in which the terminal electrically connected to the other of the gates of the transistors in FIG. 61B is electrically connected to the drain if it is a source and to the source if it is a drain may be employed.
  • the transistor in the pixel 10D has a dual gate structure, one of the transistor gates is connected in the same manner as the gate of the transistor in the pixel 10D, and the other gate of the transistor is electrically connected to a wiring.
  • the pixel 10D_5 having a configuration connected to each other is shown.
  • the other gate of the transistor 11 is electrically connected to the wiring 11L
  • the other gate of the transistor 71 is electrically connected to the wiring 71L.
  • the wiring 11L and the wiring 71L may be electrically connected to any other wiring. Further, the wiring 11L and the wiring 71L may be electrically connected to each other.
  • FIG. 62A illustrates a pixel 10D_6 in which the transistor 11 in the pixel 10D is a p-channel transistor.
  • FIG. 62B shows a pixel 10D_7 in which the directions of the anode and the cathode of the light-emitting element 14 in the pixel 10D are switched.
  • FIG. 62C illustrates a pixel 10D_8 in which the transistor 11 in the pixel 10D is a p-channel transistor and the direction of the anode and the cathode of the light-emitting element 14 in the pixel 10D is switched.
  • the wiring AL has a function as an anode line or an anode line.
  • the transistor 11 When the light-emitting element 14 emits light, the potential of the wiring AL is higher than the potential of the wiring VL. Become. Further, in the pixel shown in the pixel configuration examples 1 to 5 or the modifications thereof, the transistor 11 may be a p-channel transistor. Further, in the pixels shown in the pixel configuration examples 1 to 5 or the modification examples thereof, the direction of the anode and the cathode of the light emitting element 14 may be switched. Further, in the pixels shown in the pixel configuration examples 1 to 5 or the modifications thereof, the direction of the anode and the cathode of the light-emitting element 14 may be switched, and the transistor 11 may be a p-channel transistor.
  • the configuration of the transistor in the pixel illustrated in FIGS. 18, 61, and 62 may be replaced for each transistor.
  • Embodiment 2 a structure and a manufacturing method of the Loff transistor and the Lov transistor described in Embodiment 1 will be described with reference to FIGS.
  • a Loff transistor and a Lov transistor having a structure in which a gate electrode is located below a semiconductor film will be described as a structure of the transistor.
  • a Loff type transistor and a Lov type transistor having a structure in which gate electrodes are above and below a semiconductor film also referred to as a dual gate structure
  • a Loff transistor and a Lov transistor having a structure in which the gate electrode is above the semiconductor film also referred to as a top gate structure
  • an oxide semiconductor film is used as a semiconductor film of a transistor and two oxide semiconductor films are stacked is described below; however, the type and stacked structure of the semiconductor film are not limited thereto.
  • amorphous silicon amorphous silicon, hydrogenated amorphous silicon, microcrystalline silicon, polycrystalline silicon, single crystal silicon, or the like may be used.
  • a compound semiconductor such as gallium arsenide or gallium nitride may be used.
  • the semiconductor film may have one layer or three or more layers.
  • FIG. 19A is a top view of the transistor 100 which is a Loff-type transistor
  • FIG. 19B corresponds to a cross-sectional view of a cross section taken along the dashed-dotted line X1-X2 in FIG.
  • FIG. 19C corresponds to a cross-sectional view of a cross section taken along dashed-dotted line Y1-Y2 in FIG.
  • some components such as an insulating film functioning as a gate insulating film
  • the direction of the alternate long and short dash line X1-X2 may be referred to as a channel length direction
  • the direction of the alternate long and short dash line Y1-Y2 may be referred to as a channel width direction.
  • some components may be omitted in the following drawings as in FIG. 19A.
  • the transistor 100 includes a conductive film 104 functioning as a first gate electrode over the substrate 102, an insulating film 106 over the substrate 102 and the conductive film 104, an insulating film 107 over the insulating film 106, and an oxide over the insulating film 107.
  • the insulating film 106 and the insulating film 107 function as a first gate insulating film. Therefore, the insulating film 106 functioning as the first gate insulating film and the insulating film 107 are provided between the oxide semiconductor film 108 and the conductive film 104 functioning as the first gate electrode.
  • insulating films 114 and 116 and an insulating film 118 are provided over the transistor 100, more specifically, over the conductive films 112 a and 112 b and the oxide semiconductor film 108.
  • the insulating films 114, 116, and 118 function as protective insulating films for the transistor 100.
  • the oxide semiconductor film 108 has a region overlapping with the conductive film 104, and does not overlap with the conductive film 112a in the region and does not overlap with the conductive film 112b in the region. Note that a region where the oxide semiconductor film 108 does not overlap with the conductive film 104, the conductive film 112a, and the conductive film 112b is referred to as a Loff region.
  • the Loff area corresponds to the area 122.
  • the transistor 100 which is a Loff transistor can be used as a switching transistor or a selection transistor in a circuit in a pixel that can be used for a display device as described in Embodiment 1. Since the transistor 100 has a small parasitic capacitance, a load during driving is reduced. As a result, a high-definition panel can be manufactured and the panel can be driven at high speed. In addition, when a circuit for correcting the threshold variation of the driving transistor is provided in the pixel, the correction accuracy is improved by using the transistor 100 having a small parasitic capacitance as a switching transistor or a selection transistor.
  • FIG. 20A is a top view of a transistor 200 that is a Lov transistor
  • FIG. 20B corresponds to a cross-sectional view of a cross section taken along the dashed-dotted line X1-X2 in FIG.
  • FIG. 20C corresponds to a cross-sectional view of a cross section taken along dashed-dotted line Y1-Y2 in FIG.
  • the direction of the alternate long and short dash line X1-X2 may be referred to as a channel length direction
  • the direction of the alternate long and short dash line Y1-Y2 may be referred to as a channel width direction.
  • the transistor 200 includes a conductive film 104 functioning as a first gate electrode over the substrate 102, an insulating film 106 over the substrate 102 and the conductive film 104, an insulating film 107 over the insulating film 106, and an oxide over the insulating film 107.
  • the insulating film 106 and the insulating film 107 function as a first gate insulating film. Therefore, the insulating film 106 functioning as the first gate insulating film and the insulating film 107 are provided between the oxide semiconductor film 108 and the conductive film 104 functioning as the first gate electrode.
  • insulating films 114 and 116 and an insulating film 118 are provided over the transistor 200, more specifically, over the conductive films 112 a and 112 b and the oxide semiconductor film 108.
  • the insulating films 114, 116, and 118 function as protective insulating films for the transistor 200.
  • the insulating film 106 and the insulating film 107 function as a first gate insulating film.
  • the oxide semiconductor film 108 has a region overlapping with the conductive film 104, overlaps with the conductive film 112a in part of the region, and overlaps with the conductive film 112b in another part of the region.
  • the transistor 200 which is a Lov transistor can be used as a driving transistor in a pixel circuit as described in Embodiment 1.
  • a gate driver that generates a gate signal
  • a display with a narrow frame width also referred to as a narrow frame
  • An apparatus can be provided.
  • the oxide semiconductor film 108 includes a first oxide semiconductor film 108a on the conductive film 104 side that functions as a first gate electrode, a second oxide semiconductor film 108b over the first oxide semiconductor film 108a, Have The insulating film 106 and the insulating film 107 have a function as a first gate insulating film of the transistors 100 and 200.
  • an In-M (M represents Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) oxide or an In-M-Zn oxide is used. it can.
  • an In-M-Zn oxide is preferably used for the oxide semiconductor film 108.
  • the first oxide semiconductor film 108a includes a first region in which the atomic ratio of In is larger than the atomic ratio of M.
  • the second oxide semiconductor film 108b includes a second region in which the atomic ratio of In is smaller than that of the first oxide semiconductor film 108a. The second region has a thinner part than the first region.
  • the field-effect mobility of the transistors 100 and 200 (simply mobility or ⁇ FE may be referred to. Can be high).
  • the Loff type transistor Since the Loff type transistor has a series resistance in the Loff type transistor, the current (on current) when the transistor is turned on tends to be lower than that of the Lov type transistor. If the on-state current is small, a transistor for a display device may not be used. However, the resistance of the Loff region can be reduced by increasing the In atomic ratio of the first oxide semiconductor film 108a to be greater than the M atomic ratio. Accordingly, a reduction in on-state current can be suppressed, so that a Loff transistor can be applied to various semiconductor devices and display devices.
  • the electrical characteristics of the transistors 100 and 200 are likely to fluctuate during light irradiation.
  • the second oxide semiconductor film 108b is formed over the first oxide semiconductor film 108a.
  • the thickness of the channel region of the second oxide semiconductor film 108b is preferably smaller than the thickness of the first oxide semiconductor film 108a.
  • the second oxide semiconductor film 108b since the second oxide semiconductor film 108b includes the second region in which the atomic ratio of In is smaller than that of the first oxide semiconductor film 108a, the band gap ( Eg, also referred to as energy gap). Therefore, the oxide semiconductor film 108 having a stacked structure of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b has high resistance due to the optical negative bias stress test.
  • the band gap Eg, also referred to as energy gap
  • the oxide semiconductor film having the above structure With the oxide semiconductor film having the above structure, the amount of light absorbed by the oxide semiconductor film 108 during light irradiation can be reduced. Therefore, variation in electrical characteristics of the transistors 100 and 200 during light irradiation can be suppressed. In the transistor of one embodiment of the present invention, excess oxygen is contained in the insulating film 114 or the insulating film 116; thus, variation in electric characteristics of the transistors 100 and 200 due to light irradiation can be further suppressed. it can.
  • the substrate 102 there is no particular limitation on the material of the substrate 102, but it is necessary that the substrate 102 have at least heat resistance to withstand heat treatment performed later.
  • a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 102.
  • a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, etc., and a semiconductor element provided on these substrates May be used as the substrate 102.
  • the sixth generation (1500 mm ⁇ 1850 mm), the seventh generation (1870 mm ⁇ 2200 mm), the eighth generation (2200 mm ⁇ 2400 mm), the ninth generation (2400 mm ⁇ 2800 mm), the tenth generation.
  • a large area substrate such as a generation (2950 mm ⁇ 3400 mm)
  • a large display device can be manufactured.
  • a flexible substrate may be used as the substrate 102, and the transistors 100 and 200 may be formed directly over the flexible substrate.
  • a separation layer may be provided between the substrate 102 and the transistors 100 and 200. The separation layer can be used to separate the substrate 102 from the substrate 102 and transfer it to another substrate after part or all of the transistor is completed thereover. At that time, the transistors 100 and 200 can be transferred to a substrate having poor heat resistance or a flexible substrate.
  • the conductive film 104 functioning as the first gate electrode, the conductive film 112a functioning as the source electrode, and the conductive film 112b functioning as the drain electrode chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), cobalt
  • a metal element selected from (Co) or an alloy containing the above-described metal element as a component can be formed using an alloy or the like in which the above-described metal elements are combined.
  • the conductive films 104, 112a, and 112b may have a single-layer structure or a stacked structure including two or more layers.
  • the conductive films 104, 112a, and 112b include indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, and indium tin oxide containing titanium oxide.
  • a light-transmitting conductive material such as indium zinc oxide or indium tin oxide to which silicon oxide is added can be used.
  • a Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) may be applied to the conductive films 104, 112a, and 112b.
  • X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti
  • a Cu-X alloy film it can be processed by a wet etching process, and thus manufacturing costs can be suppressed.
  • a silicon oxide film, an oxide film, or the like is formed by a plasma enhanced chemical vapor deposition (PECVD) method, a sputtering method, or the like.
  • PECVD plasma enhanced chemical vapor deposition
  • Each insulating layer including one or more neodymium films can be used. Note that instead of the stacked structure of the insulating films 106 and 107, a single-layer insulating film selected from the above materials or an insulating film having three or more layers may be used.
  • the insulating film 106 functions as a blocking film that suppresses permeation of oxygen.
  • the insulating film 106 can suppress permeation of oxygen.
  • the insulating film 107 in contact with the oxide semiconductor film 108 functioning as a channel region of the transistors 100 and 200 is preferably an oxide insulating film, and includes a region containing oxygen in excess of the stoichiometric composition (oxygen) It is more preferable to have an excess region.
  • the insulating film 107 is an insulating film capable of releasing oxygen.
  • the insulating film 107 may be formed in an oxygen atmosphere.
  • oxygen may be introduced into the insulating film 107 after film formation to form an oxygen excess region.
  • an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used.
  • hafnium oxide has a higher dielectric constant than silicon oxide or silicon oxynitride. Accordingly, since the thickness of the insulating film 107 can be increased as compared with the case where silicon oxide is used, the leakage current due to the tunnel current can be reduced. That is, a transistor with a small off-state current can be realized. Further, hafnium oxide having a crystal structure has a higher dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with low off-state current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include a monoclinic system and a cubic system. Note that one embodiment of the present invention is not limited thereto.
  • a silicon nitride film is formed as the insulating film 106 and a silicon oxide film is formed as the insulating film 107. Since the silicon nitride film has a relative dielectric constant higher than that of the silicon oxide film and has a large film thickness necessary for obtaining the same capacitance as the silicon oxide film, the first gate insulating film of the transistors 100 and 200 is used. As described above, the insulating film can be physically thickened by including the silicon nitride film. Accordingly, a decrease in the withstand voltage of the transistors 100 and 200 can be suppressed, and further, the withstand voltage can be improved, thereby suppressing electrostatic breakdown of the transistors 100 and 200.
  • the oxide semiconductor film 108 any of the above materials can be used.
  • the oxide semiconductor film 108 is an In-M-Zn oxide
  • the atomic ratio of metal elements of a sputtering target used for forming the In-M-Zn oxide satisfies In ⁇ M and Zn ⁇ M. It is preferable.
  • the oxide semiconductor film 108 is an In-M-Zn oxide
  • a target including a polycrystalline In-M-Zn oxide is preferably used as the sputtering target.
  • the oxide semiconductor film 108 having crystallinity can be easily formed.
  • the atomic ratio of the oxide semiconductor film 108 to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal element contained in the sputtering target as an error.
  • the oxide semiconductor film 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. In this manner, off-state current of the transistors 100 and 200 can be reduced by using an oxide semiconductor with a wide energy gap.
  • an oxide semiconductor film with an energy gap of 2 eV or more, preferably 2 eV or more and 3.0 eV or less is used for the first oxide semiconductor film 108a, and an energy gap of 2 e is used for the second oxide semiconductor film 108b. It is preferable to use an oxide semiconductor film with a thickness of 0.5 eV to 3.5 eV.
  • the energy gap of the second oxide semiconductor film 108b is preferably larger than that of the first oxide semiconductor film 108a.
  • the oxide semiconductor film 108b preferably has a structure in which the energy level at the lower end of the conduction band is closer to the vacuum level than the oxide semiconductor film 108a. With such a structure, the oxide semiconductor film 108a serves as a main current path. That is, the oxide semiconductor film 108a may function as a channel region, and the oxide semiconductor film 108b may function as an oxide insulating film.
  • each of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b is 3 nm to 200 nm, preferably 3 nm to 100 nm, more preferably 3 nm to 50 nm. Note that it is preferable that the film thickness relationship described above is satisfied.
  • the second oxide semiconductor film 108b an oxide semiconductor film with low carrier density is used.
  • the second oxide semiconductor film 108b has a carrier density of 1 ⁇ 10 17 pieces / cm 3 or less, preferably 1 ⁇ 10 15 pieces / cm 3 or less, more preferably 1 ⁇ 10 13 pieces / cm 3 or less. More preferably, it is 1 ⁇ 10 11 pieces / cm 3 or less.
  • the present invention is not limited to these, and those having an appropriate atomic ratio may be used depending on required semiconductor characteristics and electrical characteristics (field effect mobility, threshold voltage, etc.).
  • the carrier density, impurity concentration, defect density, and atomic ratio of metal element to oxygen of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b It is preferable to make the interatomic distance, density, etc. appropriate.
  • the first oxide semiconductor film 108a and the second oxide semiconductor film 108b an oxide semiconductor film with a low impurity concentration and a low density of defect states is used, so that even better electrical characteristics can be obtained.
  • a transistor having the same can be manufactured, which is preferable.
  • low impurity concentration and low defect level density are referred to as high purity intrinsic or substantially high purity intrinsic.
  • a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film rarely has electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative.
  • a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and thus may have a low density of trap states. Further, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has an extremely small off-state current, a channel width of 1 ⁇ 10 6 ⁇ m, and a channel length L of 10 ⁇ m. When the voltage between the drain electrodes (drain voltage) is in the range of 1V to 10V, it is possible to obtain a characteristic that the off-current is less than the measurement limit of the semiconductor parameter analyzer, that is, 1 ⁇ 10 ⁇ 13 A or less.
  • a transistor in which a channel region is formed in the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film can have a small variation in electrical characteristics and can be a highly reliable transistor.
  • the charge trapped in the trap level of the oxide semiconductor film takes a long time to disappear, and may behave as if it were a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor film with a high trap state density may have unstable electrical characteristics.
  • impurities include hydrogen, nitrogen, alkali metals, and alkaline earth metals.
  • Hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to metal atoms to become water, and forms oxygen vacancies in a lattice from which oxygen is released (or a portion from which oxygen is released). When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. In addition, a part of hydrogen may be combined with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor including an oxide semiconductor film containing hydrogen is likely to be normally on. Therefore, it is preferable that hydrogen be reduced in the oxide semiconductor film 108 as much as possible.
  • the hydrogen concentration obtained by SIMS analysis is 2 ⁇ 10 20 atoms / cm 3 or less, preferably 5 ⁇ 10 19 atoms / cm 3 or less, more preferably 1 ⁇ 10 19. atoms / cm 3 or less, 5 ⁇ 10 18 atoms / cm 3 or less, preferably 1 ⁇ 10 18 atoms / cm 3 or less, more preferably 5 ⁇ 10 17 atoms / cm 3 or less, more preferably 1 ⁇ 10 16 atoms / cm 3 or less. cm 3 or less.
  • the first oxide semiconductor film 108a preferably includes a portion with a lower hydrogen concentration than the second oxide semiconductor film 108b. Since the first oxide semiconductor film 108a has a portion with a lower hydrogen concentration than the second oxide semiconductor film 108b, a highly reliable transistor can be obtained.
  • the concentration of silicon or carbon in the first oxide semiconductor film 108a and the concentration of silicon or carbon in the vicinity of the interface with the first oxide semiconductor film 108a are 2 ⁇ 10. 18 atoms / cm 3 or less, preferably 2 ⁇ 10 17 atoms / cm 3 or less.
  • the concentration of alkali metal or alkaline earth metal obtained by SIMS analysis is 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less. To do. When an alkali metal and an alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, and the off-state current of the transistor may be increased. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the first oxide semiconductor film 108a.
  • the nitrogen in the oxide semiconductor film is preferably reduced as much as possible.
  • the nitrogen concentration obtained by SIMS analysis is preferably 5 ⁇ 10 18 atoms / cm 3 or less.
  • the first oxide semiconductor film 108a and the second oxide semiconductor film 108b may each have a non-single-crystal structure.
  • the non-single crystal structure includes, for example, a CAAC-OS (C Axis Crystalline Oxide Semiconductor), a polycrystalline structure, a microcrystalline structure, or an amorphous structure, which will be described later.
  • CAAC-OS C Axis Crystalline Oxide Semiconductor
  • the amorphous structure has the highest density of defect states
  • the CAAC-OS has the lowest density of defect states.
  • the insulating films 114 and 116 have a function of supplying oxygen to the oxide semiconductor film 108.
  • the insulating film 118 functions as a protective insulating film for the transistors 100 and 200.
  • the insulating films 114 and 116 include oxygen.
  • the insulating film 114 is an insulating film that can transmit oxygen. Note that the insulating film 114 also functions as a damage reducing film for the oxide semiconductor film 108 when an insulating film 116 to be formed later is formed.
  • silicon oxide, silicon oxynitride, or the like with a thickness of 5 nm to 150 nm, preferably 5 nm to 50 nm can be used.
  • the insulating film 114 preferably has a small amount of defects.
  • the insulating film 114 can be formed using an oxide insulating film having a low level density due to nitrogen oxides.
  • the level density due to the nitrogen oxide can be formed between the energy (Ev_os) at the upper end of the valence band of the oxide semiconductor film and the energy (Ec_os) at the lower end of the conduction band of the oxide semiconductor film.
  • the oxide insulating film a silicon oxynitride film with a low emission amount of nitrogen oxide, an aluminum oxynitride film with a low emission amount of nitrogen oxide, or the like can be used.
  • a silicon oxynitride film with a small amount of released nitrogen oxide is a film in which the amount of released ammonia is larger than the amount of released nitrogen oxide in the temperature programmed desorption gas analysis method.
  • the amount of released ammonia is Is 1 ⁇ 10 18 pieces / cm 3 or more and 5 ⁇ 10 19 pieces / cm 3 or less.
  • the amount of ammonia released is the amount released by heat treatment at a film surface temperature of 50 ° C. to 650 ° C., preferably 50 ° C. to 550 ° C.
  • Nitrogen oxide (NO x , x is larger than 0 and 2 or less, preferably 1 or more and 2 or less), typically NO 2 or NO forms a level in the insulating film 114 or the like.
  • the level is located in the energy gap of the oxide semiconductor film 108. Therefore, when nitrogen oxide diffuses to the interface between the insulating film 114 and the oxide semiconductor film 108, the level may trap electrons on the insulating film 114 side. As a result, trapped electrons remain in the vicinity of the interface between the insulating film 114 and the oxide semiconductor film 108, so that the threshold voltage of the transistor is shifted in the positive direction.
  • Nitrogen oxide reacts with ammonia and oxygen in heat treatment. Since nitrogen oxide contained in the insulating film 114 reacts with ammonia contained in the insulating film 116 in the heat treatment, nitrogen oxide contained in the insulating film 114 is reduced. Therefore, electrons are hardly trapped at the interface between the insulating film 114 and the oxide semiconductor film 108.
  • the oxide insulating film as the insulating film 114, a shift in threshold voltage of the transistor can be reduced, and variation in electric characteristics of the transistor can be reduced.
  • the insulating film 114 has a g value of 2.037 or more in a spectrum obtained by measurement with an ESR of 100 K or less by heat treatment in a manufacturing process of the transistor, typically 300 ° C. or more and less than 350 ° C.
  • a first signal having a g value of 2.001 or more and 2.003 or less and a third signal having a g value of 1.964 or more and 1.966 or less are observed.
  • the split width of the first signal and the second signal and the split width of the second signal and the third signal are about 5 mT in the X-band ESR measurement.
  • a first signal having a g value of 2.037 or more and 2.039 or less a second signal having a g value of 2.001 or more and 2.003 or less, and a first signal having a g value of 1.964 or more and 1.966 or less.
  • the total density of the spins of the three signals is less than 1 ⁇ 10 18 spins / cm 3 , typically 1 ⁇ 10 17 spins / cm 3 or more and less than 1 ⁇ 10 18 spins / cm 3 .
  • the third signal equal to or less than .966 corresponds to a signal caused by nitrogen oxides (NO x , where x is greater than 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2).
  • nitrogen oxides include nitrogen monoxide and nitrogen dioxide. That is, a first signal having a g value of 2.037 to 2.039, a second signal having a g value of 2.001 to 2.003, and a first signal having a g value of 1.964 to 1.966. It can be said that the smaller the total density of the signal spins of 3, the smaller the content of nitrogen oxide contained in the oxide insulating film.
  • An oxide insulating film having a low level density caused by nitrogen oxides has a nitrogen concentration measured by SIMS of 6 ⁇ 10 20 atoms / cm 3 or less.
  • a substrate temperature is 220 ° C. or higher and 350 ° C. or lower, and a PECVD method using silane and dinitrogen monoxide is used to form an oxide insulating film having a low level density due to nitrogen oxides.
  • a film having high hardness can be formed.
  • the insulating film 116 is formed using an oxide insulating film containing more oxygen than that in the stoichiometric composition. Part of oxygen is released by heating from the oxide insulating film containing oxygen in excess of that in the stoichiometric composition.
  • An oxide insulating film containing oxygen in excess of the stoichiometric composition has an oxygen desorption amount of 1.0 ⁇ 10 18 in terms of oxygen atoms in TDS (Thermal Desorption Spectroscopy) analysis.
  • the surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C. to 700 ° C., or 100 ° C. to 500 ° C.
  • silicon oxide, silicon oxynitride, or the like with a thickness of 30 nm to 500 nm, preferably 50 nm to 400 nm can be used.
  • the insulating film 116 preferably has a small amount of defects.
  • the insulating films 114 and 116 can be formed using the same kind of insulating film, the interface between the insulating film 114 and the insulating film 116 may not be clearly confirmed. Therefore, in this embodiment mode, the interface between the insulating film 114 and the insulating film 116 is indicated by a broken line. Note that although a two-layer structure of the insulating film 114 and the insulating film 116 has been described in this embodiment mode, the present invention is not limited thereto, and for example, a single-layer structure of the insulating film 114 may be employed.
  • the insulating film 118 includes nitrogen.
  • the insulating film 118 includes nitrogen and silicon.
  • the insulating film 118 has a function of blocking oxygen, hydrogen, water, alkali metal, alkaline earth metal, or the like. By providing the insulating film 118, diffusion of oxygen from the oxide semiconductor film 108 to the outside, diffusion of oxygen contained in the insulating films 114 and 116, hydrogen from the outside to the oxide semiconductor film 108, Ingress of water and the like can be prevented.
  • a nitride insulating film can be used as the insulating film 118. Examples of the nitride insulating film include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide.
  • an oxide insulating film having a blocking effect of oxygen, hydrogen, water, or the like may be provided instead of the nitride insulating film having a blocking effect of oxygen, hydrogen, water, alkali metal, alkaline earth metal, or the like.
  • the oxide insulating film having a blocking effect of oxygen, hydrogen, water, and the like include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride.
  • various films such as the conductive film, the insulating film, and the oxide semiconductor film described above can be formed by a sputtering method or a PECVD method, but other methods such as a thermal CVD (Chemical Vapor Deposition) method can be used. May be formed.
  • a thermal CVD method a MOCVD (Metal Organic Chemical Vapor Deposition) method or an ALD (Atomic Layer Deposition) method may be used.
  • the thermal CVD method has an advantage that no defect is generated due to plasma damage because it is a film forming method that does not use plasma.
  • film formation may be performed by sending a source gas and an oxidant into the chamber at the same time, making the inside of the chamber under atmospheric pressure or reduced pressure, reacting in the vicinity of the substrate or on the substrate and depositing on the substrate. .
  • film formation may be performed by setting the inside of the chamber to atmospheric pressure or reduced pressure, sequentially introducing source gases for reaction into the chamber, and repeating the order of introducing the gases.
  • each switching valve also referred to as a high-speed valve
  • An active gas such as argon or nitrogen
  • a second source gas is introduced.
  • the inert gas becomes a carrier gas, and the inert gas may be introduced at the same time when the second raw material gas is introduced.
  • the second raw material gas may be introduced after the first raw material gas is exhausted by evacuation.
  • the first source gas is adsorbed on the surface of the substrate to form a first layer, reacts with a second source gas introduced later, and the second layer is stacked on the first layer.
  • a thin film is formed.
  • the thermal CVD method such as the MOCVD method or the ALD method can form various films such as the conductive film, the insulating film, the oxide semiconductor film, and the metal oxide film of the above-described embodiment, for example, an In—Ga—ZnO film.
  • Is used trimethylindium, trimethylgallium, and dimethylzinc are used.
  • the chemical formula of trimethylindium is In (CH 3 ) 3 .
  • the chemical formula of trimethylgallium is Ga (CH 3 ) 3 .
  • the chemical formula of dimethylzinc is Zn (CH 3 ) 2 .
  • Triethylgallium (chemical formula Ga (C 2 H 5 ) 3 ) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn (C 2 H 5 ) is used instead of dimethylzinc. 2 ) can also be used.
  • hafnium oxide film when a hafnium oxide film is formed by a film formation apparatus using ALD, a liquid containing a solvent and a hafnium precursor compound (hafnium amide such as hafnium alkoxide or tetrakisdimethylamide hafnium (TDMAH)) is vaporized.
  • hafnium amide such as hafnium alkoxide or tetrakisdimethylamide hafnium (TDMAH)
  • gases that is, source gas and ozone (O 3 ) as an oxidizing agent are used.
  • source gas and ozone (O 3 ) as an oxidizing agent are used.
  • the chemical formula of tetrakisdimethylamide hafnium is Hf [N (CH 3 ) 2 ] 4 .
  • Other material liquids include tetrakis (ethylmethylamide) hafnium.
  • a source gas obtained by vaporizing a liquid such as trimethylaluminum (TMA)
  • TMA trimethylaluminum
  • H 2 a solvent and an aluminum precursor compound
  • gases of O Two kinds of gases of O are used.
  • trimethylaluminum is Al (CH 3 ) 3 .
  • Other material liquids include tris (dimethylamido) aluminum, triisobutylaluminum, aluminum tris (2,2,6,6-tetramethyl-3,5-heptanedionate) and the like.
  • hexachlorodisilane is adsorbed on the film formation surface, chlorine contained in the adsorbate is removed, and an oxidizing gas (O 2 , monoxide) Dinitrogen) radicals are supplied to react with the adsorbate.
  • oxidizing gas O 2 , monoxide
  • tungsten film is formed by a film forming apparatus using ALD
  • an initial tungsten film is formed by repeatedly introducing WF 6 gas and B 2 H 6 gas successively, and then WF 6 gas and H 2.
  • a tungsten film is formed using a gas.
  • SiH 4 gas may be used instead of B 2 H 6 gas.
  • an oxide semiconductor film such as an In—Ga—ZnO film is formed by a film formation apparatus using ALD
  • In (CH 3 ) 3 gas and O 3 gas are sequentially introduced and In—O is sequentially introduced.
  • Ga (CH 3 ) 3 gas and O 3 gas are sequentially introduced repeatedly to form a GaO layer, and then Zn (CH 3 ) 2 gas and O 3 gas are successively introduced repeatedly to form ZnO.
  • a mixed compound layer such as an In—Ga—O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed by mixing these gases.
  • O 3 may be used of H 2 O gas obtained by bubbling with an inert gas such as Ar in place of the gas, but better to use an O 3 gas containing no H are preferred.
  • In (C 2 H 5 ) 3 gas may be used instead of In (CH 3 ) 3 gas.
  • Ga (C 2 H 5 ) 3 gas may be used instead of Ga (CH 3 ) 3 gas.
  • Zn (C 2 H 5 ) 2 gas may be used instead of Zn (CH 3 ) 2 gas.
  • the Loff transistor having this structure may have a structure in which the conductive film 112a is provided on the inner side and the conductive film 112b is provided on the outer side, as in the transistor 150 illustrated in the top view in FIG.
  • FIG. 21A-2 corresponds to a cross-sectional view of a cross section taken along dashed-dotted line X1-X2-X3 in FIG.
  • the Lov transistor may have a structure in which the conductive film 112a is provided on the inner side and the conductive film 112b is provided on the outer side, as in the transistor 153 illustrated in the top view in FIG. Note that FIG.
  • FIGS. 21A-1 and 21A-2 and FIGS. 22A-1 and 22A-2 corresponds to a cross-sectional view of a cross section taken along dashed-dotted line X1-X2-X3 in FIG.
  • a structure in which the conductive film 112a and the conductive film 112b are interchanged in FIGS. 21A-1 and 21A-2 and FIGS. 22A-1 and 22A-2 may be employed.
  • the transistor 100 illustrated in FIG. 19 has a structure in which the oxide semiconductor film 108b is reduced.
  • the transistor 100 in FIG. Good like the transistor 152 illustrated in FIG. 21C, a structure having a channel protective layer 125 may be employed.
  • the Lov transistor may have a structure in which the oxide semiconductor film 108b is not reduced or very small.
  • a Lov transistor may have a channel protective layer 125 like a transistor 155 illustrated in FIG.
  • FIG. 23A is a top view of a transistor 170 which is a transistor of one embodiment of the present invention
  • FIG. 23B is a cross-sectional view of a cross section taken along dashed-dotted line X1-X2 in FIG.
  • FIG. 23C corresponds to a cross-sectional view of a cross section taken along the dashed-dotted line Y1-Y2 in FIG.
  • the transistor 170 includes a conductive film 104 functioning as a first gate electrode over the substrate 102, an insulating film 106 over the substrate 102 and the conductive film 104, an insulating film 107 over the insulating film 106, and an oxidation over the insulating film 107.
  • the insulating film 106 and the insulating film 107 function as a first gate insulating film. Therefore, the insulating film 106 functioning as the first gate insulating film and the insulating film 107 are provided between the oxide semiconductor film 108 and the conductive film 104 functioning as the first gate electrode.
  • the insulating films 114, 116, and 118 function as a second gate insulating film of the transistor 170.
  • the conductive film 120a is electrically connected to the conductive film 112b through the opening 142c provided in the insulating films 114, 116, and 118.
  • the conductive film 120a functions as a pixel electrode used for a display device, for example.
  • the conductive film 120b functions as a second gate electrode (also referred to as a back gate electrode).
  • the insulating films 114, 116, and 118 functioning as the second gate insulating film are provided between the oxide semiconductor film 108 and the conductive film 120b functioning as the second gate electrode.
  • the oxide semiconductor film 108 is provided between the conductive film 104 and the conductive film 120b.
  • the oxide semiconductor film 108 has a region overlapping with the conductive film 104, and does not overlap with the conductive film 112a in the above region and does not overlap with the conductive film 112b in the above region.
  • the oxide semiconductor film 108 includes a second region overlapping with the conductive film 120b, does not overlap with the conductive film 112a in the second region, and does not overlap with the conductive film 112b in the second region. Note that the Loff region corresponds to the region 122.
  • the conductive film 104 and the conductive film 112b are drawn with the same width; however, the width, the shape, and the like may be the same or different between the conductive film 112b and the conductive film 104. .
  • the transistor 171 includes a conductive film 104 functioning as a first gate electrode over the substrate 102, an insulating film 106 over the substrate 102 and the conductive film 104, an insulating film 107 over the insulating film 106, and an oxidation over the insulating film 107.
  • the insulating film 106 and the insulating film 107 function as a first gate insulating film. Therefore, the insulating film 106 functioning as the first gate insulating film and the insulating film 107 are provided between the oxide semiconductor film 108 and the conductive film 104 functioning as the first gate electrode.
  • the insulating films 114, 116, and 118 function as a second gate insulating film of the transistor 171.
  • the conductive film 120a is electrically connected to the conductive film 112b through the opening 142c provided in the insulating films 114, 116, and 118.
  • the conductive film 120a functions as a pixel electrode used for a display device, for example.
  • the conductive film 120b functions as a second gate electrode (also referred to as a back gate electrode).
  • the insulating films 114, 116, and 118 functioning as the second gate insulating film are provided between the oxide semiconductor film 108 and the conductive film 120b functioning as the second gate electrode.
  • the oxide semiconductor film 108 is provided between the conductive film 104 and the conductive film 120b.
  • the oxide semiconductor film 108 has a region overlapping with the conductive film 104, and does not overlap with the conductive film 112a in the region and does not overlap with the conductive film 112b in the region.
  • the oxide semiconductor film 108 includes a second region overlapping with the conductive film 120b, overlaps with the conductive film 112a in part of the second region, and conductive in another part of the second region. It overlaps with the film 112b.
  • the gate electrode having a larger capacitance per unit area is used as the first gate.
  • the gate electrode on the opposite side across the semiconductor film is the second gate electrode. Note that the gate electrode and the semiconductor film may function as an electrode of the capacitor, and the gate insulating film may function as an insulator of the capacitor.
  • the insulating film 106 is a silicon nitride film having a thickness of 400 nm
  • the insulating film 107 is a silicon oxide film having a thickness of 50 nm
  • the insulating films 114 and 116 are a silicon oxide film and an insulating film having a thickness of 400 nm.
  • 118 is a 50 nm silicon nitride film.
  • the relative dielectric constant of the silicon oxide film is 3.9, and the relative dielectric constant of the silicon nitride film is 7.
  • the capacitance per unit area of the capacitor element in which the conductive film 104 and the oxide semiconductor film 108 are electrodes and the insulating film 106 and the insulating film 107 are insulators is the conductive film 112b and the oxide semiconductor film 108. Is larger than a capacitor having an insulating film 106 and an insulating film 107 as insulators. Therefore, it can be said that the conductive film 104 is the first gate electrode. In addition, it can be said that the insulating film 106 and the insulating film 107 are first gate insulating films.
  • the oxide semiconductor film 108 has a region overlapping with the conductive film 104, and does not overlap with the conductive film 112a in the region and does not overlap with the conductive film 112b in the region.
  • Reference numeral 171 denotes a Loff type transistor.
  • the transistor 172 includes the conductive film 104 functioning as the first gate electrode over the substrate 102, the insulating film 106 over the substrate 102 and the conductive film 104, the insulating film 107 over the insulating film 106, and the oxidation over the insulating film 107.
  • the insulating film 106 and the insulating film 107 function as a first gate insulating film. Therefore, the insulating film 106 functioning as the first gate insulating film and the insulating film 107 are provided between the oxide semiconductor film 108 and the conductive film 104 functioning as the first gate electrode.
  • the insulating films 114, 116, and 118 function as the second gate insulating film of the transistor 172.
  • the conductive film 120a is electrically connected to the conductive film 112b through the opening 142c provided in the insulating films 114, 116, and 118.
  • the conductive film 120a functions as a pixel electrode used for a display device, for example.
  • the conductive film 120b functions as a second gate electrode (also referred to as a back gate electrode).
  • the insulating films 114, 116, and 118 functioning as the second gate insulating film are provided between the oxide semiconductor film 108 and the conductive film 120b functioning as the second gate electrode.
  • the oxide semiconductor film 108 is provided between the conductive film 104 and the conductive film 120b.
  • the oxide semiconductor film 108 has a region overlapping with the conductive film 104, overlaps with the conductive film 112a in part of the region, and overlaps with the conductive film 112b in another part of the region.
  • the oxide semiconductor film 108 includes a second region overlapping with the conductive film 120b, overlaps with the conductive film 112a in part of the second region, and conductive in another part of the second region. It overlaps with the film 112b.
  • the conductive film 120b is formed in the openings 142a and 142b provided in the insulating films 106, 107, 114, 116, and 118. 1 is connected to the conductive film 104 functioning as a gate electrode.
  • the same potential is applied to the conductive film 120b and the conductive film 104.
  • the present invention is not limited to this.
  • a structure in which only one of the opening 142a and the opening 142b is formed and the conductive film 120b and the conductive film 104 are connected, or the conductive film 120b without the openings 142a and 142b is provided.
  • the conductive film 104 may not be connected. Note that in the case where the conductive film 120b and the conductive film 104 are not connected to each other, different potentials can be applied to the conductive film 120b and the conductive film 104, respectively.
  • the oxide semiconductor film 108 includes a conductive film 104 functioning as a first gate electrode and a second gate electrode. It is located so as to face each of the functioning conductive films 120b, and is sandwiched between the conductive films functioning as two gate electrodes.
  • the length of the conductive film 120b functioning as the second gate electrode in the channel width direction is longer than the length of the oxide semiconductor film 108 in the channel width direction, and the entire oxide semiconductor film 108 includes insulating films 114, 116, The conductive film 120 b is covered with the film 118.
  • the conductive film 120b functioning as the second gate electrode and the conductive film 104 functioning as the first gate electrode are connected to each other through openings 142a and 142b provided in the insulating films 106, 107, 114, 116, and 118. Therefore, the side surface in the channel width direction of the oxide semiconductor film 108 faces the conductive film 120b functioning as the second gate electrode with the insulating films 114, 116, and 118 interposed therebetween.
  • the conductive film 104 functioning as the first gate electrode and the conductive film 120b functioning as the second gate electrode are formed of the insulating film 106 functioning as the first gate insulating film, Insulating films 106, 107 functioning as first gate insulating films and second gate insulating films are connected in openings provided in 107 and insulating films 114, 116, 118 functioning as second gate insulating films.
  • the oxide semiconductor film 108 is surrounded by the functioning insulating films 114, 116, and 118.
  • the oxide semiconductor film 108 included in the transistor 170 is electrically formed by an electric field of the conductive film 104 functioning as the first gate electrode and the conductive film 120b functioning as the second gate electrode. Can be enclosed.
  • a device structure of a transistor that electrically surrounds an oxide semiconductor film in which a channel region is formed by an electric field of the first gate electrode and the second gate electrode is referred to as a surrounded channel (s-channel) structure. Can be called.
  • the transistor 170 Since the transistor 170 has an s-channel structure, an electric field for inducing a channel can be effectively applied to the oxide semiconductor film 108 by the conductive film 104 functioning as the first gate electrode. Current driving capability is improved, and high on-current characteristics can be obtained. Further, since the on-state current can be increased, the transistor 170 can be miniaturized. In addition, since the transistor 170 has a structure surrounded by the conductive film 104 functioning as the first gate electrode and the conductive film 120b functioning as the second gate electrode, the mechanical strength of the transistor 170 can be increased.
  • transistor 170 the transistor 171, or the transistor 172
  • those described in the above description of the transistor 100 can be used.
  • FIG. 26A is a top view of a transistor 160 which is a Loff transistor
  • FIG. 26B corresponds to a cross-sectional view of a cross section taken along dashed-dotted line X1-X2 in FIG.
  • FIG. 26C corresponds to a cross-sectional view of a cross section taken along the dashed-dotted line Y1-Y2 in FIG.
  • the transistor 160 includes an oxide semiconductor film 108 over the substrate 102, a conductive film 112a functioning as a source electrode electrically connected to the oxide semiconductor film 108, and a drain electrically connected to the oxide semiconductor film 108.
  • the conductive film 112b functioning as an electrode, the conductive film 112a, the conductive film 112b, the insulating film 107 over the oxide semiconductor film 108, the insulating film 106 over the insulating film 107, and the first gate electrode over the insulating film 107 And a conductive film 104 that functions.
  • the insulating film 106 and the insulating film 107 function as a first gate insulating film. Therefore, the insulating film 106 and the insulating film 107 functioning as the first gate insulating film are provided between the oxide semiconductor film 108 and the conductive film 104 functioning as the first gate electrode.
  • insulating films 114 and 116 and an insulating film 118 are provided over the transistor 160, more specifically, over the insulating film 107, the conductive films 112 a and 112 b, and the conductive film 104.
  • the insulating films 114, 116, and 118 function as protective insulating films for the transistor 160.
  • the oxide semiconductor film 108 has a region overlapping with the conductive film 104, does not overlap with the conductive film 112a in the above region, and does not overlap with the conductive film 112b in the above region.
  • the Loff region corresponds to the region 122.
  • parasitic capacitance between the first gate electrode and the source electrode and between the first gate electrode and the drain electrode can be reduced.
  • FIG. 27A is a top view of the transistor 161 which is a Lov transistor
  • FIG. 27B is a cross-sectional view of a cross section taken along the dashed-dotted line X1-X2 in FIG.
  • FIG. 27C corresponds to a cross-sectional view of a cross section taken along dashed-dotted line Y1-Y2 in FIG.
  • the transistor 161 includes an oxide semiconductor film 108 over the substrate 102, a conductive film 112a functioning as a source electrode electrically connected to the oxide semiconductor film 108, and a drain electrically connected to the oxide semiconductor film 108.
  • the conductive film 112b functioning as an electrode, the conductive film 112a, the conductive film 112b, the insulating film 107 over the oxide semiconductor film 108, the insulating film 106 over the insulating film 107, and the first gate electrode over the insulating film 107 And a conductive film 104 that functions.
  • the insulating film 106 and the insulating film 107 function as a first gate insulating film. Therefore, the insulating film 106 and the insulating film 107 functioning as the first gate insulating film are provided between the oxide semiconductor film 108 and the conductive film 104 functioning as the first gate electrode.
  • insulating films 114 and 116 and an insulating film 118 are provided over the transistor 161, more specifically, over the insulating film 107, the conductive films 112 a and 112 b, and the conductive film 104.
  • the insulating films 114, 116, and 118 function as protective insulating films for the transistor 161.
  • the oxide semiconductor film 108 has a region overlapping with the conductive film 104, overlaps with the conductive film 112a in part of the region, and overlaps with the conductive film 112b in another part of the region.
  • a top gate Loff transistor and a Lov transistor using a polycrystalline silicon film as a semiconductor film will be described with reference to FIGS.
  • a transistor using a polycrystalline silicon film as a semiconductor film described below may have a bottom gate structure or a dual gate structure instead of a top gate structure.
  • FIG. 63A is a top view of the transistor 180 which is a Loff transistor
  • FIG. 63B corresponds to a cross-sectional view of a cross section taken along dashed-dotted line X1-X2 in FIG. 63A
  • 63C corresponds to a cross-sectional view of a cross section taken along dashed-dotted line Y1-Y2 in FIG. 63A
  • FIG. 64A is a top view of the transistor 181 that is a Lov transistor
  • FIG. 64B is a cross-sectional view taken along the dashed-dotted line X1-X2 in FIG.
  • FIG. 64C corresponds to a cross-sectional view of a cross section taken along dashed-dotted line Y1-Y2 in FIG.
  • the transistor 180 and the transistor 181 include a polycrystalline silicon film 308 over the substrate 102, a conductive film 312 a functioning as a source electrode electrically connected to the polycrystalline silicon film 308, and a drain electrode electrically connected to the polycrystalline silicon film 308.
  • a conductive film 312b functioning as an insulating film
  • an insulating film 306 functioning as a first gate insulating film over the conductive film 312a, the conductive film 312b, and the polycrystalline silicon film 308
  • a first gate electrode over the insulating film 306.
  • a conductive film 304. Therefore, the insulating film 306 functioning as the first gate insulating film is provided between the polycrystalline silicon film 308 functioning as the semiconductor film and the conductive film 304 functioning as the first gate electrode.
  • An insulating film 314 is provided over the insulating film 306 and the conductive film 304.
  • the conductive film 316a is electrically connected to the conductive film 312a through an opening 318a provided in the insulating film 306 and the insulating film 314.
  • the conductive film 316b is electrically connected to the conductive film 312b through an opening 318b provided in the insulating film 306 and the insulating film 314.
  • the polycrystalline silicon film 308 has a region overlapping with the conductive film 304, does not overlap with the conductive film 312a in the region, and does not overlap with the conductive film 312b in the region.
  • the polycrystalline silicon film 308 has a region overlapping with the conductive film 304, overlaps with the conductive film 312a in part of the region, and overlaps with the conductive film 312b in another part of the region.
  • a silicon film that has been polycrystallized by various methods can be used.
  • a crystallization method there are a laser crystallization method using laser light, a crystallization method using a catalytic element, and the like.
  • a crystallization method using a catalytic element and a laser crystallization method can be used in combination.
  • a thermal crystallization method using an electric furnace, a lamp annealing crystallization method using infrared light, a crystallization method using a catalytic element, A crystallization method combined with high-temperature annealing at about 950 ° C. may be used.
  • the conductive film 316a and the conductive film 316b are formed, for example, by doping a polycrystalline silicon film with impurities.
  • a polycrystalline silicon film with impurities In the case of a p-channel transistor, an impurity imparting p-type conductivity is doped, and in the case of an n-channel transistor, an impurity imparting n-type conductivity is doped.
  • the polycrystalline silicon film doped with impurities as described above functions as a conductive film.
  • the impurity element imparting p-type conductivity include boron (B), aluminum (Al), and gallium (Ga).
  • the impurity element imparting n-type conductivity include phosphorus (P), arsenic (As), and antimony (Sb).
  • the conductive film 316a and the conductive film 316b may be provided with a low-concentration impurity region (LDD: Lightly Doped Drain).
  • the low concentration impurity region is preferably provided in contact with the semiconductor film. Note that in this specification, even if an n-type or p-type impurity is doped, the polycrystalline silicon film 308 may be used as long as it has a function as an active layer of a transistor.
  • the conductive film 304, the conductive film 312a, or the conductive film 312b can be formed using a material used for the conductive film 104, the conductive film 112a, or the conductive film 112b.
  • a material used for the insulating film 306 or the insulating film 314 a material used for the insulating film 106, the insulating film 107, the insulating film 114, the insulating film 116, or the insulating film 118 can be used. Note that materials such as each insulating film and each conductive film are not limited to those described in this embodiment mode.
  • FIGS. 28 to 30 are cross-sectional views illustrating a method for manufacturing a transistor.
  • the bottom-gate Loff transistor and the Lov transistor can be separately formed by changing the pattern of the first gate electrode, the oxide semiconductor, the source electrode, or the drain electrode. Therefore, a Loff transistor and a Lov transistor can be manufactured using the same manufacturing method. Therefore, a manufacturing process described below can be applied to both a Loff transistor and a Lov transistor in the following.
  • 28 to 30 are cross-sectional views of the Loff type transistor, and the right side is a cross-sectional view of the Lov type transistor.
  • (M-1) is used for the cross-sectional view of the Loff-type transistor
  • (M-2) is used for the cross-sectional view of the Lov-type transistor.
  • M is one of the letters A, B, C or D.
  • a film (an insulating film, an oxide semiconductor film, a conductive film, or the like) included in the transistors 100 and 200 is formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, or a pulsed laser deposition (PLD) method.
  • CVD chemical vapor deposition
  • PLD pulsed laser deposition
  • it can be formed by a coating method or a printing method.
  • a sputtering method and a plasma enhanced chemical vapor deposition (PECVD) method are typical, but a thermal CVD method may be used.
  • PECVD plasma enhanced chemical vapor deposition
  • an MOCVD metal organic chemical deposition
  • ALD atomic layer deposition
  • the inside of a chamber is set to atmospheric pressure or reduced pressure, and a raw material gas and an oxidant are simultaneously sent into the chamber, reacted in the vicinity of the substrate or on the substrate, and deposited on the substrate.
  • the thermal CVD method is a film forming method that does not generate plasma, and thus has an advantage that no defect is generated due to plasma damage.
  • film formation is performed by setting the inside of the chamber to atmospheric pressure or reduced pressure, sequentially introducing raw material gases for reaction into the chamber, and repeating the order of introducing the gases. For example, by switching each switching valve (also referred to as a high-speed valve), two or more kinds of source gases are sequentially supplied to the chamber, and at the same time or after the first source gas so as not to mix a plurality of kinds of source gases.
  • An inert gas (such as argon or nitrogen) is introduced, and the second source gas is introduced.
  • the inert gas becomes a carrier gas, and the inert gas may be introduced at the same time when the second raw material gas is introduced.
  • the second raw material gas may be introduced after the first raw material gas is exhausted by evacuation.
  • the first source gas is adsorbed on the surface of the substrate to form a first monoatomic layer, and reacts with a second source gas introduced later, so that the second monoatomic layer becomes the first monoatomic layer.
  • a thin film is formed by being stacked on the atomic layer.
  • a conductive film is formed over the substrate 102, and the conductive film is processed by a lithography process and an etching process, so that the conductive film 104 functioning as a first gate electrode is formed.
  • insulating films 106 and 107 functioning as first gate insulating films are formed over the conductive film 104 (see FIGS. 28A-1 and 28A-2).
  • the conductive film 104 functioning as the first gate electrode can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, or a pulsed laser deposition (PLD) method. Alternatively, it can be formed by a coating method or a printing method.
  • CVD chemical vapor deposition
  • PLD pulsed laser deposition
  • a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method is typical, but a thermal CVD method such as the metal organic chemical vapor deposition (MOCVD) method described above, or an atomic layer deposition ( (ALD) method may be used.
  • MOCVD metal organic chemical vapor deposition
  • ALD atomic layer deposition
  • a glass substrate is used as the substrate 102, and a tungsten film with a thickness of 100 nm is formed as the conductive film 104 functioning as the first gate electrode by a sputtering method.
  • the insulating films 106 and 107 functioning as the first gate insulating film can be formed by a sputtering method, a PECVD method, a thermal CVD method, a vacuum evaporation method, a PLD method, or the like.
  • a 400-nm-thick silicon nitride film is formed as the insulating film 106 and a 50-nm-thick silicon oxynitride film is formed as the insulating film 107 by PECVD.
  • the insulating film 106 can have a stacked structure of silicon nitride films. Specifically, the insulating film 106 can have a three-layer structure including a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. As an example of the three-layer structure, it can be formed as follows.
  • the first silicon nitride film for example, silane having a flow rate of 200 sccm, nitrogen having a flow rate of 2000 sccm, and ammonia gas having a flow rate of 100 sccm are supplied as source gases to the reaction chamber of the PE-CVD apparatus, and the pressure in the reaction chamber is controlled to 100 Pa. Then, a power of 2000 W may be supplied using a 27.12 MHz high frequency power source so that the thickness is 50 nm.
  • silane having a flow rate of 200 sccm, nitrogen having a flow rate of 2000 sccm, and ammonia gas having a flow rate of 2000 sccm are supplied as source gases to the reaction chamber of the PECVD apparatus, and the pressure in the reaction chamber is controlled to 100 Pa;
  • a thickness of 300 nm may be formed by supplying 2000 W of power using a 12 MHz high frequency power source.
  • silane having a flow rate of 200 sccm and nitrogen having a flow rate of 5000 sccm are supplied as source gases to the reaction chamber of the PECVD apparatus, the pressure in the reaction chamber is controlled to 100 Pa, and a high frequency power source of 27.12 MHz is used. Then, the power may be formed so as to have a thickness of 50 nm by supplying power of 2000 W.
  • the substrate temperature at the time of forming the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film can be 350 ° C.
  • the insulating film 106 has a three-layer structure of a silicon nitride film, for example, when a conductive film containing copper (Cu) is used for the conductive film 104, the following effects can be obtained.
  • the first silicon nitride film can suppress diffusion of copper (Cu) element from the conductive film 104.
  • the second silicon nitride film has a function of releasing hydrogen and can improve the withstand voltage of the insulating film functioning as the first gate insulating film.
  • the third silicon nitride film emits less hydrogen from the third silicon nitride film and can suppress diffusion of hydrogen released from the second silicon nitride film.
  • the insulating film 107 is formed using an insulating film containing oxygen in order to improve interface characteristics with the oxide semiconductor film 108 (more specifically, the first oxide semiconductor film 108a) to be formed later. preferable.
  • the first oxide semiconductor film 108 a is formed over the insulating film 107.
  • the second oxide semiconductor film 108b is formed over the first oxide semiconductor film 108a (see FIGS. 28B-1 and 28B-2).
  • a stacked oxide semiconductor film is formed by forming the oxide semiconductor film.
  • a mask is formed over the oxide semiconductor film of the previous layer by a lithography process, and the island-shaped oxide semiconductor film 108 is formed by processing the stacked oxide semiconductor film into a desired region.
  • a rare gas typically argon
  • oxygen, a rare gas, and a mixed gas of oxygen are used as appropriate as the sputtering gas.
  • a mixed gas it is preferable to increase the oxygen gas ratio relative to the rare gas.
  • oxygen gas or argon gas used as a sputtering gas is a gas having a dew point of ⁇ 40 ° C. or lower, preferably ⁇ 80 ° C. or lower, more preferably ⁇ 100 ° C. or lower, more preferably ⁇ 120 ° C. or lower.
  • an adsorption vacuum exhaust pump such as a cryopump is used as a chamber in the sputtering apparatus so as to remove water or the like that is an impurity for the oxide semiconductor film 108 as much as possible. It is preferable to perform high vacuum evacuation (from about 5 ⁇ 10 ⁇ 7 Pa to about 1 ⁇ 10 ⁇ 4 Pa) using Alternatively, it is preferable to combine a turbo molecular pump and a cold trap so that a gas, particularly a gas containing carbon or hydrogen, does not flow backward from the exhaust system into the chamber.
  • a conductive film 112 functioning as a source electrode and a drain electrode is formed over the insulating film 107 and the oxide semiconductor film 108a (see FIGS. 28C-1 and 28C-2).
  • a stacked film of a tungsten film with a thickness of 50 nm and an aluminum film with a thickness of 400 nm is formed as the conductive film 112 by a sputtering method.
  • the conductive film 112 may have a three-layer structure of a tungsten film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 100 nm.
  • masks 140a and 140b are formed in desired regions over the conductive film 112 (see FIGS. 28D-1 and 28D-2).
  • the masks 140a and 140b are formed by applying a photosensitive resin film and patterning the photosensitive resin film by a lithography process.
  • the conductive film 112 and the second oxide semiconductor film 108b are processed using the etching gas 138 over the conductive film 112 and the masks 140a and 140b (FIGS. 29A-1 and 29A-2). reference).
  • the conductive film 112 and the second oxide semiconductor film 108b are processed using a dry etching apparatus.
  • the method for forming the conductive film 112 is not limited thereto, and the conductive film 112 and the second oxide semiconductor film 108b can be formed using a wet etching apparatus by using a chemical solution for the etching gas 138, for example. It may be processed.
  • the conductive film 112 and the second oxide semiconductor film 108b were processed using a dry etching apparatus rather than the conductive film 112 and the second oxide semiconductor film 108b were processed using a wet etching apparatus. This is more preferable because a finer pattern can be formed.
  • the oxide semiconductor film 108 includes a first oxide semiconductor film 108a and a second oxide semiconductor film 108b having a depression (see FIGS. 29B-1 and 29B-2). ).
  • a chemical solution may be applied over the second oxide semiconductor film 108b and the conductive films 112a and 112b to clean the surface (back channel side) of the second oxide semiconductor film 108b.
  • the cleaning method include cleaning using a chemical solution such as phosphoric acid.
  • a chemical solution such as phosphoric acid.
  • impurities attached to the surface of the second oxide semiconductor film 108b eg, elements contained in the conductive films 112a and 112b
  • the cleaning is not necessarily performed, and in some cases, the cleaning may not be performed.
  • the second oxide semiconductor film 108b includes a second region having a thickness smaller than that of the first oxide semiconductor film 108a when the conductive films 112a and 112b are formed and / or in the cleaning step.
  • insulating films 114 and 116 are formed over the oxide semiconductor film 108 and the conductive films 112a and 112b (see FIGS. 29C-1 and 29C-2).
  • the insulating film 116 is preferably formed continuously without being exposed to the air.
  • the insulating film 114 and the insulating film are formed by continuously forming the insulating film 116 by adjusting one or more of the flow rate, pressure, high frequency power, and substrate temperature of the source gas without opening to the atmosphere.
  • the concentration of impurities derived from atmospheric components can be reduced at the interface 116, and oxygen contained in the insulating films 114 and 116 can be transferred to the oxide semiconductor film 108, so that the amount of oxygen vacancies in the oxide semiconductor film 108 can be reduced. Can be reduced.
  • a silicon oxynitride film can be formed by a PECVD method.
  • a deposition gas and an oxidation gas containing silicon as the source gas.
  • the deposition gas containing silicon include silane, disilane, trisilane, and fluorinated silane.
  • the oxidizing gas include dinitrogen monoxide and nitrogen dioxide.
  • the flow rate of the oxidizing gas is more than 20 times and less than 100 times, preferably 40 times or more and 80 times or less, and the pressure in the processing chamber is less than 100 Pa, preferably 50 Pa or less with respect to the flow rate of the deposition gas.
  • the insulating film 114 contains nitrogen and has a small amount of defects.
  • the temperature at which the substrate 102 is held is 220 ° C.
  • silane with a flow rate of 50 sccm and dinitrogen monoxide with a flow rate of 2000 sccm are used as source gases
  • the pressure in the processing chamber is 20 Pa
  • parallel plates A silicon oxynitride film is formed by a PECVD method in which high-frequency power supplied to the electrode is 13.56 MHz and 100 W (power density is 1.6 ⁇ 10 ⁇ 2 W / cm 2 ).
  • a substrate placed in a processing chamber evacuated by a PECVD apparatus is held at 180 ° C. or higher and 350 ° C. or lower, and a raw material gas is introduced into the processing chamber so that the pressure in the processing chamber is 100 Pa or higher and 250 Pa or lower. , more preferably not more than 200Pa than 100 Pa, the electrode provided in the processing chamber 0.17 W / cm 2 or more 0.5 W / cm 2 or less, more preferably 0.25 W / cm 2 or more 0.35 W / cm 2 or less of A silicon oxide film or a silicon oxynitride film is formed depending on conditions for supplying high-frequency power.
  • the oxygen content in the insulating film 116 is higher than the stoichiometric composition.
  • a film formed at the above substrate temperature since the bonding force between silicon and oxygen is weak, part of oxygen in the film is released by heat treatment in a later step. As a result, an oxide insulating film containing more oxygen than that in the stoichiometric composition and from which part of oxygen is released by heating can be formed.
  • the step of forming the insulating film 116 is performed at a temperature of 180 ° C. or higher and 350 ° C. or lower with a PECVD apparatus, and the temperature of the step of forming the insulating film 116 is highest during the manufacturing steps of the transistors 100 and 200. preferable.
  • the insulating film 116 is formed at a temperature of 350 ° C.
  • the transistors 100 and 200 can be directly formed over a flexible substrate or the like.
  • the insulating film 114 serves as a protective film of the oxide semiconductor film 108. Therefore, the insulating film 116 can be formed using high-frequency power with high power density while reducing damage to the oxide semiconductor film 108.
  • the amount of defects in the insulating film 116 can be reduced by increasing the flow rate of the deposition gas containing silicon with respect to the oxidizing gas under the deposition conditions of the insulating film 116.
  • An oxide insulating layer with a small amount of defects that is preferably 1.5 ⁇ 10 17 spins / cm 3 or less can be formed. As a result, the reliability of the transistor can be improved.
  • heat treatment may be performed after the insulating films 114 and 116 are formed.
  • nitrogen oxides contained in the insulating films 114 and 116 can be reduced.
  • part of oxygen contained in the insulating films 114 and 116 is moved to the oxide semiconductor film 108 by the heat treatment, so that the amount of oxygen vacancies contained in the oxide semiconductor film 108 can be reduced.
  • the temperature of heat treatment for the insulating films 114 and 116 is typically 150 ° C to 350 ° C inclusive.
  • the heat treatment may be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably 1 ppm or less, preferably 10 ppb or less), or a rare gas (such as argon or helium).
  • a rare gas such as argon or helium.
  • an electric furnace, an RTA apparatus, or the like can be used for the heat treatment in which hydrogen, water, or the like is preferably not contained in the nitrogen, oxygen, ultra-dry air, or the rare gas.
  • heat treatment is performed at 350 ° C. for one hour in a nitrogen atmosphere. Note that in the step of forming the transistors 100 and 200, the temperature at which the insulating film 116 is formed needs to be highest, and a temperature equivalent to the temperature at which the insulating film 116 is formed may be performed in different steps.
  • the oxide conductive film 131 is formed over the insulating film 116 (see FIGS. 29D-1 and 29D-2).
  • the oxide conductive film 131 includes oxygen and a metal (at least one selected from indium, zinc, titanium, aluminum, tungsten, tantalum, and molybdenum).
  • the oxide conductive film 131 can be formed by a sputtering method.
  • the thickness of the oxide conductive film 131 is preferably 1 nm to 20 nm, or 2 nm to 10 nm.
  • ITSO indium tin oxide to which silicon oxide with a thickness of 5 nm is added is used as the oxide conductive film 131.
  • oxygen 139 is added to the insulating films 114 and 116 and the oxide semiconductor film 108 through the oxide conductive film 131. (See FIGS. 30A-1 and A-2).
  • oxygen 139 can be effectively added to the insulating films 114 and 116 and the oxide semiconductor film 108 by applying a bias to the substrate side.
  • the bias for example, the power density may be 1 W / cm 2 or more and 5 W / cm 2 or less.
  • the oxide conductive film 131 is removed with an etchant 142 (see FIGS. 30B-1 and 30B-2).
  • a dry etching method As a method for removing the oxide conductive film 131, a dry etching method, a wet etching method, a method in which the dry etching method and the wet etching method are combined, or the like can be given.
  • the etchant 142 is an etching gas
  • the etchant 142 is a chemical solution.
  • the oxide conductive film 131 is removed by a wet etching method.
  • the insulating film 118 is formed over the insulating film 116 (see FIGS. 30C-1 and 30C-2).
  • heat treatment is performed before the insulating film 118 is formed or after the insulating film 118 is formed, so that excess oxygen contained in the insulating films 114 and 116 is diffused into the oxide semiconductor film 108. Oxygen deficiency can be compensated.
  • excess oxygen contained in the insulating films 114 and 116 can be diffused into the oxide semiconductor film 108 to fill oxygen vacancies in the oxide semiconductor film 108. .
  • the substrate temperature be 180 ° C. or higher and 350 ° C. or lower because a dense film can be formed.
  • a silicon nitride film is formed as the insulating film 118 by a PECVD method
  • a deposition gas containing silicon, nitrogen, and ammonia as a source gas.
  • ammonia is dissociated in the plasma and active species are generated.
  • the active species breaks the bond between silicon and hydrogen contained in the deposition gas containing silicon and the triple bond of nitrogen. As a result, the bonding between silicon and nitrogen is promoted, the bonding between silicon and hydrogen is small, the defects are few, and a dense silicon nitride film can be formed.
  • the flow rate ratio of nitrogen to ammonia is preferably 5 or more and 50 or less and 10 or more and 50 or less.
  • a silicon nitride film with a thickness of 50 nm is formed using a silane, nitrogen, and ammonia as source gases using a PECVD apparatus.
  • the flow rates are 50 sccm for silane, 5000 sccm for nitrogen, and 100 sccm for ammonia.
  • the processing chamber pressure is 100 Pa
  • the substrate temperature is 350 ° C.
  • high frequency power of 1000 W is supplied to the parallel plate electrodes using a high frequency power source of 27.12 MHz.
  • PECVD apparatus is a PECVD apparatus of a parallel plate type electrode area is 6000 cm 2, which is in terms 1.7 ⁇ 10 -1 W / cm 2 to the power per unit area power supplied (power density).
  • the transistor 100 illustrated in FIG. 19 and the transistor 200 illustrated in FIG. 20 can be formed.
  • FIG. 31 is a cross-sectional view illustrating a method for manufacturing a transistor.
  • 31A, 31C, 31E, and 31G are cross-sectional views in the channel length direction during the manufacture of the transistor 170.
  • FIGS. 31B, 31D, 31F, and 31H are transistors. It is sectional drawing of the channel width direction in the middle of preparation of 170.
  • FIG. 31A, 31C, 31E, and 31G are cross-sectional views in the channel length direction during the manufacture of the transistor 170.
  • FIGS. 31B, 31D, 31F, and 31H are transistors. It is sectional drawing of the channel width direction in the middle of preparation of 170.
  • the dual-gate Loff transistor and the Lov transistor can be separately formed by changing the pattern of the first gate electrode, the second gate electrode, the oxide semiconductor, the source electrode, the drain electrode, and the like. is there. Therefore, a Loff transistor and a Lov transistor can be manufactured using the same manufacturing method. Therefore, a manufacturing process described below can be applied to both a Loff transistor and a Lov transistor in the following.
  • steps similar to those for manufacturing the transistors 100 and 200 described above are performed, and the conductive film 104, the insulating films 106 and 107, the oxide semiconductor film 108, and the conductive film are formed over the substrate 102.
  • Films 112a and 112b and insulating films 114, 116, and 118 are formed (see FIGS. 31A and 31B).
  • a mask is formed over the insulating film 118 by a lithography process, and an opening 142 c is formed in a desired region of the insulating films 114, 116, and 118. Further, a mask is formed over the insulating film 118 by a lithography process, and openings 142 a and 142 b are formed in desired regions of the insulating films 106, 107, 114, 116, and 118. Note that the opening 142c is formed so as to reach the conductive film 112b. The openings 142a and 142b are formed so as to reach the conductive film 104, respectively (see FIGS. 31C and 31D).
  • the openings 142a and 142b and the opening 142c may be formed in the same process or in different processes. In the case where the openings 142a and 142b and the opening 142c are formed in the same process, for example, a gray-tone mask or a half-tone mask can be used. Further, the openings 142a and 142b may be formed in a plurality of times. For example, the insulating films 106 and 107 are processed, and then the insulating films 114, 116, and 118 are processed.
  • a conductive film 120 is formed over the insulating film 118 so as to cover the openings 142a, 142b, and 142c (see FIGS. 31E and 31F).
  • the conductive film 120 for example, a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) can be used.
  • the conductive film 120 includes indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (ITO), A light-transmitting conductive material such as indium zinc oxide or indium tin oxide added with silicon oxide (ITSO) can be used.
  • the conductive film 120 can be formed by, for example, a sputtering method. In this embodiment, an ITSO film with a thickness of 110 nm is formed by a sputtering method.
  • a mask is formed over the conductive film 120 by a lithography process, and the conductive film 112 is processed into a desired shape, so that the conductive films 120a and 120b are formed (see FIGS. 31G and 31H).
  • Examples of a method for forming the conductive films 120a and 120b include a dry etching method, a wet etching method, or a method in which the dry etching method and the wet etching method are combined.
  • the conductive film 120 is processed into the conductive films 120a and 120b by a wet etching method.
  • the transistor 170 illustrated in FIG. 23 can be manufactured.
  • FIG. 24 can be manufactured using a similar process.
  • FIG. 23 and FIG. 24 are different in the shape of the conductive film 120b functioning as the second gate electrode.
  • a transistor 172 which is a Lov transistor illustrated in FIG. 25 can be manufactured using a similar process.
  • a transistor 170 illustrated in FIG. 23 and a transistor 172 illustrated in FIG. 25 are different in the shape of the conductive film 104 functioning as the first gate electrode and the conductive film 120b functioning as the second gate electrode.
  • FIG. 32 illustrates a method for manufacturing the transistor 172 illustrated in FIGS.
  • An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor.
  • a non-single-crystal oxide semiconductor a CAAC-OS (c-axis-aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), a pseudo-amorphous oxide semiconductor (a-like oxide OS) : Amorphous-like oxide semiconductor) and amorphous oxide semiconductor.
  • oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors.
  • a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.
  • Amorphous structures are generally isotropic, have no heterogeneous structure, are metastable, have no fixed atomic arrangement, have a flexible bond angle, have short-range order, but long-range order It is said that it does not have.
  • a stable oxide semiconductor cannot be called a complete amorphous oxide semiconductor.
  • an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a complete amorphous oxide semiconductor.
  • an a-like OS is not isotropic but has an unstable structure having a void (also referred to as a void). In terms of being unstable, a-like OS is physically similar to an amorphous oxide semiconductor.
  • CAAC-OS First, the CAAC-OS will be described.
  • a CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).
  • CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction)
  • XRD X-ray Diffraction
  • CAAC-OS having an InGaZnO 4 crystal classified into the space group R-3m is subjected to structural analysis by an out-of-plane method
  • a diffraction angle (2 ⁇ ) as illustrated in FIG. Shows a peak near 31 °. Since this peak is attributed to the (009) plane of the InGaZnO 4 crystal, in CAAC-OS, the crystal has a c-axis orientation, and the plane on which the c-axis forms a CAAC-OS film (formation target) It can also be confirmed that it faces a direction substantially perpendicular to the upper surface.
  • a peak may also appear when 2 ⁇ is around 36 °.
  • the peak where 2 ⁇ is around 36 ° is attributed to the crystal structure classified into the space group Fd-3m. Therefore, the CAAC-OS preferably does not show the peak.
  • FIG. 33E shows a diffraction pattern obtained when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface.
  • a ring-shaped diffraction pattern is confirmed from FIG. Therefore, it can be seen that the a-axis and the b-axis of the pellet included in the CAAC-OS have no orientation even by electron diffraction using an electron beam with a probe diameter of 300 nm.
  • the first ring in FIG. 33E is considered to be caused by the (010) plane and the (100) plane of the InGaZnO 4 crystal.
  • the second ring in FIG. 33E is considered to be due to the (110) plane and the like.
  • FIG. 34A shows a high-resolution TEM image of a cross section of the CAAC-OS observed from a direction substantially parallel to the sample surface.
  • a spherical aberration correction function was used for observation of the high-resolution TEM image.
  • a high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image.
  • the Cs-corrected high resolution TEM image can be observed, for example, with an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.
  • FIG. 34A shows a pellet that is a region where metal atoms are arranged in a layered manner. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellet can also be referred to as a nanocrystal (nc).
  • the CAAC-OS can also be referred to as an oxide semiconductor including CANC (C-Axis aligned nanocrystals).
  • CANC C-Axis aligned nanocrystals
  • FIGS. 34B and 34C show Cs-corrected high-resolution TEM images of the plane of the CAAC-OS observed from the direction substantially perpendicular to the sample surface.
  • FIGS. 34D and 34E are images obtained by performing image processing on FIGS. 34B and 34C, respectively.
  • an image processing method will be described.
  • an FFT image is obtained by performing Fast Fourier Transform (FFT) processing on FIG.
  • FFT Fast Fourier Transform
  • IFFT inverse fast Fourier transform
  • the image acquired in this way is called an FFT filtered image.
  • the FFT filtered image is an image obtained by extracting periodic components from the Cs-corrected high-resolution TEM image, and shows a lattice arrangement.
  • FIG. 34D the portion where the lattice arrangement is disturbed is indicated by a broken line.
  • a region surrounded by a broken line is one pellet.
  • the location shown with the broken line is the connection part of a pellet and a pellet. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape.
  • the shape of a pellet is not necessarily a regular hexagonal shape, and is often a non-regular hexagonal shape.
  • FIG. 34 (E) a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned is indicated by a dotted line, and the change in the orientation of the lattice arrangement is shown. It is indicated by a broken line.
  • a clear crystal grain boundary cannot be confirmed even in the vicinity of the dotted line.
  • the CAAC-OS has a c-axis alignment and a crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction to have a strain. Therefore, the CAAC-OS can also be referred to as CAAcrystal (c-axis-aligned ab-plane-anchored crystal).
  • the CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be deteriorated by entry of impurities, generation of defects, or the like, in reverse, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).
  • the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element.
  • an element such as silicon which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor.
  • heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.
  • an oxide semiconductor has impurities or defects, characteristics may fluctuate due to light, heat, or the like.
  • an impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source.
  • oxygen vacancies in the oxide semiconductor may serve as carrier traps or may serve as carrier generation sources by capturing hydrogen.
  • a CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, less than 8 ⁇ 10 11 atoms / cm 3, preferably 1 ⁇ 10 11 / cm less than 3, more preferably less than 1 ⁇ 10 10 atoms / cm 3, 1 ⁇ 10 -9 / cm 3 or An oxide semiconductor having the above carrier density can be obtained. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.
  • the CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.
  • nc-OS is analyzed by XRD.
  • XRD X-ray diffraction
  • FIG. 35B shows a diffraction pattern (nanobeam electron diffraction pattern) obtained when an electron beam with a probe diameter of 1 nm is incident on the same sample. From FIG. 35B, a plurality of spots are observed in the ring-shaped region. Therefore, nc-OS does not confirm order when an electron beam with a probe diameter of 50 nm is incident, but confirms order when an electron beam with a probe diameter of 1 nm is incident.
  • the nc-OS has a highly ordered region, that is, a crystal in a thickness range of less than 10 nm. Note that there are some regions where a regular electron diffraction pattern is not observed because the crystal faces in various directions.
  • FIG. 35D shows a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed from a direction substantially parallel to the formation surface.
  • the nc-OS has a region in which a crystal part can be confirmed, such as a portion indicated by an auxiliary line, and a region in which a clear crystal part cannot be confirmed in a high-resolution TEM image.
  • a crystal part included in the nc-OS has a size of 1 nm to 10 nm, particularly a size of 1 nm to 3 nm in many cases. Note that an oxide semiconductor in which the size of a crystal part is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor.
  • the nc-OS may not be able to clearly confirm a crystal grain boundary in a high-resolution TEM image.
  • the nanocrystal may have the same origin as the pellet in the CAAC-OS. Therefore, the crystal part of nc-OS is sometimes referred to as a pellet below.
  • the nc-OS has a periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm).
  • the nc-OS has no regularity in crystal orientation between different pellets. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.
  • nc-OS is an oxide semiconductor having RANC (Random Aligned nanocrystals), or an oxide having NANC (Non-Aligned nanocrystals). It can also be called a semiconductor.
  • the nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an a-like OS or an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.
  • the a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor.
  • FIG. 36 shows a high-resolution cross-sectional TEM image of the a-like OS.
  • FIG. 36A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation.
  • FIG. 36B is a high-resolution cross-sectional TEM image of the a-like OS after irradiation with electrons (e ⁇ ) of 4.3 ⁇ 10 8 e ⁇ / nm 2 .
  • electrons (e ⁇ ) of 4.3 ⁇ 10 8 e ⁇ / nm 2 .
  • the a-like OS Since it has a void, the a-like OS has an unstable structure.
  • the a-like OS has an unstable structure as compared with the CAAC-OS and the nc-OS, a change in structure due to electron irradiation is shown.
  • a-like OS, nc-OS, and CAAC-OS are prepared. Each sample is an In—Ga—Zn oxide.
  • a high-resolution cross-sectional TEM image of each sample is acquired.
  • Each sample has a crystal part by a high-resolution cross-sectional TEM image.
  • a unit cell of an InGaZnO 4 crystal has a structure in which three In—O layers and six Ga—Zn—O layers have a total of nine layers stacked in the c-axis direction.
  • the spacing between these adjacent layers is about the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, in the following, a portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less is regarded as a crystal part of InGaZnO 4 .
  • the lattice fringes correspond to the ab plane of the InGaZnO 4 crystal.
  • FIG. 37 shows an example in which the average size of the crystal parts (22 to 30 locations) of each sample was investigated. Note that the length of the lattice stripes described above is the size of the crystal part. From FIG. 37, it can be seen that in the a-like OS, the crystal part becomes larger in accordance with the cumulative dose of electrons related to the acquisition of the TEM image and the like. From FIG. 37, the crystal part (also referred to as the initial nucleus), which was about 1.2 nm in the initial observation by TEM, has a cumulative electron (e ⁇ ) irradiation dose of 4.2 ⁇ 10 8 e ⁇ / nm. In FIG. 2 , it can be seen that the crystal has grown to a size of about 1.9 nm.
  • FIG. 37 indicates that the crystal part sizes of the nc-OS and the CAAC-OS are approximately 1.3 nm and 1.8 nm, respectively, regardless of the cumulative electron dose.
  • a Hitachi transmission electron microscope H-9000NAR was used for electron beam irradiation and TEM observation.
  • the electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7 ⁇ 10 5 e ⁇ / (nm 2 ⁇ s), and an irradiation region diameter of 230 nm.
  • the crystal part may be grown by electron irradiation.
  • the crystal part is hardly grown by electron irradiation. That is, it can be seen that the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.
  • the a-like OS has a lower density than the nc-OS and the CAAC-OS.
  • the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition.
  • the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of the single crystal having the same composition.
  • An oxide semiconductor that is less than 78% of the density of a single crystal is difficult to form.
  • the density of single crystal InGaZnO 4 having a rhombohedral structure is 6.357 g / cm 3 .
  • the density of a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3.
  • the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm 3 or more and 6.3 g / less than cm 3 .
  • oxide semiconductors have various structures and various properties.
  • the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.
  • FIG. 38A is a schematic diagram of a film formation chamber.
  • the CAAC-OS can be formed by a sputtering method.
  • the substrate 5220 and the target 5230 are arranged to face each other.
  • a heating mechanism 5260 is provided below the substrate 5220.
  • the target 5230 is bonded to the backing plate.
  • a plurality of magnets are arranged at positions facing the target 5230 via the backing plate.
  • a sputtering method that uses a magnetic field to increase the deposition rate is called a magnetron sputtering method.
  • a distance d (also referred to as a target-substrate distance (T-S distance)) between the substrate 5220 and the target 5230 is 0.01 m or more and 1 m or less, preferably 0.02 m or more and 0.5 m or less.
  • the film formation chamber is mostly filled with a film forming gas (for example, oxygen, argon, or a mixed gas containing oxygen at a ratio of 5% by volume or more), and is 0.01 Pa to 100 Pa, preferably 0.1 Pa to 10 Pa. Controlled.
  • a high-density plasma region is formed in the vicinity of the target 5230 by a magnetic field.
  • ions 5201 are generated by ionizing the deposition gas.
  • the ion 5201 is, for example, an oxygen cation (O + ) or an argon cation (Ar + ).
  • the target 5230 has a polycrystalline structure having a plurality of crystal grains, and any one of the crystal grains includes a cleavage plane.
  • FIG. 39 illustrates a crystal structure of InMZnO 4 (the element M is, for example, aluminum, gallium, yttrium, or tin) included in the target 5230.
  • FIG. 39 shows the crystal structure of InMZnO 4 when observed from the direction parallel to the b-axis.
  • a repulsive force is generated between two adjacent M—Zn—O layers because the oxygen atom has a negative charge. Therefore, the InMZnO 4 crystal has a cleavage plane in the opening of two adjacent M-Zn-O layers.
  • the ions 5201 generated in the high-density plasma region are accelerated toward the target 5230 by the electric field and eventually collide with the target 5230.
  • the pellet 5200 which is a flat or pellet-like sputtered particle is peeled off from the cleavage plane (see FIG. 38A).
  • the pellet 5200 is a portion sandwiched between two cleavage planes shown in FIG. Therefore, when only the pellet 5200 is extracted, the cross section becomes as shown in FIG. 38B and the upper surface becomes as shown in FIG. 38C.
  • the structure of the pellet 5200 may be distorted by the impact of the collision of the ions 5201.
  • the particles 5203 are also ejected from the target 5230 as the pellet 5200 is peeled off.
  • a particle 5203 has an aggregate of one atom or several atoms. Therefore, the particles 5203 can also be referred to as atomic particles.
  • the pellet 5200 is a sputtered particle in the form of a flat plate or a pellet having a triangular plane, for example, a regular triangular plane.
  • the pellet 5200 is a flat or pellet-like sputtered particle having a hexagonal plane, for example, a regular hexagonal plane.
  • the shape of the pellet 5200 is not limited to a triangle or a hexagon.
  • the thickness of the pellet 5200 is determined according to the type of deposition gas.
  • the pellet 5200 has a thickness of 0.4 nm to 1 nm, preferably 0.6 nm to 0.8 nm.
  • the pellet 5200 has a width of 1 nm to 3 nm, preferably 1.2 nm to 2.5 nm.
  • the ion 5201 is caused to collide with the target 5230 including an In-M-Zn oxide. Then, the pellet 5200 having three layers of an M—Zn—O layer, an In—O layer, and an M—Zn—O layer is peeled off.
  • the particles 5203 are also ejected from the target 5230 as the pellet 5200 is peeled off.
  • a particle 5203 has an aggregate of one atom or several atoms. Therefore, the particles 5203 can also be referred to as atomic particles.
  • the surface When the pellet 5200 passes through the plasma 5240, the surface may be negatively or positively charged.
  • the pellet 5200 may receive a negative charge from O 2 ⁇ in the plasma 5240.
  • oxygen atoms on the surface of the pellet 5200 may be negatively charged.
  • the pellet 5200 may grow by being combined with indium, the element M, zinc, oxygen, or the like in the plasma 5240 when passing through the plasma 5240.
  • the pellets 5200 and the particles 5203 that have passed through the plasma 5240 reach the surface of the substrate 5220. Note that part of the particles 5203 has a small mass and may be discharged to the outside by a vacuum pump or the like.
  • the first pellet 5200 is deposited on the substrate 5220. Since the pellet 5200 has a flat plate shape, the pellet 5200 is deposited with the planar side facing the surface of the substrate 5220 (see FIG. 40A). At this time, the charge on the surface of the pellet 5200 on the substrate 5220 side is released through the substrate 5220.
  • the second pellet 5200 reaches the substrate 5220. At this time, since the surface of the first pellet 5200 and the surface of the second pellet 5200 are charged, forces that repel each other are generated (see FIG. 40B).
  • the second pellet 5200 is deposited on the surface of the substrate 5220 slightly away from the first pellet 5200 (see FIG. 40C).
  • innumerable pellets 5200 are deposited on the surface of the substrate 5220 by a thickness corresponding to one layer.
  • a region where the pellet 5200 is not deposited is generated between the pellet 5200 and another pellet 5200.
  • the particle 5203 reaches the surface of the substrate 5220 (see FIG. 40D).
  • the particles 5203 cannot be deposited on an active region such as the surface of the pellet 5200. Therefore, the pellet 5200 is deposited so as to fill an undeposited region. Then, the particles 5203 grow in the horizontal direction between the pellets 5200 (also referred to as lateral growth), whereby the pellets 5200 are connected. In this manner, the particles 5203 are deposited until a region where the pellet 5200 is not deposited is filled.
  • This mechanism is similar to the deposition mechanism of the atomic layer deposition (ALD) method.
  • one of the particles 5203 is bonded to one side surface of the first M-Zn-O layer.
  • one particle 5203 is bonded to one side surface of the In—O layer.
  • FIG. 41C there is a case where one particle 5203 is bonded and bonded to one side surface of the second M-Zn-O layer (second mechanism). Note that FIG. 41A, FIG. 41B, and FIG. 41C may be connected by simultaneous occurrence (third mechanism).
  • the above three types are considered as the mechanism of the lateral growth of the particles 5203 between the pellets 5200.
  • the particles 5203 grow laterally between the pellets 5200 by other mechanisms.
  • the formation of crystal grain boundaries is suppressed by filling the spaces between the plurality of pellets 5200 while laterally growing the particles 5203.
  • the particles 5203 smoothly connect between the plurality of pellets 5200, different crystal structures are formed from single crystals and polycrystals.
  • a crystal structure having strain is formed between minute crystal regions (pellets 5200).
  • the region between the crystal regions is a distorted crystal region, it is considered inappropriate to refer to the region as an amorphous structure.
  • a first layer having the same thickness as the pellet 5200 is formed.
  • a new first pellet 5200 is deposited on the first layer.
  • a second layer is then formed. Further, by repeating this, a thin film structure having a stacked body is formed (see FIG. 38D).
  • the manner in which the pellets 5200 are deposited also varies depending on the surface temperature of the substrate 5220 and the like.
  • the pellet 5200 undergoes migration on the surface of the substrate 5220.
  • the proportion of the pellet 5200 and another pellet 5200 that are connected without the particle 5203 interposed therebetween increases, so that a CAAC-OS with high orientation is obtained.
  • the surface temperature of the substrate 5220 in forming the CAAC-OS is 100 ° C. or higher and lower than 500 ° C., preferably 140 ° C. or higher and lower than 450 ° C., more preferably 170 ° C. or higher and lower than 400 ° C. Accordingly, it can be seen that even when a large-area substrate of the eighth generation or higher is used as the substrate 5220, warping or the like hardly occurs.
  • the pellet 5200 when the surface temperature of the substrate 5220 is low, the pellet 5200 is less likely to cause migration on the surface of the substrate 5220. As a result, the pellets 5200 are stacked to form an nc-OS (nanocrystalline Oxide Semiconductor) with low orientation (see FIG. 42). In the nc-OS, since the pellet 5200 is negatively charged, the pellet 5200 may be deposited at a constant interval. Therefore, although the orientation is low, a slight regularity results in a dense structure as compared with an amorphous oxide semiconductor.
  • nc-OS nanocrystalline Oxide Semiconductor
  • one large pellet may be formed when the gap between pellets is extremely small.
  • the inside of one large pellet has a single crystal structure.
  • the size of the pellet may be 10 nm to 200 nm, 15 nm to 100 nm, or 20 nm to 50 nm when viewed from above.
  • the pellet 5200 is deposited on the surface of the substrate 5220 by the above model. Even when the formation surface does not have a crystal structure, a CAAC-OS film can be formed, which indicates that the growth mechanism is different from that of epitaxial growth.
  • the CAAC-OS and the nc-OS can form a film evenly even when the glass substrate has a large area.
  • the CAAC-OS can be formed even when the surface of the substrate 5220 (formation surface) has an amorphous structure (eg, amorphous silicon oxide).
  • the pellets 5200 are arranged along the shape.
  • FIG. 43 is a top view illustrating an example of the display device.
  • a display device 700 illustrated in FIG. 43 includes a pixel portion 702 provided over a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 provided over the first substrate 701, a pixel portion 702,
  • the sealant 712 is disposed so as to surround the source driver circuit portion 704 and the gate driver circuit portion 706, and the second substrate 705 is provided so as to face the first substrate 701.
  • the first substrate 701 and the second substrate 705 are sealed with a sealant 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed with the first substrate 701, the sealant 712, and the second substrate 705.
  • a display element is provided between the first substrate 701 and the second substrate 705.
  • the display device 700 is electrically connected to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 in a region different from the region surrounded by the sealant 712 on the first substrate 701.
  • a connected FPC terminal portion 708 FPC: Flexible printed circuit
  • an FPC 716 is connected to the FPC terminal portion 708, and various signals are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 by the FPC 716.
  • a signal line 710 is connected to each of the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708.
  • Various signals and the like supplied by the FPC 716 are supplied to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 through the signal line 710.
  • a plurality of gate driver circuit portions 706 may be provided in the display device 700.
  • the display device 700 an example in which the source driver circuit portion 704 and the gate driver circuit portion 706 are formed over the same first substrate 701 as the pixel portion 702 is shown; however, the display device 700 is not limited to this structure.
  • only the gate driver circuit portion 706 may be formed on the first substrate 701, or only the source driver circuit portion 704 may be formed on the first substrate 701.
  • a substrate on which a source driver circuit, a gate driver circuit, or the like is formed for example, a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film
  • a connection method of a separately formed drive circuit board is not particularly limited, and a COG (Chip On Glass) method, a wire bonding method, or the like can be used.
  • the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display device 700 include a plurality of transistors, and the transistor of one embodiment of the present invention can be used.
  • the display device 700 can include various elements.
  • the element include a liquid crystal element, an EL (electroluminescence) element (an EL element including an organic substance and an inorganic substance, an organic EL element, an inorganic EL element), an LED (white LED, red LED, green LED, blue LED, etc.), Display elements using transistors (transistors that emit light in response to current), electron-emitting devices, electronic ink, electrophoretic devices, grating light valves (GLV), plasma displays (PDP), and MEMS (micro electro mechanical systems) , Digital micromirror device (DMD), DMS (digital micro shutter), MIRASOL (registered trademark), IMOD (interference modulation) element, shutter type MEMS display element, optical interference type MEMS display element, elect Wetting element, a piezoelectric ceramic display, display using carbon nanotubes, such as, contrast, brightness, reflectance, etc.
  • EL electroluminescence
  • LED white LED, red LED, green LED, blue LED, etc.
  • An example of a display device using an EL element is an EL display.
  • a display device using an electron-emitting device there is a field emission display (FED), a SED type flat display (SED: Surface-conduction Electron-emitter Display), or the like.
  • FED field emission display
  • SED SED type flat display
  • a display device using a liquid crystal element there is a liquid crystal display (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, a projection liquid crystal display) and the like.
  • An example of a display device using electronic ink or an electrophoretic element is electronic paper.
  • part or all of the pixel electrode may have a function as a reflective electrode.
  • part or all of the pixel electrode may have aluminum, silver, or the like.
  • a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.
  • the color elements controlled by the pixels when performing color display are not limited to three colors of RGB (R represents red, G represents green, and B represents blue).
  • RGB red
  • G represents green
  • B represents blue
  • it may be composed of four pixels: an R pixel, a G pixel, a B pixel, and a W (white) pixel.
  • one color element may be configured by two colors of RGB, and two different colors may be selected and configured depending on the color element.
  • one or more colors such as yellow, cyan, and magenta may be added to RGB.
  • the size of the display area may be different for each dot of the color element.
  • the disclosed invention is not limited to a display device for color display, and can be applied to a display device for monochrome display.
  • a colored layer (also referred to as a color filter) may be used to display a full color display device using white light (W) in a backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, or the like).
  • white light W
  • a backlight organic EL element, inorganic EL element, LED, fluorescent lamp, or the like.
  • red (R), green (G), blue (B), yellow (Y), and the like can be used in appropriate combination for the colored layer.
  • the colored layer the color reproducibility can be increased as compared with the case where the colored layer is not used.
  • white light in a region having no colored layer may be directly used for display by arranging a region having a colored layer and a region having no colored layer.
  • a decrease in luminance due to the colored layer can be reduced during bright display, and power consumption can be reduced by about 20% to 30%.
  • a self-luminous element such as an organic EL element or an inorganic EL element
  • R, G, B, Y, and white (W) may be emitted from elements having respective emission colors.
  • W white
  • power consumption may be further reduced as compared with the case where a colored layer is used.
  • FIGS. 44 is a cross-sectional view taken along one-dot chain line QR shown in FIG. 43 and has a configuration using an EL element as a display element.
  • a display device 700 illustrated in FIG. 44 includes a lead wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. Further, the lead wiring portion 711 includes a signal line 710. In addition, the pixel portion 702 includes a transistor 750 and a capacitor 790. In addition, the source driver circuit portion 704 includes a transistor 752.
  • the above-described transistor can be used.
  • a transistor including an oxide semiconductor film which is highly purified and suppresses formation of oxygen vacancies can be used.
  • the transistor can reduce a current value in an off state (off-state current value). Therefore, the holding time of an electric signal such as an image signal can be increased, and the writing interval can be set longer in the power-on state. Therefore, since the frequency of the refresh operation can be reduced, there is an effect of suppressing power consumption.
  • the transistor exemplified in the above embodiment can be used as the transistor in the pixel portion.
  • a transistor used for the driver circuit portion it is preferable to use a Lov transistor having higher field effect mobility. Note that a Loff type transistor may be used for the driver circuit portion, or a Loff type transistor and a Lov type transistor may be mixed.
  • a Loff transistor and a Lov transistor can be separately formed by changing a pattern of a first gate electrode, a second gate electrode, a semiconductor film, a source electrode, a drain electrode, or the like.
  • the drive transistor, the selection transistor, the switching transistor, and the driver transistor used for the drive circuit portion can be formed on the same substrate. In other words, it is not necessary to use a semiconductor device formed of a silicon wafer or the like as a separate driving circuit, so that the number of parts of the display device can be reduced. Further, by using a switching transistor that functions as a switch in the pixel portion or a Loff type transistor as a selection transistor, parasitic capacitance can be reduced, so that the time constant during the switching operation of the pixel portion can be reduced. Accordingly, a display device with a large panel size or high definition can be manufactured.
  • the capacitor 790 has a structure having a dielectric between a pair of electrodes. More specifically, a conductive film formed in the same step as the conductive film functioning as the first gate electrode of the transistor 750 is used as one electrode of the capacitor 790, and a transistor is used as the other electrode of the capacitor 790. A conductive film functioning as a source electrode and a drain electrode 750 is used. As the dielectric sandwiched between the pair of electrodes, an insulating film functioning as a first gate insulating film of the transistor 750 is used.
  • insulating films 764, 766, 768, an oxide semiconductor film 767, and a planarization insulating film 770 are provided over the transistor 750, the transistor 752, and the capacitor 790.
  • the insulating films 764, 766, and 768 can be formed using a material and a manufacturing method similar to those of the insulating films 114, 116, and 118 described in the above embodiment, respectively.
  • the oxide semiconductor film 767 can be formed using a material and a manufacturing method similar to those of the oxide semiconductor film 117 described in the above embodiment.
  • an organic material having heat resistance such as polyimide resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin, or epoxy resin can be used. Note that the planarization insulating film 770 may be formed by stacking a plurality of insulating films formed using these materials. Further, the planarization insulating film 770 may be omitted.
  • the signal line 710 is formed in the same process as the conductive film functioning as the source electrode and the drain electrode of the transistors 750 and 752.
  • the signal line 710 may be a conductive film formed in a step different from that of the source and drain electrodes of the transistors 750 and 752, for example, a conductive film functioning as a first gate electrode.
  • a material containing a copper element is used as the signal line 710, signal delay due to wiring resistance is small and display on a large screen is possible.
  • the FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716.
  • the connection electrode 760 is formed in the same step as the conductive film functioning as the source and drain electrodes of the transistors 750 and 752.
  • the connection electrode 760 is electrically connected to a terminal included in the FPC 716 through an anisotropic conductive film 780.
  • first substrate 701 and the second substrate 705 for example, glass substrates can be used.
  • a flexible substrate may be used as the first substrate 701 and the second substrate 705.
  • the flexible substrate include a plastic substrate.
  • a structure body 778 is provided between the first substrate 701 and the second substrate 705.
  • the structure body 778 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the first substrate 701 and the second substrate 705.
  • a spherical spacer may be used as the structure body 778.
  • the structure body 778 is provided on the first substrate 701 side; however, the present invention is not limited to this.
  • a structure in which the structure body 778 is provided on the second substrate 705 side or a structure in which the structure body 778 is provided on both the first substrate 701 and the second substrate 705 may be employed.
  • a light-blocking film 738 functioning as a black matrix, a colored film 736 functioning as a color filter, and an insulating film 734 in contact with the light-blocking film 738 and the colored film 736 are provided.
  • a display device 700 illustrated in FIG. 44 includes a light-emitting element 782.
  • the light-emitting element 782 includes a conductive film 784, an EL layer 786, and a conductive film 788.
  • the display device 700 illustrated in FIG. 44 can display an image when the EL layer 786 included in the light-emitting element 782 emits light.
  • the conductive film 784 is connected to a conductive film functioning as a source electrode and a drain electrode of the transistor 750.
  • the conductive film 784 is formed over the planarization insulating film 770 and functions as a pixel electrode, that is, one electrode of a display element.
  • a conductive film that transmits visible light or a conductive film that reflects visible light can be used.
  • a material containing one kind selected from indium (In), zinc (Zn), and tin (Sn) may be used.
  • As the conductive film having reflectivity in visible light for example, a material containing aluminum or silver is preferably used.
  • an insulating film 730 is provided over the planarization insulating film 770 and the conductive film 784.
  • the insulating film 730 covers part of the conductive film 784.
  • the light-emitting element 782 has a top emission structure. Therefore, the conductive film 788 has a light-transmitting property and transmits light emitted from the EL layer 786.
  • the top emission structure is illustrated, but is not limited thereto. For example, a bottom emission structure in which light is emitted to the conductive film 784 side or a dual emission structure in which light is emitted to both the conductive film 784 and the conductive film 788 can be used.
  • a colored film 736 is provided at a position overlapping with the light emitting element 782, and a light shielding film 738 is provided at a position overlapping with the insulating film 730, the lead wiring portion 711, and the source driver circuit portion 704. Further, the coloring film 736 and the light shielding film 738 are covered with an insulating film 734. A space between the light emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that in the display device 700 illustrated in FIG. 44, the structure in which the colored film 736 is provided is illustrated, but the present invention is not limited to this. For example, in the case where the EL layer 786 is formed by separate coating, the coloring film 736 may not be provided.
  • a Loff transistor is illustrated as the transistor 750 in which the conductive film 784 of the light-emitting element 782 is connected to one of the source electrode and the drain electrode.
  • a Lov transistor may be used as the transistor 750.
  • the light emitting element and the Loff type transistor are connected, but the pixel configuration examples 1, 2, and 3 according to the first embodiment are modified example 1 In the configuration examples 4 and 5, the light emitting element and the Lov transistor are connected.
  • a display device illustrated in FIG. 45A includes a region having a pixel of a display element (hereinafter referred to as a pixel portion 502) and a circuit portion (hereinafter referred to as a pixel portion 502) that is disposed outside the pixel portion 502 and has a circuit for driving the pixel. , A driver circuit portion 504), a circuit having a function of protecting an element (hereinafter referred to as a protection circuit 506), and a terminal portion 507. Note that the protection circuit 506 may be omitted.
  • the pixel portion 502 includes pixels 501 for driving a plurality of display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more). Further, the pixel described in Embodiment 1 can be used as the pixel 501.
  • the driving circuit unit 504 outputs a signal for selecting a pixel (scanning signal) (hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) for driving a display element of the pixel (hereinafter referred to as a data signal). And a driver circuit such as a source driver 504b).
  • Part or all of the peristaltic circuit portion 504 is preferably formed over the same substrate as the pixel portion 502. Thereby, the number of parts and the number of terminals can be reduced.
  • part or all of the driver circuit portion 504 is formed by COG or TAB (Tape Automated Bonding). Can be implemented.
  • the gate driver 504a includes a shift register and the like.
  • the gate driver 504a receives a signal for driving the shift register via the terminal portion 507, and outputs a signal.
  • the gate driver 504a receives a start pulse signal, a clock signal, and the like and outputs a pulse signal.
  • the gate driver 504a has a function of controlling the potential of a wiring to which a scan signal is supplied (hereinafter referred to as scan lines GL_1 to GL_X).
  • scan lines GL_1 to GL_X a plurality of gate drivers 504a may be provided, and the scanning lines GL_1 to GL_X may be divided and controlled by the plurality of gate drivers 504a.
  • the gate driver 504a has a function of supplying an initialization signal.
  • the present invention is not limited to this, and the gate driver 504a can supply another signal.
  • FIG. 45A illustrates an example in which one pixel and two wirings are electrically connected, but any number of wirings that are electrically connected to one pixel may be used. For example, three wirings, three wirings, five wirings, or six wirings may be electrically connected. Further, a configuration in which seven or more wirings are electrically connected to one pixel may be employed. The number of wirings electrically connected to one pixel differs depending on the configuration of the pixel.
  • the source driver 504b includes a shift register and the like. In addition to a signal for driving the shift register, the source driver 504b receives a signal (image signal) as a source of a data signal through the terminal portion 507.
  • the source driver 504b has a function of generating a data signal to be written to the pixel 501 based on the image signal.
  • the source driver 504b has a function of controlling output of a data signal in accordance with a pulse signal obtained by inputting a start pulse, a clock signal, or the like.
  • the source driver 504b has a function of controlling the potential of a wiring to which a data signal is supplied (hereinafter referred to as data lines DL_1 to DL_Y).
  • the source driver 504b has a function of supplying an initialization signal.
  • the present invention is not limited to this, and the source driver 504b can supply another signal.
  • the source driver 504b is configured using, for example, a plurality of analog switches.
  • the source driver 504b can output a signal obtained by time-dividing the image signal as a data signal by sequentially turning on the plurality of analog switches. Further, the source driver 504b may be configured using a shift register or the like.
  • Each of the plurality of pixels 501 receives a pulse signal through one of a plurality of scanning lines GL to which a scanning signal is applied, and receives a data signal through one of the plurality of data lines DL to which a data signal is applied. Is done. Also.
  • Each of the plurality of pixels 501 is controlled to write and hold data of a data signal by the gate driver 504a.
  • the pixel 501 in the m-th row and the n-th column receives a pulse signal from the gate driver 504a via the scanning line GL_m (m is a natural number equal to or less than X), and the data line DL_n (n is a value corresponding to the potential of the scanning line GL_m).
  • a data signal is input from the source driver 504b via a natural number less than or equal to Y.
  • the protection circuit 506 illustrated in FIG. 45A is connected to, for example, the scanning line GL that is a wiring between the gate driver 504a and the pixel 501.
  • the protection circuit 506 is connected to the data line DL that is a wiring between the source driver 504 b and the pixel 501.
  • the protection circuit 506 can be connected to a wiring between the gate driver 504 a and the terminal portion 507.
  • the protection circuit 506 can be connected to a wiring between the source driver 504 b and the terminal portion 507.
  • the terminal portion 507 is a portion where a terminal for inputting a power supply, a control signal, and an image signal from an external circuit to the display device is provided.
  • the protection circuit 506 is a circuit that brings a wiring into a conductive state when a potential outside a certain range is applied to the wiring to which the protection circuit 506 is connected.
  • the configuration of the protection circuit 506 is not limited thereto, and for example, a configuration in which the protection circuit 506 is connected to the gate driver 504a or a configuration in which the protection circuit 506 is connected to the source driver 504b may be employed. Alternatively, the protection circuit 506 may be connected to the terminal portion 507.
  • FIG. 45A illustrates an example in which the driver circuit portion 504 is formed using the gate driver 504a and the source driver 504b; however, the present invention is not limited to this structure.
  • the gate driver 504a may be formed, and a substrate on which a separately prepared source driver circuit is formed (for example, a driver circuit substrate formed using a single crystal semiconductor film or a polycrystalline semiconductor film) may be mounted.
  • the pixel illustrated in Embodiment 1 can be used. Note that the number of wirings that electrically connect the gate driver 504a or the source driver 504b and the pixel varies with the configuration of each pixel.
  • the pixel 501 can have a structure illustrated in FIG.
  • a pixel 501 illustrated in FIG. 45B includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572.
  • transistors 552 and 554, a capacitor 562, and a light-emitting element 572 For example, a Loff transistor can be used as the transistor 552, and a Lov transistor can be used as the transistor 554.
  • the transistor 552 can be referred to as a selection transistor, and the transistor 554 can be referred to as a drive transistor.
  • One of a source electrode and a drain electrode of the transistor 552 is electrically connected to a wiring to which a data signal is supplied (hereinafter referred to as a data line DL_n). Further, the gate electrode of the transistor 552 is electrically connected to a wiring to which a gate signal is supplied (hereinafter referred to as a scanning line GL_m).
  • the transistor 552 has a function of controlling data writing of the data signal by being turned on or off.
  • One of the pair of electrodes of the capacitor 562 is electrically connected to a wiring to which a potential is applied (hereinafter referred to as a potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552. Is done.
  • the potential supply line VL_a may be referred to as a current supply line.
  • the capacitor 562 functions as a storage capacitor that stores written data.
  • One of an anode and a cathode of the light-emitting element 572 is electrically connected to the potential supply line VL_b, and the other is electrically connected to one of a source electrode and a drain electrode of the transistor 554.
  • the other of the source electrode and the drain electrode of the transistor 554 is electrically connected to the potential supply line VL_a. Further, the gate electrode of the transistor 554 is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.
  • the light-emitting element 572 for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used.
  • the light-emitting element 572 is not limited thereto, and an inorganic EL element made of an inorganic material may be used.
  • one of the potential supply line VL_a and the potential supply line VL_b is supplied with the high power supply potential VDD, and the other is supplied with the low power supply potential VSS.
  • the pixels 501 in each row are sequentially selected by the gate driver 504a illustrated in FIG. 45A, the transistors 552 are turned on, and data signal data is written.
  • the pixel 501 in which data is written is in a holding state when the transistor 552 is turned off. Further, the amount of current flowing between the source electrode and the drain electrode of the transistor 554 is controlled in accordance with the potential of the written data signal, and the light-emitting element 572 emits light with luminance corresponding to the amount of flowing current. By sequentially performing this for each row, an image can be displayed.
  • a parasitic capacitance C GD is generated in a region 580 where the GL_m line and the DL_n line overlap with each other as illustrated in FIG. Similarly to the parasitic capacitance of the transistor, if the parasitic capacitance CGD is large, the rise time is delayed, so that it is difficult to increase the definition of the panel. Therefore, it is preferable to reduce the capacitance between the GL_m line and the DL_n line.
  • an insulating film in the same layer as the insulating film 106 is interposed between the GL_m line and the DL_n line.
  • 106A and an insulating film 107A of the same layer as the insulating film 107 exist. It is preferable to insert an insulating film between the GL_m line and the DL_n line because the parasitic capacitance of the transistor can be reduced.
  • FIG. 46A shows a top view of the vicinity of the region 580 in FIG.
  • a cross-sectional view along Z1-Z2 in FIG. 46A is shown in FIG.
  • FIGS. 46A and 46B when the insulating film 106A, the insulating film 107A, and the insulating film 121 are stacked between the GL_m line and the DL_n line, the GL_m line and the DL_n line are insulated.
  • the thickness of the insulating film between the GL_m line and the DL_n line becomes thicker and the parasitic capacitance C GD between the GL_m line and the DL_n line becomes smaller than in the case of only the film 106A and the insulating film 107A.
  • a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like can be used as the insulating film 121.
  • the insulating film 121 can be formed by a sputtering method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like), an MBE method, an ALD method, a PLD method, or the like.
  • a CVD method including a thermal CVD method, an MOCVD method, a PECVD method, or the like
  • MBE method an MBE method
  • ALD method a PLD method
  • PLD method a PLD method, or the like.
  • a CVD method preferably a PECVD method, because the coverage can be improved.
  • thermal CVD, MOCVD or ALD is preferred.
  • a silicon carbonitride film can be used as the insulating film 121.
  • SiCN film silicon carbonitride film
  • USG Undoped Silicate Glass
  • BPSG Borosphorus Silicate Glass
  • BSG Borosicate Glass
  • USG, BPSG, and the like may be formed using an atmospheric pressure CVD method.
  • HSQ hydrogen silsesquioxane
  • a coating method for example, HSQ (hydrogen silsesquioxane) or the like may be formed using a coating method.
  • the insulating film 121 may be a stack of two or more layers.
  • USG may be stacked over an insulating film containing nitrogen and silicon.
  • a display module 8000 shown in FIG. 47 includes a touch panel 8004 connected to the FPC 8003, a display panel 8006 connected to the FPC 8005, a backlight 8007, a frame 8009, a printed circuit board 8010, and a battery between the upper cover 8001 and the lower cover 8002. 8011.
  • the display device of one embodiment of the present invention can be used for the display panel 8006, for example.
  • the shapes and dimensions of the upper cover 8001 and the lower cover 8002 can be changed as appropriate in accordance with the sizes of the touch panel 8004 and the display panel 8006.
  • a resistive touch panel or a capacitive touch panel can be used by being superimposed on the display panel 8006.
  • the counter substrate (sealing substrate) of the display panel 8006 can have a touch panel function.
  • an optical sensor can be provided in each pixel of the display panel 8006 to provide an optical touch panel.
  • the backlight 8007 has a light source 8008. Note that although the structure in which the light source 8008 is provided over the backlight 8007 is illustrated in FIG. For example, a light source 8008 may be provided at the end of the backlight 8007 and a light diffusing plate may be used. Note that in the case of using a self-luminous light-emitting element such as an organic EL element, or in the case of a reflective panel or the like, the backlight 8007 may not be provided.
  • the frame 8009 has a function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed board 8010 in addition to a protective function of the display panel 8006.
  • the frame 8009 may have a function as a heat sink.
  • the printed board 8010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal.
  • a power supply for supplying power to the power supply circuit an external commercial power supply may be used, or a power supply using a battery 8011 provided separately may be used.
  • the battery 8011 can be omitted when a commercial power source is used.
  • the display module 8000 may be additionally provided with a member such as a polarizing plate, a retardation plate, or a prism sheet.
  • 48A to 48G illustrate electronic devices. These electronic devices include a housing 9000, a display portion 9001, a speaker 9003, operation keys 9005 (including a power switch or operation switch), a connection terminal 9006, and a sensor 9007 (force, displacement, position, speed, acceleration, angular velocity, Includes functions to measure rotation speed, distance, light, liquid, magnetism, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared ), A microphone 9008, and the like.
  • operation keys 9005 including a power switch or operation switch
  • connection terminal 9006 includes a connection terminal 9006
  • a sensor 9007 force, displacement, position, speed, acceleration, angular velocity, Includes functions to measure rotation speed, distance, light, liquid, magnetism, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared
  • a microphone 9008 and the
  • the electronic devices illustrated in FIGS. 48A to 48G can have a variety of functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for controlling processing by various software (programs), Wireless communication function, function for connecting to various computer networks using the wireless communication function, function for transmitting or receiving various data using the wireless communication function, and reading and displaying the program or data recorded on the recording medium It can have a function of displaying on the section. Note that functions that the electronic device illustrated in FIGS. 48A to 48G can have are not limited to these, and can have various functions. Although not illustrated in FIGS.
  • the electronic device may have a plurality of display portions.
  • the electronic device is equipped with a camera, etc., to capture still images, to capture moving images, to store captured images on a recording medium (externally or built into the camera), and to display captured images on the display unit And the like.
  • FIGS. 48A to 48G Details of the electronic devices illustrated in FIGS. 48A to 48G are described below.
  • FIG. 48A is a perspective view showing a portable information terminal 9100.
  • FIG. A display portion 9001 included in the portable information terminal 9100 has flexibility. Therefore, the display portion 9001 can be incorporated along the curved surface of the curved housing 9000. Further, the display portion 9001 includes a touch sensor and can be operated by touching the screen with a finger, a stylus, or the like. For example, an application can be activated by touching an icon displayed on the display unit 9001.
  • FIG. 48B is a perspective view showing the portable information terminal 9101.
  • the portable information terminal 9101 has one or a plurality of functions selected from, for example, a telephone, a notebook, an information browsing device, or the like. Specifically, it can be used as a smartphone. Note that the portable information terminal 9101 is illustrated with the speaker 9003, the connection terminal 9006, the sensor 9007, and the like omitted, but can be provided at the same position as the portable information terminal 9100 illustrated in FIG. Further, the portable information terminal 9101 can display characters and image information on the plurality of surfaces. For example, three operation buttons 9050 (also referred to as operation icons or simply icons) can be displayed on one surface of the display portion 9001.
  • three operation buttons 9050 also referred to as operation icons or simply icons
  • information 9051 indicated by a broken-line rectangle can be displayed on another surface of the display portion 9001.
  • a display for notifying an incoming call such as an e-mail, SNS (social networking service), a telephone call, a title such as an e-mail or SNS, a sender name such as an e-mail or SNS, a date and time, and a time , Battery level, antenna reception strength and so on.
  • an operation button 9050 or the like may be displayed instead of the information 9051 at a position where the information 9051 is displayed.
  • FIG. 48C is a perspective view showing the portable information terminal 9102.
  • the portable information terminal 9102 has a function of displaying information on three or more surfaces of the display portion 9001.
  • information 9052, information 9053, and information 9054 are displayed on different planes.
  • the user of the portable information terminal 9102 can check the display (information 9053 here) in a state where the portable information terminal 9102 is stored in the chest pocket of clothes.
  • the telephone number or name of the caller of the incoming call is displayed at a position where it can be observed from above portable information terminal 9102.
  • the user can check the display and determine whether to receive a call without taking out the portable information terminal 9102 from the pocket.
  • FIG. 48D is a perspective view showing a wristwatch-type portable information terminal 9200.
  • the portable information terminal 9200 can execute various applications such as a mobile phone, electronic mail, text browsing and creation, music playback, Internet communication, and computer games.
  • the display portion 9001 is provided with a curved display surface, and can perform display along the curved display surface.
  • the portable information terminal 9200 can execute short-range wireless communication with a communication standard. For example, it is possible to talk hands-free by communicating with a headset capable of wireless communication.
  • the portable information terminal 9200 includes a connection terminal 9006 and can directly exchange data with other information terminals via a connector. Charging can also be performed through the connection terminal 9006. Note that the charging operation may be performed by wireless power feeding without using the connection terminal 9006.
  • FIG. 48E, 48F, and 48G are perspective views showing a foldable portable information terminal 9201.
  • FIG. 48E is a perspective view of a state in which the portable information terminal 9201 is expanded
  • FIG. 48F is a state in the middle of changing from one of the expanded state or the folded state of the portable information terminal 9201 to the other.
  • FIG. 48G is a perspective view of the portable information terminal 9201 folded.
  • the portable information terminal 9201 is excellent in portability in the folded state, and in the expanded state, the portable information terminal 9201 is excellent in display listability due to a seamless wide display area.
  • a display portion 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by a hinge 9055.
  • the portable information terminal 9201 By bending between the two housings 9000 via the hinge 9055, the portable information terminal 9201 can be reversibly deformed from the expanded state to the folded state.
  • the portable information terminal 9201 can be bent with a curvature radius of 1 mm to 150 mm.
  • 49A to 49G illustrate electronic devices. These electronic devices include a housing 5000, a display portion 5001, a speaker 5003, an LED lamp 5004, operation keys 5005 (including a power switch or operation switch), a connection terminal 5006, a sensor 5007 (force, displacement, position, speed, Measure acceleration, angular velocity, number of rotations, distance, light, liquid, magnetism, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell or infrared A microphone 5008, and the like.
  • operation keys 5005 including a power switch or operation switch
  • connection terminal 5006 a sensor 5007 (force, displacement, position, speed, Measure acceleration, angular velocity, number of rotations, distance, light, liquid, magnetism, temperature, chemical, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, smell or infrared A microphone 5008, and the like.
  • FIG. 49A illustrates a mobile computer which can include a switch 5009, an infrared port 5010, and the like in addition to the above components.
  • FIG. 49B illustrates a portable image playback device (eg, a DVD playback device) provided with a recording medium, which includes a second display portion 5002, a recording medium reading portion 5011, and the like in addition to the above components. it can.
  • FIG. 49C illustrates a goggle type display which can include a second display portion 5002, a support portion 5012, an earphone 5013, and the like in addition to the above components.
  • FIG. 49D illustrates a portable game machine that can include the memory medium reading portion 5011 and the like in addition to the above objects.
  • FIG. 49B illustrates a portable image playback device (eg, a DVD playback device) provided with a recording medium, which includes a second display portion 5002, a recording medium reading portion 5011, and the like in addition to the above components. it can.
  • FIG. 49C
  • FIG. 49E illustrates a digital camera with a television receiving function, which can include an antenna 5014, a shutter button 5015, an image receiving portion 5016, and the like in addition to the above objects.
  • FIG. 49F illustrates a portable game machine that can include the second display portion 5002, the recording medium reading portion 5011, and the like in addition to the above objects.
  • FIG. 49G illustrates a portable television receiver that can include a charger 5017 and the like capable of transmitting and receiving signals in addition to the above components.
  • the electronic devices illustrated in FIGS. 49A to 49G can have a variety of functions. For example, a function for displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function for displaying a calendar, date or time, a function for controlling processing by various software (programs), Wireless communication function, function for connecting to various computer networks using the wireless communication function, function for transmitting or receiving various data using the wireless communication function, and reading and displaying programs or data recorded on the recording medium It can have a function of displaying on the section. Further, in an electronic device having a plurality of display units, one display unit mainly displays image information and another one display unit mainly displays character information, or the plurality of display units consider parallax.
  • a function of displaying a three-dimensional image, etc. by displaying the obtained image. Furthermore, in an electronic device having an image receiving unit, a function for capturing a still image, a function for capturing a moving image, a function for correcting a captured image automatically or manually, and a captured image on a recording medium (externally or incorporated in a camera) A function of saving, a function of displaying a photographed image on a display portion, and the like can be provided. Note that the functions of the electronic devices illustrated in FIGS. 49A to 49G are not limited to these, and can have various functions.
  • the electronic device described in this embodiment includes a display portion for displaying some information.
  • the display device described in Embodiments 4 and 5 can be applied to the display portion.
  • the electronic device described in this embodiment includes a display portion for displaying some information.

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Electroluminescent Light Sources (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

L'invention concerne un dispositif d'affichage présentant une excellente qualité d'affichage. Le dispositif d'affichage est pourvu d'un transistor de commutation, d'un transistor d'attaque, d'un élément électroluminescent, d'un élément capacitif, et d'une ligne d'alimentation en courant. Soit la source, soit le drain du transistor d'attaque est connecté(e) électriquement à l'élément électroluminescent, et l'autre élément parmi la source et le drain est connecté(e) électriquement à la ligne d'alimentation en courant. Dans le transistor d'attaque, un film semi-conducteur présente une région qui chevauche une première électrode de grille, et le film semi-conducteur chevauche une électrode de source dans une partie de ladite région et chevauche une électrode de drain dans une partie différente de ladite région. Dans le transistor de commutation, un film semi-conducteur présente une région qui chevauche une première électrode de grille, et le film semi-conducteur ne chevauche pas d'électrode de source dans ladite région et ne chevauche pas d'électrode de drain dans ladite région.
PCT/IB2016/052556 2015-05-14 2016-05-05 Dispositif d'affichage, module d'affichage et dispositif électronique WO2016181261A1 (fr)

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JP2018133508A (ja) * 2017-02-17 2018-08-23 株式会社半導体エネルギー研究所 半導体装置、及び半導体装置の作製方法
CN112086526A (zh) * 2020-09-01 2020-12-15 深圳市华星光电半导体显示技术有限公司 显示面板和显示装置
JP7523106B2 (ja) 2020-02-12 2024-07-26 深▲セン▼通鋭微電子技術有限公司 表示装置

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WO2013108327A1 (fr) * 2012-01-20 2013-07-25 パナソニック株式会社 Transistor en film mince
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JP2015046561A (ja) * 2012-11-28 2015-03-12 株式会社半導体エネルギー研究所 表示装置
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JP2015187695A (ja) * 2013-08-28 2015-10-29 株式会社半導体エネルギー研究所 表示装置

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JP2009193063A (ja) * 2008-01-15 2009-08-27 Semiconductor Energy Lab Co Ltd 表示装置及び電子機器
JP2010156962A (ja) * 2008-12-04 2010-07-15 Semiconductor Energy Lab Co Ltd 表示装置及びその駆動方法並びにそれらを用いた電子機器
JP2012256829A (ja) * 2010-12-09 2012-12-27 Semiconductor Energy Lab Co Ltd 光検出回路、入力装置、及び入出力装置
WO2013108327A1 (fr) * 2012-01-20 2013-07-25 パナソニック株式会社 Transistor en film mince
JP2015046561A (ja) * 2012-11-28 2015-03-12 株式会社半導体エネルギー研究所 表示装置
JP2015015459A (ja) * 2013-06-05 2015-01-22 株式会社半導体エネルギー研究所 表示装置
JP2015187695A (ja) * 2013-08-28 2015-10-29 株式会社半導体エネルギー研究所 表示装置
JP2015073094A (ja) * 2013-09-05 2015-04-16 株式会社半導体エネルギー研究所 コンタクト抵抗測定パターンおよび半導体装置

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JP2018133508A (ja) * 2017-02-17 2018-08-23 株式会社半導体エネルギー研究所 半導体装置、及び半導体装置の作製方法
JP7523106B2 (ja) 2020-02-12 2024-07-26 深▲セン▼通鋭微電子技術有限公司 表示装置
CN112086526A (zh) * 2020-09-01 2020-12-15 深圳市华星光电半导体显示技术有限公司 显示面板和显示装置
CN112086526B (zh) * 2020-09-01 2023-11-28 深圳市华星光电半导体显示技术有限公司 显示面板和显示装置

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