WO2016179596A1 - Low-stress low-hydrogen lpcvd silicon nitride - Google Patents

Low-stress low-hydrogen lpcvd silicon nitride Download PDF

Info

Publication number
WO2016179596A1
WO2016179596A1 PCT/US2016/031509 US2016031509W WO2016179596A1 WO 2016179596 A1 WO2016179596 A1 WO 2016179596A1 US 2016031509 W US2016031509 W US 2016031509W WO 2016179596 A1 WO2016179596 A1 WO 2016179596A1
Authority
WO
WIPO (PCT)
Prior art keywords
silicon nitride
nitride layer
substrate
microelectronic device
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2016/031509
Other languages
French (fr)
Inventor
Nicholas Stephen DELLAS
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Japan Ltd
Texas Instruments Inc
Original Assignee
Texas Instruments Japan Ltd
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Japan Ltd, Texas Instruments Inc filed Critical Texas Instruments Japan Ltd
Priority to JP2017558375A priority Critical patent/JP6931208B2/en
Priority to CN201680028363.3A priority patent/CN107533974B/en
Publication of WO2016179596A1 publication Critical patent/WO2016179596A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/118—Electrodes comprising insulating layers having particular dielectric or electrostatic properties, e.g. having static charges
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00642—Manufacture or treatment of devices or systems in or on a substrate for improving the physical properties of a device
    • B81C1/0065—Mechanical properties
    • B81C1/00666—Treatments for controlling internal stress or strain in MEMS structures
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
    • B81B3/0064—Constitution or structural means for improving or controlling the physical properties of a device
    • B81B3/0067—Mechanical properties
    • B81B3/0072—For controlling internal stress or strain in moving or flexible elements, e.g. stress compensating layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems ; Auxiliary parts of microstructural devices or systems
    • B81B7/0009—Structural features, others than packages, for protecting a device against environmental influences
    • B81B7/0022—Protection against electrostatic discharge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H10D62/824—Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H10P14/6682—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H10P95/904—Thermal treatments, e.g. annealing or sintering of Group III-V semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/43—Encapsulations, e.g. protective coatings characterised by their materials comprising oxides, nitrides or carbides, e.g. ceramics or glasses
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2203/00—Basic microelectromechanical structures
    • B81B2203/01—Suspended structures, i.e. structures allowing a movement
    • B81B2203/0127—Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0161—Controlling physical properties of the material
    • B81C2201/0163—Controlling internal stress of deposited layers
    • B81C2201/0166—Controlling internal stress of deposited layers by ion implantation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/0176—Chemical vapour Deposition
    • B81C2201/0177—Epitaxy, i.e. homo-epitaxy, hetero-epitaxy, GaAs-epitaxy
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174—Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/0181—Physical Vapour Deposition [PVD], i.e. evaporation, sputtering, ion plating or plasma assisted deposition, ion cluster beam technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0212—Manufacture or treatment of FETs having insulated gates [IGFET] using self-aligned silicidation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0184—Manufacturing their gate sidewall spacers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • This relates generally to microelectronic devices, and more particularly to silicon nitride layers in microelectronic devices.
  • silicon nitride layers are desirably formed, which simultaneously have low stress that is less than 1000 megapascals (MPa), and low hydrogen content that is less than 5 atomic percent.
  • Such films would be useful for a variety of microelectronic applications.
  • Silicon nitride films formed by plasma enhanced chemical vapor deposition (PECVD) may have low stress, but have high hydrogen content, above 15 atomic percent, which can cause reliability problems and poor etch resistance.
  • Films formed by low pressure chemical vapor deposition (LPCVD) have low hydrogen content, but high stress, above 1000 MPa, which can cause device performance problems.
  • a microelectronic device contains a high performance silicon nitride layer, which is stoichiometric within 2 atomic percent, has a low stress of 600 MPa to 1000 MPa, and has a low hydrogen content, less than 5 atomic percent.
  • the high performance silicon nitride layer is formed by an LPCVD process.
  • the LPCVD process uses ammonia and dichlorosilane gases in a ratio of 4 to 6, at a pressure of 150 millitorr to 250 millitorr, and at a temperature of 800°C to 820°C.
  • FIG. 1 depicts an LPCVD furnace in an example process of forming a high performance silicon nitride on microelectronic devices and FIG. 1A is an expanded view of the silicon nitride layer formed on the microelectronic devices within the furnace of FIG. 1.
  • FIG. 2 is a cross section of an example semiconductor device with a high performance silicon nitride layer.
  • FIG. 3 A and FIG. 3B are cross sections of the semiconductor device of FIG. 2, depicted in key stages of formation.
  • FIG. 4 is a cross section of an example integrated circuit with a high performance silicon nitride layer.
  • FIG. 5 A and FIG. 5B are cross sections of the integrated circuit of FIG. 4, depicted in key stages of fabrication.
  • FIG. 6A and FIG. 6B are cross sections of an example microelectronic mechanical system (MEMS) device with a high performance silicon nitride layer, depicted in key stages of fabrication.
  • MEMS microelectronic mechanical system
  • a high performance silicon nitride layer which is stoichiometric within 2 atomic percent, has a low stress of 600 MPa to 1000 MPa, and has a low hydrogen content, less than 5 atomic percent, is formed by an LPCVD process.
  • the LPCVD process uses ammonia and dichlorosilane gases in a ratio of 4 to 6, at a pressure of 150 millitorr to 250 millitorr, and at a temperature of 800°C to 820°C.
  • the combination of stoichiometry, low stress and low hydrogen content were not expected to be provided by the disclosed process conditions, and were discovered during investigations of LPCVD processes.
  • stoichiometric silicon nitride has a silicon:nitrogen atomic ratio of 3 :4.
  • FIG. 1 depicts an LPCVD furnace in an example process of forming a high performance silicon nitride on microelectronic devices.
  • the LPCVD furnace 100 holds the microelectronic devices 102 on substrates, such as semiconductor wafers, in a boat 104.
  • the boat 104 is held in a reaction chamber 106 of the LPCVD furnace 100.
  • the reaction chamber 106 is heated to a temperature of 800°C to 820°C by heating elements 108 of the LPCVD furnace 100 disposed around the reaction chamber 106.
  • Ammonia (NH 3 ) and dichlorosilane (DCS) gases are introduced into the reaction chamber 106 at a ratio of 4 to 6.
  • the high performance silicon nitride layer 112 is formed on the microelectronic devices 102 by reaction of nitrogen in the ammonia and silicon in the dichlorosilane. Formation of the high performance silicon nitride layer 112 is continued until a desired thickness is attained. Subsequently, flows of the ammonia and dichlorosilane are ended and the microelectronic devices 102 are extracted from the LPCVD furnace 100.
  • Formation of the high performance silicon nitride layer 112 by maintaining the temperature at 800°C to 820°C, the ratio of ammonia to dichlorosilane at 4 to 6, and the pressure at 150 millitorr to 250 millitorr advantageously provides a silicon:nitrogen atomic ratio within 2 percent of the ratio 3 :4, a low stress of 600 MPa to 1000 MPa, and a low hydrogen content of less than 5 atomic percent.
  • the high performance silicon nitride layer 112 may have an index of refraction of 2.0 to 2.1 as a result of being formed by the process described in reference to FIG. 1.
  • the high performance silicon nitride layer 112 may have a dielectric breakdown strength of greater than 12 megavolts per centimeter (MV/cm), which may advantageously contribute to higher reliability of the microelectronic devices 102.
  • MV/cm megavolts per centimeter
  • Increasing the ratio of ammonia to dichlorosilane reduces the stoichiometry and the dielectric breakdown strength, which may disadvantageous ⁇ contribute to lower reliability. Reducing the ratio of ammonia to dichlorosilane disadvantageously increases the stress. Reducing the temperature and increasing the pressure also disadvantageously increases the stress.
  • FIG. 2 is a cross section of an example semiconductor device with a high performance silicon nitride layer.
  • the semiconductor device 200 is formed on a semiconductor substrate 202, such as a stack gallium nitride and aluminum gallium nitride epitaxial layers, and possibly other III-V layers.
  • a cap layer 204 of gallium nitride is disposed on the substrate 202.
  • a high performance silicon nitride layer 206 is disposed on the cap layer 204 on two sides of a gate 208 and between a source 210 and drain 212 of a gallium nitride field effect transistor (GaN FET) 214 of the semiconductor device 200.
  • the gate 208 may partially overlap the high performance silicon nitride layer 206.
  • the high performance silicon nitride layer 206 may be 10 nanometers to 20 nanometers thick.
  • Contact metal 216 is disposed on the substrate 202 in the source 210 and drain 212.
  • a field plate dielectric layer 218 is disposed over the gate 208 and the high performance silicon nitride layer 206, around the contact metal 216.
  • Source metal 220 makes an electrical connection to the contact metal 216 in the source 210 and overlaps the gate 208 and extends partway to the drain 212 over the field plate dielectric layer 218 to provide a field plate for the GaN FET 214.
  • Drain metal 222 makes electrical connection to the contact metal 216 in the drain 212. Additional dielectric layers and metal layers may be formed to provide low resistance connections to the GaN FET 214.
  • the low stress of the high performance silicon nitride layer 206 advantageously improves on-state current in the GaN FET 214 compared to a GaN FET with a silicon nitride layer having high stress.
  • the low hydrogen content of the high performance silicon nitride layer 206 advantageously reduces charge trapping and improves reliability of the GaN FET 214 compared to a GaN FET with a silicon nitride layer having a high hydrogen content.
  • FIG. 3 A and FIG. 3B are cross sections of the semiconductor device of FIG. 2, depicted in key stages of formation.
  • the cap layer 204 is formed on the substrate 202 by an epitaxial process. A portion of the cap layer 204 and the substrate 202 may be removed to provide a lateral isolation boundary 224 for the GaN FET 214.
  • the high performance silicon nitride layer 206 is formed on the cap layer 204 by an LPCVD process as described in reference to FIG. 1.
  • An etch mask 226 is formed over the high performance silicon nitride layer 206 to cover areas for the high performance silicon nitride layer 206 of the completed GaN FET 214 of FIG. 2.
  • the etch mask 226 may include photoresist formed by a photolithographic process, and may possibly include an anti -reflection layer.
  • a reactive ion etch (RIE) process 228 containing fluorine (F) removes the high performance silicon nitride layer 206 where exposed by the etch mask 226.
  • Reactant gas flows and a pressure in the RIE process 228 may be adjusted to provide sloped edges on the high performance silicon nitride layer 206 as depicted in FIG. 3B.
  • the etch mask 226 is removed, such as by an ash process. Fabrication of the semiconductor device 200 is continued to provide the structure of FIG. 2.
  • the method described in reference to FIG. 3A and FIG. 3B advantageously provides the patterned high performance silicon nitride layer 206 with the desired properties of low stress and low hydrogen content.
  • FIG. 4 is a cross section of an example integrated circuit with a high performance silicon nitride layer.
  • the integrated circuit 400 is formed on a semiconductor substrate 402 such as a silicon wafer.
  • the integrated circuit 400 includes a p-channel metal oxide semiconductor (PMOS) transistor 404 and/or an n-channel metal oxide semiconductor (NMOS) transistor 406.
  • Field oxide 408 is disposed in the substrate 402 to laterally isolate the PMOS transistor 404 and the NMOS transistor 406.
  • the PMOS transistor 404 is disposed in an n-type well 410 extending below the field oxide 408.
  • the PMOS transistor 404 includes a gate dielectric layer 412 on the n-type well 410 and a gate 414 on the gate dielectric layer 412. Offset spacers 416 are disposed on lateral surfaces of the gate 414.
  • P-type source and drain regions 418 are disposed in the n-type well 410 on two sides of the gate 414.
  • the source and drain regions 418 include source/drain extensions 420 extending under the gate 414 and deep source/drain regions 422 adjacent to the gate 414.
  • Gate sidewall spacers 424 are disposed adjacent to the gate 414, on the offset spacers 416.
  • the gate sidewall spacers 424 include one or more layers of high performance silicon nitride, with low stress and low hydrogen content.
  • Metal silicide 426 is disposed on the source and drain regions 418 adjacent to the gate sidewall spacers 424, and possibly on the gate 414.
  • the gate sidewall spacers 424 provide lateral separation between a channel layer immediately below the gate dielectric layer 412 and the deep source/drain regions 422, and between the channel layer and the metal silicide 426 on the source and drain regions 418.
  • the high performance silicon nitride in the gate sidewall spacers 424 may be within 10 nanometers of the semiconductor substrate 402.
  • the low stress of the gate sidewall spacers 424 may advantageously reduce stress in the channel layer, and so improve an on-state current and/or an off-state current of the PMOS transistor 404.
  • the low hydrogen content of the gate sidewall spacers 424 may advantageously improve reliability of the PMOS transistor 404.
  • the NMOS transistor 406 is disposed in a p-type well 428 extending below the field oxide 408.
  • the NMOS transistor 406 includes a gate dielectric layer 430 on the p-type well 428 and a gate 432 on the gate dielectric layer 430. Offset spacers 434 are disposed on lateral surfaces of the gate 432.
  • N-type source and drain regions 436 are disposed in the p-type well 428 on two sides of the gate 432.
  • the source and drain regions 436 include source/drain extensions 438 extending under the gate 432 and deep source/drain regions 440 adjacent to the gate 432.
  • Gate sidewall spacers 442 including one or more high performance silicon nitride layers are disposed adjacent to the gate 432.
  • the gate sidewall spacers 424 of the PMOS transistor 404 and the gate sidewall spacers 424 of the NMOS transistor 406 may possibly have a same layer structure as a result of being formed concurrently.
  • Metal silicide 444 is disposed on the source and drain regions 436 adjacent to the gate sidewall spacers 442, and possibly on the gate 432.
  • the NMOS transistor may accrue advantages from the low stress and low hydrogen content of the gate sidewall spacers 442 similar to those described in reference to the PMOS transistor 404.
  • FIG. 5 A and FIG. 5B are cross sections of the integrated circuit of FIG. 4, depicted in key stages of fabrication.
  • the p-type source/drain extensions 420 are formed by implanting p-type dopants into the n-type well 410 using the gate 414 and offset spacers 416 of the PMOS transistor 404 as an implant mask, so that the source/drain extensions 420 do not extend completely under the gate 414.
  • the n-type source/drain extensions 438 are formed by implanting n-type dopants into the p-type well 428 using the gate 432 and offset spacers 434 of the NMOS transistor 406 as an implant mask, so that the source/drain extensions 438 do not extend completely under the gate 432.
  • the substrate 402 is subsequently annealed to activate the implanted dopants.
  • a high performance silicon nitride layer 450 is formed over the gate 414, the offset spacers 416 and the source/drain extensions 420 of the PMOS transistor 404 and over the gate 432, the offset spacers 434 and the source/drain extensions 438 of the NMOS transistor 406.
  • the high performance silicon nitride layer 450 is formed by an LPCVD process as described in reference to FIG. 1, which provides at least a partially conformal layer as depicted in FIG. 5 A, so that a thickness of the high performance silicon nitride layer 450 on vertical surfaces of the offset spacers 416 and 434 is sufficient to form the gate sidewall spacers 424 and 442 of FIG. 4, respectively.
  • an anisotropic RIE process 452 containing fluorine (F) removes the high performance silicon nitride layer 450 of FIG. 5A over horizontal surfaces of the gate 414 and the source/drain extensions 420 of the PMOS transistor 404 and over the gate 432 and the source/drain extensions 438 of the NMOS transistor 406, leaving the high performance silicon nitride layer 450 to form the gate sidewall spacers 424 on the vertical surfaces of the offset spacers 416 of the PMOS transistor 404, and to form the gate sidewall spacers 442 on the vertical surfaces of the offset spacers 434 of the NMOS transistor 406.
  • F fluorine
  • the conformal aspect of the LPCVD process to form the high performance silicon nitride layer 450 enables the gate sidewall spacers 424 and 442 to be formed without a photolithographic operation, advantageously reducing fabrication cost and complexity of the integrated circuit 400.
  • FIG. 6A and FIG. 6B are cross sections of an example microelectronic mechanical system (MEMS) device with a high performance silicon nitride layer, depicted in key stages of fabrication.
  • the MEMS device 600 is formed in a silicon substrate 602, such as a single crystalline silicon wafer.
  • a cavity 604 is formed in the substrate 602 leaving material of the substrate 602 above the cavity 604 in the form of a cantilevered element 606 such as a perforated membrane 606.
  • the perforated membrane 606 may be part of a sensor, such as a thermal sensor or a microphone, or may be part of an actuator such as a speaker.
  • a layer of high performance silicon nitride 610 is formed on the perforated membrane 606 and interior surfaces of the cavity 604 and adjacent regions 608 of the substrate 602.
  • the high performance silicon nitride layer 610 is formed by an LPCVD process as described in reference to FIG. 1 to have low stress and a low hydrogen content, which provides at least a partially conformal layer, so that the high performance silicon nitride layer 610 covers all exposed surfaces of the perforated membrane 606 as depicted in FIG. 6A.
  • the high performance silicon nitride layer 610 is thicker on a top surface of the perforated membrane 606 outside of the cavity 604 than on a bottom surface of the perforated membrane 606 facing the cavity 604.
  • the low stress of the high performance silicon nitride layer 610 advantageously reduces deformation of the perforated membrane 606 due to the unequal thickness on the top and bottom surfaces of the perforated membrane 606.
  • the high performance silicon nitride layer 610 is removed from a portion of the substrate 602 in the regions 608 adjacent to the perforated membrane 606.
  • the MEMS device 600 is immersed in a crystallographic wet etch solution 612, such as a potassium hydroxide solution, which removes silicon from the substrate 602 in the areas exposed by the high performance silicon nitride layer 610 along crystal planes of the substrate 602 to form isolation cavities 614 adjacent to the perforated membrane 606.
  • the low hydrogen content of the high performance silicon nitride layer 610 advantageously provides etch resistance to the crystallographic wet etch solution 612 at a desired thickness.
  • the MEMS device 600 is subsequently rinsed and dried.
  • the high performance silicon nitride layer 610 may be left in place in the completed MEMS device 600 or may be removed during subsequent fabrication processes.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mechanical Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • General Health & Medical Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Micromachines (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

In described examples, a microelectronic device (102) contains a high performance silicon nitride layer, which is stoichiometric within 2 atomic percent, has a low stress of 600 MPa to 1000 MPa, and has a low hydrogen content, less than 5 atomic percent, formed by an LPCVD process. The LPCVD process uses ammonia NH3 and dichlorosilane DCS gases in a ratio of 4 to 6, at a pressure of 150 millitorr to 250 millitorr, and at a temperature of 800°C to 820°C.

Description

LOW-STRESS LOW-HYDROGEN LPCVD SILICON NITRIDE
[0001] This relates generally to microelectronic devices, and more particularly to silicon nitride layers in microelectronic devices.
BACKGROUND
[0002] In microelectronic devices, stoichiometric silicon nitride layers are desirably formed, which simultaneously have low stress that is less than 1000 megapascals (MPa), and low hydrogen content that is less than 5 atomic percent. Such films would be useful for a variety of microelectronic applications. Silicon nitride films formed by plasma enhanced chemical vapor deposition (PECVD) may have low stress, but have high hydrogen content, above 15 atomic percent, which can cause reliability problems and poor etch resistance. Films formed by low pressure chemical vapor deposition (LPCVD) have low hydrogen content, but high stress, above 1000 MPa, which can cause device performance problems.
SUMMARY
[0003] In described examples, a microelectronic device contains a high performance silicon nitride layer, which is stoichiometric within 2 atomic percent, has a low stress of 600 MPa to 1000 MPa, and has a low hydrogen content, less than 5 atomic percent. The high performance silicon nitride layer is formed by an LPCVD process. The LPCVD process uses ammonia and dichlorosilane gases in a ratio of 4 to 6, at a pressure of 150 millitorr to 250 millitorr, and at a temperature of 800°C to 820°C.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] FIG. 1 depicts an LPCVD furnace in an example process of forming a high performance silicon nitride on microelectronic devices and FIG. 1A is an expanded view of the silicon nitride layer formed on the microelectronic devices within the furnace of FIG. 1.
[0005] FIG. 2 is a cross section of an example semiconductor device with a high performance silicon nitride layer.
[0006] FIG. 3 A and FIG. 3B are cross sections of the semiconductor device of FIG. 2, depicted in key stages of formation.
[0007] FIG. 4 is a cross section of an example integrated circuit with a high performance silicon nitride layer.
[0008] FIG. 5 A and FIG. 5B are cross sections of the integrated circuit of FIG. 4, depicted in key stages of fabrication.
[0009] FIG. 6A and FIG. 6B are cross sections of an example microelectronic mechanical system (MEMS) device with a high performance silicon nitride layer, depicted in key stages of fabrication.
DETAILED DESCRIPTION OF EXAMPLE EMB ODFMENT S
[0010] The figures are not drawn to scale. Some acts may occur in different orders and/or concurrently with other acts or events. Not all illustrated acts or events are required to implement a methodology in accordance with example embodiments.
[0011] A high performance silicon nitride layer, which is stoichiometric within 2 atomic percent, has a low stress of 600 MPa to 1000 MPa, and has a low hydrogen content, less than 5 atomic percent, is formed by an LPCVD process. The LPCVD process uses ammonia and dichlorosilane gases in a ratio of 4 to 6, at a pressure of 150 millitorr to 250 millitorr, and at a temperature of 800°C to 820°C. The combination of stoichiometry, low stress and low hydrogen content were not expected to be provided by the disclosed process conditions, and were discovered during investigations of LPCVD processes. For the purposes of this disclosure, stoichiometric silicon nitride has a silicon:nitrogen atomic ratio of 3 :4.
[0012] FIG. 1 depicts an LPCVD furnace in an example process of forming a high performance silicon nitride on microelectronic devices. The LPCVD furnace 100 holds the microelectronic devices 102 on substrates, such as semiconductor wafers, in a boat 104. The boat 104 is held in a reaction chamber 106 of the LPCVD furnace 100. The reaction chamber 106 is heated to a temperature of 800°C to 820°C by heating elements 108 of the LPCVD furnace 100 disposed around the reaction chamber 106. Ammonia (NH3) and dichlorosilane (DCS) gases are introduced into the reaction chamber 106 at a ratio of 4 to 6. Pressure inside the reaction chamber 106 is maintained at 150 millitorr to 250 millitorr by an exhaust system 110, such as including a combination of an exhaust pump and an adjustable exhaust valve. As shown in the expanded view of FIG. 1 A, the high performance silicon nitride layer 112 is formed on the microelectronic devices 102 by reaction of nitrogen in the ammonia and silicon in the dichlorosilane. Formation of the high performance silicon nitride layer 112 is continued until a desired thickness is attained. Subsequently, flows of the ammonia and dichlorosilane are ended and the microelectronic devices 102 are extracted from the LPCVD furnace 100.
[0013] Formation of the high performance silicon nitride layer 112 by maintaining the temperature at 800°C to 820°C, the ratio of ammonia to dichlorosilane at 4 to 6, and the pressure at 150 millitorr to 250 millitorr advantageously provides a silicon:nitrogen atomic ratio within 2 percent of the ratio 3 :4, a low stress of 600 MPa to 1000 MPa, and a low hydrogen content of less than 5 atomic percent. The high performance silicon nitride layer 112 may have an index of refraction of 2.0 to 2.1 as a result of being formed by the process described in reference to FIG. 1. Further, the high performance silicon nitride layer 112 may have a dielectric breakdown strength of greater than 12 megavolts per centimeter (MV/cm), which may advantageously contribute to higher reliability of the microelectronic devices 102. Increasing the ratio of ammonia to dichlorosilane reduces the stoichiometry and the dielectric breakdown strength, which may disadvantageous^ contribute to lower reliability. Reducing the ratio of ammonia to dichlorosilane disadvantageously increases the stress. Reducing the temperature and increasing the pressure also disadvantageously increases the stress.
[0014] FIG. 2 is a cross section of an example semiconductor device with a high performance silicon nitride layer. The semiconductor device 200 is formed on a semiconductor substrate 202, such as a stack gallium nitride and aluminum gallium nitride epitaxial layers, and possibly other III-V layers. A cap layer 204 of gallium nitride is disposed on the substrate 202. A high performance silicon nitride layer 206 is disposed on the cap layer 204 on two sides of a gate 208 and between a source 210 and drain 212 of a gallium nitride field effect transistor (GaN FET) 214 of the semiconductor device 200. The gate 208 may partially overlap the high performance silicon nitride layer 206. For example, the high performance silicon nitride layer 206 may be 10 nanometers to 20 nanometers thick.
[0015] Contact metal 216 is disposed on the substrate 202 in the source 210 and drain 212. A field plate dielectric layer 218 is disposed over the gate 208 and the high performance silicon nitride layer 206, around the contact metal 216. Source metal 220 makes an electrical connection to the contact metal 216 in the source 210 and overlaps the gate 208 and extends partway to the drain 212 over the field plate dielectric layer 218 to provide a field plate for the GaN FET 214. Drain metal 222 makes electrical connection to the contact metal 216 in the drain 212. Additional dielectric layers and metal layers may be formed to provide low resistance connections to the GaN FET 214. [0016] The low stress of the high performance silicon nitride layer 206 advantageously improves on-state current in the GaN FET 214 compared to a GaN FET with a silicon nitride layer having high stress. The low hydrogen content of the high performance silicon nitride layer 206 advantageously reduces charge trapping and improves reliability of the GaN FET 214 compared to a GaN FET with a silicon nitride layer having a high hydrogen content.
[0017] FIG. 3 A and FIG. 3B are cross sections of the semiconductor device of FIG. 2, depicted in key stages of formation. Referring to FIG. 3A, the cap layer 204 is formed on the substrate 202 by an epitaxial process. A portion of the cap layer 204 and the substrate 202 may be removed to provide a lateral isolation boundary 224 for the GaN FET 214. The high performance silicon nitride layer 206 is formed on the cap layer 204 by an LPCVD process as described in reference to FIG. 1. An etch mask 226 is formed over the high performance silicon nitride layer 206 to cover areas for the high performance silicon nitride layer 206 of the completed GaN FET 214 of FIG. 2. The etch mask 226 may include photoresist formed by a photolithographic process, and may possibly include an anti -reflection layer.
[0018] Referring to FIG. 3B, a reactive ion etch (RIE) process 228 containing fluorine (F) removes the high performance silicon nitride layer 206 where exposed by the etch mask 226. Reactant gas flows and a pressure in the RIE process 228 may be adjusted to provide sloped edges on the high performance silicon nitride layer 206 as depicted in FIG. 3B. Subsequently, the etch mask 226 is removed, such as by an ash process. Fabrication of the semiconductor device 200 is continued to provide the structure of FIG. 2. The method described in reference to FIG. 3A and FIG. 3B advantageously provides the patterned high performance silicon nitride layer 206 with the desired properties of low stress and low hydrogen content.
[0019] FIG. 4 is a cross section of an example integrated circuit with a high performance silicon nitride layer. The integrated circuit 400 is formed on a semiconductor substrate 402 such as a silicon wafer. The integrated circuit 400 includes a p-channel metal oxide semiconductor (PMOS) transistor 404 and/or an n-channel metal oxide semiconductor (NMOS) transistor 406. Field oxide 408 is disposed in the substrate 402 to laterally isolate the PMOS transistor 404 and the NMOS transistor 406.
[0020] The PMOS transistor 404 is disposed in an n-type well 410 extending below the field oxide 408. The PMOS transistor 404 includes a gate dielectric layer 412 on the n-type well 410 and a gate 414 on the gate dielectric layer 412. Offset spacers 416 are disposed on lateral surfaces of the gate 414. P-type source and drain regions 418 are disposed in the n-type well 410 on two sides of the gate 414. The source and drain regions 418 include source/drain extensions 420 extending under the gate 414 and deep source/drain regions 422 adjacent to the gate 414.
[0021] Gate sidewall spacers 424 are disposed adjacent to the gate 414, on the offset spacers 416. The gate sidewall spacers 424 include one or more layers of high performance silicon nitride, with low stress and low hydrogen content. Metal silicide 426 is disposed on the source and drain regions 418 adjacent to the gate sidewall spacers 424, and possibly on the gate 414. The gate sidewall spacers 424 provide lateral separation between a channel layer immediately below the gate dielectric layer 412 and the deep source/drain regions 422, and between the channel layer and the metal silicide 426 on the source and drain regions 418. The high performance silicon nitride in the gate sidewall spacers 424 may be within 10 nanometers of the semiconductor substrate 402. The low stress of the gate sidewall spacers 424 may advantageously reduce stress in the channel layer, and so improve an on-state current and/or an off-state current of the PMOS transistor 404. The low hydrogen content of the gate sidewall spacers 424 may advantageously improve reliability of the PMOS transistor 404.
[0022] Similarly, the NMOS transistor 406 is disposed in a p-type well 428 extending below the field oxide 408. The NMOS transistor 406 includes a gate dielectric layer 430 on the p-type well 428 and a gate 432 on the gate dielectric layer 430. Offset spacers 434 are disposed on lateral surfaces of the gate 432. N-type source and drain regions 436 are disposed in the p-type well 428 on two sides of the gate 432. The source and drain regions 436 include source/drain extensions 438 extending under the gate 432 and deep source/drain regions 440 adjacent to the gate 432. Gate sidewall spacers 442 including one or more high performance silicon nitride layers are disposed adjacent to the gate 432. The gate sidewall spacers 424 of the PMOS transistor 404 and the gate sidewall spacers 424 of the NMOS transistor 406 may possibly have a same layer structure as a result of being formed concurrently. Metal silicide 444 is disposed on the source and drain regions 436 adjacent to the gate sidewall spacers 442, and possibly on the gate 432. The NMOS transistor may accrue advantages from the low stress and low hydrogen content of the gate sidewall spacers 442 similar to those described in reference to the PMOS transistor 404.
[0023] FIG. 5 A and FIG. 5B are cross sections of the integrated circuit of FIG. 4, depicted in key stages of fabrication. Referring to FIG. 5A, the p-type source/drain extensions 420 are formed by implanting p-type dopants into the n-type well 410 using the gate 414 and offset spacers 416 of the PMOS transistor 404 as an implant mask, so that the source/drain extensions 420 do not extend completely under the gate 414. Similarly, the n-type source/drain extensions 438 are formed by implanting n-type dopants into the p-type well 428 using the gate 432 and offset spacers 434 of the NMOS transistor 406 as an implant mask, so that the source/drain extensions 438 do not extend completely under the gate 432. The substrate 402 is subsequently annealed to activate the implanted dopants.
[0024] A high performance silicon nitride layer 450 is formed over the gate 414, the offset spacers 416 and the source/drain extensions 420 of the PMOS transistor 404 and over the gate 432, the offset spacers 434 and the source/drain extensions 438 of the NMOS transistor 406. The high performance silicon nitride layer 450 is formed by an LPCVD process as described in reference to FIG. 1, which provides at least a partially conformal layer as depicted in FIG. 5 A, so that a thickness of the high performance silicon nitride layer 450 on vertical surfaces of the offset spacers 416 and 434 is sufficient to form the gate sidewall spacers 424 and 442 of FIG. 4, respectively.
[0025] Referring to FIG. 5B, an anisotropic RIE process 452 containing fluorine (F) removes the high performance silicon nitride layer 450 of FIG. 5A over horizontal surfaces of the gate 414 and the source/drain extensions 420 of the PMOS transistor 404 and over the gate 432 and the source/drain extensions 438 of the NMOS transistor 406, leaving the high performance silicon nitride layer 450 to form the gate sidewall spacers 424 on the vertical surfaces of the offset spacers 416 of the PMOS transistor 404, and to form the gate sidewall spacers 442 on the vertical surfaces of the offset spacers 434 of the NMOS transistor 406. The conformal aspect of the LPCVD process to form the high performance silicon nitride layer 450 enables the gate sidewall spacers 424 and 442 to be formed without a photolithographic operation, advantageously reducing fabrication cost and complexity of the integrated circuit 400.
[0026] FIG. 6A and FIG. 6B are cross sections of an example microelectronic mechanical system (MEMS) device with a high performance silicon nitride layer, depicted in key stages of fabrication. Referring to FIG. 6A, the MEMS device 600 is formed in a silicon substrate 602, such as a single crystalline silicon wafer. A cavity 604 is formed in the substrate 602 leaving material of the substrate 602 above the cavity 604 in the form of a cantilevered element 606 such as a perforated membrane 606. The perforated membrane 606 may be part of a sensor, such as a thermal sensor or a microphone, or may be part of an actuator such as a speaker. It may be desirable to partially isolate the perforated membrane 606 from adjacent regions 608 of the substrate 602. A layer of high performance silicon nitride 610 is formed on the perforated membrane 606 and interior surfaces of the cavity 604 and adjacent regions 608 of the substrate 602. The high performance silicon nitride layer 610 is formed by an LPCVD process as described in reference to FIG. 1 to have low stress and a low hydrogen content, which provides at least a partially conformal layer, so that the high performance silicon nitride layer 610 covers all exposed surfaces of the perforated membrane 606 as depicted in FIG. 6A. Due to restricted access to the cavity 604 through the perforated membrane 606, the high performance silicon nitride layer 610 is thicker on a top surface of the perforated membrane 606 outside of the cavity 604 than on a bottom surface of the perforated membrane 606 facing the cavity 604. The low stress of the high performance silicon nitride layer 610 advantageously reduces deformation of the perforated membrane 606 due to the unequal thickness on the top and bottom surfaces of the perforated membrane 606.
[0027] Referring to FIG. 6B, the high performance silicon nitride layer 610 is removed from a portion of the substrate 602 in the regions 608 adjacent to the perforated membrane 606. The MEMS device 600 is immersed in a crystallographic wet etch solution 612, such as a potassium hydroxide solution, which removes silicon from the substrate 602 in the areas exposed by the high performance silicon nitride layer 610 along crystal planes of the substrate 602 to form isolation cavities 614 adjacent to the perforated membrane 606. The low hydrogen content of the high performance silicon nitride layer 610 advantageously provides etch resistance to the crystallographic wet etch solution 612 at a desired thickness. The MEMS device 600 is subsequently rinsed and dried. The high performance silicon nitride layer 610 may be left in place in the completed MEMS device 600 or may be removed during subsequent fabrication processes.
[0028] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

Claims

CLAIMS What is claimed is:
1. A microelectronic device, comprising:
a substrate; and
a silicon nitride layer disposed over the substrate, the silicon nitride layer having the following properties: a silicon:nitrogen atomic ratio within 2 percent of the ratio 3 :4; a stress of 600 megapascals (MPa) to 1000 MPa; and a hydrogen content of less than 5 atomic percent.
2. The microelectronic device of claim 1, wherein the silicon nitride layer is less than 25 nanometers thick:
3. The microelectronic device of claim 1, wherein the silicon nitride layer has an index of refraction of 2.0 to 2.1 :
4. The microelectronic device of claim 1, wherein the silicon nitride layer has a dielectric breakdown strength of greater than 12 megavolts per centimeter (MV/cm).
5. The microelectronic device of claim 1, wherein the microelectronic device includes semiconductor material, and the silicon nitride layer is within 10 nanometers of the semiconductor material.
6. The microelectronic device of claim 1, wherein the semiconductor material includes III-V semiconductor material.
7. The microelectronic device of claim 1, wherein the microelectronic device includes a gallium nitride field effect transistor (GaN FET).
8. The microelectronic device of claim 7, wherein the silicon nitride layer contacts III-V semiconductor material and contacts a gate of the GaN FET.
9. The microelectronic device of claim 1, wherein the microelectronic device includes an n-channel metal oxide semiconductor (NMOS) transistor with first gate sidewall spacers adjacent to a first gate of the NMOS transistor, and the first gate sidewall spacers include the silicon nitride layer.
10. The microelectronic device of claim 9, wherein the microelectronic device includes a p-channel metal oxide semiconductor (PMOS) transistor with second gate sidewall spacers adjacent to a second gate of the PMOS transistor, and the second gate sidewall spacers include the silicon nitride layer.
11. The microelectronic device of claim 1, wherein the microelectronic device is a microelectronic mechanical system (MEMS) device containing a cantilevered element, and the silicon nitride layer is disposed on a top surface of the cantilevered element and on a bottom surface of the cantilevered element.
12. A method of forming a microelectronic device, comprising:
providing a substrate;
placing the substrate in a low pressure chemical vapor deposition (LPCVD) furnace; heating the substrate to a temperature of 800°C to 820°C in the LPCVD furnace;
providing ammonia gas and dichlorosilane gas to the reaction chamber at a ratio of 4 to 6, and at a pressure of 150 millitorr to 250 millitorr to form a silicon nitride layer over the substrate; and
removing the substrate from the LPCVD furnace.
13. The method of claim 12, comprising:
forming an etch mask over the silicon nitride layer;
removing the silicon nitride layer exposed by the etch mask by a reactive ion etch (RLE) process with fluorine radicals; and
subsequently removing the etch mask.
14. The method of claim 13, comprising forming an electrically conductive element at least partially overlapping the silicon nitride layer.
15. The method of claim 14, wherein electrically conductive element is a gate of a GaN FET, and the silicon nitride layer is disposed on a cap layer on the substrate.
16. The method of claim 12, wherein the silicon nitride layer is formed as a conformal layer, and comprising removing the silicon nitride layer from horizontal surfaces of the substrate by an anisotropic RLE process with fluorine radicals, leaving the silicon nitride layer on vertical surfaces of the substrate.
17. The method of claim 16, wherein the microelectronic device is an integrated circuit containing an NMOS transistor, and the silicon nitride layer is formed over a gate of the NMOS transistor, and wherein the silicon nitride layer remaining after the anisotropic RLE process provides gate sidewall spacers adjacent to the gate of the NMOS transistor.
18. The method of claim 12, wherein the microelectronic device is a MEMS device containing a cantilevered element, and the silicon nitride layer is formed as a conformal layer to form on a top surface of the cantilevered element and on a bottom surface of the cantilevered element.
19. The method of claim 12, wherein the silicon nitride layer protects the substrate during a wet etch process in which material is removed from the substrate in an area exposed by the silicon nitride layer.
20. A method of forming a microelectronic device, comprising:
providing a substrate including gallium nitride;
forming a cap layer of gallium nitride on the substrate;
placing the substrate in an LPCVD furnace;
heating the substrate to a temperature of 800°C to 820°C in the LPCVD furnace;
providing ammonia gas and dichlorosilane gas to the reaction chamber at a ratio of 4 to 6, and at a pressure of 150 millitorr to 250 millitorr to form a silicon nitride layer on the cap layer, the silicon nitride layer having the following properties: a silicon:nitrogen atomic ratio within 2 percent of the ratio 3 :4; a stress of 600 megapascals (MPa) to 1000 MPa; and a hydrogen content of less than 5 atomic percent;
removing the substrate from the LPCVD furnace;
forming an etch mask over the silicon nitride layer;
removing the silicon nitride layer exposed by the etch mask by an RJE process with fluorine radicals;
subsequently removing the etch mask; and
forming a gate of a GaN FET over the cap layer between, and partially overlapping, portions of the silicon nitride layer.
PCT/US2016/031509 2015-05-07 2016-05-09 Low-stress low-hydrogen lpcvd silicon nitride Ceased WO2016179596A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2017558375A JP6931208B2 (en) 2015-05-07 2016-05-09 Low stress low hydrogen LPCVD silicon nitride
CN201680028363.3A CN107533974B (en) 2015-05-07 2016-05-09 Low-stress low-hydrogen LPCVD silicon nitride

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/706,941 2015-05-07
US14/706,941 US9580304B2 (en) 2015-05-07 2015-05-07 Low-stress low-hydrogen LPCVD silicon nitride

Publications (1)

Publication Number Publication Date
WO2016179596A1 true WO2016179596A1 (en) 2016-11-10

Family

ID=57218409

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2016/031509 Ceased WO2016179596A1 (en) 2015-05-07 2016-05-09 Low-stress low-hydrogen lpcvd silicon nitride

Country Status (4)

Country Link
US (2) US9580304B2 (en)
JP (1) JP6931208B2 (en)
CN (1) CN107533974B (en)
WO (1) WO2016179596A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018181885A (en) * 2017-04-03 2018-11-15 住友電気工業株式会社 Method of forming silicon nitride passivation film and method of manufacturing semiconductor device

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6984456B2 (en) * 2018-02-05 2021-12-22 住友電気工業株式会社 Manufacturing method of field effect transistor
CN110120347B (en) * 2018-02-05 2023-11-17 住友电气工业株式会社 Methods of forming field effect transistors
JP6997002B2 (en) 2018-02-19 2022-01-17 住友電気工業株式会社 Semiconductor devices and their manufacturing methods
CN110429024B (en) * 2019-08-08 2022-04-15 京东方科技集团股份有限公司 Preparation method of interlayer insulating layer and thin film transistor
CN113782420B (en) * 2021-08-05 2024-07-19 华虹半导体(无锡)有限公司 Wafer processing method
CN117488273A (en) * 2023-11-21 2024-02-02 华东光电集成器件研究所 Preparation method of low-roughness thick silicon nitride film

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030178633A1 (en) * 2002-03-25 2003-09-25 Flynn Jeffrey S. Doped group III-V nitride materials, and microelectronic devices and device precursor structures comprising same
US20050112817A1 (en) * 2003-11-25 2005-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having high drive current and method of manufacture thereof
US20110297961A1 (en) * 2010-05-02 2011-12-08 Visic Technologies Ltd. Field effect power transistors
US20120104505A1 (en) * 2010-10-28 2012-05-03 International Business Machines Corporation Structure and method for using high-k material as an etch stop layer in dual stress layer process

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4538343A (en) * 1984-06-15 1985-09-03 Texas Instruments Incorporated Channel stop isolation technology utilizing two-step etching and selective oxidation with sidewall masking
JPH056890A (en) * 1990-10-15 1993-01-14 Seiko Epson Corp Semiconductor device having passivation multilayer film and method of manufacturing the same
JPH04299515A (en) * 1991-03-27 1992-10-22 Shin Etsu Chem Co Ltd X-ray lithography - X-ray transparent membrane for mask and method for manufacturing the same
US5754390A (en) * 1996-01-23 1998-05-19 Micron Technology, Inc. Integrated capacitor bottom electrode for use with conformal dielectric
US6316820B1 (en) * 1997-07-25 2001-11-13 Hughes Electronics Corporation Passivation layer and process for semiconductor devices
US7235856B1 (en) * 1997-12-18 2007-06-26 Micron Technology, Inc. Trench isolation for semiconductor devices
CN1232858C (en) * 1998-09-24 2005-12-21 反射公司 Double-layer dielectric reflective spatial light modulator with self-limiting micromechanical elements
JP2005286135A (en) * 2004-03-30 2005-10-13 Eudyna Devices Inc Semiconductor device and manufacturing method of semiconductor device
WO2006022453A1 (en) * 2004-08-27 2006-03-02 National Institute Of Information And Communications Technology, Incorporated Administrative Agency GaN-BASED FIELD EFFECT TRANSISTOR AND PRODUCTION METHOD THEREFOR
TWI263265B (en) * 2005-02-13 2006-10-01 United Microelectronics Corp Method for fabricating ultra-high tensile-stressed film and strained-silicon transistors thereof
CN101976686A (en) * 2005-06-10 2011-02-16 日本电气株式会社 Field effect transistor
US7855401B2 (en) * 2005-06-29 2010-12-21 Cree, Inc. Passivation of wide band-gap based semiconductor devices with hydrogen-free sputtered nitrides
JP2008034522A (en) * 2006-07-27 2008-02-14 Oki Electric Ind Co Ltd Field effect transistor
US8063434B1 (en) * 2007-05-25 2011-11-22 Cypress Semiconductor Corporation Memory transistor with multiple charge storing layers and a high work function gate electrode
US8871595B2 (en) * 2007-05-25 2014-10-28 Cypress Semiconductor Corporation Integration of non-volatile charge trap memory devices and logic CMOS devices
WO2009011709A1 (en) * 2007-07-19 2009-01-22 The Board Of Trustees Of The University Of Illinois High resolution electrohydrodynamic jet printing for manufacturing systems
JP4719210B2 (en) * 2007-12-28 2011-07-06 富士通株式会社 Semiconductor device and manufacturing method thereof
JP5345328B2 (en) * 2008-02-22 2013-11-20 住友電工デバイス・イノベーション株式会社 Manufacturing method of semiconductor device
JPWO2010079574A1 (en) * 2009-01-09 2012-06-21 パナソニック株式会社 MEMS device
JP5609055B2 (en) * 2009-10-02 2014-10-22 富士通株式会社 Compound semiconductor device and manufacturing method thereof
US20120255932A1 (en) * 2010-07-15 2012-10-11 Massood Tabib-Azar Nanofabrication device and method for manufacture of a nanofabrication device
JP5685020B2 (en) * 2010-07-23 2015-03-18 住友電気工業株式会社 Manufacturing method of semiconductor device
CN102446840A (en) * 2011-11-02 2012-05-09 上海华力微电子有限公司 Method for increasing breakdown voltage of double-Damascus structure dielectric barrier layer film
JP5970197B2 (en) * 2012-02-08 2016-08-17 メルクパフォーマンスマテリアルズマニュファクチャリング合同会社 Inorganic polysilazane resin
KR20130097116A (en) * 2012-02-23 2013-09-02 이피션트 파워 컨버젼 코퍼레이션 Enhancement mode gan hemt device with a gate spacer and method for fabricating the same
US9111868B2 (en) * 2012-06-26 2015-08-18 Freescale Semiconductor, Inc. Semiconductor device with selectively etched surface passivation
JP2014029908A (en) * 2012-07-31 2014-02-13 Toyota Central R&D Labs Inc Semiconductor device and semiconductor device manufacturing method
US9224532B2 (en) * 2012-10-11 2015-12-29 The Board Of Trustees Of The University Of Illinois Rolled-up inductor structure for a radiofrequency integrated circuit (RFIC)
JP6339762B2 (en) * 2013-01-17 2018-06-06 富士通株式会社 Semiconductor device and manufacturing method thereof, power supply device, and high-frequency amplifier
US9035318B2 (en) * 2013-05-03 2015-05-19 Texas Instruments Incorporated Avalanche energy handling capable III-nitride transistors

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030178633A1 (en) * 2002-03-25 2003-09-25 Flynn Jeffrey S. Doped group III-V nitride materials, and microelectronic devices and device precursor structures comprising same
US20050112817A1 (en) * 2003-11-25 2005-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having high drive current and method of manufacture thereof
US20110297961A1 (en) * 2010-05-02 2011-12-08 Visic Technologies Ltd. Field effect power transistors
US20120104505A1 (en) * 2010-10-28 2012-05-03 International Business Machines Corporation Structure and method for using high-k material as an etch stop layer in dual stress layer process

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
GARDENIERS J. G. E. ET AL.: "LPCVD silicon-rich silicon nitride films for applications in micromechanics, studied with statistical experimental design.", J. VAC. SCI. TECHNOL. A, vol. 14, no. 5, September 1996 (1996-09-01), pages 2879 - 2892, XP055125330 *
JOSHI B C ET AL.: "LPCVD and PECVD silicon nitride for microelectronics technology.", INDIAN JOURNAL OF ENGINEERING & MATERIALS SCIENCES, vol. 7, October 2000 (2000-10-01), pages 303 - 309, XP055329620 *
TONNBERG SOFIA.: "Optimisation and characterisation of LPCVD silicon nitride thin film growth.", THESIS FOR MSC FOR DEPARTMENT OF MICROTECHNOLOGY AND NANOSCIENCE NANOFABRICATION LABORATORY FOR CHALMERS UNIVERSITY OF TECHNOLOGY, 2006, Goteborg, Sweden, pages 22, 23, XP055329616 *
WEBER HAO JIN K. J. ET AL.: "Characterization of Low Pressure Chemical Vapour Deposited Si3N4 films.", DENIATION RENEWABLES-ANZSES, 2006, pages 1 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018181885A (en) * 2017-04-03 2018-11-15 住友電気工業株式会社 Method of forming silicon nitride passivation film and method of manufacturing semiconductor device

Also Published As

Publication number Publication date
JP6931208B2 (en) 2021-09-01
CN107533974B (en) 2022-03-18
US9580304B2 (en) 2017-02-28
JP2018515926A (en) 2018-06-14
US10026817B2 (en) 2018-07-17
US20170133472A1 (en) 2017-05-11
CN107533974A (en) 2018-01-02
US20160325987A1 (en) 2016-11-10

Similar Documents

Publication Publication Date Title
US10026817B2 (en) Low-stress low-hydrogen LPCVD silicon nitride
US9142643B2 (en) Method for forming epitaxial feature
US9349831B2 (en) Integrated circuit device with well controlled surface proximity and method of manufacturing same
CN102549755B (en) There is semiconductor device and the manufacture method thereof of oxygen diffusion impervious layer
KR101600553B1 (en) Methods for fabricating mos devices having epitaxially grown stress-inducing source and drain regions
US20110101421A1 (en) Method of forming epi film in substrate trench
US8802523B2 (en) CMOS device and fabrication method
US8343872B2 (en) Method of forming strained structures with compound profiles in semiconductor devices
US7435657B2 (en) Method of fabricating transistor including buried insulating layer and transistor fabricated using the same
US9362402B2 (en) Semiconductor devices and fabrication method thereof
TWI831182B (en) Method for making semiconductor device
US10163724B2 (en) Integrated circuit device and method of manufacturing same
US10868133B2 (en) Semiconductor device structure and method for forming the same
KR101799647B1 (en) Semiconductor device and manufacturing method thereof
US9966466B2 (en) Semiconductor-on-insulator wafer, semiconductor structure including a transistor, and methods for the formation and operation thereof
CN101512771A (en) Semiconductor structure with enhanced performance using simplified dual stress liner configuration
CN105719971B (en) The forming method of semiconductor devices
KR20090071605A (en) Manufacturing Method of Semiconductor Device and Semiconductor Device
US11757020B2 (en) Semiconductor device and method
WO2007035660A1 (en) Method to form a device on a soi substrate
JP2007165532A (en) Manufacturing method of semiconductor device
KR101204586B1 (en) Method of forming EPI film in substrate trench
KR20090127439A (en) Thin film and manufacturing method of semiconductor device using the thin film
KR20090068465A (en) Manufacturing method of semiconductor device

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 16790236

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2017558375

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 16790236

Country of ref document: EP

Kind code of ref document: A1