WO2016174908A1

WO2016174908A1 - Power module

Info

Publication number: WO2016174908A1
Application number: PCT/JP2016/055320
Authority: WO
Inventors: 雅明山田; 史聖川原
Original assignee: 株式会社村田製作所
Priority date: 2015-04-28
Filing date: 2016-02-24
Publication date: 2016-11-03
Also published as: JPWO2016174908A1; JP6365772B2

Abstract

An electrode 141b is formed on an upper surface of an insulating substrate 14a constituting a main substrate 14, and electrodes 161b and 162b are formed on an upper surface and lower surface, respectively, of an insulating substrate 16a constituting a sub-substrate 16. A resist film is formed on the upper surface of the insulating substrate 14a constituting the main substrate 14 so that the electrode 141b is at least partially exposed. The sub-substrate 16 is layered onto the main substrate 14 so that the electrode 162b is in surface contact with the electrode 141b. Power semiconductor elements 18a, 18b are mounted on the main substrate 14. At this time, the power semiconductor element 18a is connected between the electrode 161b and a separate electrode (not shown), and the power semiconductor element 18b is connected between the electrode 141b (162b) and an electrode 143b.

Description

Power module

The present invention relates to a power module, and more particularly to a power module in which an electrode is formed on an insulating substrate and a semiconductor element is mounted.

According to the disclosure of Patent Document 1, the first wide conductor 16 connected to the positive electrode side of the DC power source and the second wide conductor 17 connected to the negative electrode side of the DC power source are interposed via the insulator 15 and They are stacked so that the direction of current flow is opposed. Thereby, the inductance is offset and the wiring inductance inside the package is reduced.

JP 2001-77260 A (see paragraphs 0026 and 0030)

In order to maintain sufficient insulation between the first wide conductor 16 and the second wide conductor 17, the thickness of the insulator 15 is made larger than the thickness of each of the first wide conductor 16 and the second wide conductor 17. It needs to be thick. However, a specific structure for realizing this is not disclosed. In particular, in the field of power modules, a lead frame is employed for manufacturing the power module, and therefore, a wide conductor forming a positive electrode wiring and a wide conductor forming a negative electrode wiring are stacked in the thickness direction. Is not easy.

Therefore, a main object of the present invention is to provide a power module that can reduce parasitic inductance and ensure insulation between wires.

A power module according to the present invention includes an insulating substrate, a first electrode, a second electrode, and a third electrode formed on the insulating substrate, and a first semiconductor element connected between the first electrode and the second electrode. A second semiconductor element connected between the second electrode and the third electrode, and a first lead terminal, a second lead terminal and a third lead connected to the first electrode, the second electrode and the third electrode, respectively. A resin mold type power module in which at least one of the first semiconductor element and the second semiconductor element is formed of a semiconductor switch element, wherein the insulating substrate is a main-side insulating substrate and a sub-side insulating substrate. The third electrode includes a main-side third electrode and a sub-side third electrode; the second electrode and the main-side third electrode are formed on the main surface of the main-side insulating substrate; and the first electrode and the sub-side third electrode Electrode A resist film formed on each of the opposing main surfaces of the main insulating substrate, and formed on the main surface of the main insulating substrate so that at least part of the main third electrode is exposed; The side insulating substrate is characterized in that it is laminated on the main insulating substrate so that the sub-side third electrode is in surface contact with the main third electrode.

Since the first semiconductor element and the second semiconductor element are sandwiched between the first electrode and the third electrode, the first electrode and the third electrode can be used as a part of the opposing current path. Based on this, the third electrode includes a main-side third electrode and a sub-side third electrode, and the first electrode and the sub-side third electrode are respectively formed on both main surfaces of the sub-side insulating substrate. As a result, the parasitic inductance of the circuit having the opposing current path can be reduced, and the insulation between the wirings forming the opposing current path can be ensured.

Further, considering that the resist film is formed on the main surface of the main-side insulating substrate so that at least a part of the main-side third electrode is exposed, the sub-side third substrate has the sub-side third electrode as the main. The main side insulating substrate is laminated so as to be in surface contact with the side third electrode. Accordingly, it is possible to reduce the concern that the electrical connection between the main-side third electrode and the sub-side third electrode becomes defective due to warpage of the main-side insulating substrate or the sub-side insulating substrate.

Preferably, the sub-side insulating substrate is made of the same material as the main-side insulating substrate. As a result, it is possible to reduce the concern that the warp stress generated during the resin molding shifts between the sub-side insulating substrate and the main-side insulating substrate.

Preferably, each of the first semiconductor element and the second semiconductor element is a switch element, and a first capacitor is connected between the first lead terminal and the third lead terminal, and the LC filter includes an inductor and a second capacitor. Is connected to the second lead terminal and performs power conversion between the first lead terminal and the second lead terminal. Thus, a step-up / down converter is realized.

Preferably, the first semiconductor element and the second semiconductor element are a rectifier element and a switch element, respectively, and an inductor is connected to the second lead terminal, and input between the second lead terminal and the third lead terminal via the inductor. A voltage is applied, and the first lead terminal is used as an output terminal. Thereby, a boost converter is realized.

Preferably, the first semiconductor element and the second semiconductor element are a switch element and a rectifier element, respectively, an input voltage is applied between the first lead terminal and the third lead terminal, and an LC filter composed of an inductor and a capacitor is formed. It is connected to the second lead terminal. Thereby, a step-down converter is realized.

According to the present invention, the parasitic inductance of a circuit having opposing current paths can be reduced, and insulation between wirings forming the opposing current paths can be ensured. Further, it is possible to reduce the concern that the electrical connection between the main-side third electrode and the sub-side third electrode becomes defective due to the warp of the main-side insulating substrate or the sub-side insulating substrate.

The above object, other objects, features, and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.

It is an illustration figure which shows the state which saw through the power module of this Example from the upper side. (A) is a cross-sectional view showing the AA ′ cross section of the power module shown in FIG. 1, and (B) is a perspective view of the power module seen from the BB ′ cross section toward the positive side in the Y-axis direction. FIG. (A) is a top view showing the upper surface of the main board constituting the power module shown in FIG. 1, and (B) is a bottom view showing the lower surface of the main board. FIG. 1A is a top view showing an upper surface of a sub-board constituting the power module in FIG. 1, and FIG. 1B is a bottom view showing a lower surface of the sub-board. It is an illustration figure which shows an example of the structure of the laminated substrate formed by laminating | stacking a sub board | substrate on a main board | substrate. (A) is an illustrative view showing an example of a process for preparing an insulating substrate as a main substrate, (B) is an illustrative view showing an example of a process for forming an electrode on the upper surface of the insulating substrate, (C ) Is an illustrative view showing an example of a step of forming an electrode on the lower surface of the main-side insulating substrate, and (D) is an example of a step of forming a resist film on the upper surface of the main-side insulating substrate on which the electrode is formed. It is an illustration figure shown. (A) is an illustrative view showing an example of a process for preparing an insulating substrate as a sub-substrate, (B) is an illustrative view showing an example of a process for forming an electrode on the upper surface of the insulating substrate, (C ) Is an illustrative view showing an example of a process of forming an electrode on the lower surface of the main-side insulating substrate, (D) is an illustrative view showing an example of a process of laminating a sub-substrate on the main substrate, and (E) is It is an illustration figure which shows an example of the process of mounting a semiconductor element on a laminated substrate, (F) is an illustration figure which shows an example of the process of connecting a semiconductor element to an electrode with a bonding wire. (A) is an illustrative view showing an example of a process of connecting a lead terminal to a laminated substrate, and (B) is an illustrative view showing an example of a process of molding the laminated substrate and a part of the lead terminal with a resin. It is a circuit diagram which shows the equivalent circuit of the power module of this Example. It is a circuit diagram which shows an example of the buck-boost converter to which the power module of this Example was applied. It is a circuit diagram which shows an example of the boost converter to which the power module of the other Example was applied. It is a circuit diagram which shows an example of the step-down converter to which the power module of the other Example was applied. It is a circuit diagram which shows an example of the circuit formed by connecting the several power module which concerns on this Example.

Referring to FIGS. 1 and 2A to 2B, the power module 10 of this embodiment includes a high-side power semiconductor element 18a and a low-side power semiconductor element 18b mounted on a laminated substrate 12. The power signal wide lead terminals 22a to 22f and the control signal narrow lead terminals 22g to 22h are connected to the multilayer substrate 12, and a part of each of the multilayer substrate 12 and each of the lead terminals 22a to 22h Is molded by resin 26.

1 shows a state where the power module 10 is seen through from above, FIG. 2 (A) shows an AA ′ section of the power module 10, and FIG. 2 (B) shows a power module 10 along the BB ′ section. A state seen through from the lead terminals 22a to 22d side is shown.

The laminated substrate 12 is formed by laminating the sub substrate 16 shown in FIGS. 4A to 4B on the upper surface of the main substrate 14 shown in FIGS. 3A to 3B. The upper surface or the lower surface of the main substrate 14 has a rectangular shape close to a square, and the upper surface or the lower surface of the sub substrate 16 has an elongated rectangular shape. Further, the length of the long side of the rectangle formed by the upper surface or the lower surface of the sub-board 16 matches the length of the long side of the rectangle formed by the upper surface or the lower surface of the main substrate 14. Further, the length of the short side of the rectangle formed by the upper surface or the lower surface of the sub substrate 16 is much shorter than the length of the short side of the rectangle formed by the upper surface or the lower surface of the main substrate 14.

In the following, the X axis is assigned along the long side of the rectangle formed by the upper surface or the lower surface of the main substrate 14, and the Y axis is assigned along the short side of the rectangle formed by the upper surface or the lower surface of the main substrate 14. The Z axis is assigned in a direction perpendicular to the upper surface or the lower surface. Further, the surface facing the positive side in the Z-axis direction is the “upper surface”, and the surface facing the negative side in the Z-axis direction is the “lower surface”.

Referring to FIGS. 3A to 3B, main substrate 14 has a ceramic insulating substrate 14a as a base material. The electrodes 141b to 143b are formed at predetermined positions on the upper surface of the insulating substrate 14a. The electrode 144b is formed over almost the entire lower surface of the insulating substrate 14a. The resist film 14c is formed on the upper surface of the insulating substrate 14a so as to partially cover the electrodes 141b to 143b. The electrodes 141b to 144b are all made of copper.

When the center of the upper surface of the insulating substrate 14a is the origin, the electrode 141b is exposed in a region R1 disposed in the vicinity of the positive side end in the X-axis direction and in the vicinity of the positive side end in the Y-axis direction, The region R2 is exposed in the vicinity of the negative end in the X-axis direction and in the vicinity of the positive end in the Y-axis direction. The electrode 141b is also exposed in a region R3 arranged so as to extend in the X-axis direction at the center position in the Y-axis direction, and is positioned slightly on the negative side in the X-axis direction and in the vicinity of the negative side end in the Y-axis direction. It is exposed in the region R4 arranged in the area.

Further, the electrode 142b is not covered with the resist film 14c, but is exposed in a region R5 disposed in the vicinity of the negative side end in the X-axis direction and in the vicinity of the negative side end in the Y-axis direction. The electrode 143b is exposed in a region R6 disposed near the positive end in the X-axis direction and near the negative end in the Y-axis direction, slightly on the positive side in the X-axis direction and in the Y-axis direction. It is exposed in a region R7 arranged in the vicinity of the negative side end portion.

In this embodiment, the electrode 142b is a dummy electrode. As can be seen from FIG. 2A, the electrode 144b formed on the lower surface of the insulating substrate 14a is exposed to the lower side of the power module 10 without being molded with the resin 26, and is accumulated on the laminated substrate 12. It functions as a heat sink that releases heat.

Referring to FIGS. 4A to 4B, sub-substrate 16 is made of a ceramic insulating substrate 16a as a base material. Strictly speaking, the material of the insulating substrate 16 a is the same as the material of the insulating substrate 14 a forming the main substrate 14. The electrode 161b is formed over almost the entire upper surface of the insulating substrate 16a, and the electrode 162b is formed over almost the entire lower surface of the insulating substrate 16a. That is, the

electrodes

161b and 162b are formed on both opposing main surfaces of the insulating substrate 16a, respectively. The electrodes 161b to 162b are also made of copper.

Referring to FIG. 5, the sub-board 16 is laminated on the main board 14 such that its lower surface faces the upper surface of the main board 14. At this time, the center of the lower surface of the sub substrate 16 is aligned with the center of the upper surface of the main substrate 14. The long side of the rectangle formed by the lower surface of the sub-substrate 16 is parallel to the long side of the rectangle formed by the upper surface of the main substrate 14. The electrode 162b formed on the sub-substrate 16 is opposed to the electrode 141b exposed in the region R3 of the main substrate 14, and is joined to the electrode 141b by solder. Of the four side surfaces forming the sub substrate 16, the two side surfaces orthogonal to the long side described above are flush with the two side surfaces orthogonal to the long side described above among the four side surfaces forming the main substrate 14.

As described above, the electrode 141b extends in the X-axis direction at the center position of the upper surface of the main substrate 14 in the Y-axis direction. The size of the electrode 162b matches the size of the electrode 141b thus formed. Therefore, when the sub-board 16 is stacked on the main board 14, the electrode 162b is in full surface contact with the electrode 141b, and in this state, the electrode 162b is soldered to the electrode 141b.

Returning to FIG. 1, the lead terminals 22a to 22f extend along the X axis, and the lead terminals 22g to 22h extend along the Y axis. Here, all of the lead terminals 22a to 22h are mainly made of copper.

The leading ends of the

lead terminals

22a and 22b are soldered to an electrode 141b provided on the main board 14, and the leading ends of the

lead terminals

22c and 22d are soldered to an electrode 161b provided on the sub-board 16. The leading end of the lead terminal 22e is soldered to an electrode 142b provided on the main board 14, and the leading end of the lead terminal 22f is soldered to an electrode 143b provided on the main board 14. Since the electrode 142b is a dummy electrode as described above, the lead terminal 22e is also a dummy terminal.

The power semiconductor element 18a is soldered to the electrode 143b exposed in the region R7 and connected to the electrode 161b by the bonding wire 20a. The power semiconductor element 18b is solder-bonded to the electrode 141b exposed in the region R4 and connected to the electrode 143b by a bonding wire 20b. Furthermore, the lead terminal 22g is connected to the power semiconductor element 18a by a bonding wire 24a, and the lead terminal 22h is connected to the power semiconductor element 18b by a bonding wire 24b. The bonding wires 20a to 20b and 24a to 24b are mainly made of gold, copper or aluminum.

As can be seen from FIG. 2A or FIG. 2B, the electrode 161b formed on the sub-substrate 16 has a larger Z than the electrodes 141b to 143b formed on the main substrate 14 by the thickness of the sub-substrate 16. It is arranged on the positive side in the axial direction. Accordingly, the tips of the

lead terminals

22c and 22d are connected to the electrode 161b in a state in which bending is performed to ensure an offset corresponding to the thickness of the sub-substrate 16.

The power module 10 is manufactured through the steps shown in FIGS. 6 (A) to 6 (D), FIGS. 7 (A) to 7 (F), and FIGS. 8 (A) to 8 (B).

First, an insulating substrate 14a that forms the main substrate 14 is prepared (see FIG. 6A). Next, the electrodes 141b to 143b are formed at predetermined positions on the upper surface of the insulating substrate 14a (see FIG. 6B), and the electrode 144b is formed over almost the entire lower surface of the insulating substrate 14a (FIG. 6C )reference). When the formation of the electrodes 141b to 144b is completed, a resist film 14c is formed at a predetermined position on one main surface of the insulating substrate 14a (see FIG. 6D). As a result, the electrode 141b is exposed in the regions R1 to R4, the electrode 142b is exposed in the region R5, and the electrode 143b is exposed in the regions R6 to R7. The main substrate 14 is completed by forming the resist film 14c.

Subsequently, an insulating substrate 16a that forms the sub-substrate 16 is prepared (see FIG. 7A). The electrode 161b is formed almost over the entire upper surface of the insulating substrate 16a (see FIG. 7B), and the electrode 162b is formed almost over the entire lower surface of the insulating substrate 16a (see FIG. 7C). Thereby, the sub-board 16 is completed.

The sub-board 16 is mounted on the main board 14 with the electrode 162b facing the electrode 141b exposed in the region R3 (see FIG. 7D). The electrode 162b is soldered to the electrode 141b. As a result, the center of the main surface of the sub substrate 16 is aligned with the center of the main surface of the main substrate 14, and the long side of the rectangle forming the main surface of the sub substrate 16 extends along the X axis.

Thus, when the multilayer substrate 12 is manufactured, the power semiconductor element 18a is soldered to the electrode 143b in the region R7, and the power semiconductor element 18b is soldered to the electrode 141b in the region R4 (see FIG. 7E). Power semiconductor element 18a is connected to electrode 161b by bonding wire 20a, and power semiconductor element 18b is connected to electrode 143b by bonding wire 20b (see FIG. 7F).

Subsequently, each of the

lead terminals

22a and 22b is soldered to the electrode 141b, each of the

lead terminals

22c and 22d is soldered to the electrode 161b, and each of the

lead terminals

22e and 22f is soldered to the

electrodes

142b and 143b, respectively ( (See FIG. 8A). The lead terminal 22g is connected to the power semiconductor element 18a by a bonding wire 24a, and the lead terminal 22h is connected to the power semiconductor element 18b by a bonding wire 24b (see FIG. 8A).

Thus, when the connection of the lead terminals 22a to 22h is completed, the laminated substrate 12 and a part of each of the lead terminals 22a to 22h are molded by the resin 26 (see FIG. 8B). When the resin 26 is cooled, the power module 10 is completed.

An equivalent circuit of the power module 10 thus manufactured is shown in FIG. The lead terminal 22c is connected to the lead terminal 22d via the parasitic inductance L1, and the lead terminal 22a is connected to the lead terminal 22b via the parasitic inductance L2. A parasitic capacitance C1 is formed between the

lead terminals

22d and 22b.

The

power semiconductor elements

18a and 18b are both semiconductor switch elements such as field effect transistors. The drain of the power semiconductor element 18a is connected to the lead terminal 22d, the source of the power semiconductor element 18a is connected to the drain of the power semiconductor element 18b, and the source of the power semiconductor element 18b is connected to the lead terminal 22b.

Further, the lead terminal 22f is connected to the source of the power semiconductor element 18a and the drain of the power semiconductor element 18b. Furthermore, the lead terminal 22g is connected to the gate of the power semiconductor element 18a, and the lead terminal 22h is connected to the gate of the power semiconductor element 18b.

As can be seen from the above description, the

electrodes

141b and 143b are formed on the upper surface of the insulating substrate 14a forming the main substrate 14, and the

electrodes

161b and 162b are formed on the upper and lower surfaces of the insulating substrate 16a forming the sub-substrate 16, respectively. The A resist film 14c is formed on the upper surface of the insulating substrate 14a forming the main substrate 14 so that at least a part of the electrode 141b is exposed. The sub substrate 16 is laminated on the main substrate 14 so that the electrode 162b is in surface contact with the electrode 141b.

Power semiconductor elements

18 a and 18 b are mounted on main board 14. At this time, the power semiconductor element 18a is connected between the electrode 161b and the electrode 143b, and the power semiconductor element 18b is connected between the electrode 141b (162b) and the electrode 143b.

Since the

power semiconductor elements

18a and 18b are sandwiched between the electrode 161b and the electrode 141b (162b), the electrode 161b and the electrode 141b (162b) can be used as a part of the opposing current path. Based on this, the electrode 161b is disposed on the upper surface side of the sub-substrate 16, and the electrode 141b (162b) is disposed on the lower surface side of the sub-substrate 16. As a result, the parasitic inductance of the circuit having the opposing current path can be reduced, and the insulation between the wirings forming the opposing current path can be ensured.

Further, considering that the resist film 14c is formed on the upper surface of the insulating substrate 14a forming the main substrate 14 so that at least a part of the electrode 141b is exposed, the sub-substrate 16 has the electrode 162b in surface contact with the electrode 141b. In this manner, the main board 14 is laminated. As a result, it is possible to reduce the concern that the electrical connection between the

electrodes

141b and 162b becomes defective due to the warp of the main board 14 or the sub board 16.

FIG. 10 shows a buck-boost converter using the power module 10 thus configured. According to FIG. 10, the lead terminal 22c is directly connected to the input / output terminal T1, and the lead terminal 22a is directly connected to the input / output terminal T2. The lead terminal 22f is connected to the input / output terminal T3 via the inductor L3, and the lead terminal 22b is directly connected to the input / output terminal T4. Furthermore, the lead terminal 22g is directly connected to the control terminal T5, and the lead terminal 22h is directly connected to the control terminal T6. The SW1 signal is applied to the control terminal T5, and the SW2 signal is applied to the control terminal T6. A capacitor C2 is provided between the input / output terminals T3 and T4, and a capacitor C3 is provided between the input / output terminals T1 and T2 (between the lead terminal 22c and the lead terminal 22a). The inductor L3 and the capacitor C2 constitute an LC filter.

When boosting is performed by the buck-boost converter thus configured, a positive voltage is applied to the input / output terminal T3 and a negative voltage is applied to the input / output terminal T4. The SW1 signal applied to the control terminal T5 is continuously set to the H level, and the SW2 signal applied to the control terminal T6 is repeatedly changed between the H level and the L level. As a result, a voltage higher than the voltage applied to the input / output terminal T3 is output from the input / output terminal T1. That is, power conversion is performed in the direction of increasing the voltage.

Conversely, when the voltage is stepped down by the buck-boost converter, a positive voltage is applied to the input / output terminal T1, and a negative voltage is applied to the input / output terminal T2. Further, the SW1 signal applied to the control terminal T5 is repeatedly changed between the H level and the L level, and the SW2 signal applied to the control terminal T6 is continuously set to the H level. As a result, a voltage lower than the voltage applied to the input / output terminal T1 is output from the input / output terminal T3. That is, power conversion is performed in the direction of decreasing the voltage.

When the power module 10 is used as a boost converter, the power semiconductor element 18a can be replaced with a diode D1 as shown in FIG. When the power module 10 is used as a step-down converter, the power semiconductor element 18b can be replaced with a diode D2 as shown in FIG. According to FIG. 11, the input voltage is applied to terminals T3 and T4, and the boosted voltage is output from terminals T1 and T2. Further, according to FIG. 12, the input voltage is applied to the terminals T1 and T2, and the stepped down voltage is output from the terminals T3 and T4.

Furthermore, as shown in FIG. 13, a plurality of

power modules

10, 10,... In this case, in any power module 10, the opposing current flows through the

electrodes

161 b and 162 b on the sub-substrate 16. As a result, in all of the connected

power modules

10, 10,..., Parasitic inductance can be reduced, and insulation between wirings forming opposing current paths can be ensured.

In this embodiment, when the sub-board 16 is laminated on the main board 14, the size of the electrode 162b is set so that the electrode 162b on the sub-board 16 is in full surface contact with the electrode 141b on the main board 14. 14 is made to coincide with the size of the electrode 141b provided in the region 14 exposed from the region R3.

However, even when the size of the electrode 141b is larger than the size of the electrode 162b, the electrode 162b is in full surface contact with the electrode 141b. Therefore, the size of the

electrodes

141b and 162b only needs to satisfy the condition that the electrode 162b fits on the outer edge of the electrode 141b when viewed from the Z-axis direction.

DESCRIPTION OF SYMBOLS 10 ... Power module 12 ... Laminated board 14 ... Main board 16 ... Sub board 14a ... Insulating board (main side insulating board)
14c: Resist film 141b: Electrode (main-side third electrode forming the third electrode)
143b ... Electrode (second electrode)
16a: Insulating substrate (sub-side insulating substrate)
161b ... Electrode (first electrode)
162b ... Electrode (sub-side third electrode forming the third electrode)
18a: Power semiconductor element (first semiconductor element)
18b: Power semiconductor element (second semiconductor element)
22a, 22b ... Lead terminal (third lead terminal)
22c, 22d ... Lead terminal (first lead terminal)
22f ... Lead terminal (second lead terminal)
C1 ... Parasitic capacitance C2 ... Capacitor (second capacitor)
C3: Capacitor (first capacitor)
L3: Inductor D1, D2: Diode (rectifier element)

Claims

An insulating substrate;
A first electrode, a second electrode and a third electrode formed on the insulating substrate;
A first semiconductor element connected between the first electrode and the second electrode;
A second semiconductor element connected between the second electrode and the third electrode;
A first lead terminal, a second lead terminal and a third lead terminal connected to the first electrode, the second electrode and the third electrode, respectively;
With
A resin mold type power module in which at least one of the first semiconductor element and the second semiconductor element is a semiconductor switch element;
The insulating substrate includes a main-side insulating substrate and a sub-side insulating substrate,
The third electrode includes a main-side third electrode and a sub-side third electrode,
The second electrode and the main third electrode are formed on a main surface of the main insulating substrate;
The first electrode and the sub-side third electrode are respectively formed on both opposing main surfaces of the sub-side insulating substrate;
A resist film formed on the main surface of the main-side insulating substrate so that at least a part of the main-side third electrode is exposed;
The power module, wherein the sub-side insulating substrate is laminated on the main-side insulating substrate so that the sub-side third electrode is in surface contact with the main-side third electrode.
The power module according to claim 1, wherein the sub-side insulating substrate is made of the same material as that of the main-side insulating substrate.
The first semiconductor element and the second semiconductor element are both switch elements,
A first capacitor is connected between the first lead terminal and the third lead terminal,
An LC filter composed of an inductor and a second capacitor is connected to the second lead terminal,
The buck-boost converter using the power module according to claim 1 or 2, wherein power conversion is performed between the first lead terminal and the second lead terminal.
The first semiconductor element and the second semiconductor element are a rectifier element and a switch element, respectively.
An inductor is connected to the second lead terminal;
An input voltage is applied between the second lead terminal and the third lead terminal via the inductor,
The boost converter using the power module according to claim 1, wherein the first lead terminal is an output terminal.
The first semiconductor element and the second semiconductor element are a switch element and a rectifier element, respectively.
An input voltage is applied between the first lead terminal and the third lead terminal,
The step-down converter using the power module according to claim 1 or 2, wherein an LC filter including an inductor and a capacitor is connected to the second lead terminal.