WO2016137030A1 - Method for enhancing performance of plasma-wave transistor - Google Patents

Method for enhancing performance of plasma-wave transistor Download PDF

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Publication number
WO2016137030A1
WO2016137030A1 PCT/KR2015/001821 KR2015001821W WO2016137030A1 WO 2016137030 A1 WO2016137030 A1 WO 2016137030A1 KR 2015001821 W KR2015001821 W KR 2015001821W WO 2016137030 A1 WO2016137030 A1 WO 2016137030A1
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nano
wire
transistor
gate electrode
plasma
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French (fr)
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Yang-Kyu Choi
Kyung Rok Kim
Chang-Hoon Jeon
Dong-il MOON
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Korea Advanced Institute of Science and Technology KAIST
UNIST Academy Industry Research Corp
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Korea Advanced Institute of Science and Technology KAIST
UNIST Academy Industry Research Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/43—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6735—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes having gates fully surrounding the channels, e.g. gate-all-around
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H10D62/118—Nanostructure semiconductor bodies
    • H10D62/119—Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/121—Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/205—Nanosized electrodes, e.g. nanowire electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/096—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by contacting with gases, liquids or plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions

Definitions

  • the present invention relates to a method for enhancing the performance of a plasma-wave transistor (PWT) for the applications of the plasma-wave transistor, and more particularly, to a method for evaluating the performance of a plasma-wave transistor, which amplifies plasma-wave emission through the increase of the electron mobility of a nano-wire, thereby determining whether or not the plasma-wave transistor operates in a terahertz (THz) band.
  • PWT plasma-wave transistor
  • a terahertz frequency range refers to a frequency ranging from 10 11 Hz to 10 13 Hz (from 0.1THz to 10THz).
  • a terahertz wave is an electromagnetic wave resource corresponding to a frequency band between a millimeter wave obtained by using a conventional semiconductor transistor and a far-infrared radiation electromagnetic wave obtained by using semiconductor laser. Since a reliable optical or electronic device has not been developed, less research has been devoted to the terahertz band in comparison with an electromagnetic wave in another wavelength band.
  • Embodiments are intended to overcome the above disadvantages and other disadvantages not described above.
  • the present inventive concept provides a method for enhancing the performance of a plasma-wave transistor, which applies the existing silicon manufacturing process at it is and more easily manufactures a silicon device operating in a terahertz band, so that it is possible to evaluate whether or not the silicon device operates as the plasma-wave transistor.
  • One embodiment is a method for enhancing the performance of a transistor comprising: forming a nano-wire on a substrate, applying strain to the nano-wire to bend the nano-wire, forming a source electrode, a drain electrode and a gate electrode, manufacturing a transistor including the bent nano-wire formed by the applying of the strain, and source electrode, drain electrode and gate electrode formed by the forming of the electrodes.
  • the method may further include evaluating whether or not the transistor operates in a predetermined band.
  • the forming the electrodes may form a grating gate having two gate electrodes.
  • the applying the strain may bend the nano-wire by forming a natural oxide layer.
  • the transistor may be a plasma-wave transistor.
  • the predetermined band may range from 10 11 Hz to 10 13 Hz (from 0.1THz to 10THz.)
  • the nano-wire may be made of at least any one selected from the group consisting of Si, Ge, Sn, Se, Te, B, C, B-Si, Si-C, Si-Ge, Si-Sn, Ge-Sn, SiC, BN/BP/BAs, AIN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SeTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, CuI, AgF, AgCl, AgBr, AgI, Be
  • the length of the gate electrode may be greater than 20 nm.
  • a silicon device may be more easily manufactured which operates in a terahertz band. Also, it is possible to evaluate whether or not the silicon device operates as the plasma-wave transistor.
  • FIG. 1 illustrates a view for comparing a field effect transistor (FET) with a plasma-wave transistor (PWT).
  • FET field effect transistor
  • PWT plasma-wave transistor
  • FIG. 2 illustrates a flowchart showing a method for enhancing the performance of the transistor in accordance with an embodiment of the present invention.
  • FIG. 3 illustrates a configuration of the transistor manufactured by the method according to the embodiment of the present invention.
  • FIG. 4 illustrates an enlarged view of a nano-wire which is an element of the transistor manufactured by the method according to the embodiment of the present invention.
  • FIG. 5 illustrates a graph of electron mobility variation according to a temperature.
  • FIG. 6 illustrates a graph for evaluating the performance of the plasma-wave transistor.
  • FIG. 1 is a view for comparing a field effect transistor (FET) with a plasma-wave transistor (PWT).
  • FET field effect transistor
  • PWT plasma-wave transistor
  • the field-effect transistor controls current by using an electric field, and, as shown in (a) of FIG. 1, includes three electrodes; a source electrode, a drain electrode and a gate electrode.
  • a channel is formed on a doped silicon substrate by applying a voltage higher than a threshold voltage to a gate electrode, and electrons or holes are allowed to flow through the formed channel by using the voltage difference between the source electrode and the drain electrode.
  • channel electrons move individually with being scattered by lattices or ions while they are moving from the source electrode to the drain electrode.
  • the electrons move, as shown in (b) of FIG. 1, in a collective way. That is, a collective spatio-temporal variation of the electron density occurs in a certain boundary condition. It is called a plasma-wave which has a velocity 10 to 100 times faster than the local electron drift velocity.
  • the local electron drift velocity refers to an average velocity of the local electron while passing through the channel.
  • the plasma-wave transistor using the principle above has a velocity about 10 to 100 times faster than the velocity of the conventional field-effect transistor. Therefore, a frequency band for the transistor may be extended to a terahertz band.
  • An existing technique for enhancing the velocity of a silicon device and an existing technology for enhancing the performance of an ultra high frequency depend on how fast the electron that forms the channel moves.
  • the terahertz band having a lot of advantages such as the coexistence of straightness of a light wave (light) and transmittance of an electric wave, harmlessness to a human body due to the low energy, etc., can be variously applied to an ultra-high speed/high-capacity communication in an ultra high frequency band, etc., on the basis of an imaging technique, a spectroscopic technique, or the like.
  • the electron mobility of the silicon device is about 250cm 2 /Vs at a room temperature (approximately 25°C or 298.15K). To achieve terahertz emission by using such a degree of the electron mobility, the length of the gate electrode should be extremely shortened.
  • the electron mobility is a measure of how easily electrons drift. Through the electron mobility, it can be understood how much the local electron drift velocity is increased in proportion to an electric field.
  • the method for enhancing the performance of the plasma-wave transistor according to the embodiment of the present invention achieves the terahertz emission even though the length of the gate electrode is relatively large, thereby making it easier to evaluate whether the transistor operates in the terahertz band.
  • the length of the gate electrode should be as short as about 5 nm.
  • the method for enhancing the performance of the plasma-wave transistor according to the embodiment of the present invention increases the electron mobility by applying strain to a nano-wire and bending it. That is, it is possible to bend the nano-wire by applying a physical or chemical force to the nano-wire, resulting in the increase of the electron mobility as described below.
  • One embodiment to bend the nano-wire is to grow a natural oxide layer on the nano-wire.
  • the electron mobility is increased to about 1000cm2/Vs at a room temperature due to the applied strain.
  • the electron mobility is increased by employing the above principle, the terahertz emission can be achieved even though the length of the gate electrode is greater than 20nm.
  • the method for enhancing the performance of the plasma-wave transistor according to the embodiment of the present invention increases the electron mobility by using the strain at the time of fabricating the natural oxide layer on the nano-wire and manufactures the transistor that includes the gate electrode with an enough length to be patterned by the current patterning technology, so that the evaluation of the performance of the plasma-wave transistor can be easily made.
  • FIG. 2 illustrates a flowchart showing the method for enhancing the performance of the transistor in accordance with the embodiment of the present invention.
  • the nano-wire is formed on a substrate (S100).
  • the nano-wire is bent by applying the strain to the nano-wire(S110).
  • An oxide layer process may be representatively taken as an example of the method for applying the strain to the nano-wire.
  • the nano-wire may be bent by another method.
  • the source electrode and the drain electrode are formed at both ends of the nano-wire before the gate electrode is formed (S120).
  • a transistor having the bent nano-wire channel is manufactured by adding a general transistor manufacturing process with the inclusion of S100 to S120 (S130).
  • the transistor is manufactured which includes the nano-wire, the source electrode, the drain electrode and the gate electrode which have been formed through the steps of S100 to S120.
  • step S140 evaluates whether or not the transistor manufactured in the step S130 operates in a predetermined band (S140). The evaluation the step S140 will be described in more detail with reference to FIG. 6.
  • the manufacturing step S130 in the method for enhancing the performance of the transistor according to the embodiment of the present invention includes the steps from S100 to S120.
  • the steps from S100 to S120 are not necessarily performed in sequence. That is, the order of S100 to S120 may be changed, or an extra common transistor manufacturing process may be added between each of the steps.
  • FIG. 2 includes the step S140 of evaluating the transistor, it will be apparent to those skilled in the art that the performance of the transistor can be enhanced only by up to the step S130.
  • FIG. 3 illustrates a configuration of the transistor manufactured by the method according to the embodiment of the present invention.
  • FIG. 4 illustrates an enlarged view of the nano-wire which is an element of the transistor manufactured by the method according to the embodiment of the present invention.
  • the transistor manufactured by the method for enhancing the performance of the plasma-wave transistor according to the embodiment of the present invention includes a substrate 10, a drain electrode 20, a source electrode 30, a nano-wire 40 and a gate electrode 50.
  • the gate electrode 50 is illustrated as a grating gate electrode having a first gate electrode 52 and a second gate electrode 54.
  • the transistor that is used in the method for enhancing the performance of the plasma-wave transistor according to the embodiment of the present invention has the nano-wire channel bent by the steps; forming the nano-wire 40 on the substrate 10 and applying the strain to the nano-wire 40. Subsequently, each of the electrodes 20, 30 and 50 is formed.
  • the gate electrode 50 may be the grating gate electrode including the two gate electrodes 52 and 54.
  • the gate electrode 50 is not necessarily implemented by the grating gate electrode.
  • the measurement of the plasma wave emission by using the gate electrode employs a principle in which, when the plasma wave excited in the channel is transmitted as a mirror image wave to the gate electrode and dipoles are generated, an electromagnetic wave is radiated in the air in the form of free radiation, and then the electric power of the radiated electromagnetic wave is measured.
  • the gate electrode 50 has the two electrodes 52 and 54. However, it can be considered that the gate electrode 50 includes more than two electrodes.
  • the grating gate electrode 50 is formed to surround the bent nano-wire 40.
  • the first gate electrode 52 and second gate electrode 54 constituting the grating gate electrode 50 include a longitudinal base and a plurality of protrusions which protrude perpendicularly to the base.
  • the protrusion of the first gate electrode 52 and the protrusion of the second gate electrode 54 are spaced from each other at a predetermined distance so as not to contact each other and are inserted opposite to each other.
  • the shape of the grating gate electrode 50 illustrated in FIG. 3 is no more than one embodiment, and the grating gate electrode 50 may have a shape different from the shape shown in FIG. 3.
  • the method for enhancing the performance of the plasma-wave transistor according to the embodiment of the present invention may further include forming an insulation spacer.
  • the nano-wire 40 may be made of any one selected from the group consisting of Si, Ge, Sn, Se, Te, B, C, B-Si, Si-C, Si-Ge, Si-Sn, Ge-Sn, SiC, BN/BP/BAs, AIN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SeTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, CuI, AgF, AgCl, AgBr, AgI, Be
  • FIG. 5 illustrates a graph of electron mobility variation according to a temperature.
  • the electron mobility of the silicon device is about 250cm2/Vs at a room temperature (approximately 25°C or 298.15K.)
  • the length of the gate electrode should be as short as about 5nm.
  • the length of the gate electrode can be relatively longer, so that it becomes easier to manufacture the gate electrode.
  • the silicon device In case of manufacturing the silicon device with the nano-wire bent by applying the strain, the silicon device has a high electron mobility represented by two lines (a line (d) and a line (f)) in the top part of FIG. 5.
  • L means the length of the nano-wire
  • W means the diameter of the nano-wire.
  • the transistor manufactured by the method for enhancing the performance of the plasma-wave transistor according to the embodiment of the present invention includes the bent nano-wire channel, so that the transistor has a higher electron mobility at a room temperature.
  • the nano-wire channel of the transistor manufactured by the method for enhancing the performance of the plasma-wave transistor according to the embodiment of the present invention has a higher electron mobility
  • the length of the gate electrode can be implemented within a technical scope of the current technology.
  • FIG. 6 illustrates a graph for evaluating the performance of the plasma-wave transistor.
  • the local electron drift velocity is plotted on the x-axis
  • the plasma wave velocity is plotted on the y-axis
  • the channel length is plotted on the z-axis.
  • the method for enhancing the performance of the plasma-wave transistor generates a design window including a relational expression between the x-axis, y-axis and z-axis, and measures whether or not the manufactured transistor operates as a terahertz emitter in accordance with the change of a performance parameter value of the manufactured transistor.
  • the design window 3-dimensionally represents the change of emission boundary according to the channel mobility and channel length at the same time, and thus, decides the range of the channel length ensuring a function as a terahertz emitter, the range of the plasma wave velocity and the range of the electron drift velocity.
  • the emission boundary of the design window changes according to the channel mobility and channel length
  • the design window may be generated by the performance parameter corresponding to the point of the emission boundary acquired by a user's input. That is, prior to the real plasma-wave transistor process and experiment, a parameter suitable for the channel mobility or channel length, which should be confirmed experimentally and obtained later, is assumed, and then the calculated momentum relaxation time and the calculated injection velocity are input to the relational expression between the x-axis, y-axis and z-axis, so that the design window can be generated.
  • the performance of the plasma-wave transistor that operates as a terahertz emitter can be evaluated by checking the plasma-wave velocity and the electron drift velocity in the design window.
  • the design window may be designed to include a physical condition satisfying the mathematical formula "(plasma-wave velocity - electron drift velocity) x momentum relaxation time > channel length" which uses a property that the emission of the terahertz emitter is caused by the multiple reflection.
  • the electron mobility can be increased to 1000cm2/Vs by using the nano-wire bent by the strain.
  • the length of the gate electrode can be increased to the range that enables the terahertz emission, so that it becomes easier to evaluate whether or not the terahertz emission occurs.

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Abstract

The method for enhancing the performance of a transistor may be provided that includes forming a nano-wire on a substrate, applying strain to the nano-wire to bend the nano-wire, forming a source electrode, a drain electrode and a gate electrode, and manufacturing a transistor including the bent nano-wire formed by the applying of the strain, and source electrode, drain electrode and gate electrode formed by the forming of the electrodes. Through the above configuration, a silicon device that operates in a terahertz band can be more easily manufactured, and it is possible to evaluate whether or not the silicon device operates as a plasma-wave transistor.

Description

METHOD FOR ENHANCING PERFORMANCE OF PLASMA-WAVE TRANSISTOR
The present invention relates to a method for enhancing the performance of a plasma-wave transistor (PWT) for the applications of the plasma-wave transistor, and more particularly, to a method for evaluating the performance of a plasma-wave transistor, which amplifies plasma-wave emission through the increase of the electron mobility of a nano-wire, thereby determining whether or not the plasma-wave transistor operates in a terahertz (THz) band.
A terahertz frequency range refers to a frequency ranging from 1011Hz to 1013Hz (from 0.1THz to 10THz). A terahertz wave is an electromagnetic wave resource corresponding to a frequency band between a millimeter wave obtained by using a conventional semiconductor transistor and a far-infrared radiation electromagnetic wave obtained by using semiconductor laser. Since a reliable optical or electronic device has not been developed, less research has been devoted to the terahertz band in comparison with an electromagnetic wave in another wavelength band.
Up to the present time, it has been believed that a silicon electron moves with vibration at a frequency of gigahertz and cannot moves with vibration at a frequency higher than gigahertz. Due to such a limitation of a silicon semiconductor, current electronic products can use only a frequency up to the gigahertz range. In order to overcome the limitation of the silicon device, a compound semiconductor is now being developed. However, the compound semiconductor requires a very high cost and is not able to use the existing cutting-edge silicon manufacturing process.
Embodiments are intended to overcome the above disadvantages and other disadvantages not described above. The present inventive concept provides a method for enhancing the performance of a plasma-wave transistor, which applies the existing silicon manufacturing process at it is and more easily manufactures a silicon device operating in a terahertz band, so that it is possible to evaluate whether or not the silicon device operates as the plasma-wave transistor.
One embodiment is a method for enhancing the performance of a transistor comprising: forming a nano-wire on a substrate, applying strain to the nano-wire to bend the nano-wire, forming a source electrode, a drain electrode and a gate electrode, manufacturing a transistor including the bent nano-wire formed by the applying of the strain, and source electrode, drain electrode and gate electrode formed by the forming of the electrodes.
The method may further include evaluating whether or not the transistor operates in a predetermined band.
The forming the electrodes may form a grating gate having two gate electrodes.
The applying the strain may bend the nano-wire by forming a natural oxide layer.
The transistor may be a plasma-wave transistor.
The predetermined band may range from 1011Hz to 1013Hz (from 0.1THz to 10THz.)
The nano-wire may be made of at least any one selected from the group consisting of Si, Ge, Sn, Se, Te, B, C, B-Si, Si-C, Si-Ge, Si-Sn, Ge-Sn, SiC, BN/BP/BAs, AIN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SeTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, CuI, AgF, AgCl, AgBr, AgI, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu,Ag)(Al,Ga,In,Tl,Fe)(S,Se,Te)2, Si3N4, Ge3N4, Al2O3, (Al,Ga,In)2, (S,Se,Te)3 and Al2CO.
The length of the gate electrode may be greater than 20 nm.
Through a method for enhancing the performance of a plasma-wave transistor according to various embodiments of the present invention, a silicon device may be more easily manufactured which operates in a terahertz band. Also, it is possible to evaluate whether or not the silicon device operates as the plasma-wave transistor.
FIG. 1 illustrates a view for comparing a field effect transistor (FET) with a plasma-wave transistor (PWT).
FIG. 2 illustrates a flowchart showing a method for enhancing the performance of the transistor in accordance with an embodiment of the present invention.
FIG. 3 illustrates a configuration of the transistor manufactured by the method according to the embodiment of the present invention.
FIG. 4 illustrates an enlarged view of a nano-wire which is an element of the transistor manufactured by the method according to the embodiment of the present invention.
FIG. 5 illustrates a graph of electron mobility variation according to a temperature.
FIG. 6 illustrates a graph for evaluating the performance of the plasma-wave transistor.
Hereafter, embodiments of the present invention will be described in greater detail with reference to the accompanying drawings.
FIG. 1 is a view for comparing a field effect transistor (FET) with a plasma-wave transistor (PWT).
The field-effect transistor (FET) controls current by using an electric field, and, as shown in (a) of FIG. 1, includes three electrodes; a source electrode, a drain electrode and a gate electrode.
Briefly describing the operation principle of the field-effect transistor, a channel is formed on a doped silicon substrate by applying a voltage higher than a threshold voltage to a gate electrode, and electrons or holes are allowed to flow through the formed channel by using the voltage difference between the source electrode and the drain electrode.
In general, according to the theory of the field-effect transistor, it is described that channel electrons move individually with being scattered by lattices or ions while they are moving from the source electrode to the drain electrode.
However, when the density of the channel electrons exceeds a certain level, the electrons move, as shown in (b) of FIG. 1, in a collective way. That is, a collective spatio-temporal variation of the electron density occurs in a certain boundary condition. It is called a plasma-wave which has a velocity 10 to 100 times faster than the local electron drift velocity. The local electron drift velocity refers to an average velocity of the local electron while passing through the channel.
The plasma-wave transistor using the principle above has a velocity about 10 to 100 times faster than the velocity of the conventional field-effect transistor. Therefore, a frequency band for the transistor may be extended to a terahertz band.
An existing technique for enhancing the velocity of a silicon device and an existing technology for enhancing the performance of an ultra high frequency depend on how fast the electron that forms the channel moves.
The terahertz band having a lot of advantages, such as the coexistence of straightness of a light wave (light) and transmittance of an electric wave, harmlessness to a human body due to the low energy, etc., can be variously applied to an ultra-high speed/high-capacity communication in an ultra high frequency band, etc., on the basis of an imaging technique, a spectroscopic technique, or the like.
The electron mobility of the silicon device is about 250cm2/Vs at a room temperature (approximately 25℃ or 298.15K). To achieve terahertz emission by using such a degree of the electron mobility, the length of the gate electrode should be extremely shortened.
The electron mobility is a measure of how easily electrons drift. Through the electron mobility, it can be understood how much the local electron drift velocity is increased in proportion to an electric field.
The method for enhancing the performance of the plasma-wave transistor according to the embodiment of the present invention achieves the terahertz emission even though the length of the gate electrode is relatively large, thereby making it easier to evaluate whether the transistor operates in the terahertz band.
In order to achieve the terahertz emission with the electron mobility of a common silicon device, the length of the gate electrode should be as short as about 5 nm. However, with the current silicon integration technology, it is difficult to perform the patterning to form the gate electrode with a length of about 5 nm. In addition, it is not easy to prevent a short channel effect.
Specifically, the method for enhancing the performance of the plasma-wave transistor according to the embodiment of the present invention increases the electron mobility by applying strain to a nano-wire and bending it. That is, it is possible to bend the nano-wire by applying a physical or chemical force to the nano-wire, resulting in the increase of the electron mobility as described below.
One embodiment to bend the nano-wire is to grow a natural oxide layer on the nano-wire. When the natural oxide layer is grown on the nano-wire, the electron mobility is increased to about 1000㎠/Vs at a room temperature due to the applied strain. When the electron mobility is increased by employing the above principle, the terahertz emission can be achieved even though the length of the gate electrode is greater than 20nm.
In other words, the method for enhancing the performance of the plasma-wave transistor according to the embodiment of the present invention increases the electron mobility by using the strain at the time of fabricating the natural oxide layer on the nano-wire and manufactures the transistor that includes the gate electrode with an enough length to be patterned by the current patterning technology, so that the evaluation of the performance of the plasma-wave transistor can be easily made.
FIG. 2 illustrates a flowchart showing the method for enhancing the performance of the transistor in accordance with the embodiment of the present invention. First, the nano-wire is formed on a substrate (S100). Next, the nano-wire is bent by applying the strain to the nano-wire(S110). An oxide layer process may be representatively taken as an example of the method for applying the strain to the nano-wire. However, the nano-wire may be bent by another method.
Next, the source electrode and the drain electrode are formed at both ends of the nano-wire before the gate electrode is formed (S120). Subsequently, a transistor having the bent nano-wire channel is manufactured by adding a general transistor manufacturing process with the inclusion of S100 to S120 (S130). In other words, the transistor is manufactured which includes the nano-wire, the source electrode, the drain electrode and the gate electrode which have been formed through the steps of S100 to S120.
Lastly, it is to evaluate whether or not the transistor manufactured in the step S130 operates in a predetermined band (S140). The evaluation the step S140 will be described in more detail with reference to FIG. 6.
It is enough as long as the manufacturing step S130 in the method for enhancing the performance of the transistor according to the embodiment of the present invention includes the steps from S100 to S120. The steps from S100 to S120 are not necessarily performed in sequence. That is, the order of S100 to S120 may be changed, or an extra common transistor manufacturing process may be added between each of the steps.
In the meantime, while FIG. 2 includes the step S140 of evaluating the transistor, it will be apparent to those skilled in the art that the performance of the transistor can be enhanced only by up to the step S130.
FIG. 3 illustrates a configuration of the transistor manufactured by the method according to the embodiment of the present invention. FIG. 4 illustrates an enlarged view of the nano-wire which is an element of the transistor manufactured by the method according to the embodiment of the present invention.
As illustrated in FIG. 3, the transistor manufactured by the method for enhancing the performance of the plasma-wave transistor according to the embodiment of the present invention includes a substrate 10, a drain electrode 20, a source electrode 30, a nano-wire 40 and a gate electrode 50. Herein, the gate electrode 50 is illustrated as a grating gate electrode having a first gate electrode 52 and a second gate electrode 54.
As described above with reference to FIG. 2, the transistor that is used in the method for enhancing the performance of the plasma-wave transistor according to the embodiment of the present invention has the nano-wire channel bent by the steps; forming the nano-wire 40 on the substrate 10 and applying the strain to the nano-wire 40. Subsequently, each of the electrodes 20, 30 and 50 is formed.
Particularly, the gate electrode 50, as shown in FIG. 3, may be the grating gate electrode including the two gate electrodes 52 and 54. By adopting a structure in which the grating gate electrode 50 surrounds the nano-wire 40, the field-effect transistor can be more integrated. However, the gate electrode 50 is not necessarily implemented by the grating gate electrode.
The measurement of the plasma wave emission by using the gate electrode employs a principle in which, when the plasma wave excited in the channel is transmitted as a mirror image wave to the gate electrode and dipoles are generated, an electromagnetic wave is radiated in the air in the form of free radiation, and then the electric power of the radiated electromagnetic wave is measured.
In particular, since the electromagnetic wave radiated from the gate electrode is added and amplified by using the grating gate electrode having the two electrodes , the plasma-wave emission can be measured more easily. In this embodiment, the gate electrode 50 has the two electrodes 52 and 54. However, it can be considered that the gate electrode 50 includes more than two electrodes.
The grating gate electrode 50 is formed to surround the bent nano-wire 40. The first gate electrode 52 and second gate electrode 54 constituting the grating gate electrode 50 include a longitudinal base and a plurality of protrusions which protrude perpendicularly to the base. The protrusion of the first gate electrode 52 and the protrusion of the second gate electrode 54 are spaced from each other at a predetermined distance so as not to contact each other and are inserted opposite to each other. However, the shape of the grating gate electrode 50 illustrated in FIG. 3 is no more than one embodiment, and the grating gate electrode 50 may have a shape different from the shape shown in FIG. 3.
Meanwhile, the method for enhancing the performance of the plasma-wave transistor according to the embodiment of the present invention may further include forming an insulation spacer.
Meanwhile, the nano-wire 40 may be made of any one selected from the group consisting of Si, Ge, Sn, Se, Te, B, C, B-Si, Si-C, Si-Ge, Si-Sn, Ge-Sn, SiC, BN/BP/BAs, AIN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SeTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, CuI, AgF, AgCl, AgBr, AgI, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu,Ag)(Al,Ga,In,Tl,Fe)(S,Se,Te)2, Si3N4, Ge3N4, Al2O3, (Al,Ga,In)2, (S,Se,Te)3 and Al2CO.
FIG. 5 illustrates a graph of electron mobility variation according to a temperature.
The electron mobility of the silicon device is about 250㎠/Vs at a room temperature (approximately 25℃ or 298.15K.) As described above, to achieve the terahertz emission by using the electron mobility of about 250㎠/Vs, the length of the gate electrode should be as short as about 5nm. However, there is a technical limitation in patterning for forming of the electrode or preventing the short channel effect, etc.
However, with the increase of the electron mobility of the silicon device, the length of the gate electrode can be relatively longer, so that it becomes easier to manufacture the gate electrode.
In case of manufacturing the silicon device with the nano-wire bent by applying the strain, the silicon device has a high electron mobility represented by two lines (a line (d) and a line (f)) in the top part of FIG. 5. Herein, "L" means the length of the nano-wire, and "W" means the diameter of the nano-wire. As shown in FIG. 5, it can be found that the mobility is increased to about 1000㎠/Vs at a room temperature by using the bent nano-wire channel.
Also, referring to FIG. 5, it can be seen that the effect of applying the strain is increased with the decrease of the diameter of the nano-wire.
The transistor manufactured by the method for enhancing the performance of the plasma-wave transistor according to the embodiment of the present invention includes the bent nano-wire channel, so that the transistor has a higher electron mobility at a room temperature.
Further, since the nano-wire channel of the transistor manufactured by the method for enhancing the performance of the plasma-wave transistor according to the embodiment of the present invention has a higher electron mobility, the length of the gate electrode can be implemented within a technical scope of the current technology.
FIG. 6 illustrates a graph for evaluating the performance of the plasma-wave transistor.
In the method for enhancing the performance of the plasma-wave transistor according to the embodiment of the present invention, as shown in FIG. 6, the local electron drift velocity is plotted on the x-axis, the plasma wave velocity is plotted on the y-axis and the channel length is plotted on the z-axis.
In addition, the method for enhancing the performance of the plasma-wave transistor according to the embodiment of the present invention generates a design window including a relational expression between the x-axis, y-axis and z-axis, and measures whether or not the manufactured transistor operates as a terahertz emitter in accordance with the change of a performance parameter value of the manufactured transistor.
Herein, it is desirable that the design window 3-dimensionally represents the change of emission boundary according to the channel mobility and channel length at the same time, and thus, decides the range of the channel length ensuring a function as a terahertz emitter, the range of the plasma wave velocity and the range of the electron drift velocity.
Specifically, the emission boundary of the design window changes according to the channel mobility and channel length, and the design window may be generated by the performance parameter corresponding to the point of the emission boundary acquired by a user's input. That is, prior to the real plasma-wave transistor process and experiment, a parameter suitable for the channel mobility or channel length, which should be confirmed experimentally and obtained later, is assumed, and then the calculated momentum relaxation time and the calculated injection velocity are input to the relational expression between the x-axis, y-axis and z-axis, so that the design window can be generated.
Subsequently, according to the embodiment of the present invention, the performance of the plasma-wave transistor that operates as a terahertz emitter can be evaluated by checking the plasma-wave velocity and the electron drift velocity in the design window.
Also, the movement of the plasma-wave is divided into upstream and downstream movements. The design window may be designed to include a physical condition satisfying the mathematical formula "(plasma-wave velocity - electron drift velocity) x momentum relaxation time > channel length" which uses a property that the emission of the terahertz emitter is caused by the multiple reflection.
According to the embodiment of the present invention, the electron mobility can be increased to 1000㎠/Vs by using the nano-wire bent by the strain. As a result, the length of the gate electrode can be increased to the range that enables the terahertz emission, so that it becomes easier to evaluate whether or not the terahertz emission occurs.
To avoid making the subject matter of the present invention unclear, the specific method and process of evaluating the performance of the transistor have been described in a brief summary. It will be apparent to those skilled in the art that the evaluation of the performance of the plasma-wave transistor can be made by using the performance evaluating method disclosed by other various types (published patent document, thesis, etc).
The foregoing embodiments and advantages are merely exemplary and are not to be construed as limiting the present invention. It can be understood by those skilled in the art that the embodiments may be changed and modified in various ways without departing from the essential features of the embodiments. Also, the scope of the right specified by the matters described in the claims of the present specification includes all the various modifications and applications.

Claims (8)

  1. A method for enhancing the performance of a transistor, the method comprising:
    forming a nano-wire on a substrate;
    applying strain to the nano-wire to bend the nano-wire;
    forming a source electrode, a drain electrode and a gate electrode; and
    manufacturing a transistor including the bent nano-wire formed by the applying of the strain, and source electrode, drain electrode and gate electrode formed by the forming of the electrodes.
  2. The method of claim 1, further comprising evaluating whether or not the transistor operates in a predetermined band.
  3. The method of claim 1, wherein the forming the electrodes forms a grating gate electrode having two gate electrodes.
  4. The method of claim 1, wherein the applying the strain on the nano-wire bends the nano-wire by forming a natural oxide layer.
  5. The method of claim 1, wherein the transistor is a plasma-wave transistor.
  6. The method of claim 2, wherein the predetermined band ranges from 1011Hz to 1013Hz (from 0.1THz to 10THz.)
  7. The method of claim 1, wherein the nano-wire is made of at least any one selected from the group consisting of Si, Ge, Sn, Se, Te, B, C, B-Si, Si-C, Si-Ge, Si-Sn, Ge-Sn, SiC, BN/BP/BAs, AIN/AlP/AlAs/AlSb, GaN/GaP/GaAs/GaSb, InN/InP/InAs/InSb, ZnO/ZnS/ZnSe/ZnTe, CdS/CdSe/CdTe, HgS/HgSe/HgTe, BeS/BeSe/BeTe/MgS/MgSe, GeS, GeSe, GeTe, SnS, SnSe, SeTe, PbO, PbS, PbSe, PbTe, CuF, CuCl, CuBr, CuI, AgF, AgCl, AgBr, AgI, BeSiN2, CaCN2, ZnGeP2, CdSnAs2, ZnSnSb2, ZnSnSb2, CuGeP3, CuSi2P3, (Cu,Ag)(Al,Ga,In,Tl,Fe)(S,Se,Te)2, Si3N4, Ge3N4, Al2O3, (Al,Ga,In)2, (S,Se,Te)3 and Al2CO.
  8. The method of claim 1, wherein the length of the gate electrode is greater than 20nm.
PCT/KR2015/001821 2015-02-24 2015-02-25 Method for enhancing performance of plasma-wave transistor Ceased WO2016137030A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008258622A (en) * 2007-04-04 2008-10-23 Sharp Corp Nanowire transistor and manufacturing method therefor
CN102683205A (en) * 2012-05-04 2012-09-19 上海华力微电子有限公司 Method for manufacturing semiconductor built-in stress nanowire and semiconductor device
JP2014131044A (en) * 2012-12-28 2014-07-10 Renesas Electronics Corp Field-effect transistor having channel core modified for back gate bias, and manufacturing method therefor
US20140225184A1 (en) * 2013-02-08 2014-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Inducing Strain in Vertical Semiconductor Columns

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008258622A (en) * 2007-04-04 2008-10-23 Sharp Corp Nanowire transistor and manufacturing method therefor
CN102683205A (en) * 2012-05-04 2012-09-19 上海华力微电子有限公司 Method for manufacturing semiconductor built-in stress nanowire and semiconductor device
JP2014131044A (en) * 2012-12-28 2014-07-10 Renesas Electronics Corp Field-effect transistor having channel core modified for back gate bias, and manufacturing method therefor
US20140225184A1 (en) * 2013-02-08 2014-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method for Inducing Strain in Vertical Semiconductor Columns

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
K.E. MOSELUND ET AL.: "The High-Mobility Bended n-Channel Silicon Nanowire Transistor", IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 57, no. 4, 17 February 2010 (2010-02-17), pages 866 - 876, XP011303021 *

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