WO2016132101A1 - Wafer metallization of high power semiconductor devices - Google Patents

Wafer metallization of high power semiconductor devices Download PDF

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Publication number
WO2016132101A1
WO2016132101A1 PCT/GB2016/050336 GB2016050336W WO2016132101A1 WO 2016132101 A1 WO2016132101 A1 WO 2016132101A1 GB 2016050336 W GB2016050336 W GB 2016050336W WO 2016132101 A1 WO2016132101 A1 WO 2016132101A1
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WIPO (PCT)
Prior art keywords
semiconductor device
layer
power semiconductor
metal layer
metal
Prior art date
Application number
PCT/GB2016/050336
Other languages
French (fr)
Inventor
Ian DEVINY
Maolong Ke
Original Assignee
Dynex Semiconductor Limited
Zhuzhou Crrc Times Electric Co. Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dynex Semiconductor Limited, Zhuzhou Crrc Times Electric Co. Ltd filed Critical Dynex Semiconductor Limited
Priority to CN201680006076.2A priority Critical patent/CN107210280B/en
Publication of WO2016132101A1 publication Critical patent/WO2016132101A1/en

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Definitions

  • This invention relates to wafer metallization of high power semiconductor devices, particularly but not exclusively, to wafer metallization of insulated gate bipolar transistors (IGBTs).
  • IGBTs insulated gate bipolar transistors
  • wire bonding technology itself has other disadvantages, such as speed limitation due to inductance of bonding wires and difficulty to control temperature on device top surface. Therefore, in some advanced packaging technology, the wire bonding has been replaced with other technology. For example, in press-pack packaging, the power chips are directly pressed into contact with certain force. The chips, therefore, need to withstand enough pressure in the package.
  • Another advanced packaging concept is to use double-sided silver sintering to contact chips on both top and bottom surfaces. Again, significant pressure is applied to chips during the sintering, in addition to the requirement of finishing the metallization with silver metal.
  • the pressure applied during the packaging process could be harmful for the sensitive regions of the semiconductor devices.
  • a power semiconductor device for high current density applications comprising: a plurality of semiconductor regions formed on top of one another;
  • the contact layer comprises a first portion placed in direct contact of said first surface of said one of the semiconductor regions and a second portion formed over an insulation region formed in direct contact of said first surface of said one of the semiconductor regions;
  • a second metal layer formed at least partly on the first metal layer, wherein the first and second metal layers are formed in such a way that the first portion of the contact layer and at least a part of the second portion of the contact layer are not pressurised during a packaging process of the power semiconductor device.
  • high current density applications are referred by the effect of high current density in bipolar power devices such as IGBT or BJT. Therefore the invention may be particularly relevant to bipolar power semiconductor devices.
  • MOS metal oxide semiconductor
  • a contact layer formed above a first surface of one of the semiconductor regions, wherein the contact layer comprises a first portion placed in direct contact of said first surface of said one of the semiconductor regions and a second portion formed over an insulation region formed in direct contact of said first surface of said one of the semiconductor regions;
  • the first metal layer may be selected from a group comprising nickel, gold and platinum.
  • the first metal layer is nickel (Ni).
  • the second metal layer may be selected from a group comprising silver, gold and copper.
  • the second metal layer may be silver (Ag).
  • other metals on top of the original aluminium layer are added. For example, Ni and Ag layers can be easily electroplated onto existing aluminium layer.
  • Ni layer is mechanically very hard with Young's modulus of around 200GPa as compared to aluminium of around 70GPa. Most of the pressure will therefore be borne by the Ni layer, which is unlikely to be squashed and flatted out under pressure, and effectively protecting the sensitive semiconductor dies underneath. It will be appreciated that any other metals which are mechanically hard can be used instead of Ni.
  • a silver layer on top is advantageous for several reasons.
  • silver is a noble metal resistant to oxidation; secondly, silver is a soft metal with excellent electric conductivity, hence suitable for making a good Ohmic contact through direct pressing (press pack); thirdly, silver can also be used in either silver sintering or silver soldering to form robust bonds which can be operated under high temperature (>175°C) with increased reliability and lifetime. So a combination of Ni and Ag plating on top of existing aluminium will greatly enhance the prospect of chips surviving high pressure applications such as press-pack or silver sintering. Furthermore, both metals can be grown easily on top of existing aluminium layer through either standard electroplating or electro-less plating. It will be appreciated that any other material having good conductivity can be used instead of silver.
  • the first and second metal layers may be formed to provide a recess which may be defined by the first portion of the contact layer and at least partly of the second portion of the contact layer and the heights of the first and second metal layers.
  • the recess may be filled with air or a gas.
  • the recess can be represented by pockets of voids which protect the sensitive regions from any pressure applied in the press-pack or silver sintering packaging process.
  • the recess may be configured such that no pressure is applied to the first portion of the contact layer and said at least a part of the second portion of the contact layer which is over a channel region in the first surface of one of the semiconductor regions.
  • the power semiconductor device may further comprise a dielectric layer formed on the first portion of the contact metal layer and at least partly on the second portion of the contact layer. These regions are sensitive and therefore the dielectric layer will protect these regions from the pressure applied during the packaging process.
  • the recess or pockets of voids are formed on top of the dielectric layer because it can prevent the deposition of both the first and the second metals on top of the dielectric layer.
  • the recess or pockets of voids are formed over the first portion of the contact layer and at least partly on the second portion of the contact layer so that no pressure is applied on these regions.
  • the at least partly second portion of the contact layer on which the recess is formed is the adjacent part of the first portion of the contact layer.
  • the at least part of the second portion of the contact layer on which the Ni and Ag layers are formed is away from the first portion of the contact layer which is directly in contact with the semiconductor region.
  • the height of the dielectric layer may be about 1 ⁇ .
  • the height of each of the first and second metal layers may be about 5 ⁇ . It will be appreciated that variations in heights in these layers may be possible.
  • the power semiconductor device may further comprise a gate busbar metal layer formed over the insulator region on the first surface of one of the semiconductor regions.
  • the gate busbar layer may be configured to connect to a channel region formed in the first surface of one of the semiconductor regions.
  • the gate busbar region is a sensitive region which needs to be protected from the applied pressure during the packing process.
  • the power semiconductor device may further comprise a dielectric layer formed on the gate busbar metal layer.
  • the first and second metal layers may be formed to provide a further recess which is defined by the surface of the dielectric layer on the gate busbar metal layer and the heights of the first and second metal layers.
  • the further recess may be configured such that no pressure is applied to the gate busbar metal layer.
  • the power semiconductor device may further comprise a second contact layer formed on a second surface of one of the semiconductor regions, wherein the second surface may be located at an opposite end to the first surface of one of the semiconductor regions.
  • the first metal layer may be formed on the second contact layer and the second metal layer is formed on the first metal layer.
  • the power semiconductor device may further comprise a first external metal layer formed on the second metal layer formed over the first surface of one of the semiconductor regions.
  • the power semiconductor device may further comprise a second external metal layer formed on the second metal layer formed over the second surface of one of the semiconductor regions.
  • the first and second external metal layers may comprise a material comprising moly.
  • the first and second external metal layers may be silver-plated. The silver plating assists the contact layer and reduces the contact resistance.
  • the first and second external metal layers may be formed by applying a pressure of about 20 kN.
  • the first and second external metal layers may be formed by using a press-pack packaging technique.
  • the first external metal layer may comprise a material comprising silver
  • the second metal layer over the first surface of the semiconductor regions may comprise a material comprising silver
  • the second external metal layer may comprise a material comprising silver
  • the second metal layer over the second surface of the semiconductor regions may comprise a material comprising silver.
  • At least one of the first and second external metal layers may be formed on the respective second metal layer by using a silver-sintering packaging technique.
  • the at least one of the first and second external metal layers may be formed on the respective second metal layer by applying a pressure of about 4kN and by applying a predetermined temperature.
  • the first and second external metal layers may be bonded with a substrate.
  • the first and second metal layers may be formed using an electroplating technique.
  • the first and second metal layers may be formed using an electro-less plating technique.
  • electro-less plating is its selective metal growth/deposition on top of existing metal contact region. It will not grow in regions where no metal layer (seed layer) existed before. So it is very easy to stop metal deposition on any regions by simply mask the regions with a dielectric layer. Also, both top and bottom surfaces can be electrolessly plated at the same time, greatly simplify the fabrication processes.
  • the device may be an insulated gate bipolar transistor (IGBT).
  • IGBT may be a planner gate IGBT or a trench gate IGBT.
  • the power device may be a metal oxide gate field effect transistor (MOSFET).
  • the power device may be a bipolar junction transistor (BJT).
  • BJT bipolar junction transistor
  • a method of manufacturing a MOS gate controlled power semiconductor device comprising:
  • first and second metal layers are formed in such a way that the first portion of the contact layer and at least a part of the second portion of the contact layer are not pressurised during a packaging process of the power semiconductor device.
  • the forming of the first and second metal layers may comprise providing a recess which is defined by the first portion of the contact layer and at least partly of the second portion of the contact layer and the heights of the first and second metal layers.
  • the method may further comprise forming a dielectric layer on the first portion of the contact metal layer and at least partly on the second portion of the contact layer.
  • the method may further comprise forming a gate busbar metal layer over the insulator region on the first surface of one of the semiconductor regions.
  • the gate busbar layer may connect to a channel region formed in the first surface of one of the semiconductor regions.
  • the method may further comprise forming a dielectric layer on the gate busbar metal layer.
  • the forming of the first and second metal layers may further comprise providing a further recess which is defined by the first surface of the dielectric layer on the gate busbar metal layer and the heights of the first and second metal layers.
  • the method may further comprise forming a second contact layer on a second surface of one of the semiconductor regions, wherein the second surface may be located at an opposite end to the first surface of one of the semiconductor regions.
  • the method may further comprise forming the first metal layer on the second contact layer on the second surface and forming the second metal layer on the first metal layer.
  • the first metal layer may be selected from a group comprising nickel, gold and platinum.
  • the second metal layer may be selected from a group comprising silver, gold and copper.
  • the first and second metal layers are may be formed using an electroplating technique.
  • the first and second metal layers may be formed using an electro-less plating technique.
  • the power semiconductor device may be packaged using any of press-pack, double- sided silver sintering, double-sided soldering technique.
  • Fig. 1 a illustrates a schematic cross section of a prior art power semiconductor device
  • Fig. 1 b illustrates a schematic cross section of a power semiconductor device in accordance with the present invention
  • Fig. 2a illustrates a schematic cross-section of a planar gate vertical IGBT
  • Fig. 2b illustrates a schematic cross-section of the IGBT of Fig. 2a in which subsequent metal layers are formed on non-sensitive regions;
  • Fig. 2c illustrates a schematic cross section of a trench gate IGBT
  • Fig. 3 is a schematic cross-sectional diagram of a press pack package where pressure is borne on regions without sensitive contact underneath;
  • Fig. 4 illustrates a schematic diagram for double-sided silver sintering package
  • Fig. 5 illustrates an example of a cross-sectional image of a silver sintering bond.
  • Fig. 1 a illustrates a schematic cross section of a prior art power semiconductor device.
  • the device includes an active silicon region 101.
  • An aluminium contact layer 103 is formed on a first surface or a front top end surface of the device.
  • a tri-metal contact 105 is deposited on a second surface or a back bottom end surface of the device. It is evident that this structure would have adverse effect from the pressure applied in the press-pack, double-sided silver sintering or double sided soldering packaging process.
  • Fig. 1 b illustrates a schematic cross section of a power semiconductor device in accordance with the present invention.
  • a nickel (Ni) layer 107 is formed on the aluminium layer 103 on the front end (or the first) surface and a silver layer 109 is formed on the nickel layer 107 on the front end surface.
  • the nickel layer 107 is also deposited on the aluminium contact layer 103 and then a silver layer 109 is deposited on the nickel layer 107. Since these two layers are deposited on the aluminium contact layers (on the front and back end surfaces) 103, the active semiconductor region 101 can take on more pressure from a packaging process. Thus, this structure is more suitable for the press-pack, double- sided silver sintering or double sided soldering packaging process.
  • Fig. 2a illustrates a schematic cross-section of a planar gate vertical IGBT 200.
  • the device 200 includes an active semiconductor region 201 in which a p-type body 203 region is formed. Highly doped n+ type regions 205 are formed inside the p-type body region 203.
  • a gate oxide (Si02) or insulation material 209 is formed on the first surface or front top end surface of the device.
  • a polysilicon 211 layer is formed on the gate oxide 209 and a further oxide layer 213 is formed on the polysilicon 211 layer.
  • An emitter metal 207 is formed in which a first portion of the emitter metal layer (or a contact layer) 207 is in direct contact with the p-type body 203 and a second portion of the metal contact 207 is over the gate oxide 209 and polysilicon 21 1 layer.
  • a gate busbar 217 which is a metal contact, is formed over the polysilicon 211 layer so that the gate busbar 217 is connected to the gate region.
  • IGBT devices most of the top emitter metal layer on top of oxide layer (Si02) 209, 213 rather than in direct contact with the semiconductor layer 203, and they provide an easy connection with outside circuits through wire bonding, for example.
  • the first portion of the emitter layer 207 there are areas (for example, the first portion of the emitter layer 207) where the top emitter metal is in direct contact with semiconductor 203, such as gate busbars 217 and first portion of the emitter regions 207, and these areas are sensitive to external pressure.
  • the first portion of the emitter layer 207 which is in direct contact with the semiconductor region 203 and a part of the second portion of the emitter metal 207 which is just above the channel region 204 are masked to form a dielectric layer 215 on these regions.
  • the part of the second portion of the emitter metal 207 is located immediately adjacent the first portion of the emitter metal 207. This part of the second portion of the emitter layer 207 is just above the channel region.
  • a further dielectric layer 217 is also formed over the gate busbar 217. Therefore, all sensitive regions, such as the gate busbars 217 and emitters 207, are covered with the dielectric layers (Si02 for example) 215, 217. The regions close to edge termination are also covered with the dielectric layer 215, 217 to avoid any potential complications.
  • Fig. 2b illustrates a schematic cross-section of the IGBT of Fig. 2a in which subsequent metal layers are formed on non-sensitive regions.
  • Ni layer 230 and Ag layer 235 are formed on both top and bottom end of aluminium (top and bottom) surfaces.
  • the Ni layer 230 and Ag 235 are formed on the part of the second portion of the contact layer 207 which is distant/away from the first portion of the emitter contact layer 207. Therefore the pressure put on the device is borne on areas which have no sensitive regions underneath, i.e. the pressure is borne in the second portion of the emitter layer 207 which is away from the channel region 204 and the region where the emitter layer 207 contacts the semiconductor region 203.
  • the typical height for the dielectric layer is about 1 um, but the typical height of the plated Ni and Ag layers 230, 235 are around 5um respectively, hence providing a height step/difference of about 9 urn.
  • the height step creates pockets of voids or a recess filled with air or gases during subsequent press-pack assembly. These pockets of voids or recess protect the sensitive regions from any pressure applied in the press-pack or silver sintering packaging processes.
  • Fig. 2c illustrates a schematic cross section of a trench gate IGBT.
  • Many features of the trench gate IGBT are the same as the IGBT of Fig. 2b, except that there is a trench type gate 280 configuration in the IGBT structure.
  • the gate oxide goes around the trench which is a sensitive region of the device. The trench area needs to be protected from the pressure and thus the recess or void is formed over the trench gate as well.
  • Figure 3 is a schematic cross-sectional diagram of a press pack package where pressure is borne on regions without sensitive contact underneath.
  • the external metal layer 240 for press-pack is generally moly. The contact between moly and silver relies on sufficient pressure being applied. Generally around 20kN or higher pressure is applied in a press-pack package. Although a number of dies are included inside each package, hence pressure on individual die is likely to be less than 20kN. However, due to the likely height difference between the poles and dies inside the press-pack package, some dies is likely to experience higher pressure than others. Generally each die should be able to withstand the full load ( ⁇ 20kN) for the package and the proposed layout should be able to do that. Also, the external metal (moly) can be silver-plated as well to assist the contact and reduce the contact resistance.
  • FIG. 4 illustrates a schematic diagram for double-sided silver sintering package. Many features of Fig. 4 are the same as Fig. 3, except that an Ag paste layer 250 is used to bond with the Ag metal layer 235 in both front and back end surfaces. The Ag paste 250 is used to bond to a substrate 255. A silver sinter joint 260 is formed between the Ag paste 250 and Ag metal layer 235.
  • the proposed new metallization with extra metals on both top and bottom end surfaces are not only useful in the above-mentioned press-pack packages (in Fig. 3), but also in silver sintering process.
  • Silver sintering is an emerging technology in high power module production for bonding the semiconductor chip onto substrates. It is a silver to silver bonding under pressure and temperature.
  • Fig. 5 shows an example of a cross- sectional image of such a bond.
  • the bond is robust and more reliable than normal soldered bond.
  • significant pressure typically 4kN per dies, is applied during the sintering process. Therefore the structure should be able to improve production yield due to aforementioned reasons, even if sintering on the bottom side only (or at the second surface of the device).
  • the power semiconductor device can also be used for double-sided sintering (both top and bottom).
  • Double sided silver sintering is an emerging packaging concept, where current aluminium wire-bonding to connect the top of the chips to substrates is replaced with direct silver bond between chip and another substrate circuit.
  • the advantages of that are multi-folds firstly, much increased reliability and lifetime expected as currently the aluminium wire bonding is the weak point; secondly, reduced inductance will improve switching speed and module performance; Thirdly, the loss due to joule heating (also called resistive heating) from the bonding wires will be eliminated.
  • the Joule heating is proportional to current, wire resistivity and time (Q ⁇ I 2 R t) .
  • resistivity R is small (around 0.05 ⁇ per typical 15mil Al bonding wire), but due to large current (1500A per module for example) is used in operation, the loss due to joule heating from the bonding wires alone can be several hundreds of Watts per module.
  • Replacing bonding wires with silver sintering can eliminate the Joule heating loss caused by the bonding wires.
  • the bonding wires also induce inductance, normally called stray inductance.
  • This formula is normally applied to discrete components. For modules with a large number (n) of parallel chips, the formula for the inductive energy per chip is given as:
  • the double sided silver sintering, soldering or press pack packaging will enable thermal control through both surfaces.
  • the thermal resistance of aluminium wire is large, and therefore, the temperature control is currently conducted primarily through the bottom surface.
  • Double sided silver sintering/soldering package will afford a way of thermal management through both surfaces. Since the active region is close to the top surface, hence temperature control through the top surface will be more effective.
  • a vertical power MOSFET can use the metallization layer proposed in this invention.
  • the MOSFET is a unipolar device and thus it does not have the injector at the bottom end surface.
  • a vertical bipolar junction transistor BJT
  • the skilled person would be able to identify the sensitive regions of a vertical BJT and grow the additional metal layers on top of the top contact metal layer to form the void or recess which would reduce the pressure during the packaging process.

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Abstract

We disclose a power semiconductor device for high current density applications, the device comprising: a plurality of semiconductor regions formed on top of one another and a contact layer formed above a first surface of one of the semiconductor regions. The contact layer comprises a first portion placed in direct contact of said first surface of said one of the semiconductor regions and a second portion formed over an insulation region formed in direct contact of said first surface of said one of the semiconductor regions. The device further comprises a first metal layer (230) formed at least partly on the second portion of the contact layer; and a second metal layer (235) formed at least partly on the first metal layer. The first and second metal layers are formed in such a way that the first portion of the contact layer and at least a part of the second portion of the contact layer are not pressurised during a packaging process of the power semiconductor device.

Description

WAFER METALLIZATION OF HIGH POWER SEMICONDUCTOR DEVICES
FIELD OF THE INVENTION This invention relates to wafer metallization of high power semiconductor devices, particularly but not exclusively, to wafer metallization of insulated gate bipolar transistors (IGBTs).
BACKGROUND TO THE INVENTION
The industry standard of chip metallization and interconnection for high power devices are aluminium metal and aluminium wires. However, due to the inherent softness of aluminium, the device lifetime and reliability have almost reached their limits. Further significant improvement in reliability with current aluminium wire bonding system is difficult.
Also, wire bonding technology itself has other disadvantages, such as speed limitation due to inductance of bonding wires and difficulty to control temperature on device top surface. Therefore, in some advanced packaging technology, the wire bonding has been replaced with other technology. For example, in press-pack packaging, the power chips are directly pressed into contact with certain force. The chips, therefore, need to withstand enough pressure in the package. Another advanced packaging concept is to use double-sided silver sintering to contact chips on both top and bottom surfaces. Again, significant pressure is applied to chips during the sintering, in addition to the requirement of finishing the metallization with silver metal.
The pressure applied during the packaging process could be harmful for the sensitive regions of the semiconductor devices. Thus it is an objective of the present invention to reduce the pressure applied to the sensitive regions of the semiconductor regions during the packaging process.
SUMMARY
According to one aspect of the invention, there is provided a power semiconductor device for high current density applications, the device comprising: a plurality of semiconductor regions formed on top of one another;
a contact layer formed above a first surface of one of the semiconductor regions, wherein the contact layer comprises a first portion placed in direct contact of said first surface of said one of the semiconductor regions and a second portion formed over an insulation region formed in direct contact of said first surface of said one of the semiconductor regions;
a first metal layer formed at least partly on the second portion of the contact layer; and
a second metal layer formed at least partly on the first metal layer, wherein the first and second metal layers are formed in such a way that the first portion of the contact layer and at least a part of the second portion of the contact layer are not pressurised during a packaging process of the power semiconductor device. Here high current density applications are referred by the effect of high current density in bipolar power devices such as IGBT or BJT. Therefore the invention may be particularly relevant to bipolar power semiconductor devices.
According to a further aspect of the present invention, there is provided a metal oxide semiconductor (MOS) gate controlled power semiconductor device comprising:
a plurality of semiconductor regions formed on top of one another; a contact layer formed above a first surface of one of the semiconductor regions, wherein the contact layer comprises a first portion placed in direct contact of said first surface of said one of the semiconductor regions and a second portion formed over an insulation region formed in direct contact of said first surface of said one of the semiconductor regions;
a first metal layer formed at least partly on the second portion of the contact layer;
a second metal layer formed at least partly on the first metal layer, wherein the first and second metal layers are formed in such a way that the first portion of the contact layer and at least a part of the second portion of the contact layer are not pressurised during a packaging process of the power semiconductor device. The first metal layer may be selected from a group comprising nickel, gold and platinum. Preferably the first metal layer is nickel (Ni). The second metal layer may be selected from a group comprising silver, gold and copper. Preferably the second metal layer may be silver (Ag). In order to make the power device chips withstand more pressure, other metals on top of the original aluminium layer are added. For example, Ni and Ag layers can be easily electroplated onto existing aluminium layer. The advantage of the Ni layer is that it is mechanically very hard with Young's modulus of around 200GPa as compared to aluminium of around 70GPa. Most of the pressure will therefore be borne by the Ni layer, which is unlikely to be squashed and flatted out under pressure, and effectively protecting the sensitive semiconductor dies underneath. It will be appreciated that any other metals which are mechanically hard can be used instead of Ni. A silver layer on top is advantageous for several reasons. Firstly, silver is a noble metal resistant to oxidation; secondly, silver is a soft metal with excellent electric conductivity, hence suitable for making a good Ohmic contact through direct pressing (press pack); thirdly, silver can also be used in either silver sintering or silver soldering to form robust bonds which can be operated under high temperature (>175°C) with increased reliability and lifetime. So a combination of Ni and Ag plating on top of existing aluminium will greatly enhance the prospect of chips surviving high pressure applications such as press-pack or silver sintering. Furthermore, both metals can be grown easily on top of existing aluminium layer through either standard electroplating or electro-less plating. It will be appreciated that any other material having good conductivity can be used instead of silver.
The first and second metal layers may be formed to provide a recess which may be defined by the first portion of the contact layer and at least partly of the second portion of the contact layer and the heights of the first and second metal layers. The recess may be filled with air or a gas. The recess can be represented by pockets of voids which protect the sensitive regions from any pressure applied in the press-pack or silver sintering packaging process. The recess may be configured such that no pressure is applied to the first portion of the contact layer and said at least a part of the second portion of the contact layer which is over a channel region in the first surface of one of the semiconductor regions.
The power semiconductor device may further comprise a dielectric layer formed on the first portion of the contact metal layer and at least partly on the second portion of the contact layer. These regions are sensitive and therefore the dielectric layer will protect these regions from the pressure applied during the packaging process. In this case, the recess or pockets of voids are formed on top of the dielectric layer because it can prevent the deposition of both the first and the second metals on top of the dielectric layer. Furthermore, the recess or pockets of voids are formed over the first portion of the contact layer and at least partly on the second portion of the contact layer so that no pressure is applied on these regions. It will be understood that the at least partly second portion of the contact layer on which the recess is formed is the adjacent part of the first portion of the contact layer. By way of contrast, the at least part of the second portion of the contact layer on which the Ni and Ag layers are formed is away from the first portion of the contact layer which is directly in contact with the semiconductor region.
The height of the dielectric layer may be about 1 μηι. The height of each of the first and second metal layers may be about 5 μηι. It will be appreciated that variations in heights in these layers may be possible.
The power semiconductor device may further comprise a gate busbar metal layer formed over the insulator region on the first surface of one of the semiconductor regions. The gate busbar layer may be configured to connect to a channel region formed in the first surface of one of the semiconductor regions. The gate busbar region is a sensitive region which needs to be protected from the applied pressure during the packing process. The power semiconductor device may further comprise a dielectric layer formed on the gate busbar metal layer.
The first and second metal layers may be formed to provide a further recess which is defined by the surface of the dielectric layer on the gate busbar metal layer and the heights of the first and second metal layers. The further recess may be configured such that no pressure is applied to the gate busbar metal layer.
The power semiconductor device may further comprise a second contact layer formed on a second surface of one of the semiconductor regions, wherein the second surface may be located at an opposite end to the first surface of one of the semiconductor regions.
The first metal layer may be formed on the second contact layer and the second metal layer is formed on the first metal layer.
The power semiconductor device may further comprise a first external metal layer formed on the second metal layer formed over the first surface of one of the semiconductor regions. The power semiconductor device may further comprise a second external metal layer formed on the second metal layer formed over the second surface of one of the semiconductor regions.
The first and second external metal layers may comprise a material comprising moly. The first and second external metal layers may be silver-plated. The silver plating assists the contact layer and reduces the contact resistance.
The first and second external metal layers may be formed by applying a pressure of about 20 kN. The first and second external metal layers may be formed by using a press-pack packaging technique.
The first external metal layer may comprise a material comprising silver, and the second metal layer over the first surface of the semiconductor regions may comprise a material comprising silver. The second external metal layer may comprise a material comprising silver, and the second metal layer over the second surface of the semiconductor regions may comprise a material comprising silver. These material combinations may be particularly suitable for a silver-sintering process.
At least one of the first and second external metal layers may be formed on the respective second metal layer by using a silver-sintering packaging technique. The at least one of the first and second external metal layers may be formed on the respective second metal layer by applying a pressure of about 4kN and by applying a predetermined temperature. The first and second external metal layers may be bonded with a substrate. The advantages of silver-sintering process are multi-folds: firstly, much increased reliability and lifetime expected as currently the aluminium wire bonding is the weak point; secondly, reduced inductance will improve switching speed and module performance; Thirdly, the loss due to joule heating (also called resistive heating) from the bonding wires will be eliminated.
The first and second metal layers may be formed using an electroplating technique.
The first and second metal layers may be formed using an electro-less plating technique. The key advantage of electro-less plating is its selective metal growth/deposition on top of existing metal contact region. It will not grow in regions where no metal layer (seed layer) existed before. So it is very easy to stop metal deposition on any regions by simply mask the regions with a dielectric layer. Also, both top and bottom surfaces can be electrolessly plated at the same time, greatly simplify the fabrication processes.
The device may be an insulated gate bipolar transistor (IGBT). The IGBT may be a planner gate IGBT or a trench gate IGBT. The power device may be a metal oxide gate field effect transistor (MOSFET).
The power device may be a bipolar junction transistor (BJT).
According to a further aspect of the present invention, there is provided a method of manufacturing a MOS gate controlled power semiconductor device, the method comprising:
forming a plurality of semiconductor regions formed on top of one another; forming a contact layer above a first surface of one of the semiconductor regions, wherein the contact layer comprises a first portion placed in direct contact of said first surface of said one of the semiconductor regions and a second portion formed over an insulation region formed in direct contact of said first surface of said one of the semiconductor regions;
forming a first metal layer at least partly on the second portion of the contact layer;
forming a second metal layer at least partly on the first metal layer, wherein the first and second metal layers are formed in such a way that the first portion of the contact layer and at least a part of the second portion of the contact layer are not pressurised during a packaging process of the power semiconductor device.
The forming of the first and second metal layers may comprise providing a recess which is defined by the first portion of the contact layer and at least partly of the second portion of the contact layer and the heights of the first and second metal layers. The method may further comprise forming a dielectric layer on the first portion of the contact metal layer and at least partly on the second portion of the contact layer.
The method may further comprise forming a gate busbar metal layer over the insulator region on the first surface of one of the semiconductor regions. The gate busbar layer may connect to a channel region formed in the first surface of one of the semiconductor regions.
The method may further comprise forming a dielectric layer on the gate busbar metal layer.
The forming of the first and second metal layers may further comprise providing a further recess which is defined by the first surface of the dielectric layer on the gate busbar metal layer and the heights of the first and second metal layers. The method may further comprise forming a second contact layer on a second surface of one of the semiconductor regions, wherein the second surface may be located at an opposite end to the first surface of one of the semiconductor regions.
The method may further comprise forming the first metal layer on the second contact layer on the second surface and forming the second metal layer on the first metal layer.
The first metal layer may be selected from a group comprising nickel, gold and platinum. The second metal layer may be selected from a group comprising silver, gold and copper.
The first and second metal layers are may be formed using an electroplating technique.
The first and second metal layers may be formed using an electro-less plating technique.
The power semiconductor device may be packaged using any of press-pack, double- sided silver sintering, double-sided soldering technique.
BRIEF DESCRIPTION OF THE DRAWINGS
The present disclosure will be understood more fully from the detailed description that follows and from the accompanying drawings, which however, should not be taken to limit the invention to the specific embodiments shown, but are for explanation and understanding only.
Fig. 1 a illustrates a schematic cross section of a prior art power semiconductor device; Fig. 1 b illustrates a schematic cross section of a power semiconductor device in accordance with the present invention;
Fig. 2a illustrates a schematic cross-section of a planar gate vertical IGBT;
Fig. 2b illustrates a schematic cross-section of the IGBT of Fig. 2a in which subsequent metal layers are formed on non-sensitive regions;
Fig. 2c illustrates a schematic cross section of a trench gate IGBT;
Fig. 3 is a schematic cross-sectional diagram of a press pack package where pressure is borne on regions without sensitive contact underneath;
Fig. 4 illustrates a schematic diagram for double-sided silver sintering package; and Fig. 5 illustrates an example of a cross-sectional image of a silver sintering bond.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
Fig. 1 a illustrates a schematic cross section of a prior art power semiconductor device. The device includes an active silicon region 101. An aluminium contact layer 103 is formed on a first surface or a front top end surface of the device. A tri-metal contact 105 is deposited on a second surface or a back bottom end surface of the device. It is evident that this structure would have adverse effect from the pressure applied in the press-pack, double-sided silver sintering or double sided soldering packaging process. Fig. 1 b illustrates a schematic cross section of a power semiconductor device in accordance with the present invention. In one embodiment, a nickel (Ni) layer 107 is formed on the aluminium layer 103 on the front end (or the first) surface and a silver layer 109 is formed on the nickel layer 107 on the front end surface. On the back end (second) surface, the nickel layer 107 is also deposited on the aluminium contact layer 103 and then a silver layer 109 is deposited on the nickel layer 107. Since these two layers are deposited on the aluminium contact layers (on the front and back end surfaces) 103, the active semiconductor region 101 can take on more pressure from a packaging process. Thus, this structure is more suitable for the press-pack, double- sided silver sintering or double sided soldering packaging process.
Fig. 2a illustrates a schematic cross-section of a planar gate vertical IGBT 200. The device 200 includes an active semiconductor region 201 in which a p-type body 203 region is formed. Highly doped n+ type regions 205 are formed inside the p-type body region 203. A gate oxide (Si02) or insulation material 209 is formed on the first surface or front top end surface of the device. A polysilicon 211 layer is formed on the gate oxide 209 and a further oxide layer 213 is formed on the polysilicon 211 layer. An emitter metal 207 is formed in which a first portion of the emitter metal layer (or a contact layer) 207 is in direct contact with the p-type body 203 and a second portion of the metal contact 207 is over the gate oxide 209 and polysilicon 21 1 layer. A gate busbar 217, which is a metal contact, is formed over the polysilicon 211 layer so that the gate busbar 217 is connected to the gate region. In IGBT devices, most of the top emitter metal layer on top of oxide layer (Si02) 209, 213 rather than in direct contact with the semiconductor layer 203, and they provide an easy connection with outside circuits through wire bonding, for example. On the other hand, there are areas (for example, the first portion of the emitter layer 207) where the top emitter metal is in direct contact with semiconductor 203, such as gate busbars 217 and first portion of the emitter regions 207, and these areas are sensitive to external pressure. In this embodiment, the first portion of the emitter layer 207 which is in direct contact with the semiconductor region 203 and a part of the second portion of the emitter metal 207 which is just above the channel region 204 are masked to form a dielectric layer 215 on these regions. The part of the second portion of the emitter metal 207 is located immediately adjacent the first portion of the emitter metal 207. This part of the second portion of the emitter layer 207 is just above the channel region. A further dielectric layer 217 is also formed over the gate busbar 217. Therefore, all sensitive regions, such as the gate busbars 217 and emitters 207, are covered with the dielectric layers (Si02 for example) 215, 217. The regions close to edge termination are also covered with the dielectric layer 215, 217 to avoid any potential complications.
Fig. 2b illustrates a schematic cross-section of the IGBT of Fig. 2a in which subsequent metal layers are formed on non-sensitive regions. Many features of Fig. 2b are the same as Fig. 2a and hence carry the same reference numbers, except in Fig. 2b, Ni layer 230 and Ag layer 235 are formed on both top and bottom end of aluminium (top and bottom) surfaces. On the top end surface, the Ni layer 230 and Ag 235 are formed on the part of the second portion of the contact layer 207 which is distant/away from the first portion of the emitter contact layer 207. Therefore the pressure put on the device is borne on areas which have no sensitive regions underneath, i.e. the pressure is borne in the second portion of the emitter layer 207 which is away from the channel region 204 and the region where the emitter layer 207 contacts the semiconductor region 203.
In one embodiment, the typical height for the dielectric layer is about 1 um, but the typical height of the plated Ni and Ag layers 230, 235 are around 5um respectively, hence providing a height step/difference of about 9 urn. The height step creates pockets of voids or a recess filled with air or gases during subsequent press-pack assembly. These pockets of voids or recess protect the sensitive regions from any pressure applied in the press-pack or silver sintering packaging processes.
Fig. 2c illustrates a schematic cross section of a trench gate IGBT. Many features of the trench gate IGBT are the same as the IGBT of Fig. 2b, except that there is a trench type gate 280 configuration in the IGBT structure. The gate oxide goes around the trench which is a sensitive region of the device. The trench area needs to be protected from the pressure and thus the recess or void is formed over the trench gate as well.
Figure 3 is a schematic cross-sectional diagram of a press pack package where pressure is borne on regions without sensitive contact underneath. Many features of Figure 3 are the same as those shown and described in respect of Figures 2a and 2b, except that external metal layers 240 are formed on the Ag layers 235 in both the front and back surfaces of the power semiconductor device. The external metal layer 240 for press-pack is generally moly. The contact between moly and silver relies on sufficient pressure being applied. Generally around 20kN or higher pressure is applied in a press-pack package. Although a number of dies are included inside each package, hence pressure on individual die is likely to be less than 20kN. However, due to the likely height difference between the poles and dies inside the press-pack package, some dies is likely to experience higher pressure than others. Generally each die should be able to withstand the full load (~20kN) for the package and the proposed layout should be able to do that. Also, the external metal (moly) can be silver-plated as well to assist the contact and reduce the contact resistance.
Figure 4 illustrates a schematic diagram for double-sided silver sintering package. Many features of Fig. 4 are the same as Fig. 3, except that an Ag paste layer 250 is used to bond with the Ag metal layer 235 in both front and back end surfaces. The Ag paste 250 is used to bond to a substrate 255. A silver sinter joint 260 is formed between the Ag paste 250 and Ag metal layer 235. The proposed new metallization with extra metals on both top and bottom end surfaces are not only useful in the above-mentioned press-pack packages (in Fig. 3), but also in silver sintering process. Silver sintering is an emerging technology in high power module production for bonding the semiconductor chip onto substrates. It is a silver to silver bonding under pressure and temperature. Fig. 5 shows an example of a cross- sectional image of such a bond.
Despite the existence of some holes 501 in Fig. 5, the bond is robust and more reliable than normal soldered bond. However, significant pressure, typically 4kN per dies, is applied during the sintering process. Therefore the structure should be able to improve production yield due to aforementioned reasons, even if sintering on the bottom side only (or at the second surface of the device).
The power semiconductor device can also be used for double-sided sintering (both top and bottom). Double sided silver sintering is an emerging packaging concept, where current aluminium wire-bonding to connect the top of the chips to substrates is replaced with direct silver bond between chip and another substrate circuit. The advantages of that are multi-folds: firstly, much increased reliability and lifetime expected as currently the aluminium wire bonding is the weak point; secondly, reduced inductance will improve switching speed and module performance; Thirdly, the loss due to joule heating (also called resistive heating) from the bonding wires will be eliminated.
The Joule heating is proportional to current, wire resistivity and time (Q κ I2 R t) . Despite the resistivity R is small (around 0.05 Ω per typical 15mil Al bonding wire), but due to large current (1500A per module for example) is used in operation, the loss due to joule heating from the bonding wires alone can be several hundreds of Watts per module. Replacing bonding wires with silver sintering can eliminate the Joule heating loss caused by the bonding wires.
The bonding wires also induce inductance, normally called stray inductance. The self- inductance of a typical aluminium bonding wire is calculated to be around 19nH, for example. It has been demonstrated that the stray inductance can cause energy loss through formula (EL(ChiP) = (Lxl2)/2), where L is the stray inductance and I is the current through the inductance. This formula is normally applied to discrete components. For modules with a large number (n) of parallel chips, the formula for the inductive energy per chip is given as:
Ei_(chip) = EL(module)/n = L x (n x l2)/2 x n = n x L x l2/2
So inside a large module with a number of chips (n), the inductive loss per chip increases significantly compared with discrete devices. Replacing the Al wire bonding with topside silver sintering will get rid of the inductance caused by the Al wire and decrease the overall inductance per chip, hence energy losses per chip, significantly.
In addition to the aforementioned benefits of elimination of both resistance heating and inductance losses caused by Al wire bonding, the double sided silver sintering, soldering or press pack packaging will enable thermal control through both surfaces. The thermal resistance of aluminium wire is large, and therefore, the temperature control is currently conducted primarily through the bottom surface. Double sided silver sintering/soldering package will afford a way of thermal management through both surfaces. Since the active region is close to the top surface, hence temperature control through the top surface will be more effective.
Although the above description mainly describes the use of an IGBT as the power semiconductor device, but it would be appreciated that other types of vertical power semiconductor devices can be applicable in the invention as well. For example, a vertical power MOSFET can use the metallization layer proposed in this invention. The MOSFET is a unipolar device and thus it does not have the injector at the bottom end surface. It would be appreciated that a vertical bipolar junction transistor (BJT) could also be applicable in this invention. The skilled person would be able to identify the sensitive regions of a vertical BJT and grow the additional metal layers on top of the top contact metal layer to form the void or recess which would reduce the pressure during the packaging process. The skilled person will understand that in the preceding description and appended claims, positional terms such as 'above', 'below', 'front', 'back', 'vertical', 'underneath' etc. are made with reference to conceptual illustrations of a semiconductor device, such as those showing standard cross-sectional perspectives and those shown in the appended drawings. These terms are used for ease of reference but are not intended to be of limiting nature. These terms are therefore to be understood as referring to a semiconductor device when in an orientation as shown in the accompanying drawings.
Although the invention has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only and that the claims are not limited to those embodiments. Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. Each feature disclosed or illustrated in the present specification may be incorporated in the invention, whether alone or in any appropriate combination with any other feature disclosed or illustrated herein.

Claims

CLAIMS:
1. A power semiconductor device for high current density applications, the device comprising:
a plurality of semiconductor regions formed on top of one another; a contact layer formed above a first surface of one of the semiconductor regions, wherein the contact layer comprises a first portion placed in direct contact of said first surface of said one of the semiconductor regions and a second portion formed over an insulation region formed in direct contact of said first surface of said one of the semiconductor regions;
a first metal layer formed at least partly on the second portion of the contact layer;
a second metal layer formed at least partly on the first metal layer, wherein the first and second metal layers are formed in such a way that the first portion of the contact layer and at least a part of the second portion of the contact layer are not pressurised during a packaging process of the power semiconductor device.
2. A MOS gate controlled power semiconductor device comprising:
a plurality of semiconductor regions formed on top of one another; a contact layer formed above a first surface of one of the semiconductor regions, wherein the contact layer comprises a first portion placed in direct contact of said first surface of said one of the semiconductor regions and a second portion formed over an insulation region formed in direct contact of said first surface of said one of the semiconductor regions;
a first metal layer formed at least partly on the second portion of the contact layer;
a second metal layer formed at least partly on the first metal layer, wherein the first and second metal layers are formed in such a way that the first portion of the contact layer and at least a part of the second portion of the contact layer are not pressurised during a packaging process of the power semiconductor device.
3. A power semiconductor device according to claim 1 or 2, wherein the first and second metal layers are formed to provide a recess which is defined by the first portion of the contact layer and at least partly of the second portion of the contact layer and the heights of the first and second metal layers.
4. A power semiconductor device according to claim 3, wherein the recess is filled with air or a gas.
5. A power semiconductor device according to claim 3 or 4, wherein the recess is configured such that no pressure is applied to the first portion of the contact layer and said at least a part of the second portion of the contact layer which is over a channel region in the first surface of one of the semiconductor regions.
6. A power semiconductor device according to any one of claims 3 to 5, further comprising a dielectric layer formed on the first portion of the contact metal layer and at least partly on the second portion of the contact layer.
7. A power semiconductor device according to claim 6, wherein the height of the dielectric layer is about 1 μηι.
8. A power semiconductor device according to any preceding claim, wherein the height of each of the first and second metal layers is about 5 μηι.
9. A power semiconductor device according to any preceding claim, further comprising a gate busbar metal layer formed over the insulator region on the first surface of one of the semiconductor regions, wherein the gate busbar layer is configured to connect to a channel region formed in the first surface of one of the semiconductor regions.
10. A power semiconductor device according to claim 9, further comprising a dielectric layer formed on the gate busbar metal layer.
1 1. A power semiconductor device according to claim 10, wherein the first and second metal layers are formed to provide a further recess which is defined by the surface of the dielectric layer on the gate busbar metal layer and the heights of the first and second metal layers.
12. A power semiconductor device according to claim 1 1 , wherein the further recess is configured such that no pressure is applied to the gate busbar metal layer.
13. A power semiconductor device according to any preceding claim, further comprising a second contact layer formed on a second surface of one of the semiconductor regions, wherein the second surface is located at an opposite end to the first surface of one of the semiconductor regions.
14. A power semiconductor device according to claim 13, wherein the first metal layer is formed on the second contact layer and the second metal layer is formed on the first metal layer.
15. A power semiconductor device according to any preceding claim, wherein the first metal layer is selected from a group comprising nickel, gold and platinum.
16. A power semiconductor device according to any preceding claim, wherein the second metal layer is selected from a group comprising silver, gold and copper.
17. A power semiconductor device according to any one of claims 13 to 16, further comprising a first external metal layer formed on the second metal layer formed over the first surface of one of the semiconductor regions.
18. A power semiconductor device according to claim 17, further comprising a second external metal layer formed on the second metal layer formed over the second surface of one of the semiconductor regions.
19. A power semiconductor device according to claim 18, wherein the first and second external metal layers comprise a material comprising moly.
20. A power semiconductor device according to claim 18 or 19, wherein the first and second external metal layers are silver-plated.
21. A power semiconductor device according to any one of claims 18 to 20, wherein the first and second external metal layers are formed by applying a pressure of about 20 kN.
22. A power semiconductor device according to any one of claims 19 to 21 , wherein the first and second external metal layers are formed by using a press-pack packaging technique.
23. A power semiconductor device according to claim 18, wherein the first external metal layer comprises a material comprising silver, and the second metal layer over the first surface of the semiconductor regions comprises a material comprising silver.
24. A power semiconductor device according to claim 23, wherein the second external metal layer comprises a material comprising silver, and the second metal layer over the second surface of the semiconductor regions comprises a material comprising silver.
25. A power semiconductor device according to claim 24, wherein at least one of the first and second external metal layers is formed on the respective second metal layer by using a silver-sintering packaging technique.
26. A power semiconductor device according to claim 24 or 25, wherein said at least one of the first and second external metal layers is formed on the respective second metal layer by applying a pressure of about 4kN and by applying a predetermined temperature.
27. A power semiconductor device according to claim 25 or 26, wherein the first and second external metal layers are bonded with a substrate.
28. A power semiconductor device according to any preceding claim, wherein the first and second metal layers are formed using an electroplating technique.
29. A power semiconductor device according to any one of claims 1 to 27, wherein the first and second metal layers are formed using an electro-less plating technique.
30. A power semiconductor device according to any preceding claim, wherein the device is an insulated gate bipolar transistor (IGBT).
31. A power semiconductor device according to claim 30, wherein the IGBT is a planner gate IGBT or a trench gate IGBT.
32. A power semiconductor device according to any one of claims 1 to 29, wherein the power device is a metal oxide gate field effect transistor (MOSFET).
33. A power semiconductor device according to claim 1 , wherein the power device is a bipolar junction transistor (BJT).
34. A method of manufacturing a MOS gate controlled power semiconductor device, the method comprising:
forming a plurality of semiconductor regions formed on top of one another; forming a contact layer above a first surface of one of the semiconductor regions, wherein the contact layer comprises a first portion placed in direct contact of said first surface of said one of the semiconductor regions and a second portion formed over an insulation region formed in direct contact of said first surface of said one of the semiconductor regions;
forming a first metal layer at least partly on the second portion of the contact layer;
forming a second metal layer at least partly on the first metal layer, wherein the first and second metal layers are formed in such a way that the first portion of the contact layer and at least a part of the second portion of the contact layer are not pressurised during a packaging process of the power semiconductor device.
35. A method according to claim 34, wherein forming the first and second metal layers comprises providing a recess which is defined by the first portion of the contact layer and at least partly of the second portion of the contact layer and the heights of the first and second metal layers.
36. A method according to claim 34 or 35, further comprising forming a dielectric layer on the first portion of the contact metal layer and at least partly on the second portion of the contact layer.
37. A method according to any one of claims 34 to 36, further comprising forming a gate busbar metal layer over the insulator region on the first surface of one of the semiconductor regions, wherein the gate busbar layer connects to a channel region formed in the first surface of one of the semiconductor regions.
38. A method according to claim 37, further comprising forming a dielectric layer on the gate busbar metal layer.
39. A method according to claim 38, wherein forming the first and second metal layers further comprises providing a further recess which is defined by the first surface of the dielectric layer on the gate busbar metal layer and the heights of the first and second metal layers.
40. A method according to any one of claims 34 to 39, further comprising forming a second contact layer on a second surface of one of the semiconductor regions, wherein the second surface is located at an opposite end to the first surface of one of the semiconductor regions.
41. A method according to claim 40, further comprising forming the first metal layer on the second contact layer on the second surface and forming the second metal layer on the first metal layer.
42. A method according to any one of claims 34 to 41 , wherein the first metal layer is selected from a group comprising nickel, gold and platinum.
43. A method according to any one of claims 34 to 42, wherein the second metal layer is selected from a group comprising silver, gold and copper.
44. A method according to any one of claims 34 to 43 wherein the first and second metal layers are formed using an electroplating technique.
45. A method according to any one of claims 34 to 44, wherein the first and second metal layers are formed using an electro-less plating technique.
46. A method according to any one of claims 34 to 45, wherein the power semiconductor device is packaged using any of press-pack, double-sided silver sintering, double-sided soldering technique.
PCT/GB2016/050336 2015-02-17 2016-02-12 Wafer metallization of high power semiconductor devices WO2016132101A1 (en)

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