WO2016128127A1 - Method for producing a plated-through hole in a multilayer printed circuit board - Google Patents

Method for producing a plated-through hole in a multilayer printed circuit board Download PDF

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Publication number
WO2016128127A1
WO2016128127A1 PCT/EP2016/000210 EP2016000210W WO2016128127A1 WO 2016128127 A1 WO2016128127 A1 WO 2016128127A1 EP 2016000210 W EP2016000210 W EP 2016000210W WO 2016128127 A1 WO2016128127 A1 WO 2016128127A1
Authority
WO
WIPO (PCT)
Prior art keywords
bore
circuit board
printed circuit
multilayer printed
hole diameter
Prior art date
Application number
PCT/EP2016/000210
Other languages
German (de)
French (fr)
Inventor
Johann Hackl
Norbert REDL
Stefan Hörth
Original Assignee
Häusermann GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to DE102015001652.0A priority Critical patent/DE102015001652A1/en
Priority to DE102015001652.0 priority
Application filed by Häusermann GmbH filed Critical Häusermann GmbH
Publication of WO2016128127A1 publication Critical patent/WO2016128127A1/en

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42Plated through-holes or plated via connections
    • H05K3/429Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203Cooling of mounted components
    • H05K1/0204Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0201Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203Cooling of mounted components
    • H05K1/0207Cooling of mounted components using internal conductor planes parallel to the surface for thermal conduction, e.g. power planes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/095Conductive through-holes or vias
    • H05K2201/09581Applying an insulating coating on the walls of holes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/0969Apertured conductors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09809Coaxial layout
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/10416Metallic blocks or heatsinks completely inserted in a PCB
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4046Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire

Abstract

Method for producing a plated-through hole between conductor tracks which are arranged at the top and at the bottom in a multilayer printed circuit board which is composed of a printed circuit board material and comprises at least one copper profile which is embedded in the composite of the multilayer printed circuit board, wherein the plated-through hole is produced by the following method steps: producing a first bore with a first bore diameter through the multilayer printed circuit board by drilling through the top and the bottom conductor track and the embedded copper profile; filling the first bore with an insulating filling material; producing a second bore coaxially in relation to the first bore with a second, smaller bore diameter than the bore diameter of the first bore; lining the bore wall of the second bore with an electrically conductive material and in this way making electrical contact with the top and bottom conductor tracks.

Description

 Method for producing a via in the case of a multi-layer

circuit board

The invention relates to a method for producing a via in a multilayer printed circuit board according to the preamble of claim 1.

Under a via (vertical interconnect access, abbreviated VIA), the present invention understands a vertical electrical connection between the interconnect levels of a printed circuit board. In the simplest case, wire pins or hollow rivets are inserted into a bore of a double-sided circuit board.

Through-hole printed circuit boards provide a better hold and more reliable connection of wired components. In addition to the connection of the individual layers of the printed circuit board, the metallized plated-through holes ensure a better cohesion of the printed circuit board.

With the help of vias, it is possible to change the conductor levels in two- or multi-layer printed circuit boards, which is a prerequisite for the unbundling of complex circuits.

Smaller plated-through holes (micro-via) are drilled in the printed circuit board production with, for example, a laser. Larger plated-through holes are preferably drilled or milled, whereby other geometries (for example elongated holes) can also be produced herewith.

For example, one prior art method of providing a chemical free (electroplating-free) via is the polymer through-hole method, in which silver or copper pastes are pored through or through vacuum. Other methods of making a via are via-plating, conductive paste, riveting or double-sided soldering.

A major disadvantage of the prior art methods is that they have not previously been applicable to multi-layer printed circuit boards with embedded thick copper profiles, in which the thick copper profile should not be electrically connected to the via. Especially with copper profiles wide with thicknesses of> 200 pm, in particular thicknesses> 500 pm and copper profile widths of about 0.5 mm to 12 mm, creating a via with the etching process is no longer possible.

Another drawback with the created plated-through holes according to the prior art is that in the region of the bore in a multilayer printed circuit board, an electrical connection between the individual copper layers occurs, since these are exposed by the drilling process.

The invention is therefore the object of developing a method for creating a via in a multilayer printed circuit board so that a via can be created even with multi-layer printed circuit boards with a wide thick copper profile. Furthermore, a multilayer printed circuit board produced by the method should have a reliable and reliable through-connection without the thick copper profile being electrically connected to the plated-through hole.

To solve the problem, the invention is characterized by the technical teaching of claim 1.

The method according to the invention for producing through-plating has the following method steps:

 • Making a first hole with a first hole diameter through the multi-layer board with holes in the top and bottom traces and the embedded copper profile;

• filling the first hole with an insulating filler material; • making a second bore coaxial with the first bore having a second, smaller bore diameter than the bore diameter of the first bore;

 • Lining of the bore wall of the second bore with an electrically conductive material and electrical contacting of the top and bottom traces.

Preference is given to a so-called. Germination in the sense of low electrical conductivity before the galvanic via.

In a further preferred embodiment of the method steps according to the invention, for example, a:

 • producing printed conductors above the plated-through holes;

 • checking the circuit board;

 • Separation of the printed circuit board

respectively.

With the process essential to the invention it is now possible for a relatively wide copper profile, which has a width between 2 and 12 mm, to pass a foreign potential.

In order to be able to carry out such a foreign potential by means of such a copper profile, it is necessary to drill at least twice into an already plunged hole. A hole-in-hole procedure is performed.

 The method according to the invention has, inter alia, the advantage that an insulating layer is present through the filling material in the region of the bore, which has the potential carried out in comparison to other copper tracks which are in the region of the bore

Area of the middle layer of the conductor track are arranged, isolated.

Furthermore, it is possible with the inventive method to perform a foreign potential through a printed circuit board with at least one copper profile. The subject of the present invention results not only from the subject matter of the individual claims, but also from the combination of the individual claims with each other.

All information and features disclosed in the documents, including the abstract, in particular the spatial design shown in the drawings, are claimed to be essential to the invention insofar as they are novel individually or in combination with respect to the prior art.

In the following, the invention will be explained in more detail with reference to drawings illustrating several execution paths. Here are from the drawings and their description further features essential to the invention and advantages of the invention.

Show it:

FIG. 1A: Schematic representation of plated-through holes after

 State of the art

Figure 2: a schematic representation of a pressing process

Figure 3: schematic representation of a drilling operation of the pluggierten

 Holes in the copper profile

Figure 4: schematic representation of the filling process of the holes in

 copper profile

Figure 5: schematic representation of the drilling process

Figure 6: schematic representation of the copper plating process

Figure 7: Schematic cross section of a multilayer printed circuit board with a

via Figure 8: Schematic plan view of a multi-layer printed circuit board with a via

Figure 9a: Schematic cross-section of a multilayer printed circuit board with a

 Through-hole through two thick copper profiles without electrical contact

Figure 9b: Schematic plan view of a multilayer printed circuit board with a

 Through-hole through two thick copper profiles without electrical contact

FIG. 1 shows a multilayer printed circuit board 1 with different plated-through contacts according to the prior art. The printed circuit board 1 consists of a conventional printed circuit board base material 6, which is FR-4, for example. Also suitable as circuit board material 6 is FR-2, FR-3, FR-4-Low-Tg, CEM-1 CEM-x, PI, CE, aramid or other substrate materials.

The conductor track structure 8, 8 ', 8 "may for example consist of an etched copper layer, wherein the copper overlay is usually thick at a one- or two-sided material 18 pm or 35μιτι.

According to FIG. 1, three different plated-through holes 2, 3, 4 are shown. If the through-hole extends in the vertical direction through the entire printed circuit board 1, this is referred to as a through-hole 2. If the through-connection does not extend through the entire printed circuit board 1, but only to one of the middle layers 7, this is called a blind via 3. A blind via thus connects an outer layer with one or more middle layers 7 (inner layers). If plated-through holes are only between the middle layers 7, they are called buried via 4. A buried via is therefore a through-connection between at least two inner layers, which are of the outer layers is not visible from. This technology allows more functionality to be accommodated on a small PCB surface (packing density)

To the plated-through hole 2, 3, a circumferential copper ring is arranged, which has arisen by a previous copper plating process. This copper ring is also called Restring (narrow Annular Ring).

A significant disadvantage of the plated-through hole 2, 3, 4 according to the prior art is that it comes in the area of the conductor tracks 8 and the copper profile 5 by the copper plating 15 of the entire through-hole 2. This contact should therefore be avoided.

2 shows the structure of a circuit board 1 according to the invention is shown schematically. The view according to FIG. 2 is a cross section through the profile of a multilayer printed circuit board 1. In the composite of the multilayer printed circuit board 1, at least one copper profile 5 is embedded.

At least one strip conductor 8 'is arranged on the surface of the printed circuit board 1 and at least one further strip conductor 8 " on the underside so that the two strip conductors 8 ' , 8 " can be interconnected with a potential from the upper side to the lower side through the profile the circuit board 1 are driven by. For this purpose, a via 2 is necessary.

FIG. 3 shows the printed circuit board 1 of FIG. 2, in which a first (through) bore 9 having a relatively large hole diameter 1 1 has already been created. The first bore 9 has, for example, a hole diameter of about 0.5 mm and extends through the entire profile of the printed circuit board first Of course, the present invention is not limited to a through hole. All method steps according to the invention can also be used in blind via 3 or buried via 4.

FIG. 4 shows the first bore 9, which is filled with an insulating filling material 12. The filling material 12 consists for example of plastic, metal or solder, for example, and preferably fills the entire first bore 9. The next method step is shown with reference to FIG. After filling the first bore 9 with the insulating filling material 12, a second, second drilling operation takes place in the coaxial region of the first bore 9, with which a second bore 14 having a hole diameter 13 is produced. Both holes 9 and 14 have here Favor the same center line 10. However, it is also possible that, for example, the bore 14 is arranged outside the center line 10 of the bore 9.

It is important that the second hole diameter 13 of the second bore 14 is smaller than the first hole diameter 1 1 of the first bore 9. In a preferred embodiment, the second hole diameter 13 is at least 1/10 smaller than the first hole diameter 11.

The following hole diameters 1 1 and 13 are possible, for example:

 • 0.5 mm for the first hole diameter 11 and 0.3 mm for the second hole diameter 13;

 • 0.4 mm for the first hole diameter 11 and 0.2 mm for the second hole diameter 13;

 • 0.6 mm for the first hole diameter 11 and 0.4 mm for the second hole diameter 13.

The ratios of the two diameters 11, 13 of the first and second bores 9, 14 are preferably selected such that an edge region 18 of the insulating filling material 12 always remains in the region of the through-bore 2. The edge region 18 thus serves as an insulating layer, which extends through the entire profile of the printed circuit board 1.

FIG. 6 shows the lining of the bore wall of the second bore 14 with an electrically conductive material 15. For mounting the conductive material, it is possible, for example, to carry out a galvanic copper plating process with which a copper layer is applied in the region of the through-hole 2 or bore 14. In a further preferred embodiment, as a conductive material 15, for example, a sleeve or a plug can be inserted into the through-hole 2.

According to FIG. 7, the multilayer printed circuit board 1 is shown, in which the plated-through hole 2 is closed with a filling material 16. This may be, for example, a hole-in-pad technology, in which a subsequent closing of the holes takes place in order to allow direct loading and soldering at these locations. The subsequent closing of the via holes is performed with a filler material 16 such as e.g. a plied via or a copper-filled via possible.

With the figure 8, the finished multilayer printed circuit board 1 is shown with the through-hole 2 in plan view. The circular plated-through hole 2 has, starting from the outer edge of the first bore diameter 1 1, first a ring made of the insulating filler material 12 and then the filling material 16.

As a result of the above process steps, a hole is obtained in the hole with an integrated thick copper profile.

The type of double penetration is particularly interesting when using several or larger-scale thick copper elements. The application is therefore preferably used in printed circuit boards, as well as in thick copper inserts or in two superposed thick copper elements.

Furthermore, contacting bores and additional heat conducting bores (thermal vias) in the multilayer printed circuit board 1 are possible. Thus, in a preferred embodiment, a number of heat-emitting components, such as LEDs are arranged on the circuit board 1, wherein the heat dissipation is realized, inter alia, on the thick copper profile. According to the figure 9.a, the multilayer printed circuit board 1 is shown schematically in section, wherein the through-hole is made by means of conductive material 15 by two thick copper profiles 5 without electrical contact. The implementation is carried out by the insulating filler material 12, for example, to electrically connect an upper conductor 8 'and a lower conductor 8 ".

In this particular embodiment, prior to making the inner via 15, another outer via 15 is made to electrically connect the thick copper profiles 5.

FIG. 9b shows the top view of the multilayer printed circuit board 1 according to FIG. 9a, whereby in this embodiment no conductive filling material 16 is shown, which however is usually used for closing the hole.

drawing Legend

Multi-layer printed circuit board

 Through hole / through hole blind via

buried via

 copper profile

 PCB material

 center position

Conductor, 8 'conductor above, 8 " conductor below

Bore big

 center line

 Hole diameter large

 Insulating filler

 Hole diameter small

 Bore small

 Conductive material

 Conductive filling material

border area

Claims

claims
1 . Method for producing a via (2) between upper and lower side arranged conductor tracks (8, 8 ' , 8 " ) in a multi-layer printed circuit board (1), which consists of a printed circuit board material (6) and at least one in the composite of the multilayer printed circuit board embedded copper profile (5), wherein the via (2) is produced by the following process steps:
• Producing a first bore (9) with a first bore diameter (1 1) through the multilayer printed circuit board (1) with perforation of the top and bottom interconnect (8, 8 ' , 8 " ) and the embedded copper profile (5);
 Filling the first bore (9) with an insulating filler (12);
• making a second bore (14) coaxial with the first bore (9) with a second, smaller bore diameter (13) than the bore diameter (11) of the first bore (9);
 • Lining of the bore wall of the second bore (14) with an electrically conductive material (15).
2. multilayer printed circuit board produced by the method according to claim 1, characterized in that the hole diameter (13) of the second bore (14) is smaller than the hole diameter (1 1) of the first bore (9) is selected such that an electrical insulation between the electrically conductive material (15) and the thick copper profile (5) and any conductor tracks (8) is ensured.
3. Multi-layer printed circuit board produced by the method according to claim 1 or 2, characterized in that the hole diameter (13) of the second bore (14) is smaller by 1/10 than the hole diameter (1 1) of the first bore (9).
4. multilayer printed circuit board produced by the method according to claim 1, characterized in that the hole diameter (1 1) of the first bore (9) about 0.5 mm and hole diameter (13) of the second bore (14) is about 0.3 mm ,
5. multilayer printed circuit board produced by the method according to claim 1, characterized in that the hole diameter (1 1) of the first bore (9) about 0.6 mm and hole diameter (13) of the second bore (14) is about 0.4 mm ,
6. multilayer printed circuit board produced by the method according to one of claims 1 to 5, characterized in that the filling material (12) for the bore (9) consists of an insulating material.
7. multilayer printed circuit board produced by the method according to one of claims 1 to 6, characterized in that the copper profile (5) has at least a width greater than 500 prn and a thickness of greater than 200 pm, in particular greater than 500 pm.
8. Multi-layer printed circuit board produced by the method according to one of claims 1 to 6, characterized in that in the region of the through-contact (2) an edge region (18) of the filling material (12) is present, which is a distance between the first Hole diameter (1) and the second hole diameter (13) ensures.
9. multilayer printed circuit board produced by the method according to one of claims 1 to 7, characterized in that for lining the bore wall of the second bore (14) a sleeve or a plug of a conductive material (15) can be used.
10. A method for producing a via (2) one of claims 1 to 9, characterized in that following the lining of the bore wall of the second bore (14) with an electrically conductive material (15) closing the bore (14) another filling material (16) takes place.
PCT/EP2016/000210 2015-02-12 2016-02-06 Method for producing a plated-through hole in a multilayer printed circuit board WO2016128127A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE102015001652.0A DE102015001652A1 (en) 2015-02-12 2015-02-12 A process for producing a plated-through hole in a multilayer printed circuit board
DE102015001652.0 2015-02-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP16706131.6A EP3257335A1 (en) 2015-02-12 2016-02-06 Method for producing a plated-through hole in a multilayer printed circuit board

Publications (1)

Publication Number Publication Date
WO2016128127A1 true WO2016128127A1 (en) 2016-08-18

Family

ID=55411343

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP2016/000210 WO2016128127A1 (en) 2015-02-12 2016-02-06 Method for producing a plated-through hole in a multilayer printed circuit board

Country Status (3)

Country Link
EP (1) EP3257335A1 (en)
DE (1) DE102015001652A1 (en)
WO (1) WO2016128127A1 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5208068A (en) * 1989-04-17 1993-05-04 International Business Machines Corporation Lamination method for coating the sidewall or filling a cavity in a substrate
DE10332579A1 (en) * 2003-07-17 2004-11-25 Siemens Ag Electronic circuit board is manufactured with both external and internal conductor tracks
US20130319734A1 (en) * 2012-05-31 2013-12-05 Samsung Electro-Mechanics Co., Ltd. Package substrate and method of manufacturing the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6937120B2 (en) * 2003-04-02 2005-08-30 Harris Corporation Conductor-within-a-via microwave launch
ITTV20060030A1 (en) * 2006-03-10 2007-09-11 Elettrolab Srl An electronic device for the ambient lighting.
DE102011101805B4 (en) * 2011-05-17 2016-08-25 Fela Holding Gmbh circuit support

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5208068A (en) * 1989-04-17 1993-05-04 International Business Machines Corporation Lamination method for coating the sidewall or filling a cavity in a substrate
DE10332579A1 (en) * 2003-07-17 2004-11-25 Siemens Ag Electronic circuit board is manufactured with both external and internal conductor tracks
US20130319734A1 (en) * 2012-05-31 2013-12-05 Samsung Electro-Mechanics Co., Ltd. Package substrate and method of manufacturing the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
None

Also Published As

Publication number Publication date
DE102015001652A1 (en) 2016-08-18
EP3257335A1 (en) 2017-12-20

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