WO2016115601A1

WO2016115601A1 - A method of anodising a surface of a semiconductor device

Info

Publication number: WO2016115601A1
Application number: PCT/AU2016/050027
Authority: WO
Inventors: Alison Joan Lennon; Zhong Lu
Original assignee: NewSouth Innovations Pty Ltd
Current assignee: NewSouth Innovations Pty Ltd
Priority date: 2015-01-20
Filing date: 2016-01-20
Publication date: 2016-07-28
Anticipated expiration: 2017-07-20

Abstract

The present disclosure provides a method of anodising a surface comprising a metallic material. The method comprises the step of exposing a portion of the surface to an electrolytic solution that is suitable for anodising the metallic material. Further, the method comprises the steps of exposing a portion of an electrode to the electrolytic solution; selecting one or more parameters of an alternate waveform; and applying an electric wave having the alternate waveform to the exposed portion of the surface to anodise the portion of the surface. The one or more parameters of the alternate waveform are selected in a manner to influence an amount of stored charge embedded in the anodised material.

Description

A METHOD OF ANODISING A SURFACE OF A SEMICONDUCTOR DEVICE

Technical Field of the Invention The present invention relates generally to the field of anodisation of surfaces containing a metallic material, in particular, to a method and apparatus for anodising a surface of a device containing a metallic material. Background of the Invention

Dielectric layers are used in electronic devices to perform a variety of functions. In silicon solar cells, for example, dielectric layers are used to ^>passivate' surfaces of the cell and ensure high operating voltages. In MOSFETs a very thin dielectric layer is used to

separate the gate electrode from the channel of the device and form a metal-oxide-semiconductor capacitor. Dielectric layers can be fabricated by direct deposition, thermal growth or anodisation. No matter which fabrication technique is used, dielectric layers always contain a residual amount of stored charge. Thermally-grown layers of silicon dioxide and PECVD layers of silicon nitride, for example, can store positive charges. PECVD or ALD aluminium oxide layers can contain stored negative

charges .

In many applications, the residual charge stored in the dielectric layers, can be used to improve the performance of the devices. For example, in solar cells, stored charge can be used to repel electrical carriers of one polarity from a surface of the device to decrease the probability of carrier recombination at that surface. Anodisation provides a series of advantages, such as atmospheric pressure and room temperature operation and low environmental impact. For the fabrication of solar cells, for example, anodisation allows meeting the

challenging cost/volume production requirements and can be integrated in existing cell production lines. However, the amount of residual stored charge in dielectric layers grown by anodisation, and also by other techniques, is not controllable, preventing the optimisation of device properties and performance.

Different methods have been previously used in the art to control stored charge in dielectric layers. For example, the stored charge in AI₂O₃/S1O₂ stacks, deposited by ALD on Si substrates, can be controlled in both magnitude and polarity, by varying the S1O₂ thickness. However, this requires a very accurate control of the ALD S1O₂ thickness which makes the process costly and time consuming. A corona discharge has been shown to create and store negative charge in SiN_x/Si0₂ stacks, grown by PECVD on Si substrates. This method however may introduce extra damages to the interfaces as the negative charge origins from the tunneling of electrons from silicon to silicon nitride. Furthermore the stored negative charge appears to be unstable at elevated temperatures.

Improved anodisation methods and apparatuses are needed in the art to allow for enhanced device performance. Summary of the Invention

In accordance with a first aspect, the present invention provides a method of anodising a surface comprising a metallic material, the method comprising the steps of: exposing a portion of the surface to an electrolytic solution that is suitable for anodising the metallic material ;

exposing a portion of an electrode to the

electrolytic solution;

selecting one or more parameters of an alternate waveform; and

applying an electric wave having the alternate waveform to the exposed portion of the surface to anodise the portion of the surface;

wherein the one or more parameters of the alternate waveform are selected in a manner to influence an amount of stored charge embedded in the anodised material.

In accordance with a second aspect, the present invention provides a method of controlling stored charge in an anodised material comprising the steps of:

selecting one or more parameters of an alternate waveform; and

applying an electric wave having the alternate waveform between a metallic material and an electrode while the metallic material is being anodised.

In embodiments, the electrode can be made of one or a combination of nickel, copper or aluminium. In alternative embodiments, the electrode can be an inert electrode, such as a platinum, palladium or graphite electrode.

In an embodiment, the one or more parameters of the alternate waveform are selected in a manner to influence sign and magnitude of stored charge embedded in the anodised material. The alternate waveform may be a square waveform and the step of selecting one or more parameters of the alternate waveform may comprise selecting one or a combination of:

i. a positive value of the waveform;

ii. a negative value of the waveform;

iii. a duty cycle value of the waveform; and iv. a frequency value of the waveform.

The selected value of duty cycle may be between 30% and 100%. The selected value of frequency may be between

0.05Hz and 10Hz. Furthermore, the alternate waveform may be a pulsed waveform.

In an embodiment, the step of selecting one or more parameters of the alternate waveform comprises at least selecting the positive value or the negative value.

In embodiments, the alternate waveform is a current waveform. The positive current value may be between 1 mA/cm² and 5 mA/cm² and the negative current value may be between -1 mA/cm² and -5 mA/cm².

In other embodiments, the alternate waveform is a voltage waveform. The positive voltage value may be between 10 V and 50 V. The negative voltage value may be between -10 V and -50 V.

In an embodiment, the one or more parameters of the alternate waveform are selected in a manner such that the stored charge embedded in the anodised material has an effective density between -10 10¹¹ q/cm² to 10 10¹² q/cm².

In accordance with the third aspect, the present invention provides an apparatus for anodising a surface comprising a metallic material, the apparatus comprising:

a container for containing an electrolytic solution; an electrode element positioned for contacting the electrolytic solution; and

an alternate waveform generator arranged to apply an electric wave having an alternate waveform to the exposed portion while the metallic material is being anodised. In an embodiment, the generator is arranged to apply a current waveform through the surface comprising the metallic material and the electrode and to provide tunability of one or more parameters of the alternate waveform.

The alternate waveform may be a square waveform and the generator may be arranged to provide tunability of one or a combination of:

i. a positive current value of the waveform;

ii. a negative current value of the waveform;

iii. a duty cycle value of the waveform; and

iv. a frequency value of the waveform. By tuning one or a combination of parameters i to iv the amount of stored charge embedded in the anodised material may be influenced. In embodiments, the amount of stored charge embedded in the anodised material is controllable between -10 10¹¹ q/cm² to 10 10¹² q/cm².

In embodiments, the apparatus further comprises a support arranged to support a device, the surface comprising the metallic material being part of the device, such that in use the surface is exposed to the electrolytic solution when the container is charged with the electrolytic solution .

In embodiments, the apparatus further comprises a

radiation source arranged to illuminate a portion of the device in a manner such that a radiation-induced current is generated in the device to promote anodisation of the surface comprising the metallic material.

In accordance with a fourth aspect, the present invention provides a charge filtering structure for separating positive charge carriers from negative charge carriers comprising an anodised material which is anodised in accordance with the first aspect.

In accordance with a fifth aspect, the present invention provides a Perovskite based photovoltaic cell comprising a charge filtering structure in accordance with the fourth aspect .

In accordance with a sixth aspect, the present invention provides a kesterite based photovoltaic cell comprising a charge filtering structure in accordance with the fourth aspect .

In accordance with a seventh aspect, the present invention provides a photovoltaic cell device comprising an anodised layer formed by a method in accordance with the first aspect .

In accordance with an eight aspect, the present invention provides a photovoltaic cell device comprising a

negatively doped base region and a positively doped emitter region wherein the emitter region is in contact with an anodised layer formed by a method in accordance with the first aspect, the anodised layer having a net negative stored charge and being arranged to electrically passivate at least a portion of the emitter region.

In accordance with a ninth aspect, the present invention provides a photovoltaic cell device comprising a

positively doped base region and a negatively doped emitter region wherein the emitter region is in contact with an anodised layer formed by a method in accordance with the first aspect, the anodised layer having a net positive stored charge and being arranged to electrically passivate at least a portion of the emitter region.

In accordance with a tenth aspect, the present invention provides a photovoltaic cell device comprising:

a base region;

an emitter region;

a contacting region, the contacting region comprising a plurality of interdigitated negatively doped and

positively doped semiconducting portions; and

an anodised layer, disposed in proximity of the contacting region, the anodised layer being formed by a method in accordance with the first aspect.

In an embodiment, the anodised layer has a quasi-neutral net stored charge.

In accordance with an eleventh aspect, the present

invention provides a metal-oxide-semiconductor capacitor structure comprising:

a semiconducting substrate or a semiconducting layer; a thin dielectric layer disposed on a surface portion of the semiconducting substrate or semiconducting layer, the thin dielectric layer being formed by a method in accordance with the first aspect; and

an electrode disposed in contact with at least a portion of the thin dielectric layer. In accordance with a twelfth aspect, the present invention provides a metal-oxide-semiconductor field effect

transistor comprising a metal-oxide-semiconductor

capacitor in accordance with the eleventh aspect. Brief Description of the Drawings

The embodiments of the invention will now be described, by way of example, with reference to the accompanying

drawings in which:

Figure 1 is a flow chart of an anodisation process; Figure 2 is a schematic representation of an

anodisation apparatus;

Figure 3 is a schematic illustration of an alternate waveform generator;

Figure 4 is an illustration on an alternate pulsed current waveform;

Figures 5 and 6 are simplified schematic illustrations of solar cell devices comprising an anodised layer;

Figure 7 is an illustration of the band structure of a solar cell comprising carrier filtering contacts;

Figure 8 shows current and voltage profiles of a sample anodised by a pulsed current with a 50% duty cycle;

Figure 9 shows a comparison of voltage profiles for pulsed anodisation;

Figure 10 shows plots of the effective stored charge density and dark saturation current density as a function of positive cycle percentage for different anodised samples ;

Figure 11 shows a schematic diagram of a stacked dielectric structure used to determine the stored charge distribution;

Figure 12 is a plot showing the measured flat-band voltage as a function of dielectric thickness; and

Figure 13 is a plot showing the simulated effective charge as a function of the anodised layer thickness for different dielectric inter-layer thicknesses.

Detailed Description of Embodiments Embodiments of the present invention relate to a method and an apparatus for anodising a surface comprising a metallic material. The method uses an electrolytic bath with an electrolytic solution. The surface to be anodised is put into contact with the solution together with an additional electrode. The electrode can be made of one or a combination of nickel, copper or aluminium. Alternatively, the electrode can be an inert electrode, such as a platinum, palladium or graphite electrode.

A wave with an alternate waveform is then applied to the system comprising the surface to be anodised, the bath and the electrode. The waveform can be obtained from a current generator, in which case a predetermined current will be flowing through the system. Alternatively, the waveform can be a voltage waveform, in which case the current flowing through the system will be related to specific properties of the electrolytic bath, the surface being anodised and the electrode.

Prior to the application of the waveform to the system, the waveform is tailored' by selecting one or more

Vaveform parameters' . The selection of these parameters allows influencing the amount of stored charge embedded in the anodised material. Embodiments of the method allow controlling the sign and magnitude, with a certain level of precision, of the stored charge in the material being anodised using the tailored waveform. Parameters of the waveform which can be tailored include the positive value of the waveform, the negative value of the waveform, the duty cycle value and the frequency of the waveform. In advantageous

embodiments, the waveform is a square waveform with a positive and a negative value. Referring now to figure 1, there is shown a flow chart 100 of an anodisation process in accordance with an

embodiment. A portion of the surface of the device to be anodised is exposed to the electrolytic solution in the electrolytic bath at step 105 and the electrode is also exposed to the solution 110. At step 115 the one or more parameters of the alternate waveform are selected based on the sign and magnitude of the stored charge desired in the final anodised layer. At step 120 the alternate waveform is applied to the system and the anodisation process is commenced .

Referring now to figure 2, there is shown a schematic representation of an anodisation apparatus 200 suitable to perform method 100 in accordance with an embodiment.

Apparatus 200 comprises a container 202 for containing an electrolytic solution 204. An electrode 206 is partially submerged in solution 204. The system includes alternate waveform generator 214 which applies an alternate waveform to the surface 205 being anodised and the electrode 206. The system may also include a support to support device 201 in a manner such that a specific surface of device 201 is exposed to the electrolytic solution.

Chemical solution 204 is typically an electrolytic

solution containing an oxygen source. Chemical solution 204 may for example comprise an electrolyte with 0.5 M sulphuric acid. However, concentrations in the range of 0.2 M and 2.0 M can also be used. Sulphuric acid is known to result in faster anodisation compared to other

electrolytes (i.e., phosphoric acid and oxalic acid) .

In the example of figure 2, the device being anodised could be a silicon solar cell or a silicon substrate. The surfaces of device 201 could comprise a thin oxide and a metallic layer, such as an aluminium layer which is exposed to the electrolytic solution to be anodised.

Device 201 could be positioned on a support in a manner such that only the aluminium layer is exposed to

electrolytic solution 204 during the anodisation process. In some embodiments, apparatus 200 includes a radiation source arranged to illuminate a portion of the device being anodised. If the device being anodised is capable of generating a photocurrent , such as a solar cell, the photocurrent is used to promote anodisation of the surface portion. In some embodiments the radiation source and the alternate waveform generator 214 generator are used in synergy and the radiation source may be driven using a specular waveform to the one applied by waveform generator 214. In some other embodiments, the photocurrent may be sufficient to sustain the anodisation process and the radiation induced current may be the primary or sole drive of the process.

In the embodiment illustrated in figure 2, alternate waveform generator 214 is a current generator which provides a current with a square waveform (pulsed) through the electrochemical circuit comprising device 201, electrolytic solution 204 and electrode 206.

Referring now to figure 3, there is shown a schematic of a simplified implementation of an alternate waveform current generator 300 in accordance with an embodiment. Current generator 300 comprises a pulse generator 302 capable of generating currents with an alternate waveform and, in particular, pulsed waveforms. Generator 300 also comprises a metering function implemented by ammeter unit 304 and volt meter unit 306. The metering function allows

monitoring the applied current and the equivalent

resistance at the output of the waveform generator. In addition, generator 302 includes a data logging module 308 to store data related to the applied waveforms.

An example of current waveform 400 used to anodise a metallic surface is shown in figure 4. In the example of figure 4, the waveform is designed to be symmetric in respect to the amplitude axis, meaning that the positive value of current applied to the circuit has the same magnitude of the negative value of current. The duty cycle of waveform 400 is 50%. This means that the duration of the positive current equals the duration of the negative current. Depending on the material being anodised, and the electrochemical solution being used, waveform 400 provides a different value of stored charge in the anodised layer.

The ability to control the magnitude and also the sign of the stored charge simultaneously provides a great

advantage for the fabrication of numerous electronic devices. In the case of silicon solar cells, for example, anodised layers can be used to passivate silicon surfaces. Generally highly doped silicon surfaces are positioned in proximity of electrical contacts to minimise minority carrier recombination. Depending on the type of doping of the silicon material, anodised layers with a different type of residual charge are required to improve the passivation performance. Referring now to figure 5, there are shown two schematic representations of solar cell devices 500 and 550. Figure 5(a) shows a solar cell with a phosphorous doped emitter 502. For this type of emitter an anodised layer 504 containing a high positive stored charge ( +Q_eff) is used for passivation. In the case of the solar cell device 550 of figure 5(b), the highly boron doped emitter 552, must be passivated with a dielectric layer 554 with a highly negative stored charge to provide optimal performance (-

Referring now to figure 6(a), there is shown a schematic representation of a solar cell device 600. The back surface 602 of solar cell 600 has a plurality of closely spaced n⁺ (604) and p⁺ (606) regions. For surface 602 a passivation layer containing a high amount of positive or negative stored charge is not suitable. An anodised layer with a quasi-neutral stored charge 608 provides better performance in this case. Figure 6(b) shows an actual implementation of device 600. In the Interdigitated Back Contact (IBC) Cell 650, n-type regions 652 and p-type regions 654 are interdigitated at the back of the device. The rear surface can be passivated by an anodic aluminium oxide layer 656 which can be in accordance with method 100 to obtain an interface with very low interface defects and a neutral stored charge.

Anodised layers manufactured in accordance with method 100 can be used in other electronic devices and, in particular in other types of solar cells where a control over the stored charge of the anodised layer is desirable. These solar cell structures include perovskite and kesterite based photovoltaic cells.

In general, semiconducting metal oxides realised by anodising a metallic material by method 100 provide the possibility of creating a charge type filtering structure for separating positive charge carriers from negative charge carriers. These types of structures can be used as charge type selective contacts in a plurality of

photovoltaic devices. In particular, these structures can be beneficial to form charge type selective molybdenum oxide layers, tungsten oxide layers and titanium oxide layers. Charge type filtering is provided by the

capability of tuning the electronic environment of the 0 atoms using method 100 and apparatus 200. Current

deposition methods of sputtering and evaporation allow little material control.

Referring now to figure 7, there is shown a schematic band diagram 700 of a photovoltaic device comprising two charge type selective contacts. These can also be referred to as ^xhole selective membrane' 702 and Electron selective membrane' 704, depending on whether they are designed to filter electrons or holes. Carrier-selective contacts for silicon solar cells require aligned band edges for

electron/hole transport. They need to minimise

recombination at the silicon interface and provide a good diffusion barrier for the metal contact. In addition they need to comply with the series resistance requirements of the device. By tuning the parameters of the alternate waveform

provided by alternate waveform generator 214, the amount of stored charge in the anodised layer can be engineered and so the carrier selectivity of semiconductive metal oxides layers realised in accordance with method 100.

Figure 8 shows a plot 800 with a current profile 702

(dashed line) and a voltage profile 704 (full line) of a sample anodised by a pulsed waveform with a 50% duty cycle used in a series of experiments performed on solar cells. In these experiments, an alternate waveform generator was used in constant current mode with I = 30 mA with a voltage limit of 30V. The duty cycle was varied between 50% and 95%. Cycle lengths of 20 s and 10 s were used. Figure 9 shows a plot 900 with a comparison of two voltage profiles for anodised layers formed by conventional 902 and pulsed 904 (with negative cycles removed from the graph) anodisation techniques. The voltage profiles of the two anodisation processes have a similar shape while the pulsed anodisation 904 takes longer time to complete. This indicates that the introduced negative portion of the cycle in the pulsed waveform is likely to stimulate reverse reactions for which the positive cycle has to compensate .

Referring now to Figure 10, there are shown two plots 130 saturation current density for different MIS structures comprising a silicon dioxide interlayer and an anodised metallic layer. Plot 130 shows the effective stored charge density as a function of positive cycle percentage for samples with three different of AAO thicknesses: 400 nm (triangles 132); 280 nm (circles 134) and 50 nm (squares 136) on 17 nm intervening S1O₂ layer. Error bars indicate the standard deviation of independent samples.

The Qe_ff of the S1O₂/AAO dielectric stack varied as a function of the duty cycle of the applied waveform for dielectric stacks with different AAO thickness. With decreasing duty cycle, the magnitude of the positive Q_eff decreases and then, for thicker AAO layers, is inverted to a net negative charge at low duty cycle values.

In these specific experiments, for the MIS structures with a 50 nm AAO layer, however, varying the duty cycle was only able to change the magnitude of Q_eff but not the polarity even at a 30% positive duty cycle. For the MIS structures with thicker AAO layers, the magnitudes of the achieved negative Q_eff were similar in all cases,

indicating the presence of limiting factors other than duty cycle and AAO thickness. The S1O₂ interlayers, for example, have been found to have strong impact on the limiting Q_eff range. By reducing the S1O₂ from 17 nm to 12 nm, more negative Q_eff can be achieved, as shown in plot 150.

Plot 150 shows the effective stored charge density as a function of duty cycle for samples with two types of AAO thicknesses: 300 nm (squares 152) and 100 (circles 154) nm on 12 nm intervening S1O₂ layer. Error bars indicated the standard deviation of independent samples. The Q_eff follows a similar trend with the varying positive pulse percentage for the two different AAO thicknesses. However, the 300 nm AAO samples demonstrated high positive stored charge under low positive pulse condition. A prolonged negative DC bias can cause an increase in both interface defect density and positive Q_eff. In this case, the samples with 300 nm AAO experienced a longer anodisation process in which a negative bias was applied for 70% of the total duration. This relates to the increase in Q_eff shown in plot 150 for the 300 nm AAO samples. The 100 nm AAO samples did not go through a longer anodisation process, thus the interface damages were less severe and could be readily regenerated by the subsequent annealing process.

Figure 11 shows a schematic diagram 180 of a test

structure used to determine the stored charge

distribution. In the experiments discussed above, the amount of stored charge has been calculated using the model discussed below. This model focuses on the effective value of stored charge at the Si0₂/Si interface. Structure 180 consists of an interface charge of Q_Sio at Si0₂/Si interface, Q_Aio at A10_x/Si02 interface and bulk stored charge p.

The test structures consist of a series of AAO layers 182 formed by 85% positive pulse anodisation with different thicknesses. AAO layers 182 were deposited on a S1O₂ interlayer 184 that forms a gate dielectric for a MOS CV structure with p-type silicon layer 186. Two interface charges and a bulk stored charge are the main contributors to the induced surface voltage, and thus the measured effective stored charge (Q_eff) · Based on this model, the flatband voltage is given as:

where C_tot is the total capacitance of the stack; t_{eff A}I_O is - li the effective oxide thickness of the A10_x layers. t_eff AIO is calculated by multiplying the physical thickness of the A10_x layer by a ratio between the dielectric constants of Si and AI₂O₃ . The total effective oxide thickness, t_eff, is the physical thickness of the interlayer oxide: t_sio₂ plus t_eff AIO- The position, x, is defined to be zero at the outmost surface of the A10_x layers. The A10_x bulk stored charge is assumed to be constant through the AAO

thickness. With a few rearrangements, the previous

equation can be simplified to:

VFB — 0MS ^~~

Based on this equation, the flatband voltage of the step MIS structures shall display a parabolic relationship to the total effective oxide thickness.

Referring now to figure 12, there is shown a plot 250 comprising a parabolic fitting of the measured V_FB as a function of t_eff. The fitting can be used to extract Qsio , Q_Aio and p by comparing the fitted analytic formula to the last equation. The extracted parameters are shown in table I .

Table I. Parameters extracted from a parabolic fitting of flatband voltage as a function of effective oxide thickness.

Referring now to figure 13, there is shown a plot 350 of the simulated effective charge as a function of the anodised layer thickness for different dielectric inter^¬ layer thicknesses. The measured Q_{ef f} is related to Qsio ^ QAIO and p by the following equation:

teff t, eff

The input parameters for this equation can be extracted from the fitting in figure 12, (85% duty cycle) . Figure 13 shows the behaviour of Q_eff for interlayer thicknesses of 30 nm (352), 20 nm (354), 17 nm (356), 12 nm (358) and 3 nm (360) . Plot 350 demonstrates that with a thinner interlayer S1O₂, a higher value of negative charge can be achieved .

The anodisation method described herein can be also used to control the stored residual charge in the channel oxide of metal-oxide-semiconductor (MOS) capacitors and other types of capacitors. The accurate control of the stored residual charge in the channel oxide is important to optimise the performance of MOS based devices, such as MOS field effect transistors.

Any discussion of documents, acts, materials, devices, articles or the like which has been included in the present specification is not to be taken as an admission that any or all of these matters form part of the prior art base or were common general knowledge in the field relevant to the present invention as it existed before the priority date of each claim of this application.

Throughout this specification the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element, integer or step, or group of elements, integers or steps, but not the exclusion of any other element, integer or step, or group of elements, integers or steps.

Claims

The Claims

1. A method of anodising a surface comprising a metallic material, the method comprising the steps of:

exposing a portion of the surface to an electrolytic solution that is suitable for anodising the metallic material ;

exposing a portion of an electrode to the

electrolytic solution;

selecting one or more parameters of an alternate waveform; and

2. A method of controlling stored charge in an anodised material comprising the steps of:

selecting one or more parameters of an alternate waveform; and

3. The method of claim 1 or claim 2 wherein the one or more parameters of the alternate waveform are selected in a manner to influence sign and magnitude of stored charge embedded in the anodised material.

4. The method of claim 3 wherein the alternate waveform is a square waveform and the step of selecting one or more parameters of the alternate waveform comprises selecting one or a combination of:

i. a positive value of the waveform; ii. a negative value of the waveform;

iii. a duty cycle value of the waveform; and

iv. a frequency value of the waveform.

5. The method of claim 4 wherein the selected value of duty cycle is between 30% and 100%.

6. The method of claim 4 or claim 5 wherein the selected value of frequency is between 0.05Hz and 10Hz.

7. The method of any one of claims 4 to 6 wherein the alternate waveform is a pulsed waveform.

8. The method of any one of claims 4 to 7 wherein the alternate waveform is a square waveform and the step of selecting one or more parameters of the alternate waveform comprises at least selecting the positive value or the negative value.

9. The method of claim 8 wherein the alternate waveform is a current waveform.

10. The method of claim 9 wherein the positive current value is between 1 mA/cm² and 5 mA/cm².

11. The method of claim 9 or claim 10 wherein the negative current value is between -1 mA/cm² and -5 mA/cm².

12. The method of claim 8 wherein the alternate waveform is a voltage waveform.

13. The method of claim 12 wherein the positive voltage value is between 10 V and 50 V.

14. The method of claim 12 or claim 13 wherein the negative voltage value is between -10 V and -50 V.

15. The method of any one of the preceding claims wherein the one or more parameters of the alternate waveform are selected in a manner such that the stored charge embedded in the anodised material has an effective density between -10 10¹¹ q/cm² to 10 10¹² q/cm².

16. The method of any one of the preceding claims wherein the electrode comprises one or a combination of nickel, copper and aluminium.

17. An apparatus for anodising a surface comprising a metallic material, the apparatus comprising:

an alternate waveform generator arranged to apply an electric wave having an alternate waveform to the exposed portion and the electrode while the metallic material is being anodised.

18. The apparatus of claim 17 wherein the generator is arranged to apply a current waveform through the surface comprising the metallic material and the electrode and to provide tunability of one or more parameters of the alternate waveform.

19. The apparatus of claim 18 wherein the alternate waveform is a square waveform and the generator is

arranged to provide tunability of one or a combination of: i. a positive current value of the waveform;

ii. a negative current value of the waveform;

iii. a duty cycle value of the waveform; and

iv. a frequency value of the waveform.

20. The apparatus of claim 19 wherein by tuning one or a combination of parameters i to iv the amount of stored charge embedded in the anodised material is influenced.

21. The apparatus of claim 20 wherein the amount of stored charge embedded in the anodised material is controllable between -10 10¹¹ q/cm² to 10 10¹² q/cm².

22. The apparatus of any one of claims 17 to 21 wherein the electrode comprises one or a combination of nickel, copper and aluminium.

23. The apparatus of any one of claims 17 to 22 further comprising a support arranged to support a device, the surface comprising the metallic material being part of the device, such that in use the surface is exposed to the electrolytic solution when the container is charged with the electrolytic solution.

24. The apparatus of claim 23 further comprising a radiation source arranged to illuminate a portion of the device in a manner such that a radiation-induced current is generated in the device to promote anodisation of the surface comprising the metallic material.

25. A charge filtering structure for separating positive charge carriers from negative charge carriers comprising an anodised material which is anodised in accordance with any one of claims 1 to 16.

26. A Perovskite based photovoltaic cell comprising a charge filtering structure in accordance with claim 25.

27. A kesterite based photovoltaic cell comprising a charge filtering structure in accordance with claim 25.

28. A photovoltaic cell device comprising an anodised layer formed by a method in accordance with any one of claims 1 to 16.

29. A photovoltaic cell device comprising a negatively doped base region and a positively doped emitter region wherein the emitter region is in contact with an anodised layer formed by a method in accordance with any one of claims 1 to 16, the anodised layer having a net negative stored charge and being arranged to electrically passivate at least a portion of the emitter region.

30. A photovoltaic cell device comprising a positively doped base region and a negatively doped emitter region wherein the emitter region is in contact with an anodised layer formed by a method in accordance with any one of claims 1 to 16, the anodised layer having a net positive stored charge and being arranged to electrically passivate at least a portion of the emitter region.

31. A photovoltaic cell device comprising:

a base region;

an emitter region;

positively doped semiconducting portions; and

an anodised layer, disposed in proximity of the contacting region, the anodised layer being formed by a method in accordance with any one of claims 1 to 16.

32. The photovoltaic cell of claim 31 wherein the

anodised layer has a quasi-neutral net stored charge.

33. A metal-oxide-semiconductor capacitor structure comprising :

a semiconducting substrate or a semiconducting layer; a thin dielectric layer disposed on a surface portion of the semiconducting substrate or a semiconducting layer the thin dielectric layer being formed by a method in accordance with any one of claims 1 to 16; and

an electrode disposed in contact with at least a portion of the thin dielectric layer.

34. A metal-oxide-semiconductor field effect transistor comprising a metal-oxide-semiconductor capacitor in accordance with claim 33.