WO2016106863A1 - 阵列基板、显示面板及阵列基板的检测方法 - Google Patents

阵列基板、显示面板及阵列基板的检测方法 Download PDF

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Publication number
WO2016106863A1
WO2016106863A1 PCT/CN2015/070834 CN2015070834W WO2016106863A1 WO 2016106863 A1 WO2016106863 A1 WO 2016106863A1 CN 2015070834 W CN2015070834 W CN 2015070834W WO 2016106863 A1 WO2016106863 A1 WO 2016106863A1
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sub
pixel
array substrate
pixel electrode
capacitor
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English (en)
French (fr)
Inventor
陈政鸿
王醉
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US14/435,542 priority Critical patent/US9671450B2/en
Publication of WO2016106863A1 publication Critical patent/WO2016106863A1/zh
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/52Testing for short-circuits, leakage current or ground faults
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/134309Electrodes characterised by their geometrical arrangement
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/134309Electrodes characterised by their geometrical arrangement
    • G02F1/134345Subdivided pixels, e.g. for grey scale or redundancy
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136254Checking; Testing
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/02Improving the quality of display appearance
    • G09G2320/029Improving the quality of display appearance by monitoring one or more pixels in the display panel, e.g. by monitoring a fixed reference pixel
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/12Test circuits or failure detection circuits included in a display system, as permanent part thereof

Definitions

  • the invention relates to the field of display, and in particular to a method for detecting an array substrate, a display panel and an array substrate.
  • each pixel includes three sub-pixels arranged in sequence, such as a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B), each sub-pixel including a sub-pixel electrode
  • R red sub-pixel
  • G green sub-pixel
  • B blue sub-pixel
  • Each pixel is opposite to a shared capacitor.
  • the uppermost layer of the shared capacitor is usually a transparent conductive layer, such as ITO.
  • the present invention provides an array substrate, the array substrate comprising a plurality of pixels distributed in a matrix, each pixel comprising a plurality of sequentially arranged sub-pixels, each sub-pixel being opposite to and spaced apart from a capacitor, each sub-pixel including a sub-pixel
  • the pixel electrode includes at least one sub-pixel electrode including an extension portion, and an extension portion of the sub-pixel electrode of the at least one sub-pixel is disposed corresponding to a gap between adjacent sub-pixels and a capacitance corresponding to the adjacent sub-pixel.
  • each pixel includes three sub-pixels arranged in sequence, and three sub-pixels arranged in order are a sub-pixel, a second sub-pixel, and a third sub-pixel, the first sub-pixel is opposite to and spaced apart from the first capacitor, and the second sub-pixel is opposite to and spaced apart from the second capacitor, the third sub-pixel Opposite and spaced apart from the third capacitance, the first sub-pixel includes a first sub-pixel electrode, the second sub-pixel includes a second sub-pixel electrode, and the third sub-pixel includes a third sub-pixel electrode,
  • the first sub-pixel electrode includes a first extension portion, and the first extension portion is disposed corresponding to a gap between the second sub-pixel of the pixel and the second capacitor.
  • the second sub-pixel electrode includes a second extension portion, and the second extension portion is disposed corresponding to a gap between the third sub-pixel and the third capacitor in the pixel.
  • the third sub-pixel electrode includes a third extension portion, and the third extension portion is disposed corresponding to a gap between the first sub-pixel and the first capacitor of the pixels adjacent to the pixel.
  • the present invention also provides a display panel, the display panel comprising an array substrate, the array substrate comprising a plurality of pixels distributed in a matrix, each pixel comprising a plurality of sequentially arranged sub-pixels, each sub-pixel being opposite to a capacitor Arranged, each sub-pixel includes one sub-pixel electrode, and at least one sub-pixel electrode includes an extension portion, and an extension portion of the sub-pixel electrode of the at least one sub-pixel corresponds to a capacitance corresponding to the adjacent sub-pixel and the adjacent sub-pixel The gap between the settings.
  • Each of the pixels includes three sequentially arranged sub-pixels, and the three sequentially arranged sub-pixels are a first sub-pixel, a second sub-pixel, and a third sub-pixel, and the first sub-pixel is opposite to and spaced apart from the first capacitor.
  • the second sub-pixel is opposite to and spaced apart from the second capacitor
  • the third sub-pixel is opposite to and spaced apart from the third capacitor
  • the first sub-pixel includes a first sub-pixel electrode
  • the second sub-pixel The pixel includes a second sub-pixel electrode
  • the third sub-pixel includes a third sub-pixel electrode
  • the first sub-pixel electrode includes a first extension
  • the first extension corresponds to a second sub-pixel of the pixel
  • a gap is provided with the second capacitor.
  • the second sub-pixel electrode includes a second extension portion, and the second extension portion is disposed corresponding to a gap between the third sub-pixel and the third capacitor in the pixel.
  • the third sub-pixel electrode includes a third extension portion, and the third extension portion is disposed corresponding to a gap between the first sub-pixel and the first capacitor of the pixels adjacent to the pixel.
  • the present invention also provides a method for detecting an array substrate, the array substrate comprising a plurality of pixels distributed in a matrix, each pixel comprising a plurality of sequentially arranged sub-pixels, each sub-pixel being opposite to a capacitor and spaced apart, each sub-pixel
  • the pixel includes one sub-pixel electrode, and at least one sub-pixel electrode includes an extension a portion of the sub-pixel electrode of the at least one sub-pixel is disposed corresponding to a gap between the adjacent sub-pixel and a capacitor corresponding to the adjacent sub-pixel;
  • the array substrate When there is no color other than the lit color in the array substrate, the array substrate is normal.
  • the array substrate of the present invention and the display panel including the array substrate and the array substrate are detected by disposing at least one sub-pixel electrode to include an extension portion, and extending the sub-pixel electrode The portion corresponds to a gap between adjacent sub-pixel electrodes and a capacitance corresponding to the adjacent sub-pixels.
  • FIG. 1 is a schematic structural view of an array substrate according to a preferred embodiment of the present invention.
  • FIG. 2 is a schematic structural view of a display panel according to a preferred embodiment of the present invention.
  • FIG. 3 is a flow chart of a method for detecting an array substrate according to a preferred embodiment of the present invention.
  • FIG. 1 is a schematic structural diagram of an array substrate according to a preferred embodiment of the present invention.
  • the thin film transistor array 10 includes a plurality of pixels 100 distributed in a matrix, each pixel 100 includes a plurality of sequentially arranged sub-pixels, each sub-pixel being opposite to and spaced apart from a capacitor, each sub-pixel including a sub-pixel electrode, the at least one sub-pixel electrode includes an extension portion, and an extension portion of the sub-pixel electrode of the at least one sub-pixel is disposed corresponding to a gap between adjacent sub-pixels and a capacitance corresponding to the adjacent sub-pixel.
  • the pixel 100 includes three sub-pixels as an example for description.
  • Each pixel 100 includes three sequentially arranged sub-pixels as a first sub-pixel 110, a second sub-pixel 120, and a third sub-pixel 130.
  • the first sub-pixel 110 is opposite to and spaced apart from the first capacitor C1.
  • the second sub-pixel 120 is opposite to and spaced apart from the second capacitor C2.
  • the third sub-pixel 130 is opposite to the third capacitor C3 and is spaced apart.
  • the first sub-pixel 110 includes a first sub-pixel electrode 111
  • the second sub-pixel 120 includes a second sub-pixel electrode 121
  • the third sub-pixel electrode 130 includes a third sub-pixel electrode 131.
  • the first sub-pixel electrode 111 includes a first extension portion 112 corresponding to a gap between the second sub-pixel 120 and the second capacitor C2 in the pixel 100.
  • the first sub-pixel 110, the second sub-pixel 120, and the third sub-pixel 130 are a combination of red, green, and blue.
  • the first sub-pixel 110, the second sub-pixel 120, and the third sub-pixel 130 are respectively described as red sub-pixels, green sub-pixels, and blue sub-pixels.
  • the second sub-pixel electrode 121 includes a second extension portion 122 corresponding to a gap between the third sub-pixel 130 and the third capacitor C3 in the pixel 100.
  • the third sub-pixel electrode 131 includes a third extension portion 132 , and the third extension portion 132 is disposed in a gap between the first sub-pixel 110 and the first capacitor C1 in the adjacent pixels 100 of the pixel 100 .
  • the case of determining whether the array substrate 10 is normal or whether there is a short circuit between the capacitor and the sub-pixel electrode is as follows. Illuminating the sub-pixels of one color in turn and observing the array substrate 10; determining whether there are other colors in the array substrate 10 in addition to the color of the lighting; in addition to the points in the array substrate 10 If there is no other color than the bright color, the array substrate 10 is normal; When there are other colors in the array substrate 10 other than the lighted color, the sub-pixels of the currently lit color corresponding to the sub-pixels of the other color on the array substrate 10 appear between the sub-pixels of the currently lit color and their corresponding capacitors. Short circuit.
  • Short circuit is an example of lighting a green sub-pixel as an example.
  • Illuminating the green sub-pixels ie, lighting the second sub-pixels 120
  • observing the array substrate 10 determining whether there are other colors in the array substrate 10 other than green; if the array substrate 10 is If no other colors (such as red or blue, or red and blue) are displayed outside the green display, the array substrate 10 is normal. Other colors such as red or blue, or red and blue are displayed in the array substrate 10 in addition to displaying green.
  • the array substrate 10 also displays red when the green sub-pixel is lit is described.
  • a short circuit between the extension portion 111 of the red sub-pixel (ie, the first sub-pixel 110) and the second sub-pixel electrode 120 and the second capacitor C2 will be described.
  • FIG. 2 is a schematic structural diagram of a display panel according to a preferred embodiment of the present invention.
  • the display panel 1 includes an array substrate 10, a color filter substrate 20, and a liquid crystal layer 30 as shown in FIG.
  • the array substrate 10 is disposed opposite to the color filter substrate 20 , and the liquid crystal layer 30 is disposed between the array substrate 10 and the color filter substrate 20 .
  • the thin film transistor array 10 includes a plurality of pixels 100 distributed in a matrix, each pixel 100 includes a plurality of sequentially arranged sub-pixels, each sub-pixel being opposite to and spaced apart from a capacitor, each sub-pixel including a sub-pixel electrode, the at least one sub-pixel electrode includes an extension portion, and an extension portion of the sub-pixel electrode of the at least one sub-pixel is disposed corresponding to a gap between adjacent sub-pixels and a capacitance corresponding to the adjacent sub-pixel.
  • the pixel 100 includes three sub-pixels as an example for description.
  • Each pixel 100 includes three sequentially arranged sub-pixels as a first sub-pixel 110, a second sub-pixel 120, and a third sub-pixel 130.
  • the first sub-pixel 110 is opposite to and spaced apart from the first capacitor C1.
  • the second sub-pixel 120 is opposite to and spaced apart from the second capacitor C2.
  • the third sub-pixel 130 is opposite to the third capacitor C3 and is spaced apart.
  • the first sub-pixel 110 includes a first sub-pixel electrode 111
  • the second sub-pixel 120 includes a second sub-pixel electrode 121
  • the third sub-pixel electrode 130 includes The third sub-pixel electrode 131.
  • the first sub-pixel electrode 111 includes a first extension portion 112 corresponding to a gap between the second sub-pixel 120 and the second capacitor C2 in the pixel 100.
  • the first sub-pixel 110, the second sub-pixel 120, and the third sub-pixel 130 are a combination of red, green, and blue.
  • the first sub-pixel 110, the second sub-pixel 120, and the third sub-pixel 130 are respectively described as red sub-pixels, green sub-pixels, and blue sub-pixels.
  • the second sub-pixel electrode 121 includes a second extension portion 122 corresponding to a gap between the third sub-pixel 130 and the third capacitor C3 in the pixel 100.
  • the third sub-pixel electrode 131 includes a third extension portion 132 , and the third extension portion 132 is disposed in a gap between the first sub-pixel 110 and the first capacitor C1 in the adjacent pixels 100 of the pixel 100 .
  • the case of determining whether the array substrate 10 is normal or whether there is a short circuit between the capacitor and the sub-pixel electrode is as follows. Illuminating the sub-pixels of one color in turn and observing the array substrate 10; determining whether there are other colors in the array substrate 10 in addition to the color of the lighting; in addition to the points in the array substrate 10 If there is no other color than the bright color, the array substrate 10 is normal; when the array substrate 10 has other colors besides the lighted color, the sub-pixel corresponding to the other colors is displayed on the array substrate 10.
  • a short circuit occurs between the sub-pixel of the currently lit color and its corresponding capacitor.
  • lighting a green sub-pixel as an example.
  • Illuminating the green sub-pixels ie, lighting the second sub-pixels 120
  • observing the array substrate 10 determining whether there are other colors in the array substrate 10 other than green; if the array substrate 10 is If no other colors (such as red or blue, or red and blue) are displayed outside the green display, the array substrate 10 is normal. Other colors such as red or blue, or red and blue are displayed in the array substrate 10 in addition to displaying green.
  • the array substrate 10 also displays red when the green sub-pixel is lit is described.
  • a short circuit between the extension portion 111 of the red sub-pixel (ie, the first sub-pixel 110) and the second sub-pixel electrode 120 and the second capacitor C2 will be described.
  • the method for detecting the array substrate of the present invention will be described below with reference to FIGS. 1 and 2. Please participate together 3 is a flow chart of a method for detecting an array substrate according to a preferred embodiment of the present invention.
  • the method of detecting the array substrate 10 includes, but is not limited to, the following steps.
  • step S101 the sub-pixels of one color are sequentially illuminated and the array substrate 10 is observed.
  • step S102 it is determined whether there are other colors in the array substrate 10 in addition to the lighted color.
  • step S103 when there is no color other than the lighted color in the array substrate 10, the array substrate 10 is normal.
  • step S104 when there are other colors in the array substrate 10 other than the color of the light, the extension of the sub-pixels of the other colors and the sub-pixels of the currently lit color are displayed on the array substrate 10. A short circuit occurs between the pixel electrode and its corresponding capacitor.
  • a green sub-pixel Illuminating the green sub-pixels (ie, lighting the second sub-pixels 120), observing the array substrate 10; determining whether there are other colors in the array substrate 10 other than green; if the array substrate 10 is If no other colors (such as red or blue, or red and blue) are displayed outside the green display, the array substrate 10 is normal. Other colors such as red or blue, or red and blue are displayed in the array substrate 10 in addition to displaying green.
  • the array substrate 10 also displays red when the green sub-pixel is lit is described.
  • the array substrate of the present invention and the display panel including the array substrate and the array substrate are detected by disposing at least one sub-pixel electrode to include an extension portion, and extending the sub-pixel electrode The portion corresponds to a gap between adjacent sub-pixel electrodes and a capacitance corresponding to the adjacent sub-pixels.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板、显示面板及阵列基板的检测方法。所述阵列基板(10)包括呈矩阵分布的多个像素(100),每个像素(100)包括多个依次排列的子像素,每个子像素与一个电容相对且间隔设置,每个子像素包括一个子像素电极,至少一子像素电极包括一延伸部,至少一子像素的子像素电极的延伸部对应相邻的子像素与所述相邻的子像素对应的电容之间的间隙设置。

Description

阵列基板、显示面板及阵列基板的检测方法
本发明要求2014年12月30日递交的发明名称为“阵列基板、显示面板及阵列基板的检测方法”的申请号201410848799.X的在先申请优先权,上述在先申请的内容以引入的方式并入本文本中。
技术领域
本发明涉显示领域,尤其涉及一种阵列基板、显示面板及阵列基板的检测方法。
背景技术
液晶显示装置作为一种常见的电子设备由于其具有质量轻、大视角等优点而被广泛地应用。为了改变垂直取向型的业绩显示装置在大视角出现的色偏现象,通常采用电荷共享的像素设计。在电荷共享的像素设计中,每个像素包括依次排列的三个子像素,比如红色子像素(R),绿色子像素(G)和蓝色子像素(B),每个子像素包括一个子像素电极,每个像素与一个共享电容相对。所述共享电容的最上层通常为透明导电层,比如为ITO,在实际生产过程中可能会出现ITO的残留,则会造成共享电容与子像素电极之间的短路。当所述共享电容与子像素电极之间短路时,在液晶显示装置的显示面板上会出现微亮点现象,从而造成显示面板的显示质量不高。且现有技术中不能够检测出共享电容与子像素电极之间短路的情况。
发明内容
本发明提供一种阵列基板,所述阵列基板包括呈矩阵分布的多个像素,每个像素包括多个依次排列的子像素,每个子像素与一个电容相对且间隔设置,每个子像素包括一个子像素电极,至少一子像素电极包括一延伸部,至少一子像素的子像素电极的延伸部对应相邻的子像素与所述相邻的子像素对应的电容之间的间隙设置。
其中,每个像素包括三个依次排列的子像素,三个依次排列的子像素为第 一子像素、第二子像素及第三子像素,所述第一子像素与第一电容相对且间隔设置,所述第二子像素与第二电容相对且间隔设置,所述第三子像素与第三电容相对且间隔设置,所述第一子像素包括第一子像素电极,所述第二子像素包括第二子像素电极,所述第三子像素包括第三子像素电极,所述第一子像素电极包括第一延伸部,所述第一延伸部对应所述像素中的第二子像素与所述第二电容之间的间隙设置。
其中,所述第二子像素电极包括第二延伸部,所述第二延伸部对应所述像素中的第三子像素与所述第三电容之间的间隙设置。
其中,所述第三子像素电极包括第三延伸部,所述第三延伸部对应所述像素相邻的像素中的第一子像素与第一电容之间的间隙设置。
本发明还提供一种显示面板,所述显示面板包括阵列基板,所述阵列基板包括呈矩阵分布的多个像素,每个像素包括多个依次排列的子像素,每个子像素与一个电容相对且间隔设置,每个子像素包括一个子像素电极,至少一子像素电极包括一延伸部,至少一子像素的子像素电极的延伸部对应相邻的子像素与所述相邻的子像素对应的电容之间的间隙设置。
其中,每个像素包括三个依次排列的子像素,三个依次排列的子像素为第一子像素、第二子像素及第三子像素,所述第一子像素与第一电容相对且间隔设置,所述第二子像素与第二电容相对且间隔设置,所述第三子像素与第三电容相对且间隔设置,所述第一子像素包括第一子像素电极,所述第二子像素包括第二子像素电极,所述第三子像素包括第三子像素电极,所述第一子像素电极包括第一延伸部,所述第一延伸部对应所述像素中的第二子像素与所述第二电容之间的间隙设置。
其中,所述第二子像素电极包括第二延伸部,所述第二延伸部对应所述像素中的第三子像素与所述第三电容之间的间隙设置。
其中,所述第三子像素电极包括第三延伸部,所述第三延伸部对应所述像素相邻的像素中的第一子像素与第一电容之间的间隙设置。
本发明还提供一种阵列基板的检测方法,所述阵列基板包括呈矩阵分布的多个像素,每个像素包括多个依次排列的子像素,每个子像素与一个电容相对且间隔设置,每个子像素包括一个子像素电极,至少一子像素电极包括一延伸 部,至少一子像素的子像素电极的延伸部对应相邻的子像素与所述相邻的子像素对应的电容之间的间隙设置;
依次点亮一种颜色的子像素并观测所述阵列基板;
判断所述阵列基板中除了所述点亮的颜色之外是否还有其他颜色;
当所述阵列基板中除了所述点亮的颜色之外没有其他颜色,则所述阵列基板为正常。
其中,当所述阵列基板中除了点亮的颜色之外还有其他颜色,则所述阵列基板上显示其他颜色的子像素的延伸部与当前被点亮的颜色的子像素的子像素电极以及其所对应的电容之间出现短路。
相较于现有技术,本发明的阵列基板及包括所述阵列基板的显示面板以及阵列基板的检测方法通过在将至少一个子像素电极设置为包括一个延伸部,并将此子像素电极的延伸部对应相邻的子像素电极与所述相邻的子像素对应的电容之间的间隙设置。当依次点亮所述阵列基板中各个颜色的子像素时,可以通过所述阵列基板中除了现实当前被点亮的颜色之外是否还有其他颜色被点亮,从而能够判断出所述阵列基板上显示其他颜色的子像素的延伸部与当前被点亮的颜色的子像素的子像素电极以及其所对应的电容之间出现短路。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明一较佳实施方式的阵列基板的结构示意图。
图2为本发明一较佳实施方式的显示面板的结构示意图。
图3为本发明一较佳实施方式的阵列基板的检测方法的流程图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是 全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
请参阅图1,图1为本发明一较佳实施方式的阵列基板的结构示意图。所述阵列基板(thin film transistor array)10包括呈矩阵分布的而多个像素100,每个像素100包括多个依次排列的子像素,每个子像素与一个电容相对且间隔设置,每个子像素包括一个子像素电极,至少一个子像素电极包括一延伸部,至少一子像素的子像素电极的延伸部对应相邻的子像素与所述相邻的子像素对应的电容之间的间隙设置。下面以所述像素100包括三个子像素为例进行说明。
每个像素100包括三个依次排列的子像素为第一子像素110、第二子像素120及第三子像素130。所述第一子像素110与第一电容C1相对且间隔设置,所述第二子像素120与第二电容C2相对且间隔设置,所述第三子像素130与第三电容C3相对且间隔设置。所述第一子像素110包括第一子像素电极111,所述第二子像素120包括第二子像素电极121,所述第三子像素电极130包括第三子像素电极131。所述第一子像素电极111包括第一延伸部112,所述第一延伸部对应所述像素100中的第二子像素120与所述第二电容C2之间的间隙设置。所述第一子像素110、所述第二子像素120及所述第三子像素130为红色、绿色以及蓝色的组合。在本实施方式中以所述第一子像素110、所述第二子像素120及所述第三子像素130分别为红色子像素、绿色子像素以及蓝色子像素为例进行介绍。
所述第二子像素电极121包括第二延伸部122,所述第二延伸部122对应所述像素100中的第三子像素130与所述第三电容C3之间的间隙设置。
所述第三子像素电极131包括第三延伸部132,所述第三延伸部132所述像素100中相邻的像素100中的第一子像素110与第一电容C1之间的间隙设置。
判断所述阵列基板10是否正常或者是否存在电容与子像素电极发生短路的情况介绍如下。依次点亮一种颜色的子像素并观测所述阵列基板10;判断所述阵列基板10中除了所述点亮的颜色之外是否还有其他颜色;当所述阵列基板10中除了所述点亮的颜色之外没有其他颜色,则所述阵列基板10正常; 当所述阵列基板10中除了点亮的颜色之外还有其他颜色,则所述阵列基板10上显示其他颜色的子像素对应的当前被点亮的颜色的子像素与其对应的电容之间出现短路。这里以点亮绿色子像素为例进行介绍。点亮所述绿色子像素(即点亮第二子像素120),观测所述阵列基板10;判断所述阵列基板10中除了绿色之外是否还有其他颜色;如果所述阵列基板10中除了显示绿色之外没有显示其他颜色(比如红色或者蓝色,或者红色和蓝色),则表明所述阵列基板10正常。如果所述阵列基板10中除了显示绿色之外还显示其他颜色,比如红色或者蓝色,或者红色和蓝色。这里以所述阵列基板10在点亮绿色子像素时还显示红色为例进行介绍。此时,则说明红色子像素(即第一子像素110)的延伸部111与所述第二子像素电极120以及第二电容C2之间发生短路。这说明所述第二子像素电极120与所述第二子像素电极120对应的第二电容C2之间残留较多的导电材料,需要对第二子像素电极120及所述第二电容C2之间残留的导电材料进行清理,以提高所述阵列基板10的品质。
下面结合图1对本发明显示面板进行介绍。请参阅图2,图2为本发明一较佳实施方式的显示面板的结构示意图。所述显示面板1包括如图1所示的阵列基板10、彩色滤光基板20及液晶层30。所述阵列基板10与所述彩色滤光基板20相对设置,所述液晶层30设置于所述阵列基板10与所述彩色滤光基板20之间。
所述阵列基板(thin film transistor array)10包括呈矩阵分布的而多个像素100,每个像素100包括多个依次排列的子像素,每个子像素与一个电容相对且间隔设置,每个子像素包括一个子像素电极,至少一个子像素电极包括一延伸部,至少一子像素的子像素电极的延伸部对应相邻的子像素与所述相邻的子像素对应的电容之间的间隙设置。下面以所述像素100包括三个子像素为例进行说明。
每个像素100包括三个依次排列的子像素为第一子像素110、第二子像素120及第三子像素130。所述第一子像素110与第一电容C1相对且间隔设置,所述第二子像素120与第二电容C2相对且间隔设置,所述第三子像素130与第三电容C3相对且间隔设置。所述第一子像素110包括第一子像素电极111,所述第二子像素120包括第二子像素电极121,所述第三子像素电极130包括 第三子像素电极131。所述第一子像素电极111包括第一延伸部112,所述第一延伸部对应所述像素100中的第二子像素120与所述第二电容C2之间的间隙设置。所述第一子像素110、所述第二子像素120及所述第三子像素130为红色、绿色以及蓝色的组合。在本实施方式中以所述第一子像素110、所述第二子像素120及所述第三子像素130分别为红色子像素、绿色子像素以及蓝色子像素为例进行介绍。
所述第二子像素电极121包括第二延伸部122,所述第二延伸部122对应所述像素100中的第三子像素130与所述第三电容C3之间的间隙设置。
所述第三子像素电极131包括第三延伸部132,所述第三延伸部132所述像素100中相邻的像素100中的第一子像素110与第一电容C1之间的间隙设置。
判断所述阵列基板10是否正常或者是否存在电容与子像素电极发生短路的情况介绍如下。依次点亮一种颜色的子像素并观测所述阵列基板10;判断所述阵列基板10中除了所述点亮的颜色之外是否还有其他颜色;当所述阵列基板10中除了所述点亮的颜色之外没有其他颜色,则所述阵列基板10正常;当所述阵列基板10中除了点亮的颜色之外还有其他颜色,则所述阵列基板10上显示其他颜色的子像素对应的当前被点亮的颜色的子像素与其对应的电容之间出现短路。这里以点亮绿色子像素为例进行介绍。点亮所述绿色子像素(即点亮第二子像素120),观测所述阵列基板10;判断所述阵列基板10中除了绿色之外是否还有其他颜色;如果所述阵列基板10中除了显示绿色之外没有显示其他颜色(比如红色或者蓝色,或者红色和蓝色),则表明所述阵列基板10正常。如果所述阵列基板10中除了显示绿色之外还显示其他颜色,比如红色或者蓝色,或者红色和蓝色。这里以所述阵列基板10在点亮绿色子像素时还显示红色为例进行介绍。此时,则说明红色子像素(即第一子像素110)的延伸部111与所述第二子像素电极120以及第二电容C2之间发生短路。这说明所述第二子像素电极120与所述第二子像素电极120对应的第二电容C2之间残留较多的导电材料,需要对第二子像素电极120及所述第二电容C2之间残留的导电材料进行清理,以提高所述阵列基板10的品质。
下面结合图1和图2对本发明的阵列基板的检测方法进行介绍。请一并参 阅图3,图3为本发明一较佳实施方式的阵列基板的检测方法的流程图。所述阵列基板10的检测方法包括但不仅限于以下步骤。
步骤S101,依次点亮一种颜色的子像素并观测所述阵列基板10。
步骤S102,判断所述阵列基板10中除了点亮的颜色之外是否还有其他颜色。
步骤S103,当所述阵列基板10中除了所述点亮的颜色之外没有其他颜色,则所述阵列基板10为正常。
步骤S104,当所述阵列基板10中除了点亮的颜色之外还有其他颜色,则所述阵列基板10上显示其他颜色的子像素的延伸部与当前被点亮的颜色的子像素的子像素电极以及其所对应的电容之间出现短路。
这里以点亮绿色子像素为例进行介绍。点亮所述绿色子像素(即点亮第二子像素120),观测所述阵列基板10;判断所述阵列基板10中除了绿色之外是否还有其他颜色;如果所述阵列基板10中除了显示绿色之外没有显示其他颜色(比如红色或者蓝色,或者红色和蓝色),则表明所述阵列基板10正常。如果所述阵列基板10中除了显示绿色之外还显示其他颜色,比如红色或者蓝色,或者红色和蓝色。这里以所述阵列基板10在点亮绿色子像素时还显示红色为例进行介绍。此时,则说明红色子像素(即第一子像素110)的延伸部111与所述第二子像素电极120以及第二电容C2之间发生短路。这说明所述第二子像素电极120与所述第二子像素电极120对应的第二电容C2之间残留较多的导电材料,需要对第二子像素电极120及所述第二电容C2之间残留的导电材料进行清理,以提高所述阵列基板10的品质。
相较于现有技术,本发明的阵列基板及包括所述阵列基板的显示面板以及阵列基板的检测方法通过在将至少一个子像素电极设置为包括一个延伸部,并将此子像素电极的延伸部对应相邻的子像素电极与所述相邻的子像素对应的电容之间的间隙设置。当依次点亮所述阵列基板10中各个颜色的子像素时,可以通过所述阵列基板10中除了现实当前被点亮的颜色之外是否还有其他颜色被点亮,从而能够判断出所述阵列基板10上显示其他颜色的子像素的延伸部与当前被点亮的颜色的子像素的子像素电极以及其所对应的电容之间出现短路。
以上所揭露的仅为本发明一种较佳实施例而已,当然不能以此来限定本发明之权利范围,本领域普通技术人员可以理解实现上述实施例的全部或部分流程,并依本发明权利要求所作的等同变化,仍属于发明所涵盖的范围。

Claims (10)

  1. 一种阵列基板,其特征在于,所述阵列基板包括呈矩阵分布的多个像素,每个像素包括多个依次排列的子像素,每个子像素与一个电容相对且间隔设置,每个子像素包括一个子像素电极,至少一子像素电极包括一延伸部,至少一子像素的子像素电极的延伸部对应相邻的子像素与所述相邻的子像素对应的电容之间的间隙设置。
  2. 如权利要求1所述的阵列基板,其特征在于,每个像素包括三个依次排列的子像素,三个依次排列的子像素为第一子像素、第二子像素及第三子像素,所述第一子像素与第一电容相对且间隔设置,所述第二子像素与第二电容相对且间隔设置,所述第三子像素与第三电容相对且间隔设置,所述第一子像素包括第一子像素电极,所述第二子像素包括第二子像素电极,所述第三子像素包括第三子像素电极,所述第一子像素电极包括第一延伸部,所述第一延伸部对应所述像素中的第二子像素与所述第二电容之间的间隙设置。
  3. 如权利要求2所述的阵列基板,其特征在于,所述第二子像素电极包括第二延伸部,所述第二延伸部对应所述像素中的第三子像素与所述第三电容之间的间隙设置。
  4. 如权利要求3所述的阵列基板,其特征在于,所述第三子像素电极包括第三延伸部,所述第三延伸部对应所述像素相邻的像素中的第一子像素与第一电容之间的间隙设置。
  5. 一种显示面板,其特征在于,所述显示面板包括阵列基板,所述阵列基板包括呈矩阵分布的多个像素,每个像素包括多个依次排列的子像素,每个子像素与一个电容相对且间隔设置,每个子像素包括一个子像素电极,至少一子像素电极包括一延伸部,至少一子像素的子像素电极的延伸部对应相邻的子像素与所述相邻的子像素对应的电容之间的间隙设置。
  6. 如权利要求5所述的显示面板,其特征在于,每个像素包括三个依次排列的子像素,三个依次排列的子像素为第一子像素、第二子像素及第三子像素,所述第一子像素与第一电容相对且间隔设置,所述第二子像素与第二电容相对且间隔设置,所述第三子像素与第三电容相对且间隔设置,所述第一子像素包括第一子像素电极,所述第二子像素包括第二子像素电极,所述第三子像素包括第三子像素电极,所述第一子像素电极包括第一延伸部,所述第一延伸部对应所述像素中的第二子像素与所述第二电容之间的间隙设置。
  7. 如权利要求6所述的显示面板,其特征在于,所述第二子像素电极包括第二延伸部,所述第二延伸部对应所述像素中的第三子像素与所述第三电容之间的间隙设置。
  8. 如权利要求7所述的显示面板,其特征在于,所述第三子像素电极包括第三延伸部,所述第三延伸部对应所述像素相邻的像素中的第一子像素与第一电容之间的间隙设置。
  9. 一种阵列基板的检测方法,其特征在于,所述阵列基板包括呈矩阵分布的多个像素,每个像素包括多个依次排列的子像素,每个子像素与一个电容相对且间隔设置,每个子像素包括一个子像素电极,至少一子像素电极包括一延伸部,至少一子像素的子像素电极的延伸部对应相邻的子像素与所述相邻的子像素对应的电容之间的间隙设置;
    依次点亮一种颜色的子像素并观测所述阵列基板;
    判断所述阵列基板中除了所述点亮的颜色之外是否还有其他颜色;
    当所述阵列基板中除了所述点亮的颜色之外没有其他颜色,则所述阵列基板为正常。
  10. 如权利要求9所述的阵列基板的检测方法,其特征在于,当所述阵列基板中除了点亮的颜色之外还有其他颜色,则所述阵列基板上显示其他颜色的 子像素的延伸部与当前被点亮的颜色的子像素的子像素电极以及其所对应的电容之间出现短路。
PCT/CN2015/070834 2014-12-30 2015-01-16 阵列基板、显示面板及阵列基板的检测方法 Ceased WO2016106863A1 (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101231434A (zh) * 2006-09-08 2008-07-30 三星电子株式会社 阵列面板及其驱动方法
CN101324729A (zh) * 2008-05-23 2008-12-17 上海广电光电子有限公司 液晶显示装置及其驱动方法
CN101354512A (zh) * 2007-07-24 2009-01-28 三星电子株式会社 液晶显示器及其驱动方法
US20120033148A1 (en) * 2010-08-06 2012-02-09 Samsung Electronics Co., Ltd. Liquid crystal display

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100467584B1 (ko) * 2002-05-17 2005-01-24 삼성전자주식회사 색 수차 보정 장치 및 방법
KR101313154B1 (ko) * 2007-02-06 2013-10-01 삼성디스플레이 주식회사 액정표시장치
CN101581864B (zh) * 2009-06-19 2011-06-08 友达光电股份有限公司 液晶显示面板及其像素驱动方法
US8482709B2 (en) * 2010-04-22 2013-07-09 Samsung Display Co., Ltd. Liquid crystal display
KR20120036109A (ko) * 2010-10-07 2012-04-17 삼성전자주식회사 액정 표시 장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101231434A (zh) * 2006-09-08 2008-07-30 三星电子株式会社 阵列面板及其驱动方法
CN101354512A (zh) * 2007-07-24 2009-01-28 三星电子株式会社 液晶显示器及其驱动方法
CN101324729A (zh) * 2008-05-23 2008-12-17 上海广电光电子有限公司 液晶显示装置及其驱动方法
US20120033148A1 (en) * 2010-08-06 2012-02-09 Samsung Electronics Co., Ltd. Liquid crystal display

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