WO2016091501A1

WO2016091501A1 - A signal processing stage for an amplifier

Info

Publication number: WO2016091501A1
Application number: PCT/EP2015/076083
Authority: WO
Inventors: Keith FINNERTY; Ronan Farrell; John Dooley
Original assignee: National University Of Ireland, Maynooth
Priority date: 2014-12-12
Filing date: 2015-11-09
Publication date: 2016-06-16

Abstract

A signal processing stage for an amplifier comprises an input arranged to receive a modulated input signal (Input Signal) and a converter (40) for splitting the modulated input signal (Input Signal) into a magnitude signal component (Signal Magnitude) and a phase signal component (Signal Phase). A detector (46) detects a time (Tc) when the magnitude signal has a magnitude less than a threshold level (M). A phase modifier (44) modifies the phase signal by reducing a maximum rate of change of the phase signal component while the magnitude signal is less than the threshold level. A combiner (48) combines a magnitude signal derived from the magnitude signal with the modified phase signal to provide a modulated output signal for amplification.

Description

A signal processing stage for an amplifier

Field

The present invention relates to a signal processing stage for an amplifier. Background Power amplifiers are commonly used in radio transmission systems to provide increased signal power to a transmission antenna. For radio transmission, the amplifier generally has to make a trade-off between three parameters, efficiency, linearity and bandwidth :

Efficiency: The amplifier increases its input signal power by converting the power from its power supply to a higher power version of the input signal. During this process a percentage of the power from the power supply is consumed by the amplifier, the ratio of the power consumed verses the output signal power is the amplifier efficiency. Ideally 100% of amplifier power would be converted to output power, however in reality this is not possible. Linearity: The accuracy with which the amplifier converts the low power input signal to the high power output signal is referred to as linearity. It is an important factor for two reasons, as it will determine the quality of the received signal and whether the amplifier can meet the legal specifications for transmission. Bandwidth: This is the frequency range over which the amplifier can operate. Bandwidth can be a determining factor over which signal standards the amplifier is suitable for example, 2G, 3G, 4G.

Referring now to Figure 1 which shows a typical outphasing amplifier, such as disclosed in : "A 19W high-efficiency wide-band CMOS-GaN class-E Chireix RF outphasing power amplifier", van der Heijden, M .P., Acar, M., Vromans, J.S., Calvillo-Cortes, D.A., Microwave Symposium Digest (MTT), 2011 IEEE MTT-S International , vol., no., pp.1,4, 5- 10 June 2011; or "A 90-W Peak Power GaN Outphasing Amplifier With Optimum Input Signal Conditioning", Qureshi et al, IEEE Transactions on Microwave Theory and Techniques, Vol. 57, No. 8, August 2009. Here, an amplitude modulated signal S(t) is converted by a signal component separator (SCS) to a pair of phase modulated signals, Sl(t) and S2(t) with constant amplitude. These signals are then amplified by ideally identical saturated linear or switch mode power amplifiers (G). The constant envelope amplified signals are then re-combined in a power combiner stage, such as the Chireix combiner shown, resulting in an amplified version of the amplitude modulated input signal S(t). An outphasing power amplifier potentially improves both efficiency and linearity in amplitude modulation transmitters. However, the linearity of the outphasing amplifier relies on the individual paths of the amplifier being balanced in amplitude, phase and time delay, and this can be difficult to achieve in practice. Referring to Figure 2, in a typical amplifier, linearity is reduced when operating closer to the high power limit. However, in an outphasing amplifier, linearity is reduced at low signal power. Due to the amplifier structure, it is difficult to increase linearity in this low power region through design changes or standard linearization techniques such as digital pre-distortion (DPD) or crest factor reduction (CFR).

DPD is a method where by a mathematical model of the amplifier is compiled . From the model, the mechanisms of distortion can be derived and inverted, so that by applying the inversion to the input signal the non-linearity of the amplifier output is reduced. A variety of DPD methods have been explored in order to improve linearity, for example as described in J.K Cavers, "Amplifier linearization using a digital predistorter with fast adaptation and low memory requirements," IEEE Transactions on Vehicular Technology, vol. 39, no. 4, pp. pp.374-382, Nov 1990; V. John Mathews and Giovanni L. Sicuranza, Polynomial Signal Processing, 1st ed., Wiley & Sons, Ed., 2000; and P.N. Fritzin, J. Van Moer, W. Isaksson, M. Alvandpour, A. Landin, "Modeling and Digital Predistortion of Class-D Outphasing RF Power Amplifiers," Microwave Theory and Techniques, IEEE Transactions on, vol. 60, no. 6, pp. 1907-1915, 2012.

CFR is a method of modifying the input signal in order to avoid high output power non-linear regions of typical power amplifier structures for example as described in US6529925 and US7634024. Note that CFR does not require prior knowledge of the non-linearity of the amplifier and can be used in conjunction with DPD, either preceding or following a DPD signal processing stage.

The majority of the non-linearity occuring at higher powers is relatively easily linearised, for example using DPD or CFR. However, the residual non-linearity which occurs at lower output power is very difficult to correct using current techniques, preventing the output of some amplifiers including outphasing amplifiers meeting the legal specifications for the wireless transmission standard.

At the same time, the phase of the amplifier input signal can be problematic. As a quadrature transmission signal passes through the zero point of the unit circle, a large phase shift occurs - often as large as 180 degrees. In the quadrature modulated input signal S(t) of an outphasing amplifier, this is not an issue, as there is zero amplitude at this point. However, within the outphasing amplifier, the amplitude of the phase modulated signals Sl(t) and S2(t) is constant, and so large phase deviations have the same power as all other phase deviations. The outphasing signal is therefore no longer band limited, and in most cases will expand bandwidth to the limits of the sample rate of the system.

This bandwidth expansion thus places a strain on the transmit signal path design, because for ideal operation of an outphasing amplifier, the phase modulated signals Sl(t) and S2(t) must not experience any asymmetric amplitude or phase effects. This means that each amplification path must have exactly the same frequency profile. As the bandwidth requirements for the amplifier paths increase, especially due to bandwidth expansion, this becomes a more difficult parameter to achieve, generally requiring over-specified or high precision system components, resulting in additional if not prohibitive cost.

Summary

According to a first aspect of the present invention, there is provided a signal processing stage for an amplifier according to claim 1.

In embodiments, the phase of the signal in the amplifier non-linear region at lower amplitudes is modified, to create a more gradual rate of change of phase.

Where the amplifier is an outphasing amplifier, the result is a reduction in the bandwidth expansion (BER) experienced in the phase modulated signals Sl(t) and S2(t). The bandwidth reduction that occurs due to phase modification reduces the requirements for frequency-flat high-precision components in the dual path transmitter required for outphasing.

In a second aspect of the present invention, there is provided a signal processing stage for an amplifier according to claim 25.

Embodiments based on this aspect reduce the requirement for dynamic range of the amplifier and have the potential to allow for a reduction in the manufacturing tolerances required for the system with a view to making the system more realisable. Thus, in an outphasing amplifier, the requirement to balance each path of the amplification stage exactly can be reduced, leaving a more flexible design which could allow a wider bandwidth or more frequency flexible amplifier to be designed. These embodiments operate on the principle that it is better to avoid non-linearity rather than the more complex process of correcting it.

Embodiments reduce the overall complexity of the linearization problem and can be implemented along with other standard linearization techniques to achieve the required performance.

Brief Description of the Drawings

Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which :

Figure 1 shows a conventional digital outphasing power amplifier with Chireix combiner;

Figure 2 illustrates high and low power non-linearities in amplifiers;

Figure 3 is a block diagram illustrating signal processing of a transmission signal for amplification by an outphasing transmitter according to an embodiment of the present invention (locations of problems including bandwidth expansion and limited dynamic range are highlighted);

Figure 4 is a detailed block diagram of the BER/ZCR signal processing stage of Figure 3;

Figure 5 shows the effect of BER/ZCR signal processing according to an embodiment in the quadrature domain; Figure 6 shows the effect of ZCR processing on signal magnitude in the time domain; and

Figure 7 shows the effect of BER processing on signal phase in the time domain.

Description of the Embodiments Referring now to Figu re 3, there is shown a block diagram of an outphasing transmitter, including a bandwidth expansion reduction (BER)/zero crossing reduction (ZCR) signal processing block according to an embodiment of the present invention . The transmission chain comprises a digital data source which is fed to a signal modulator, for example, an IQ signal modulator. The modulated signal output is then fed to a filter, for example, a Root Raised Cosine (RRC) Filter which shapes the signal to provide a band limited signal before the signal is fed to a digital signal processing (DSP) block for processing prior to being fed to the outphasing amplifier.

While in the illustrated example, a complex modulated signal is described, the modulation could comprise any of amplitude modulation, phase modulation or any combination of amplitude and phase modulation commonly referred to as a complex signal. In the embodiment DSP comprises performing CFR, BER/ZCR and DPD in succession, although it will be appreciated that for example, the order of these blocks can be changed and one or both CFR or DPD may not be employed.

Embodiments of the invention employing ZCR modify a signal to be transmitted to either reduce the amount of time or where possible, completely prevent the amplifier from operating in the low power non-linear region . Nonetheless, the modified signal must still maintain the information that is intended to be sent, the measure for which is Error Vector Magnitude (EVM) and the modified signal must still maintain the properties required for legal transmission e.g . Adjacent Channel Power Ratio (ACPR). Within the BER/ZCR processing block, a low power sig nal is added to the original input signal every time it enters the low power non-linear region outlined in Fig. 2, but limited by the amount of error which can be introduced according to EVM requirements. The signal is then filtered to remove any unwanted effects resulting from the signal addition, allowing the modified signal to meet the legal transmission requirements.

A block diagram outlining of BER/ZCR signal processing block can be seen in Fig. 4 and the result of the process can be seen in Fig . 5-7.

Referring to Figure 4, the process for BER/ZCR is outlined in the following steps:

An input signal is separated into amplitude A(t) and phase φ(ΐ) using for example, a CORDIC processing block 40. The input signal could be provided directly from the RRC filter of Figure 3 or from a CFR or DPD processing block if these are being employed and precede BER/ZCR processing.

As can be seen, the phase and amplitude signals are processed in parallel and while a delay block 42 is shown explicitly in Figu re 4, it will be appreciated that the phase signal φ(ΐ) is also delayed by the same amount within the phase modification block 44.

The degree of delay incurred by BER/ZCR processing depends on which of a variety of approaches might be employed as will be explained in more detail below.

Referring first to Figure 5, which shows a number of I, Q symbols A,B,C,D which can be generated by the modulation stage shown in Figure 3. By upsampling the modulated signal, either before or after the RRC filter, it is possible to have a signal encoding symbols, for example, A, B, C, D in succession transition more smoothly through those signal values as indicated by the signal path 50 rather than for example, transitioning from A to origin, origin to B, B to origin, origin to C etc. and so bandwidth limit the modulated signal. However, as will be seen in certain cases, as when the signal transitions from symbol B to symbol C or symbol A to symbol D (shown), the signal phase will transition through a + 180° phase shift. This could cause excessive bandwidth expansion in an outphasing amplifier using such a signal.

Obviously, in a practical system, there could be many more symbols than 4 and thus many more possibilities for transition. Nonetheless, the limited example provided should illustrate the operation of the invention.

Referring now to Figures 6 and 7, in embodiments of the present invention, a threshold detection circuit 46 monitors the magnitude signal A(t) to determine when its magnitude falls below a threshold value M. Typically, M is chosen as the level below which the outphasing amplifier begins to behave in a non-linear fashion.

In the example, of Figures 6 and 7, in a signal transitioning from symbol B to C, this crossing occurs at time Tc. As will be appreciated, detecting this transition requires that the input signal be upsampled at multiple of the symbol rate, and typically this is between 10- 12x.

In one approach where incurring delay is not critical, the system delay will be at least that required for the signal to exceed the threshold M and this occurs at time Te. (Nonetheless, it will be seen that this delay is still less than a single symbol time.)

In embodiments of the invention, the phase in the window between the original signal phase value at time Tc and time Te is interpolated linearly i.e. with a continuous rate of change, to provide a set of values indicated by the line 72 in Figure 7.

These gradually changing phase values replace the original signal phase values which would otherwise have involved a rapid phase change around time Tm during the period between Tc and Te.

Nonetheless, it will be seen that the phase discontinuity involved in changing from and to the original signal phase at times Tc and Te will involve an element of bandwidth expansion .

Thus, once the modified phase signal cp'(t) is recombined with the equally delayed and possibly modified amplitude signal A'(t) in a second CORDIC block 48, this leakage can be removed in a suitable filter 49 before the filtered signal is provided either for DPD or CFR processing or to the amplifier.

Alternatively, a non-linear function may be chosen to interpolate the phase values between Tc and Te to provide less discontinuity at Tc and Te and possibly avoid the need for the filter 49. (This of course would involve an increased rate of change at some point in the transition between Tc and Te and clearly this increase needs to be balanced against any discontinuity at Tc or Te.)

In any case, because of the phase adjustment provided by the block 44, the signal supplied to the amplifier should comprise a bandwidth limited signal, as indicated by the signal 32 in Figure 3, so that the bandwidth expansion caused by the outphasing amplifier will be limited below acceptable levels, represented by the signal 34 in Figure 3. If the delay caused by the BER/ZCR processing block is critical, then it may not be possible to delay the input signal for longer than Te-Tm .

In this case, an element of extrapolation is required within the phase modification block.

In one example, of this extrapolation, rather than Tc and Te, the threshold detection block 46 is modified to detect: Tc, again the time when the magnitude of the input signal drops below M ; and Tm, the time at which the magnitude of the amplitude signal reaches a minimum.

Tm is assumed to be the time when the phase of the input signal would have passed -through a 180° phase shift and it is assumed Tm-Tc=Te-Tm. So based on a given phase at Tc, and assuming a phase of 180° at Tm, the phase modification block extrapolates phase values linearly until time Te after which the modified phase signal cp'(t) reverts to the phase of the original input signal.

This approach is likely to cause greater phase discontinuity at time Te than the first approach based on incurring a longer delay, but this is acceptable as long as the post-filtering block 49 can remove any leakage without causing data error and so meet EVM requirements.

In a still further variant, the length of the window Te-Tc could be assumed and the phase modification block could interpolate between the phase at time Tc and an inverted value of that phase a fixed time later at Te before continuing with the phase of the original input signal .

In any case, it will be appreciated that when extrapolating, rather than delaying until Te; the time at which the modified phase is replaced with the original phase and the time at which the original signal magnitude re-exceeds M may not coincide - as indicated in Figures 6 and 7.

In parallel with the phase modification block 44, zero crossing reduction is provided by a magnitude modification block 47.

The block 47 provides a band limited window function W(k) which is added to the original magnitude signal when its magnitude is detected as falling below M at Tc. In one embodiment, the Chebyshev windowing function is used as this is highly flexible as both the bandwidth of the window function and the out of band noise suppression can be specified when constructing the function. The real valued discrete Fourier transform of such a windowing function \N(k) is outlined in equation 2:

cos{/V co5^{_ 1} [ ?cos(? )]}

W k =

cosk(Ncosh ¹ ?)]

The length of the window N controls the pass band of the window while the level of the out of band ripple is set by alpha in equation (3):

N in the example extends a time X before time Tc and a time X after Te. Thus, when Te-Tc is fixed, the window function values for samples k=0...l\l can be stored in the block 47; otherwise, multiple sets of values would need to be stored for various possible window lengths; or the values would need to be calculated at run time depending on the required window length. In any case, the window function values for samples k=0...l\l are scaled according to the minimum detected value of the amplitude signal min(A(t) detected at Tm, the scaling factor S = (M - min(A(t)). Using this approach, the minimum delay required by the system would be X+(Tm-Tc), as in order to begin signal modification before Tc, a delay X is incurred, and before being able to calculate the scaling factor S, the system needs to wait until Tm. However, if delay is especially critical, then either X can be minimised or the system could attempt to extrapolate the required scaling factor S at time Tc, possibly adjusting this as required as the signal approaches Tm. In any case, once scaled, the window function signal W(k) is added to the delayed original signal in adder 45 and the modified signal A'(t) provided to the CORDIC block 48 for recombination with the modified phase signal before being filtered in block 49. The line 62 in Figure 6 shows the effect in the time domain of the magnitude modification, and Figure 5 shows the effect in the I,Q domain. Here the signal which would otherwise have transitioned through the non-linear region of the amplifier, denoted by a circle of diameter corresponding to M, now avoids this amplifier region.

As mentioned, the filtering block 49 can remove out of band signal components that are generated by BER and possibly ZCR processing described above.

In one implementation, a FFT based filtering process is used. Here, the process involves performing an FFT; applying a custom spectral mask to remove unwanted signal components; and performing the inverse FFT. The custom spectral mask is an array of attenuation values to apply to each point of the FFT. The flexibility of this process is in the ability to dynamically change the spectral mask without recalculating filter coefficients. However, such a process can be very resource intensive; and alternative implementations could employ either an RRC filter similar to the RRC filter of Figure 3; or an FIR digital filter.

In any case, once filtered, the modified signal can be passed either for DPD (as shown in Figure 3); or CFR processing or passed directly to the amplifier.

Here is will be seen that the BER processing which modifies the phase of the quadrature input signal S(t) limits the bandwidth expansion generated within the outphasing amplifier. Separately, the ZCR processing which modifies the magnitude of the signal S(t) limits the dynamic range required for the amplifier.

While this problem addressed above is not limited to outphasing amplifiers, it is more pronounced within this structure than other amplifiers. Alternative implementations of the invention can provide improvements in linearity for other amplifier architectures, for example: envelope tracking amplifier and class-S amplifiers.

Claims

Claims:

1. A signal processing stage for an amplifier comprising : an input arranged to receive a modulated input signal; a converter for splitting said modulated input signal into a magnitude signal component and a phase signal component; a detector for detecting a time Tc when said magnitude signal has a magnitude less than a threshold level, M; a phase modifier for modifying said phase signal by reducing a maximum rate of change of said phase signal component while said magnitude signal is less than said threshold level; and a combiner for combining a magnitude signal derived from said magnitude signal with said modified phase signal to provide a modulated output signal for amplification.

2. A signal processing stage as claimed in claim 1 where said detector is arranged to determine a time Tm after said time Tc when said magnitude signal is at a minimum value min(A(t)).

3. A signal processing stage as claimed in claim 2, wherein said phase modifier is arranged to interpolate between a first phase value of said phase signal at time Tc and a phase value of 180° at time Tm and to extrapolate between said phase value of said phase signal at said time Tm and an inverse value of said first phase value at a time Te=Tm-Tc after time Tm.

4. A signal processing stage as claimed in claim 3 wherein each of said interpolation and said extrapolation is a linear interpolation.

5. A signal processing stage as claimed in claim 1 where said detector is arranged to determine a time Te after said time Tc when said magnitude signal exceeds said threshold level.

6. A signal processing stage as claimed in claim 5, wherein said phase modifier is arranged to interpolate between a first phase value of said phase signal at time Tc and a second phase value of said phase signal at time Te.

7. A signal processing stage as claimed in claim 6 wherein said interpolation is a linear interpolation.

8. A signal processing stage as claimed in claim 1 where said detector is arranged to estimate a time Te after said time Tc when said magnitude signal is to exceed said threshold level.

9. A signal processing stage as claimed in claim 8, wherein said phase modifier is arranged to interpolate between a first phase value of said phase signal at time Tc and an inverse value of said first phase value at said time Te.

10. A signal processing stage as claimed in claim 9 wherein said interpolation is a linear interpolation.

11. A signal processing stage as claimed in claim 1 wherein said a magnitude signal derived from said magnitude signal is a delayed version of said magnitude signal.

12. A signal processing stage as claimed in claim 11 wherein said phase signal is delayed to the same extent within said processing stage as said magnitude signal.

13. A signal processing stage as claimed in claim 1 further comprising a magnitude modifier for modifying said magnitude signal by adding a signal component to a delayed version of said magnitude signal to maintain said magnitude signal derived from said magnitude signal above said threshold level M.

14. A signal processing stage as claimed in claim 13 wherein said signal component comprises a windowing function with a duration N at least as long said magnitude signal would not exceed said threshold level.

15. A signal processing stage as claimed in claim 14 wherein said windowing function comprises a band limiting windowing function, preferably, a Chebyshev window.

16. A signal processing stage as claimed in claim 13 where said detector is arranged to determine a time Tm after said time Tc when said magnitude signal is at a minimum value min(A(t)).

17. A signal processing stage as claimed in claim 16 wherein said magnitude modifier is arranged to scale said signal component with a scaling factor S, and preferably S = (M - min(A(t))).

18. A signal processing stage as claimed in claim 13 wherein said magnitude modifier is arranged to begin adding said signal component to said delayed version of said magnitude signal a time X before Tc.

19. A signal processing stage as claimed in claim 13 wherein said magnitude modifier is arranged to cease adding said signal component to said delayed version of said magnitude signal a time X after time Te after said time Tc when said magnitude signal exceeds said threshold level.

20. A signal processing stage as claimed in claim 19 wherein said detector is arranged to detect said time Te.

21. A signal processing stage as claimed in claim 19 wherein said detector is arranged to determine a time Tm after said time Tc when said magnitude signal is at a minimum value min(A(t)) and wherein time Te=Tm-Tc after time Tm.

22. A signal processing stage as claimed in claim 1 further comprising a filter for limiting the spectrum of said modulated output signal.

23. A signal processing stage as claimed in claim 22 wherein said filter comprises one of an FFT based filter; an RRC filter; or an FIR filter.

24. A signal processing stage as claimed in claim 1 wherein each of said converter and said combiner are CORDIC based.

25. A signal processing stage for an amplifier comprising : an input arranged to receive a modulated input signal; a converter for splitting said modulated input signal into a magnitude signal component and a phase signal component; a detector for detecting a time Tc when said magnitude signal has a magnitude less than a threshold level, M; a magnitude modifier for modifying said magnitude signal at least after time Tc by adding a signal component to a delayed version of said magnitude signal to maintain a modified magnitude signal derived from said magnitude signal above said threshold level M ; and a combiner for combining a phase signal derived from said phase signal with said modified magnitude signal to provide a modulated output signal for amplification.

26. A transmission system comprising a transmission chain including a data source, a modulator connected to said data source for providing a modulated signal; a band limiting filter for filtering said modulated signal, the signal processing stage of claim 1 for processing said filtered modulated signal and an amplifier connected to said signal processing stage for amplifying said processed filtered modulated signal.

27. A transmission system as claimed in claim 26 wherein said amplifier is an outphasing amplifier.

28. A transmission system as claimed in claim 26 wherein said transmission chain further includes one or more of a crest factor reduction stage and a digital pre-distortion stage.