WO2016077488A1

WO2016077488A1 - Package for electronic system having semiconductor chips

Info

Publication number: WO2016077488A1
Application number: PCT/US2015/060208
Authority: WO
Inventors: Osvaldo Jorge LOPEZ; Jonathan Almeria NOQUIL; Thomas Eugene GREBS; Simon John MOLLOY
Original assignee: Texas Instruments Incorporated; Texas Instruments Japan Limited
Priority date: 2014-11-11
Filing date: 2015-11-11
Publication date: 2016-05-19
Also published as: EP3218930B1; JP6709785B2; US9305852B1; CN107078124B; CN107078124A; EP3218930A1; EP3218930A4; US10109614B2; US20160172338A1; JP2017535960A

Abstract

In described examples, an electronic system includes a first chip (101) of single-crystalline semiconductor, including a first electronic device embedded in a second chip (102) of single-crystalline semiconductor shaped as a container having a slab (104) bordered by ridges (103), and including a second electronic device. The nested chips are assembled in a container of low-grade silicon shaped as a slab (130) bordered by retaining walls (131) and including conductive traces and terminals. The first electronic device is connected to the second electronic device by attaching the first chip onto the slab of the second chip. The first and second electronic devices are connected to the container by embedding the second chip in the container. The nested first and second chips operate as an electronic system, and the container operates as the package of the system. For first and second devices as field effect transistors, the system is a power block.

Description

PACKAGE FOR ELECTRONIC SYSTEM HAVING SEMICONDUCTOR CHIPS

[0001] This relates in general to semiconductor devices and processes, and more particularly to the structure and wafer-scale fabrication method of a low-grade silicon package for embedded semiconductor power block and half bridge devices.

BACKGROUND

[0002] In a majority of today's semiconductor devices, the semiconductor chip is typically assembled on a substrate (such as a metallic leadframe or a multi-level laminate), and encapsulated in a package of a robust material (such as ceramic or hardened plastic compound). The assembly process typically includes the process of attaching the chip to a substrate pad or the leadframe pad, and the process of connecting the chip terminals to substrate leads using bonding wires or solder balls.

[0003] The use of widely different materials (such as metals, ceramics and plastics) cause challenges for mutual parts adhesion, and for long-term device stability. An example is delamination of adjacent parts. For plastic-packaged semiconductor devices, extensive research has been dedicated to identify corrective measures for device reliability issues caused by thermos-mechanical stress, due to material-based mismatches of the coefficients of thermal expansion. Degradation due to stress effects could be mitigated, but not eliminated. Also, moisture-related degradation of electrical characteristics in plastic-encapsulated devices has been well-documented, but has been controlled to only a certain degree. Much effort has further been extended to prevent the onset of fatigue and cracking in metallic connections in devices after operational temperature excursions, but with only limited success.

[0004] Popular families of power supply circuits include the power switching devices for converting a DC voltage to another DC voltage. For the emerging power delivery requirements, suitable options include the power blocks with two power MOS field effect transistors (FETs) connected in series and coupled together by a common switch node; such assembly is also called a half bridge. When a regulating driver and controller is added, the assembly is referred to as power stage or, more commonly, as synchronous buck converter. In the synchronous buck converter, the control FET chip (also called the high-side switch) is connected between the supply voltage Vi_N and the LC output filter, and the synchronous (sync) FET chip (also called the low side switch) is connected between the LC output filter and ground potential. The gates of the control FET chip and the sync FET chip are connected to a semiconductor chip including the circuitry for the driver of the converter and the controller; the chip is also connected to ground potential.

[0005] For many of today's power switching devices, the chips of the power MOSFETs and the chip of the driver and controller IC are assembled horizontally side -by-side as individual components. Each chip is typically attached to a rectangular or square-shaped pad of a metallic leadframe, and the pad is surrounded by leads as output terminals. In other power switching devices, the power MOSFET chips and the driver-and-controller IC are assembled horizontally side -by-side on a single leadframe pad, which in turn is surrounded on all four sides by leads serving as device output terminals. The leads are commonly shaped without cantilever extensions, and arranged in the manner of quad flat no-lead (QFN) or small outline no-lead (SON) devices. The electrical connections from the chips to the leads may be provided by bonding wires, whose lengths and resistances introduce significant parasitic inductance into the power circuit. In some recently introduced advanced assemblies, clips substitute for many connecting wires. These clips are wide and introduce minimum parasitic inductance, but are more expensive than wire bonds and require a more involved assembly process. Each assembly is typically packaged in a plastic encapsulation, and the packaged components are employed as discrete building blocks for board assembly of power supply systems.

[0006] In other recently introduced schemes, the control FET chip and the sync FET chip are assembled vertically on top of each other as a stack, with the physically larger-area chip (among those two) being attached to the leadframe pad, and with clips providing the connections to the switch node and the stack top. Independent of the physical size, the sync FET chip needs a larger active area than the active area of the control FET chip, due to considerations of duty cycle and conduction loss. When both the sync chip and the control chip are assembled source-down, the larger (both physically and active area) sync chip is assembled onto the leadframe pad and the smaller (both physically and active area) control chip has its source tied to the drain of the sync chip, forming the switch node, and its drain to the input supply VIN; a clip is connected to the switch node between the two chips. The pad is at ground potential and serves as a spreader of operationally generated heat; the elongated clip of the stack top is tied to input supply Vm. SUMMARY

[0007] In described examples, an electronic system includes a first chip of single-crystalline semiconductor, including a first electronic device embedded in a second chip of single-crystalline semiconductor shaped as a container having a slab bordered by ridges, and including a second electronic device. The nested chips are assembled in a container of low-grade silicon shaped as a slab bordered by retaining walls and including conductive traces and terminals. The first electronic device is connected to the second electronic device by attaching the first chip onto the slab of the second chip. The first and second electronic devices are connected to the container by embedding the second chip in the container. The nested first and second chips operate as an electronic system, and the container operates as the package of the system. For first and second devices as field effect transistors, the system is a power block. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 illustrates a perspective view of an embodiment that includes a power block with stacked silicon MOS field effect transistors (FETs) flip-attached to and embedded in a silicon package.

[0009] FIG. 2 shows a cross section of the assembled system of FIG. 1 along line A-A.

[0010] FIG. 3 depicts a cross section of a portion of a low-grade-silicon (L-g-Si) wafer with stacked MOSFET chips of a power block attached and embedded.

[0011] FIG. 4 illustrates a perspective view of a site of a 1-g-Si wafer after etching and metallizing a depression suitable for assembling stacked chips for a power block.

[0012] FIG. 5A shows a perspective view of the metal terminals of a MOSFET chip used in assembling a power block.

[0013] FIG. 5B depicts a perspective view of a site of an 1-g-Si wafer after etching a depression and depositing and patterning metal layers matching the FET terminals of the chip of FIG. 5A.

[0014] FIG. 6 illustrates a perspective view of a single-crystalline silicon chip with a depression etched into one chip side before fabricating a FET with terminals into the chip.

[0015] FIG. 7 shows a perspective view of an assembled power block with stacked silicon MOS FETs flip-attached to and embedded in a 1-g-Si slab operating as package.

[0016] FIG. 8 depicts a perspective view of an assembled power converter with stacked MOS FETs and an adjacent driver-and-controller chip embedded in the depression etched into a 1-g-Si slab operating as package.

[0017] FIG. 9 is a flow chart of the method for fabricating an electronic system with stacked component chips embedded in a silicon package.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0018] Example embodiments significantly improve semiconductor transistor devices, power blocks and power converters with respect to reducing parasitic resistances and inductances, improving thermal performances and speed, enhancing operational reliability in moist and temperature -variable ambient, and reducing manufacturing cost. The conventional composite package, where semiconductor chips are assembled on a metallic carrier and packaged in a plastic encapsulation, combines materials of widely different coefficients of thermal expansion, leading to a propensity for thermo-mechanical stresses, and requires a lengthy, time-consuming and costly fabrication flow.

[0019] The market trend, especially for automotive and hand-held applications, requires miniaturized semiconductor products. For example, this trend favors DC-DC converters structures whose semiconductor chips are stacked on top of each other to save precious real estate, instead of being assembled side by side.

[0020] The materials and cost problems of a semiconductor package are solved by a structure concept and manufacturing flow for packages, which adopts and parallels the mass production and controlled processes of routine semiconductor wafer manufacturing. The new package is based on using silicon slabs cut from wafers made of low-grade and thus low cost silicon, such as those obtained from reclaimed, unrefined and undoped silicon. While processed in wafer form, a slab obtains a depression suitable for assembling a single-crystal device chip, and it can act as a carrier as well as the final package.

[0021] The new package concept eliminates leadframes, bonding wires, metallic clips, solder balls, and plastic, ceramic and metallic housings. Instead, the fabrication processes use proven front-end techniques, such as etching semiconductors, metals and insulators, depositing layers of metals, insulators and passivation, growing insulating layers, and patterning by photoresist technologies.

[0022] Also, for stacking chips without clips, the assembly problem is solved by a concept and manufacturing flow for chips with completed transistors or circuits, which includes the etching of depressions into the completed chips having contours and depth for embedding smaller chips into the depression.

[0023] The resulting devices do not suffer from mismatched coefficients of thermal expansion, but instead allow the minimization of thermo-mechanical stresses. Also, parasitic resistances and inductances are reduced because wire bonds and clips are eliminated. Thermal conductivity (and thus electrical performance) of the new devices is enhanced by attaching the chips of the finished devices directly onto circuit boards. Also, the resulting power blocks and power converters (with stacked and embedded chips) allow concurrent device miniaturization in x-dimension, y-dimension and z-dimension.

[0024] FIG. 1 illustrates system 100 as an example embodiment that includes a power block 110 embedded into, and attached to, a container of low-grade silicon (1-g-Si) including a slab 130 and ridges, or retaining walls 131. The container exhibits certain terminals of the system and also operates as the system package. FIG. 2 shows a cross section through power block 101 along lines A-A. The cross section illustrates the attachments of the transistor chips and the layer sequence of metals and insulators. FIG. 3 depicts a cross section through multiple packaged systems after completing the assembly, yet before sawing the wafer of low-grade silicon into discrete packaged systems.

[0025] Referring to the example of FIG. 1 , slab 130 has a flat surface 135 and is made of low-grade silicon (1-g-Si), which is selected from a group including (but not limited to) reclaimed silicon, unrefined silicon, undoped silicon, polycrystalline silicon, intrinsic polycrystalline silicon, lowly doped n-type polycrystalline silicon and lowly doped p-type polycrystalline silicon. In other embodiments, the 1-g-Si material may be heavily doped to obtain low resistivity. In the example of FIG. 1, slab 130 has a thickness 130a of -300 μιη, a length 130b of ~5.8 mm, and a width 130c of ~3.7 mm. Thickness 130a is herein referred to as first thickness. The material of the 1-g-Si slab is exposed at the edges 131a of the slab. The slab top proper, viewed in FIG. 1, is made of a first insulating layer 133, which determines first plane 191. Portions of the insulating layer are exposed at certain locations, while other portions are covered by a metal layer, which is configured as terminals 120 (e.g., switch node of the power block), terminal 121 (e.g., gate of the high side FET) and terminal 122 (e.g., drain of the high side FET tied to input supply Vm) of system 100. The insulating surface of the slab is called herein first surface 130d, which is in a first plane 191. [0026] As FIG. 1 shows, slab 130 is configured as a set of elevated ridges 131 with the top surface 130d in plane 191, so that the ridges are framing a depression. In FIG. 1, the system has two parallel ridges. In other embodiments, the system may have more ridges. The depression includes a recessed central area with a surface 134 in a second plane 191. Surface 134 is covered by a second insulating layer 136. The central area is suitable to accommodate at least semiconductor chip 102. Another embodiment is shown in FIG. 8, where the central area is suitable to accommodate more than one chip. FIG. 1 illustrates that the surface of the central area is in a second plane 192, which is spaced from the first plane 191 by depression depth 132a, which is referred to herein as first depth. Preferably, first depth 132a is equal to the sum of the chip thickness 102a and the thickness of the adhesive material used for attaching chip 102 to the recessed central area. In the example of FIG. 1, first depth 132a may be ~64 μιη. As depicted in later figures, the central area is covered by a patterned metal layer configured as attachment pads for the device terminals, such as transistor terminals. As FIGS. 2 and 3 show, the pads of the central area are grouped into an inner set and a peripheral set.

[0027] The portion of power block 110 visible in FIG. 1 is semiconductor chip 102, which is referred to herein as second chip (first chip 101 is shown in FIGS. 2 and 3). In the example of FIG. 1, chip 102 is made of heavily doped single-crystalline silicon, which allows direct contact to a metal layer, often referred to as back metal. The doped silicon is topped by an epitaxial layer of intrinsic silicon, which includes a drain-down MOS field effect transistor (FET) serving as the low side transistor of the power block and is herein referred to as the second semiconductor chip. Chip 102 has a thickness 102a, such as -50 μιη, which is herein referred to as third thickness. Third thickness 102a is smaller than first thickness 130a, but greater than second thickness 101a (which is depicted in FIGS. 2 and 3 as the thickness of the first semiconductor chip 101). Chip 102 has a flat side 102d (FIG. 1), which is referred to herein as the third side.

[0028] The example MOS FET of FIG. 1 has its source terminal 140 and gate terminal 141 on the third side facing away from slab 130. Source terminal 140 is electrically tied to ground potential. In other examples, the semiconductor chip may be made of silicon-germanium, gallium arsenide, gallium nitride, or other III-V and II-VI compounds used as semiconductor device materials. In yet other FET embodiments, the drain terminal may be facing away from the slab. In still other embodiments, the transistor may be a bipolar transistor having the collector contact facing away from the slab; or the bipolar transistor may have the emitter terminal facing away from the slab.

[0029] Because FIG. 2 shows a cross section of system 100 along lines A-A in FIG. 1, the ridges of slab 130 are not represented. Instead, FIG. 2 shows the flat surface 135 of the slab and the flat surface 134 of the recessed central area, which is in the second plane 192. FIG. 2 further displays a first semiconductor chip 101 and a second semiconductor chip 102, which may be larger than fist chip 101. Both chips are made of a single-crystalline semiconductor material, such as silicon. For second chip 102, FIG. 2 indicates flat side 102d, which is referred to herein as third side. FIG. 2 further illustrates that chip 102 has a fourth side 102b, which is contoured. The contour of fourth side 102b is configured as a set of ridges 103 with a surface in third plane 193; ridges 103 frame a depression. In FIG. 2, chip 102 has two parallel ridges. In other embodiments, chip 102 may have more ridges. The depression includes a recessed flat central area with a surface 102c in a fourth plane 194 parallel to plane 193. The central area is suitable to accommodate first chip 101, which is thus embedded in second chip 102. FIG. 1 illustrates that fourth plane 194 is spaced from the third plane 193 by a second depth 132b smaller than the first depth 132a and suitable to accommodate the thickness of first chip 101 with its metal layers and layers of attachment material.

[0030] FIG. 2 indicates that fourth side 102b including surface 102c of chip 102 is uniformly covered by a metal layer 221, which is sometimes referred to as back metal. Preferably, layer 221 includes a layer of refractory metal (such as titanium or tungsten) for adhesion to the semiconductor crystal, followed by a layer of nickel and an outermost layer of a noble metal (such as silver, palladium or gold). In some products, the refractory metal layer is omitted. Portions of the third side 102d of chip 102 also have a sequence of stacked layers of similar metal selections, such as titanium, nickel and silver, or just nickel and gold. The stacked metal layers are patterned into pads 222 and 223.

[0031] In the example embodiment of FIG. 2, chip 102 includes a field effect transistor (FET), which serves as the low-side FET of the power block. As mentioned, the bulk single-crystal silicon of chip 102 is heavily doped and makes good contact to the so-called back metal layer 221. In this example of FIG. 2, the metallized fourth chip side 102b with metal layer 221 serves as the drain terminal of the low-side FET, electrically tied to the switch node, pad 222 is the source terminal electrically tied to ground potential, and pad 223 the gate terminal of the low-side FET. As FIG. 2 shows, the fourth chip side 102b of chip 102 includes the ridges and the central area, which is depressed relative to the ridges.

[0032] Based on its smaller size and thickness, first chip 101 is embedded in the depression of second chip 102. As stated, first chip 101 is made of a single-crystalline semiconductor material, such as silicon. In contrast to second chip 102, both first side lOld and second side 101b of first chip 101 are flat. First chip 101 has thickness 101a, which is smaller than second depth 132b, so that first chip 101 (together with its metal layers and attachment layers) can be embedded in the depressed central area of second chip 102.

[0033] In the example embodiment of FIG. 2, chip 101 includes a field effect transistor (FET), which serves as the high-side FET of the power block and has terminals on the first and the second chip side. In this example, the metal pad 211 of first chip side lOld serves as the drain terminal of the high-side FET, electrically tied to the input supply V_IN, and pad 213 is the gate terminal of the high-side FET.

[0034] As FIG. 2 illustrates, the 1-g-Si material of slab 130 is covered by an insulating layer 136, preferably thermally grown silicon dioxide. In some places, the insulating layer has increased thickness, which is a secondary effect of the patterning of the metal layer, discussed by the process flow below. In turn, insulating layer 136 is covered by a metal layer. One metal layer may be sufficient, but FIG. 2 illustrates a preferred method of a sequence of metal layers. The first layer 231 is made of a refractory metal such as titanium, followed by a compound layer such as titanium nitride. Alternative choices include a layer of tungsten, titanium-tungsten or another refractory metal. The refractory metal adheres strongly to insulating layer 136. Then, a layer 232 of aluminum is deposited onto the refractory metal layer; layer 232 is preferably thicker than layer 231. For some applications, it is preferred to deposit a layer of nickel and a thin layer of gold (both layers designated 233 in FIG. 2) on top or the aluminum layer 232 to facilitate the attachment of transistor terminals.

[0035] The metal layers 231 and 232 (and optional 233) are patterned in the depressed central area of slab 130. The result of the patterning is multiple pads grouped into an inner set and a peripheral set. The pads of the inner set match the terminals of the transistors of the first chip 101, and the pads of the peripheral set match the terminals of the ridges of second chip 102. For the first chip 101 of FIG. 2, the patterned metal pads of the inner set include the drain terminal 241 and the gate terminal 243 of the high-side FET. For the second chip 102 of FIG. 2, the patterned metal pads of the peripheral set include the switch node terminals 242 of the power block, which combines the source terminal of the high-side FET and the drain terminal of the low-side FET.

[0036] FIG. 3 depicts a portion of a 1-g-Si wafer 330 with multiple slab sites after completing the assembly of first and second FET chips in each slab site. As FIG. 3 shows, for each slab site, the assembly encompasses a first chip 101 embedded in the depression of a second chip 102 and, in turn, the second chip embedded in the depression of a respective slab. Second chip 102 is formed as a container including a slab 104 bordered by ridges 103. The embedded positions imply that the metallized depressed central area of the fourth side of second chip 102 is attached to the terminals on the second side of the first chip, and the metallized ridges of the second chip is attached to the pads of the peripheral set of the central 1-g-Si area, so the transistor terminals on the third side of the second chip are co-planar with the metal layer on the ridges of the respective 1-g-Si slab. In FIG. 3, the plane of co-planarity is designated 191; it is referred to herein as first plane.

[0037] In FIG. 3, the cut lines through the wafer for separating the slab sites are marked 340. After singulation, a discrete system looks as system 100 depicted in FIG. 1. Metal layer 222 (as the source terminal 140) and metal layer 223 (as the gate terminal 141) are ready for attachment to external parts, when system 100 is connected to a circuit board.

[0038] Another embodiment is a method of fabricating semiconductor slabs bordered by retaining walls suitable as device packages, and a method of fabricating a packaged electronic system using a silicon slab as a package for semiconductor devices. Certain processes are summarized in FIGS. 4, 5A, 5B, 6 and 7. An overview of the process flow for fabricating an electronic system with stacked chips embedded in a silicon package is presented in the flow chart of FIG. 9. The process flow of fabricating semiconductor slabs starts with providing a wafer of low-grade silicon (1-g-Si), which includes multiple slab sites (process 901). The wafer has two parallel flat surfaces, one of which is referred to as first surface. The preferred wafer diameter is 300 mm, but smaller diameters may be used; the plane of the first surface is referred to as first plane 191. Preferably, the final wafer (before dicing) has a thickness 130a (referred to as first thickness) of -300 μιη. Nevertheless, the preceding process steps may be executed using a thicker wafer and obtaining the final thickness by back-grinding. Consequently, designation 110a of FIG. 3 intends to indicate such wafer thickness greater than 130a. The 1-g-Si may be selected from a group including reclaimed silicon, unrefined silicon, undoped silicon, polycrystalline silicon and intrinsic polycrystalline silicon. For devices with transistor terminals isolated from the slab, the 1-g-Si material may also include lowly doped n-type polycrystalline silicon and lowly doped p-type polycrystalline silicon. By comparison, for devices with transistor terminals shorted to the slab, the 1-g-Si material may also include low resistivity n-type polycrystalline silicon and low resistivity p-type polycrystalline silicon.

[0039] In the next process for either 1-g-Si choice, a first insulating layer 133 is formed on the first surface of the wafer (process 902); the layer covers all slab sites. The preferred technique of forming an insulating surface layer is thermally oxidizing the silicon. Alternative techniques include depositing a layer of silicon dioxide, silicon nitride, silicon carbide, or a combination thereof, and depositing an insulating compound different from a silicon compound.

[0040] Then, the first insulating layer is removed from the central portion of each slab site to expose the underlying 1-g-Si, while leaving unremoved the first insulating layer 133 over the peripheral site portions to form ridges framing each central portion (process 903). The ridges are sometimes referred to as retaining walls or rims bordering the central portion.

[0041] In the next process (process 904), the exposed 1-g-Si of the central area of each slab site is etched, such as using KOH, to create a depression with a second 1-g-Si surface having a flat central portion in a second plane 192 recessed from the first plane by a depth 132a. FIG. 4 depicts an individual slab site at a processing state, which summarizes the results of the above-referenced fabrication processes; the depicted site is an integral portion of a larger wafer, as indicated by the phantom lines.

[0042] For the discrete slab site in FIG. 4, the depression has a rectangular configuration bordered by two parallel ridges. For other devices, other configurations for the depression and for the ridges may be used. The depression, which is formed by the etching process, also creates a step of 1-g-Si between the first plane 191 and the second plane 192. Preferably, the step is inclined less than 90°. More preferably, the step forms a gradual slope 401 between the first and the second 1-g-Si surface, so that an uninterrupted metal layer can easily be deposited on slope 401.

[0043] In the process flow leading up to the packaged transistor device of FIG. 2, the flow starts by providing a wafer of undoped or weakly doped 1-g-Si, which includes multiple slab sites 210. Each site is configured into ridges with a top in a first plane 290 and a depression framed by the ridges. The depression includes a recessed central area in a second plane 291, spaced from the first plane by a depth 112. A second insulating layer 136 is formed on the second silicon surface; layer 136 covers all slab sites (process 905). Other techniques are possible, but preferably the second insulating layer is thermally grown, so that the silicon dioxide of the second layer 136 merges with the left-over silicon dioxide of the first layer 133.

[0044] Next, at least one layer 231 of metal is deposited onto the second insulating layer 136, covering all slab sites (process 906). Preferably, first a layer of a refractory metal such as titanium is selected, followed by a compound layer such as titanium nitride. Alternative choices include a layer of tungsten, titanium-tungsten or another refractory metal. The refractory metal adheres strongly to insulating layer 136. Then, a layer 232 of aluminum is deposited onto the refractory metal layer. Layer 232 is preferably thicker than layer 231. For some applications, it is preferred to deposit a layer of nickel and a thin layer of gold (both layers designated 233 in FIG. 2) on top or the aluminum layer 232 to facilitate the attachment of transistor terminals.

[0045] Next, the metal layers 231 and 232 (and 233) are patterned at each slab site (process 907). FIG. 4 gives an overview of the patterned metal pads of a discrete slab. On the ridges, system terminals are formed. In the central site portion, pads for transistor terminals (or for other device terminals) are created, which are grouped in an inner set and a peripheral set.

[0046] On the ridges for the example shown in FIG. 4, metal layers 120 are destined to be system terminals for the switch node of a power block; metal layer 121 will be the terminal for the gate of the high-side FET; and layer 122 will be system terminal of the drain of the high-side FET tied to the input supply V_IN of the system. In the central site portion of the example of FIG. 4, the result of the patterning is multiple pads grouped in an inner and a peripheral set, matching the terminals of transistors. The pads of the inner set include pad 411 for the drain terminal 211 of the high-side FET (ending as terminal 122 on the ridge) and pad 413 for the gate terminal 213 of the high-side FET (ending as terminal 121 on the ridge). The pads of the peripheral set include pads 420 for the switch node terminal (ending as terminals 120 on the ridges).

[0047] After the patterning, a layer 205 of passivation material such as silicon nitride is deposited onto the patterned metal layer, covering all slab sites (process 908). Passivation layer 237 is then removed, at each slab site, from the terminals on the ridges and from the pads in the central portion to expose the underlying metal. By comparison, the passivation material over the slopes and between the pads is left unremoved. [0048] In the next process 909, first semiconductor chips 101 have a flat first side 101b and an opposite flat second side lOld, and a second thickness 101a smaller than the first thickness 130a of the 1-g-Si slab. The first chips may include transistors with terminals on the first and the second chip side. For the example of FIG. 5 A, the chips are shaped as a hexahedron and made of single-crystalline silicon. The chips may include a FET with a source terminal on the first chip side and a drain terminal 211 and a gate terminal 213 on the opposite second chip side. For other systems, chip 101 may include a bipolar transistor, or it may have different terminal distribution, or chip 101 may be made of gallium arsenide, gallium nitride or any other semiconductor single crystalline compound.

[0049] Next, the terminals of the first side of first chips 101 are attached to respective pads of the inner set of the central area of each slab 130 of the 1-g-Si wafer (process 910). The preferred attach material is a conductive paste, which includes an adhesive polymeric compound. FIG. 5B depicts an example slab site after the attachment, which creates sub-assemblies designated 500 in FIG. 5B. In the subassembly, the terminals 212 of the second side of the first chip face towards the first plane 191. In the example of FIG. 5B, terminal 212 represents the source terminal of the FET of the first chip.

[0050] In the next process 911, shown in FIG. 6, second semiconductor chips 102 have a flat third side 102d and an opposite contoured fourth side 102b, and a third thickness 102a smaller than the first thickness but greater than the second thickness 101a. The fourth side 102b is configured as a ridge, or retaining wall, in a third plane 193 framing a depression including a flat central area in a parallel fourth plane 194 recessed from the third plane by a second depth 132b. Second depth 132b is configured to be smaller than the first depth 132a of a slab, and suitable to accommodate a first chip 101.

[0051] Second chips 102 are made of a single crystalline semiconductor, frequently silicon, which is heavily doped and makes good contact to the uniform metal layer covering the fourth side 102b. Also, chips 102 include an epitaxial layer suitable for forming active devices, such as FETs or bipolar transistors. In the example of FIG. 6, the transistor is a FET with a source terminal 222 and a gate terminal 223 on the third side 102d, and a drain terminal on the fourth side 102b.

[0052] FIG. 7 illustrates the assembly of a second chip 102 with a subassembly 500 of FIG. 5B (process 912). In this process, the metallized depressed central area of the fourth side 102b of a second chip 102 is attached to the terminals on the second side 101b of the respective first chip 101, and the metallized ridges of the second chip 102 are attached to the pads of the respective peripheral set of the central 1-g-Si area. In this assembly process, the transistor terminals 222 and 223 on the third side 102d of the second chips become co-planar with the terminals 120, 121 and 122 on the ridges of the respective 1-g-Si slab 130. All attachment processes are preferably performed using a conductive paste of an adhesive polymeric compound; alternatively, they may be performed using a lead-free solder. The co-planarity of all system terminals facilitates the assembly of the system onto external boards.

[0053] After the chips have been assembled in the depressions of the sites of the wafer, the 1-g-Si wafer is cut by saws or laser into singulated systems, as depicted in FIG. 1 (process 913).

[0054] The electronic system with stacked semiconductor chips embedded in a silicon package offers numerous technical advantages. Compared to conventional systems, multiple parts are eliminated, all of which are costly, labor-intensive in manufacturing, and parasitic in electrical parameters, such as: bonding wires, connecting clips, metallic leadframes, plastic molding compounds, and solders with lead. Thermal performance is greatly improved by low theta parameters to case, to top, to ambient, and heat sinks. The ratio of active silicon versus package is high, and the overall system thickness can be kept very thin (-0.3 to -0.5 mm). Differences between the coefficients of thermal expansion of chips and package are minimized or eliminated; thermo-mechanical stresses are thus minimized.

[0055] Other embodiments are electronic systems, such as a DC-DC power converter, often referred to as synchronous Buck converter. The example converter depicted in FIG. 8 includes a vertical stack of two FET chips, embedded into each other, and an adjacent driver-and-controller chip assembled on a 1-g-Si container formed as a slab with retaining walls. The example system has a length 801 of 5.0 mm, a width 802 of 3.0 mm, and a height 803 of 0.45 mm. All metal terminals and the silicon back side 810a of the driver-and-controller chip 810 are co-planar; the common plane is designated 191. By adopting and expanding the designations employed in FIGS. 1 and 7, FIG. 8 shows both the power block 110 with the embedded FETs and the flipped driver-and-controller chip 810 attached to slab 130. In the example of FIG. 8, metal layer 222 is the source terminal of the low-side FET (sync FET), layer 223 is the gate terminal of the low- side FET (sync FET), metal layer 122 is the drain terminal of the high-side FET, electrically tied to the input supply Vi_N, layer 121 is the gate terminal of the high-side FET, layers 120 are the terminals of the switch node, and metal layers 811, 812, 813, 814, 815 and 816 are the output pins of the integrated driver-and-controller circuit of flipped chip 810. The exposed silicon surface 810a may be metallized to facilitate the attachment to an external board.

[0056] Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims. For example, example embodiments apply to field effect transistors, and also to other suitable power transistors, bipolar transistors, insulated gate transistors, thyristors and others.

[0057] As another example, the above considerations for structure and fabrication method of power converters apply to regulators, multi-output power converters, applications with sensing terminals, and applications with Kelvin terminals and others.

[0058] As another example, the high current capability of the packaged transistors and converter can be further extended, and the efficiency further enhanced, by using the blank backside of the 1-g-Si, after attachment of the devices to a board, so that the back side can be connected to a heat sink, preferably. In this configuration, the device can dissipate its heat into the board and into the heat sink.

Claims

CLAIMS What is claimed is:

1. An electronic system comprising:

a first chip of single-crystalline semiconductor, the first chip shaped as a hexahedron and including a first electronic device;

a second chip of single-crystalline semiconductor, the second chip shaped as a container having a slab bordered by retaining walls, and including a second electronic device;

a container of low-grade silicon, the container shaped as a slab bordered by retaining walls and including conductive traces and terminals;

the first chip attached to the slab of second chip, forming nested chips; and

the first and second chips embedded in the container, wherein the nested first and second chips are operable as an electronic system, and the container is operable as the package of the system.

2. The system of claim 1, wherein the single-crystal semiconductor is silicon, the first and the second electronic device are MOS field-effect transistors, and the electronic system is a power block.

3. The system of claim 1, wherein the single-crystal semiconductor is silicon, the first and the second electronic device are bipolar transistors, and the electronic system is a regulator.

4. An electronic system comprising:

a third chip of single-crystalline semiconductor, the third chip shaped as a hexahedron and including a third electronic device;

the first chip attached to the slab of the second chip, forming a stack of nested chips; and the nested first and second chips and the adjacent third chip embedded in the container, wherein the nested first and second chips and the adjacent third chip are operable as an electronic system, and the container is operable as the package of the system.

5. The system of claim 4, wherein the single-crystal semiconductor is silicon, the first and the second electronic device are MOS field-effect transistors, the third electronic device is an integrated circuit, and the electronic system is a power converter.

6. A packaged electronic system comprising:

a slab of low-grade silicon (1-g-Si) having a first thickness and a surface in a first plane, the slab configured as a ridge in the first plane framing a depression including a recessed central area in a second plane spaced from the first plane by a first depth, the ridge and the central area covered by a metal layer patterned into pads for contacting transistor terminals, the pads of the central area grouped into an inner set and a peripheral set;

a first semiconductor chip having a flat first and an opposite flat second side, and a second thickness smaller than the first thickness, the first chip including a transistor having terminals on the first and the second side, the terminals of the first chip side attached to respective pads of the inner set of the central area of the 1-g-Si slab, creating a sub-assembly wherein the terminals of the second chip side face towards the first plane;

a second semiconductor chip having a flat third and an opposite contoured fourth side, and a third thickness smaller than the first thickness but greater than the second thickness, the fourth side configured as a ridge in a third plane framing a depression including a flat central area in a parallel fourth plane recessed from the third plane by a second depth smaller than the first depth and suitable to accommodate the first chip, the fourth side uniformly metallized, the second chip including a transistor having terminals on the third and the fourth side; and

the metallized depressed central area of the fourth side attached to the terminals on the second side of the first chip, and the metallized ridges of the second chip attached to the pads of the peripheral set of the central 1-g-Si area, so the transistor terminals on the third side of the second chip are co-planar with the metal layer on the ridges of the respective 1-g-Si slab.

7. The device of claim 6, wherein the transistors of the first and the second chips are MOS field-effect transistors, and the electronic system is a power block.

8. The device of claim 6, wherein the transistors of the first and the second chips are bipolar transistors, and the electronic system is a regulator.

9. A method for fabricating a packaged electronic system comprising:

providing a wafer of low-grade silicon (1-g-Si) including a plurality of slab sites, the wafer having a first thickness and a first surface in a first plane, each site configured as a ridge in the first plane framing a depression including a recessed central area in a second plane spaced from the first plane by a first depth, the ridge and the central area covered by a metal layer patterned into pads for contacting transistor terminals, the pads of the central area grouped into an inner set and a peripheral set;

providing a plurality of first semiconductor chips having a flat first and an opposite flat second side, and a second thickness smaller than the first thickness, the first chips including transistors having terminals on the first and the second side;

attaching the terminals of the first chip side to respective pads of the inner set of the central area of each 1-g-Si slab, creating sub-assemblies, wherein the terminals of the second chip side face towards the first plane;

providing a plurality of second semiconductor chips having a flat third and an opposite contoured fourth side, and a third thickness smaller than the first thickness but greater than the second thickness, the fourth side configured as a ridge in a third plane framing a depression including a flat central area in a parallel fourth plane recessed from the third plane by a second depth smaller than the first depth and suitable to accommodate the first chips, the fourth side uniformly metallized, the second chips including transistors having terminals on the third and the fourth side; and

for each subassembly, attaching the metallized depressed central area of the fourth side of a second chip to the terminals on the second side of the respective first chip, and the metallized ridges of the second chip to the pads of the respective peripheral set of the central 1-g-Si area, so the transistor terminals on the third side of the second chips are co-planar with the metal layer on the ridges of the respective 1-g-Si slab.

10. The method of claim 9 wherein the process of attaching employs conductive adhesives.

11. The method of claim 9 further including the process of dicing the 1-g-Si wafer to singulate discrete multi-output devices having transistor chips embedded in a 1-g-Si slab as a package.

12. The method of claim 11, wherein the transistors of the first and the second chips are MOS field-effect transistors, and the electronic system is a power block.

13. The method of claim 11 wherein the transistors of the first and the second chips are bipolar transistors, and the electronic system is a regulator.

14. The method of claim 9 wherein the process of providing a wafer of low-grade silicon (1-g-Si) includes the processes of:

providing a wafer of 1-g-Si including a plurality of slab sites, the wafer having a first thickness and a first surface in a first plane;

forming a first insulating layer on the first surface, the first insulating layer covering all slab sites;

removing the insulating layer from the central portion of each slab site to expose the underlying 1-g-Si, leaving unremoved the insulating layer over the peripheral site portions to form a ridge framing each central portion;

etching the exposed 1-g-Si of the central area of each device site to create a depression with a second 1-g-Si surface having a central flat portion in a second plane recessed from the first plane by a first depth, and slopes between the first and the second poly-Si surface;

forming a second insulating layer on the second 1-g-Si surface, the second insulating layer covering the central area of each device site;

depositing at least one layer of metal onto the whole wafer;

patterning the metal layer at each device site to form device terminals on the ridges and a plurality of pads matching transistor terminals in the central portion, the pads grouped into an inner set and a peripheral set;

depositing a passivation layer onto the wafer surface, covering all device sites; and removing, at each device site, the passivation layer from the terminals on the frames and from the pads in the central portion, to expose the underlying metal, while leaving unremoved the passivation material over the slopes and between the pads.

15. The method of claim 14 wherein the etching process creating the depression forms a step of 1-g-Si between the first and second plane, which is inclined at an angle < 90°.

16. The method of claim 14 wherein the low-grade silicon (1-g-Si) of the wafer is selected from a group including, but not limited to, reclaimed silicon, unrefined silicon, undoped silicon, polycrystalline silicon, intrinsic polycrystalline silicon, lowly doped n-type polycrystalline silicon and lowly doped p-type polycrystalline silicon.

17. The method of claim 14 wherein the layers of metal include a layer each of titanium, titanium nitride and aluminum.

18. The method of claim 14 further including the process of depositing a layer of nickel followed by an outermost layer of gold on the aluminum layer.

19. The method of claim 9 wherein the process of providing a plurality of second chips includes the processes of:

providing a semiconductor wafer including a low-resistivity bulk semiconductor and an epitaxial layer of intrinsic semiconductor, the wafer having a third thickness and including a plurality of device sites;

forming a transistor in each site, the transistor having terminals on the surfaces of the epitaxial and the bulk semiconductor;

etching the bulk semiconductor of each site to form a cavity with a flat central area framed by a ridge of bulk semiconductor, the central area having a size and a depth suitable to house a first chip, yet leaving un-etched the bulk semiconductor frame of third thickness;

depositing at least one layer of metal onto the surfaces of the epitaxial and the etched bulk semiconductor of the whole wafer;

forming metallized transistor terminals by patterning the metal layer on the surface of the epitaxial semiconductor of each site, yet leaving un-patterned the metal layer over the central area and the ridge of the cavity of each site; and

dicing the wafer to singulate discrete second chips of third thickness having metallized ridges.