WO2016060337A1

WO2016060337A1 - Field effect transistor manufacturing method

Info

Publication number: WO2016060337A1
Application number: PCT/KR2015/001129
Authority: WO
Inventors: 최양규; 전창훈
Original assignee: 한국과학기술원
Priority date: 2014-10-13
Filing date: 2015-02-04
Publication date: 2016-04-21

Abstract

The present invention relates to a semiconductor field effect transistor manufacturing technique comprising the steps of: forming a lower semiconductor layer having a first energy band gap, wherein the lower semiconductor layer is doped in a p-type; forming, on the upper part of the lower semiconductor layer, a middle semiconductor layer having a second energy band gap having a smaller value than that of the first energy band gap; and forming, on the upper part of the middle semiconductor layer, an upper semiconductor layer having the first energy band gap. Therefore, the present invention can increase a threshold voltage by OV or more while maintaining the advantages of a conventional electron well channel having high mobility.

Description

Method of manufacturing field effect transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (hereinafter referred to as FET) fabrication technology, in particular a FET suitable for regulating a threshold voltage without deterioration in mobility in a FET having a channel of an electronic well structure. It relates to a manufacturing method.

Part of the present invention was carried out with the support of the Future Convergence Pioneer Project of the Korea Research Foundation with the funds of the government (Ministry of Future Creation Science) (2012-0009594).

Devices utilizing high mobility characteristics, for example, devices using compound semiconductors such as High Electron Mobility Transistors (HEMTs) having an electron well structure channel, are already partially used in analog amplifiers.

The channel of the electron well structure has a small energy bandgap that is not doped due to the 2-DEG (Dimensional Electron Gas) generated by supplying the necessary electrons to the channel layer in the upper doping layer having the large energy bandgap. The channel layer can avoid collisions by ionized impurities and has high mobility characteristics because the mobility characteristics are limited only by lattice collisions.

However, there is a need to overcome threshold voltage limitations for more applications such as logic circuit design.

That is, even though no gate voltage is applied, 2-DEG is already formed in the channel layer, and thus the logic circuit and the enhancement mode in which the threshold voltage is greater than 0V are operated in a depletion mode in which the threshold voltage is less than 0V. It is not applicable where a transistor operating in an enhancement mode is required.

7 is a general structure of a conventional high mobility field effect transistor.

As shown in FIG. 7, the carrier of the conductive channel moves from the doped large bandgap semiconductor layer to the channel layer with the smaller bandgap to form 2DEG.

In particular, semiconductors used as channel regions have higher carrier mobility than doped regions. Therefore, collision by the ionized impurities in the channel layer can be avoided, and movement characteristics are limited only by mobility due to lattice collision. However, even if the gate voltage is not applied, the 2DEG is already formed in the channel layer, and thus operates in the depletion mode in which the threshold voltage is less than 0V.

Current silicon (Si) logic semiconductor technology has a method of doping additional channel layers to adjust the threshold voltage. At this time, the collision of the carrier by the ionized impurities is inevitable, thereby reducing the carrier mobility.

Another method to increase the threshold voltage is to use a material having a large work function of the metal material used as a gate, but this is difficult to apply to a semiconductor process with many constraints such as subsequent thermal processes and contamination issues.

In the present invention, by doping the semiconductor layer having a large energy bandgap under the channel layer of the FET in the p-type (p) type, a technique that can increase the threshold voltage while maintaining the advantages of the existing well-moving electron well channel I would like to suggest.

In addition, the present invention proposes a technique capable of lowering the threshold voltage while maintaining the advantages of the existing well-moved electron well channel by doping the semiconductor layer having a large energy bandgap on the channel layer of the FET to the n-type. I would like to.

According to an embodiment of the present invention, forming a lower semiconductor layer having a first energy band gap, doping the lower semiconductor layer to a p-type (type), and the first energy on the lower semiconductor layer Forming an intermediate semiconductor layer having a second energy band gap having a smaller value than the band gap, and forming an upper semiconductor layer having the first energy band gap on the intermediate semiconductor layer; Field Effect Transistor) can be provided.

Here, the method of manufacturing the field effect transistor may be characterized in that the threshold voltage (rising) rises.

The method may further include forming a gate electrode after forming the upper semiconductor layer, and forming a source electrode and a drain electrode on the semiconductor substrate on which the gate electrode is formed. The source electrode and the drain electrode may be spaced apart from each other by the width of the gate electrode.

The field effect transistor may have a structure in which an electron channel is surrounded in three dimensions by the gate electrode.

According to another embodiment of the present invention, a process of forming a lower semiconductor layer having a first energy band gap, and an intermediate semiconductor having a second energy band gap having a value smaller than the first energy band gap on the lower semiconductor layer. Forming a layer, and forming an upper semiconductor layer having the first energy bandgap on the intermediate semiconductor layer, and doping the upper semiconductor layer to n-type. Can provide.

Here, the method of manufacturing the field effect transistor may be characterized in that the threshold voltage is lowered.

The method may further include forming a gate electrode after forming the upper semiconductor layer, and forming a source electrode and a drain electrode on the semiconductor substrate on which the gate electrode is formed. The source electrode and the drain electrode may have a structure overlapping with the gate electrode.

In addition, the field effect transistor may have a structure in which an electron channel is surrounded in three dimensions by the gate electrode.

The present invention utilizes the advantages of the 2-DEG channel structure of the conventional high mobility field effect transistor while doping a semiconductor layer having a large lower energy bandgap of the electron well structure into a p-type, thereby reducing the threshold voltage of the existing high mobility field effect transistor. The disadvantage of operating in a depletion mode smaller than 0V can be solved. In addition, it is possible to avoid the disadvantage that the mobility is reduced by doping the existing channel layer. Therefore, the present invention can be more easily applied to various circuit designs using various threshold voltages, and thus, it can be effectively used for logic technology application of high mobility compound semiconductors.

1 is a cross-sectional view of a semiconductor layer for explaining a method of manufacturing a FET according to an embodiment of the present invention;

2 is a graph illustrating a simulation result of a p-type doping of a semiconductor layer having a large lower energy bandgap of an electron well structure according to an embodiment of the present invention;

3 is a graph illustrating a simulation of a threshold voltage control method expected by changing a p-type doping concentration of a semiconductor having a large lower energy band gap.

4 is a cross-sectional view of a semiconductor layer for explaining a method of manufacturing a FET according to another embodiment of the present invention;

FIG. 5 is a graph illustrating a simulation result of n-type doping of a semiconductor layer having a large upper energy bandgap of an electron well structure according to another embodiment of the present invention;

FIG. 6 is a three-dimensional cross-sectional view of a semiconductor layer in which a 2-DEG electron channel is formed by changing the semiconductor layer of FIG. 1 to a three-dimensional structure as another embodiment of the present invention; FIG.

7 illustrates a conventional high mobility FET.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, and only the embodiments make the disclosure of the present invention complete, and the general knowledge in the art to which the present invention belongs. It is provided to fully inform the person having the scope of the invention, which is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

In describing the embodiments of the present invention, if it is determined that a detailed description of a known function or configuration may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. In addition, terms to be described below are terms defined in consideration of functions in the embodiments of the present invention, which may vary according to intentions or customs of users and operators. Therefore, the definition should be made based on the contents throughout the specification.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

1 is a cross-sectional view of a semiconductor layer for explaining a method of manufacturing a FET according to an embodiment of the present invention. When forming a 2-DEG conductive channel carrier from two compound semiconductors having different energy bandgaps, a lower energy bandgap is shown. This large semiconductor layer is doped p-type.

This will be described in detail for each process.

First, a lower semiconductor layer, which is the first semiconductor layer 100, is formed on a semiconductor substrate (not shown). Here, the first semiconductor layer 100 may be a semiconductor layer having a relatively large energy band gap, for example, a semiconductor layer having an energy band gap of 1.3 eV or more.

In this case, the first semiconductor layer 100 may be doped (p-type) in accordance with an embodiment of the present invention, thereby raising the threshold voltage.

After forming the first semiconductor layer 100, an intermediate semiconductor layer, which is the second semiconductor layer 102, is formed thereon. Here, the second semiconductor layer 102 may be a semiconductor layer having a relatively small energy band gap, for example, a semiconductor layer having an energy band gap of 0.7 eV or less.

Thereafter, an upper semiconductor layer, which is the third semiconductor layer 104, is formed on the second semiconductor layer 102. Here, the third semiconductor layer 104 may be a semiconductor layer having a relatively large energy band gap, for example, a semiconductor layer having an energy band gap of 1.3 eV or more.

Various techniques are known for adjusting the energy bandgap of the first semiconductor layer 100, the second semiconductor layer 102, and the third semiconductor layer 104. For example, when the indium ratio is increased, the energy band gap may be reduced. When the gallium ratio is increased, the energy band gap may be increased. However, such a technique is merely an example, and it will be readily apparent to those skilled in the art that various techniques for adjusting the energy band gap are applicable.

By forming the first semiconductor layer 100, the second semiconductor layer 102, and the third semiconductor layer 104, a transistor having a channel having an electron well structure can be manufactured.

Thereafter, the gate electrode 108 is formed on the semiconductor substrate on which the third semiconductor layer 104 is formed. The gate electrode 108 may be formed by a deposition process, an etching process, a patterning process, and the like, and a process of forming the gate electrode 108 may be easily understood by those skilled in the art. In this case, specific process steps will be omitted.

In addition, in forming the gate electrode 108, a process of forming the gate insulating layer 106 may be further performed.

After the gate electrode 108 is formed, a spacer 110 may be formed on both sidewalls of the gate electrode 108 by performing an etching process or the like.

Subsequently, a source / drain ion implantation process using a dopant is performed on the semiconductor substrate on which the gate electrode 108 and the spacer 110 are formed, and sources spaced apart from each other by the width of the gate electrode 108 and the spacer 110. Drain electrode 112 can be formed.

At this time, the process of forming the source / drain electrode 112 and the process of forming the gate electrode 108 may be reversed.

FIG. 2 is a graph illustrating a simulation result of p-type doping of a semiconductor layer having a large lower energy bandgap of an electron well structure according to an exemplary embodiment of the present invention.

As shown in FIG. 2, it can be seen that the threshold voltage increases greatly from the doping concentration of 1016 cm −3 or more.

In the simulation results of FIG. 3, it is expected to be most utilized in the doping concentration of 1016 cm-3 to 1017 cm-3.

4 is a cross-sectional view of a semiconductor layer for explaining a method of manufacturing a FET according to another embodiment of the present invention, illustrating a case where a source electrode or a drain electrode overlaps with a gate electrode.

This will be described in detail for each process.

First, a lower semiconductor layer, which is the first semiconductor layer 200, is formed on a semiconductor substrate (not shown). Here, the first semiconductor layer 200 may be a semiconductor layer having a relatively large energy band gap, for example, a semiconductor layer having an energy band gap of 1.3 eV or more.

After forming the first semiconductor layer 200, an intermediate semiconductor layer, which is the second semiconductor layer 202, is formed thereon. Here, the second semiconductor layer 202 may be a semiconductor layer having a relatively small energy band gap, for example, a semiconductor layer having an energy band gap of 0.7 eV or less.

Thereafter, an upper semiconductor layer, which is the third semiconductor layer 204, is formed on the second semiconductor layer 202. The third semiconductor layer 204 may be a semiconductor layer having a relatively large energy band gap, for example, a semiconductor layer having an energy band gap of 1.3 eV or more.

In this case, the third semiconductor layer 200 may be doped with an n-type according to an embodiment of the present invention, thereby lowering the threshold voltage.

Various techniques are known in adjusting the energy bandgap of the first semiconductor layer 200, the second semiconductor layer 202, and the third semiconductor layer 204, as described above.

By forming the first semiconductor layer 200, the second semiconductor layer 202, and the third semiconductor layer 204 as described above, a transistor having a channel having an electron well structure can be manufactured.

Thereafter, the gate electrode 208 is formed on the semiconductor substrate on which the third semiconductor layer 204 is formed. The gate electrode 208 may be formed by a deposition process, an etching process, a patterning process, and the like, and a process of forming the gate electrode 208 may be easily understood by those skilled in the art. In this case, specific process steps will be omitted.

In addition, in forming the gate electrode 208, a process of forming the gate insulating layer 206 may be further performed.

After the gate electrode 208 is formed, an etching process may be performed to form the spacer 210 on both sidewalls of the gate electrode 208.

Thereafter, a source / drain ion implantation process using a dopant may be performed on the semiconductor substrate on which the gate electrode 208 and the spacer 210 are formed to form the source / drain electrode 212. Here, the source / drain electrode 212 according to another embodiment of the present invention may be formed to overlap the gate electrode 208. That is, as shown in FIG. 4, it can be seen that the source / drain electrode 212 partially overlaps the lower region of the gate electrode 208.

At this time, the process of forming the source / drain electrode 212 and the process of forming the gate electrode 208 may be reversed.

FIG. 5 is a graph illustrating a simulation result of n-type doping of a semiconductor layer having a large upper energy bandgap of an electron well structure according to another exemplary embodiment of the present invention.

As shown in Figure 5, it can be seen that the threshold voltage is reduced from the doping concentration 1017 cm-3 or more.

FIG. 6 is a three-dimensional cross-sectional view of a semiconductor layer in which a 2-DEG electron channel is formed by changing the semiconductor layer of FIG. 1 into a three-dimensional structure as another embodiment of the present invention.

As shown in FIG. 6, the structure in which the electron channel is surrounded in three dimensions by the gate electrode can be confirmed.

According to the embodiment of the present invention as described above, the semiconductor layer having a large energy bandgap at the bottom of the channel layer of the FET is doped with p-type, or the semiconductor layer having a large energy bandgap at the top is n-type doped. It is characterized by one. As a result, the conventional high mobility field effect transistor has a disadvantage that the threshold voltage is less than 0V, and thus cannot be applied to a circuit design requiring a larger threshold voltage such as a logic circuit. While maintaining the advantages of the well channel, the threshold voltage can be raised or lowered above 0V.

The present invention makes it easier to apply logic technology of compound semiconductors that are expected to be applied at 10 nm technology nodes.

Claims

Forming a lower semiconductor layer having a first energy band gap, and doping the lower semiconductor layer to a p-type;

Forming an intermediate semiconductor layer on the lower semiconductor layer, the intermediate semiconductor layer having a second energy bandgap smaller than the first energy bandgap;

Forming an upper semiconductor layer having the first energy bandgap on the intermediate semiconductor layer;

Method of manufacturing a field effect transistor.
The method of claim 1,

The method of manufacturing the field effect transistor,

A method for manufacturing a field effect transistor, characterized in that the threshold voltage rises.
The method of claim 1,

The method of manufacturing the field effect transistor,

Forming a gate electrode after forming the upper semiconductor layer;

The method may further include forming a source electrode and a drain electrode on the semiconductor substrate on which the gate electrode is formed.

The source electrode and the drain electrode are spaced apart from each other by the width of the gate electrode.

Method for manufacturing a field effect transistor.
The method of claim 3, wherein

The field effect transistor has a structure in which an electron channel is surrounded in three dimensions by the gate electrode.

Method for manufacturing a field effect transistor.
Forming a lower semiconductor layer having a first energy bandgap;

Forming an intermediate semiconductor layer on the lower semiconductor layer, the intermediate semiconductor layer having a second energy bandgap smaller than the first energy bandgap;

Forming an upper semiconductor layer having the first energy bandgap on the intermediate semiconductor layer, and doping the upper semiconductor layer to n-type.

Method for manufacturing a field effect transistor.
The method of claim 5, wherein

The method of manufacturing the field effect transistor,

The threshold voltage falls, The manufacturing method of the field effect transistor characterized by the above-mentioned.
The method of claim 5, wherein

The method of manufacturing the field effect transistor,

Forming a gate electrode after forming the upper semiconductor layer;

The method may further include forming a source electrode and a drain electrode on the semiconductor substrate on which the gate electrode is formed.

The source electrode and the drain electrode have a structure overlapping with the gate electrode.

Method for manufacturing a field effect transistor.
The method of claim 7, wherein

The field effect transistor has a structure in which an electron channel is surrounded in three dimensions by the gate electrode.

Method for manufacturing a field effect transistor.