WO2016043271A1 - Processor and processor system - Google Patents

Processor and processor system Download PDF

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Publication number
WO2016043271A1
WO2016043271A1 PCT/JP2015/076486 JP2015076486W WO2016043271A1 WO 2016043271 A1 WO2016043271 A1 WO 2016043271A1 JP 2015076486 W JP2015076486 W JP 2015076486W WO 2016043271 A1 WO2016043271 A1 WO 2016043271A1
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Prior art keywords
instruction
error correction
data
storage unit
valid
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PCT/JP2015/076486
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French (fr)
Japanese (ja)
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一隆 池上
武田　進
紘希 野口
藤田　忍
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株式会社 東芝
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead

Definitions

  • the present invention relates to a processor and a processor system that use a memory to speed up memory access.
  • SRAM Static RAM
  • MRAM Magneticoresistive RAM
  • SRAM static random access memory
  • MRAM Magnetic RAM
  • MRAM Magnetic RAM
  • Data errors can be corrected by providing an error correction circuit, but it is known that the delay due to error correction increases rapidly as the number of correction bits increases. Therefore, when a multi-bit error occurs, the delay due to error correction reduces the processing capability of the processor.
  • the present invention has been made to solve the above-described problems, and provides a processor and a processor system capable of suppressing a decrease in processing capability even if there is an error in data read from a memory. is there.
  • an arithmetic unit that performs an operation using the data before error correction, A register for storing a calculation value calculated by the calculator; Based on the result of the error correction process, it is determined whether or not the calculation is valid. If the calculation is not valid, recalculation is performed by the computing unit using data after error correction by the error correction process. And a calculation control unit that stores a calculation value obtained by the calculation in the register when the calculation is valid.
  • FIG. 1 is a block diagram showing a schematic configuration of a processor system according to a first embodiment.
  • FIG. 2A shows a case where there is no error in the cache data read from the cache data storage unit
  • FIG. 2B shows a case where there is an error.
  • the block diagram which shows schematic structure of the processor system by 2nd Embodiment.
  • the block diagram which shows an example of an internal structure of an extended cache controller.
  • the block diagram which shows the internal structure of an extended cache controller.
  • FIG. 1 is a block diagram showing a schematic configuration of a processor system 1 according to the first embodiment.
  • the processor system 1 in FIG. 1 includes a processor core (arithmetic control unit, arithmetic unit, register) 2, a cache memory 3, and an error correction circuit (ECC) 4.
  • ECC error correction circuit
  • FIG. 1 only the L2 cache 3 is illustrated as the cache memory 3 in FIG. 1, but a higher-order cache memory higher than tertiary (L3) may be provided.
  • L3 tertiary
  • the L1 cache is omitted, but the L1 cache is built in the processor core 2.
  • the L2 cache 3 in FIG. 1 has a tag storage unit 5, a cache data storage unit 6, and a cache controller 7.
  • the tag storage unit 5 stores tag data that is address information of cache data.
  • the cache data storage unit 6 stores cache data corresponding to tag data.
  • the cache controller 7 performs a hit / miss determination as to whether or not the address requested to be accessed from the processor core 2 matches the tag data stored in the tag storage unit 5.
  • the cache controller 7 performs control to read data corresponding to the address requested to be accessed from the processor core 2 from the cache data storage unit 6 or to write data to the cache data storage unit 6.
  • the error correction circuit 4 performs error correction processing on the cache data stored in the cache data storage unit 6 and transmits an error signal indicating the presence / absence of an error and the data after error correction to the processor core 2.
  • FIG. 2 is a diagram for explaining the processing operation of the processor system 1 of FIG. 1, and the arrow line indicates the time axis.
  • FIG. 2A shows a case where there is no error in the cache data read from the cache data storage unit 6, and
  • FIG. 2B shows a case where there is an error.
  • FIG. 2A shows an example in which cache data is read from the cache data storage unit 6 between times t1 and t2.
  • the processor core 2 When the data is read from the cache data storage unit 6 (time t1 to t2), the processor core 2 according to the present embodiment starts the calculation without waiting for the result of the error correction processing (time t2 to t5). Such an operation is called a speculative operation.
  • the error correction circuit 4 performs error correction processing in parallel with the operation of the processor core 2 (time t3 to t4).
  • the error correction circuit 4 determines that there is no error, and sets the error signal to low, for example. Thereby, the processor core 2 commits the operation value obtained by performing the speculative operation (time t6 to t7). Commit is a process of writing a calculation value obtained by performing a speculative calculation into a register by regarding it as valid.
  • the error correction circuit 4 performs ECC calculation to set the error signal to, for example, high and perform error correction (time t3 to t4).
  • the processor core 2 receives the error signal and the error-corrected data from the error correction circuit 4, it performs recalculation using this data (time t6 to t7), and commits the recalculated calculation value (time t7). To t8).
  • the processor core 2 determines whether or not the calculation is valid based on the result of the error correction process. If the calculation is not valid, the processor core 2 uses the data after error correction by the error correction process. The recalculation is executed in step S1, and if the calculation is valid, the calculation value obtained by the calculation is stored in the register. That is, in the processor system 1 according to the first embodiment, speculation is performed using this cache data in parallel with performing error correction processing on the cache data read in response to a read request from the processor core 2. If it is found that there is no error, the operation value by the speculative operation is regarded as valid and committed.
  • the calculation time can be greatly reduced and the processing performance of the processor can be improved as compared with the case where the calculation is started after the result of the error correction processing is obtained. Note that when an error is detected by the error correction circuit 4 and error correction is performed, recalculation is performed using the data after error correction, so there is no possibility that the reliability will be lowered.
  • the error correction circuit 4 is provided in the cache memory 3.
  • FIG. 3 is a block diagram showing a schematic configuration of the processor system 1 according to the second embodiment.
  • the same reference numerals are given to components common to FIG. 1, and different points will be mainly described below.
  • the processor system 1 of FIG. 3 has an extended cache controller 7a with a built-in error correction circuit 4.
  • the extended cache controller 7a performs hit / miss determination and access control of the cache memory 3 as well as the cache controller 7 of FIG. 1, and performs error correction processing.
  • FIG. 4 is a block diagram showing an example of the internal configuration of the extended cache controller 7a.
  • the extended cache controller 7 a in FIG. 4 has a cache logic 8 and an error correction circuit 4.
  • the cache logic 8 performs hit / miss determination using the tag data, and transmits the hit cache data to the processor core 2 and also to the error correction circuit 4.
  • the error correction circuit 4 performs error correction processing on the cache data, determines the logic of the error signal, that is, the presence or absence of an error, and transmits the corrected data to the processor core 2.
  • the error correction circuit 4 in FIG. 4 performs the error correction process only on the cache data read from the cache data storage unit 6, but the error correction process may also be performed on the tag data read from the tag storage unit 5.
  • the internal configuration of the extended cache controller 7b in this case is represented by a block diagram as shown in FIG.
  • the extended cache controller 7 b of FIG. 5 includes an error correction circuit (first error correction unit) 4 a for tag data in addition to the error correction circuit (second error correction unit) 4. .
  • the tag data error correction circuit 4 a is provided between the tag storage unit 5 and the cache logic 8.
  • the tag data read from the tag storage unit 5 is subjected to error correction processing by the error correction circuit 4a.
  • the error-corrected tag data is input to the cache logic 8. Therefore, the cache logic 8 can improve the accuracy of the hit / miss determination by performing the hit / miss determination using the error-corrected tag data.
  • the extended cache controller 7b shown in FIG. 5 performs speculative computation for the cache data read from the cache data storage unit 6 while performing the error correction process. After error correction is performed, hit / miss determination is performed.
  • the reason for not performing speculative processing for tag data is that an error in tag data means an error in the address of data to be accessed, and speculative processing is much more difficult than data errors. This is because it becomes complicated.
  • Whether or not to perform error correction processing for tag data may be determined in consideration of the following.
  • the power consumption can be reduced, but the reliability of the data is lowered and errors are likely to occur.
  • the power supply voltage level is set to a level that can ensure the reliability of the tag data, and the configuration of the processor system 1 without error correction of the tag data as shown in FIG. Just choose.
  • the power supply voltage level is lowered and the configuration of the processor system 1 that performs error correction of tag data as shown in FIG. 5 may be selected.
  • the error correction circuit 4 is provided in the cache memory 3, it is not necessary to provide the error correction circuit 4 in addition to the cache memory 3 and the processor core 2.
  • the form can be simplified.
  • an error correction circuit 4 is provided inside the processor core 2, contrary to the second embodiment.
  • FIG. 6 is a block diagram showing a schematic configuration of the processor system 1 according to the third embodiment.
  • the processor system 1 shown in FIG. 6 has a processor core 2 with a built-in error correction circuit 4.
  • the clock signal of the processor core 2 is often faster than the clock signals of other circuit blocks. Therefore, when the error correction circuit 4 is provided inside the processor core 2, there is a high possibility that error correction processing can be performed at a higher speed than when the error correction circuit 4 is provided outside the processor core 2.
  • the bus between the processor core 2 and the cache memory 3 is occupied when the corrected data is written back to the cache memory 3.
  • the occupancy rate of the bus also increases, so that the amount of data transmitted from the cache memory 3 to the processor core 2 via the bus may be reduced.
  • the error correction circuit 4 since the error correction circuit 4 is provided in the processor core 2, the error signal output from the error correction circuit 4 and the corrected data can be acquired quickly. Therefore, it is possible to quickly determine whether or not the speculative calculation is valid, it is also possible to quickly determine that the speculative calculation is invalid, and to advance the timing of the recalculation.
  • Which of the processor systems 1 according to the first to third embodiments described above is adopted is determined in consideration of the error occurrence rate of the cache memory 3, the bus occupation rate by the processor core 2, the bus width, and the like. Is desirable.
  • the fourth embodiment described below embodies the internal configuration of the processor core 2 in the first to third embodiments described above.
  • FIG. 7 is a block diagram showing an internal configuration of the processor core 2 of the processor system 1 according to the fourth embodiment. 7 includes an L1 data cache 11, an L1 data cache controller 12, an instruction cache 13, an instruction cache controller 14, an instruction issuing unit 15, an instruction queue (instruction storage unit) 16, an extended reorder A buffer (Reorder Buffer) 17, a register 18, a reservation station (Reservation Stations) 19, and an arithmetic unit 20 are included.
  • the extended reorder buffer 17 and the reservation station 19 correspond to the calculation control unit, the extended reorder buffer 17 corresponds to the first storage unit, and the reservation station 19 corresponds to the second storage unit.
  • the L1 data cache 11 stores data requested by the processor core 2 for access. Although omitted in FIG. 7, data that cannot be stored in the L1 data cache 11 is stored in the higher-order cache memory 3 or the main memory after the L2 cache 3.
  • the L1 data cache controller 12 determines the hit / miss of whether or not the data requested by the processor core 2 is stored in the L1 data cache 11, the access control for the L1 data cache 11, and the data in the L1 data cache 11. Is not stored, control to access the L2 cache 3 is performed.
  • the L1 data cache controller 12 transmits this data to the extended reorder buffer 17.
  • the extended reorder buffer 17 stores flag information W (wait) indicating that it is waiting for error correction. Whether there is an error in the data from the L2 cache 3 is determined by the logic of the error signal from the error correction circuit 4 of the L2 cache 3.
  • the L1 data cache controller 12 determines that there is no error in the data from the L2 cache 3 based on the error signal, the L1 data cache controller 12 stores the data in the L1 data cache 11. As a result, data with no error can be stored in the L1 data cache 11.
  • the instruction cache controller 14 When the instruction cache controller 14 receives an instruction from the L2 cache 3, the instruction cache controller 14 stores the instruction in the instruction queue 16 via the instruction issue unit 15. At this point, since it is not known whether or not there is an error in this instruction, flag information W (wait) indicating that it is waiting for error correction is stored in the instruction queue 16. Thereafter, when it is found from the error signal from the L2 cache 3 that the instruction has no error, the flag information is changed to V (valid). On the other hand, if the error signal indicates that there is an error in the instruction, the error corrected by the error correction circuit 4 of the L2 cache 3 is transmitted to the instruction queue 16 and the flag information is changed to V (valid).
  • the instruction queue 16 has a plurality of entries, and each entry stores an instruction issued by the instruction issuing unit 15 and flag information 16a of the corresponding instruction.
  • the flag information 16a includes W (wait) information indicating that the corresponding instruction is waiting for error correction, and V (valid) information indicating that the corresponding instruction is valid.
  • Instructions issued from the instruction queue 16 are sequentially sent to the reservation station 19.
  • the reservation station 19 receives an instruction from the instruction queue 16, the reservation station 19 acquires an operand corresponding to the instruction from the register 18.
  • the reservation station 19 can store a plurality of entries by associating instructions and operands as one entry. Then, the reservation station 19 gives priority to the entry having the instructions and operands, transmits the information of the entry to the computing unit 20, and the computation in the computing unit 20 is executed.
  • the calculated value calculated by the calculator 20 is stored in the extended reorder buffer 17.
  • reservation station 19 in FIG. 7 associates an instruction with two operands
  • the number of operands associated with one entry is not particularly limited.
  • the instruction issued from the instruction queue 16 is also sent to the extended reorder buffer 17.
  • the instruction sent to the extended reorder buffer 17 is deleted from the instruction queue 16. If there is an error in the instruction, the extended reorder buffer 17 stores the error-corrected instruction and deletes (flushes) subsequent entries. The subsequent entry is deleted because there is no guarantee that the operation result after the wrong instruction is correct.
  • FIG. 8 is a diagram showing an example of the data configuration of the extended reorder buffer 17.
  • the extended reorder buffer 17 includes an entry number (Entry), busy information (Busy), an instruction (Instruction), instruction flag information, operand 1, operand 1 flag information, and operand. 2, operand 2 flag information, storage destination (Destination), storage destination flag information, operation value (Value), and state (State) of each entry are associated with each other as a single entry. The entry is memorized.
  • Each information stored in the extended reorder buffer 17 is transmitted from the L2 cache 3, the data cache controller 7 or the instruction queue 16. Since the instruction, operand 1, operand 2 and storage destination information are stored in the extended reorder buffer 17, an error correction result has not yet been obtained, so the flag information is set to W (wait).
  • the extended reorder buffer 17 transmits the instruction, operand 1 and operand 2 information as a set to the reservation station 19.
  • the extended reorder buffer 17 stores the calculation value calculated by the calculator 20 using these pieces of information.
  • the error signal output from the error correction circuit 4 is input to the extended reorder buffer 17, if the error signal logic indicates that there is no error in the corresponding information, the flag information of V (valid) is set. Is done. If the logic of the error signal indicates that there is an error in the corresponding information, all information after the corresponding entry is deleted (flashed). For example, after the instruction in the extended reorder buffer 17 is flushed, the instruction issuing unit 15 may continue to perform the operation by fetching a new instruction, or the entry in the extended reorder buffer 17 may be stored in the instruction queue 16. The calculation may be continued by writing back to.
  • the busy information of the entry where the operation is being executed is set to yes, and set to no when the operation is completed.
  • the state of each entry is Commit.
  • the operation value of the entry is stored in the register 18.
  • the error correction process is performed in parallel on the cache data read from the higher-level cache memory 3 such as the L2 cache 3. Then, speculative calculation is performed using this cache data. During speculative computation, each flag information corresponding to the instruction, operand, and storage destination is set to wait. The calculated value obtained by performing speculative calculation in this state is stored in the extended reorder buffer 17, and the state of the entry corresponding to the calculated value is also set to W (wait).
  • the extended reorder buffer 17 sets the state of the corresponding entry to Commit. Thus, the operation value obtained by speculative operation is written into the register 18.
  • the processor core 2 since the processor core 2 according to the fourth embodiment provides the instruction queue 16 with the flag information 16a corresponding to each instruction, it can grasp whether or not there is an error in the instruction of each entry in the instruction queue 16. . When there is an error in the instruction, the instruction queue 16 deletes all entries after the instruction. Therefore, even when the instruction is speculatively executed, the calculation result of the execution of the erroneous instruction is written in the register 18. There is no fear.
  • FIG. 9 is a block diagram showing an internal configuration of the processor core 2 of the processor system 1 according to the fifth embodiment.
  • the processor core 2 of FIG. 9 is common to FIG. 7 except that the data structure of the reservation station 19 is different from that of FIG.
  • the reservation station 19 of FIG. 9 has flag information 19a corresponding to each information of instruction, operand 1 and operand 2.
  • the flag information 19a is set based on the flag information stored in the instruction queue 16 and the extended reorder buffer 17.
  • the calculator 20 preferentially selects an instruction having V (valid) flag information from each entry of the reservation station 19 and executes the calculation. Thereby, the computing unit 20 can perform computation using only correct data, can increase the probability that the computed value is valid, and can improve the processing capability of the processor.
  • the computing unit 20 can determine the computation order with reference to the flag information 19a, and the computation performed by the computing unit 20 can be performed. The probability that the value is valid can be improved.
  • FIG. 10 is a block diagram showing an internal configuration of the processor core 2 of the processor system 1 according to the sixth embodiment.
  • the processor core 2 in FIG. 9 has a backup register 21 and the data configuration of the register 18 is different from that in FIG. The rest is the same as FIG.
  • the 10 has flag information 18a for each entry.
  • the flag information 18 a is set by an error signal sent from the error correction circuit 4 or the extended reorder buffer 17.
  • the backup register 21 When the backup register 21 stores data in each entry of the register 18, the backup register 21 stores the data stored so far in this entry. The reason why the backup register 21 is provided is to allow the data newly stored in the register 18 to be restored to the original data when there is an error.
  • the backup register 21 also stores flag information 21a indicating whether the backed up data is before or after error correction, that is, whether the backed up data is valid.
  • the data stored in the register 18 is transmitted from the extended reorder buffer 17 to the register 18, but in FIG. 10, the data can be directly stored in the register 18 from the L2 cache 3. Thereby, the data transfer to the register 18 can be speeded up, and the data transfer to the arithmetic unit 20 can be speeded up.
  • FIG. 11 is a block diagram showing an internal configuration of the processor core 2 of the processor system 1 according to the seventh embodiment.
  • the processor core 2 in FIG. 11 is provided with flag information 19a in the reservation station 19 in FIG. 10 in the same manner as in FIG. 9, and the rest is common to the processor core 2 in FIG.
  • the calculator 20 can determine the calculation order with reference to the flag information 19a, and the calculation value calculated by the calculator 20 is valid. And the processing performance of the processor can be improved.
  • FIG. 12 is a block diagram showing an internal configuration of the processor core 2 of the processor system 1 according to the eighth embodiment.
  • the processor core 2 in FIG. 12 is different from that in FIG. 7 in the data configuration of the register 18. The rest is the same as FIG.
  • the register 18 shown in FIG. 12 includes a register field (first field) 18b, a backup field 18c (second field), and flag information 18a (third field) of data in the register field 18b for each entry. And flag information 18d (fourth field) of data in the backup field 18c.
  • the register field 18b stores original data to be stored in the register 18. When the data in the corresponding register field 18b is updated, the data stored in the register field 18b is stored in the backup field 18c, and the data is stored before or after error correction. Flag information 18d indicating whether or not it is valid is stored.
  • the flag information in the register 18 is set by an error signal sent from the error correction circuit 4 or the extended reorder buffer 17.
  • the backup field 18c is used for the same purpose as the backup register 21 of FIG. 10, but since the backup field 18c is provided for each entry of the register 18, even if there are many errors, the backup field 18c. There is little risk of shortage. Therefore, it is possible to perform speculative calculation by effectively using the backup field 18c.
  • FIG. 13 is a block diagram showing an internal configuration of the processor core 2 of the processor system 1 according to the seventh embodiment.
  • the processor core 2 in FIG. 13 is provided with flag information 19a in the reservation station 19 in FIG. 12 in the same manner as in FIG. 9, and the rest is common to the processor core 2 in FIG.
  • the arithmetic unit 20 can determine the arithmetic order with reference to the flag information 19a, and the arithmetic value calculated by the arithmetic unit 20 is valid. And the processing performance of the processor can be improved.

Abstract

　In order to minimize reductions in processing performance even when errors occur in data that has been read from memory, this processor is provided with: an arithmetic unit that carries out error correction processing (time t3-t4) on cache data that has been read from cache memory in parallel with carrying out computations (time t2-t5) using cache data that has not been error corrected; a register that stores computed values computed by the arithmetic unit; and an arithmetic control unit that determines whether computations are valid on the basis of the results of error correction processing, and, if a computation is not valid (I), makes the arithmetic unit carry out the computation again using data that has been error corrected according to error correction processing, and, if a computation is valid (V), stores the computed value in the register.

Description

プロセッサおよびプロセッサシステムProcessor and processor system
　本発明は、メモリを用いてメモリアクセスの高速化を図るプロセッサおよびプロセッサシステムに関する。 The present invention relates to a processor and a processor system that use a memory to speed up memory access.
　プロセッサによるメモリアクセスの高速化を図る方策として、キャッシュメモリを大容量化することが検討されている。従来のキャッシュメモリは、ＳＲＡＭ（Static RAM）を用いることが多かったが、ＳＲＡＭは消費電力が大きく、メモリセルの小型化も困難であるという問題があり、ＳＲＡＭの代わりにＭＲＡＭを用いたキャッシュメモリが注目されている。 Increasing the capacity of the cache memory is being studied as a measure to speed up memory access by the processor. Conventional cache memory often uses SRAM (Static RAM), but SRAM has a problem that power consumption is large and miniaturization of the memory cell is difficult, and cache memory using MRAM instead of SRAM. Is attracting attention.
　ＭＲＡＭ（Magnetoresistive RAM）は不揮発性メモリであり、ＳＲＡＭと比べて待機時のリーク電力ははるかに少ない。ところが、ＭＲＡＭは、ＳＲＡＭよりもデータの誤り率が高いという問題がある。データの誤りは、誤り訂正回路を設けることで、誤り訂正を行うことができるが、誤り訂正による遅延は、訂正ビット数が増えると急激に増大することが知られている。したがって、多ビットの誤りが生じた場合には、誤り訂正による遅延がプロセッサの処理能力を低下させてしまう。 MRAM (Magnetoresistive RAM) is a non-volatile memory and has much less leakage power during standby than SRAM. However, MRAM has a problem that the data error rate is higher than that of SRAM. Data errors can be corrected by providing an error correction circuit, but it is known that the delay due to error correction increases rapidly as the number of correction bits increases. Therefore, when a multi-bit error occurs, the delay due to error correction reduces the processing capability of the processor.
　本発明は、上述した課題を解決するためになされたものであり、メモリから読み出されたデータ中に誤りがあっても、処理能力の低下を抑制可能なプロセッサおよびプロセッサシステムを提供するものである。 The present invention has been made to solve the above-described problems, and provides a processor and a processor system capable of suppressing a decrease in processing capability even if there is an error in data read from a memory. is there.
　上記の課題を解決するために、本実施形態では、
　メモリから読み出されたデータの誤り訂正処理に並行して、誤り訂正前のデータを用いて演算を実行する演算器と、
　前記演算器にて演算された演算値を記憶するレジスタと、
　前記誤り訂正処理の結果に基づいて前記演算が有効か否かを判断するとともに、前記演算が有効でない場合には、前記誤り訂正処理による誤り訂正後のデータを用いて前記演算器にて再演算を実行させ、前記演算が有効な場合には、前記演算による演算値を前記レジスタに記憶する演算制御部と、を備えるプロセッサが提供される。 In order to solve the above problem, in this embodiment,
In parallel with the error correction processing of the data read from the memory, an arithmetic unit that performs an operation using the data before error correction,
A register for storing a calculation value calculated by the calculator;
Based on the result of the error correction process, it is determined whether or not the calculation is valid. If the calculation is not valid, recalculation is performed by the computing unit using data after error correction by the error correction process. And a calculation control unit that stores a calculation value obtained by the calculation in the register when the calculation is valid.
第１の実施形態によるプロセッサシステムの概略構成を示すブロック図。1 is a block diagram showing a schematic configuration of a processor system according to a first embodiment. （ａ）はキャッシュデータ記憶部から読み出したキャッシュデータに誤りがなかった場合を示し、図２（ｂ）は誤りがあった場合を示す図。FIG. 2A shows a case where there is no error in the cache data read from the cache data storage unit, and FIG. 2B shows a case where there is an error. 第２の実施形態によるプロセッサシステムの概略構成を示すブロック図。The block diagram which shows schematic structure of the processor system by 2nd Embodiment. 拡張キャッシュコントローラの内部構成の一例を示すブロック図。The block diagram which shows an example of an internal structure of an extended cache controller. 拡張キャッシュコントローラの内部構成を示すブロック図。The block diagram which shows the internal structure of an extended cache controller. 第３の実施形態によるプロセッサシステムの概略構成を示すブロック図。The block diagram which shows schematic structure of the processor system by 3rd Embodiment. 第４の実施形態によるプロセッサシステムのプロセッサコアの内部構成を示すブロック図。The block diagram which shows the internal structure of the processor core of the processor system by 4th Embodiment. 拡張リオーダ・バッファのデータ構成の一例を示す図。The figure which shows an example of a data structure of an extended reorder buffer. 第５の実施形態によるプロセッサシステムのプロセッサコアの内部構成を示すブロック図。The block diagram which shows the internal structure of the processor core of the processor system by 5th Embodiment. 第６の実施形態によるプロセッサシステムのプロセッサコアの内部構成を示すブロック図。The block diagram which shows the internal structure of the processor core of the processor system by 6th Embodiment. 第７の実施形態によるプロセッサシステムのプロセッサコアの内部構成を示すブロック図。The block diagram which shows the internal structure of the processor core of the processor system by 7th Embodiment. 第８の実施形態によるプロセッサシステムのプロセッサコアの内部構成を示すブロック図。The block diagram which shows the internal structure of the processor core of the processor system by 8th Embodiment. 第９の実施形態によるプロセッサシステムのプロセッサコアの内部構成を示すブロック図。The block diagram which shows the internal structure of the processor core of the processor system by 9th Embodiment.
　以下、図面を参照して本発明の実施形態を説明する。以下の実施形態では、プロセッサおよびプロセッサシステム内の特徴的な構成および動作を中心に説明するが、プロセッサおよびプロセッサシステムには以下の説明で省略した構成および動作が存在しうる。ただし、これらの省略した構成および動作も本実施形態の範囲に含まれるものである。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, characteristic configurations and operations in the processor and the processor system will be mainly described. However, configurations and operations omitted in the following description may exist in the processor and the processor system. However, these omitted configurations and operations are also included in the scope of the present embodiment.
　（第１の実施形態）
　図１は第１の実施形態によるプロセッサシステム１の概略構成を示すブロック図である。図１のプロセッサシステム１は、プロセッサコア（演算制御部、演算器、レジスタ）２と、キャッシュメモリ３と、誤り訂正回路（ＥＣＣ：Error Correction Circuit）４とを備えている。キャッシュメモリ３は、図１では、キャッシュメモリ３としてＬ２キャッシュ３のみを図示しているが、３次（Ｌ３）以上の高次のキャッシュメモリを設けてもよい。図１では、Ｌ１キャッシュを省略しているが、Ｌ１キャッシュはプロセッサコア２に内蔵されている。 (First embodiment)
FIG. 1 is a block diagram showing a schematic configuration of a processor system 1 according to the first embodiment. The processor system 1 in FIG. 1 includes a processor core (arithmetic control unit, arithmetic unit, register) 2, a cache memory 3, and an error correction circuit (ECC) 4. In FIG. 1, only the L2 cache 3 is illustrated as the cache memory 3 in FIG. 1, but a higher-order cache memory higher than tertiary (L3) may be provided. In FIG. 1, the L1 cache is omitted, but the L1 cache is built in the processor core 2.
　図１のＬ２キャッシュ３は、タグ記憶部５と、キャッシュデータ記憶部６と、キャッシュコントローラ７とを有する。タグ記憶部５は、キャッシュデータのアドレス情報であるタグデータを記憶する。キャッシュデータ記憶部６は、タグデータに対応するキャッシュデータを記憶する。キャッシュコントローラ７は、プロセッサコア２からアクセス要求のあったアドレスがタグ記憶部５に記憶されたタグデータに一致するか否かのヒット／ミス判定を行う。また、キャッシュコントローラ７は、プロセッサコア２からアクセス要求のあったアドレスに対応するデータをキャッシュデータ記憶部６から読み出したり、キャッシュデータ記憶部６に書き込む制御を行う。 The L2 cache 3 in FIG. 1 has a tag storage unit 5, a cache data storage unit 6, and a cache controller 7. The tag storage unit 5 stores tag data that is address information of cache data. The cache data storage unit 6 stores cache data corresponding to tag data. The cache controller 7 performs a hit / miss determination as to whether or not the address requested to be accessed from the processor core 2 matches the tag data stored in the tag storage unit 5. In addition, the cache controller 7 performs control to read data corresponding to the address requested to be accessed from the processor core 2 from the cache data storage unit 6 or to write data to the cache data storage unit 6.
　誤り訂正回路４は、キャッシュデータ記憶部６に記憶されたキャッシュデータに対して誤り訂正処理を行い、エラーの有無を示すエラー信号と、誤り訂正後のデータとをプロセッサコア２に伝送する。 The error correction circuit 4 performs error correction processing on the cache data stored in the cache data storage unit 6 and transmits an error signal indicating the presence / absence of an error and the data after error correction to the processor core 2.
　図２は図１のプロセッサシステム１の処理動作を説明する図であり、矢印線は時間軸を示している。図２（ａ）はキャッシュデータ記憶部６から読み出したキャッシュデータに誤りがなかった場合を示し、図２（ｂ）は誤りがあった場合を示している。 FIG. 2 is a diagram for explaining the processing operation of the processor system 1 of FIG. 1, and the arrow line indicates the time axis. FIG. 2A shows a case where there is no error in the cache data read from the cache data storage unit 6, and FIG. 2B shows a case where there is an error.
　図２（ａ）は、時刻ｔ１～ｔ２の間に、キャッシュデータ記憶部６からキャッシュデータが読み出される例を示している。 FIG. 2A shows an example in which cache data is read from the cache data storage unit 6 between times t1 and t2.
　本実施形態によるプロセッサコア２は、キャッシュデータ記憶部６からデータが読み出されると（時刻ｔ１～ｔ２）、誤り訂正処理の結果を待たずに演算を開始する（時刻ｔ２～ｔ５）。このような演算を投機的な演算と呼ぶ。誤り訂正回路４は、プロセッサコア２が演算を行うのに並行して、誤り訂正処理を行う（時刻ｔ３～ｔ４）。 When the data is read from the cache data storage unit 6 (time t1 to t2), the processor core 2 according to the present embodiment starts the calculation without waiting for the result of the error correction processing (time t2 to t5). Such an operation is called a speculative operation. The error correction circuit 4 performs error correction processing in parallel with the operation of the processor core 2 (time t3 to t4).
　図２（ａ）の場合、誤り訂正回路４は、誤りがないと判断し、例えばエラー信号をロウにする。これにより、プロセッサコア２は、投機的な演算を行って得た演算値をコミットする（時刻ｔ６～ｔ７）。コミットとは、投機的な演算を行って得た演算値を有効とみなしてレジスタに書き込む処理である。 In the case of FIG. 2A, the error correction circuit 4 determines that there is no error, and sets the error signal to low, for example. Thereby, the processor core 2 commits the operation value obtained by performing the speculative operation (time t6 to t7). Commit is a process of writing a calculation value obtained by performing a speculative calculation into a register by regarding it as valid.
　図２（ｂ）の場合、誤り訂正回路４は、ＥＣＣ計算を行って、エラー信号を例えばハイにするとともに、誤り訂正を行う（時刻ｔ３～ｔ４）。プロセッサコア２は、誤り訂正回路４からのエラー信号と誤り訂正済のデータを受信すると、このデータを用いて再演算を行い（時刻ｔ６～ｔ７）、再演算した演算値をコミットする（時刻ｔ７～ｔ８）。 In the case of FIG. 2B, the error correction circuit 4 performs ECC calculation to set the error signal to, for example, high and perform error correction (time t3 to t4). When the processor core 2 receives the error signal and the error-corrected data from the error correction circuit 4, it performs recalculation using this data (time t6 to t7), and commits the recalculated calculation value (time t7). To t8).
　このように、プロセッサコア２は、誤り訂正処理の結果に基づいて演算が有効か否かを判断するとともに、演算が有効でない場合には、誤り訂正処理による誤り訂正後のデータを用いて演算器にて再演算を実行させ、演算が有効な場合には、演算による演算値をレジスタに記憶する。すなわち、第１の実施形態によるプロセッサシステム１では、プロセッサコア２からの読出し要求に応じて読み出されたキャッシュデータに対して誤り訂正処理を施すのに並行して、このキャッシュデータを用いて投機的な演算を行い、誤りがないことがわかると、投機的な演算による演算値を有効なものとみなしてコミットする。これにより、誤り訂正処理の結果が得られてから演算を開始するのに比べて、演算時間を大幅に削減でき、プロセッサの処理性能を向上できる。なお、誤り訂正回路４で誤りが検出されて、誤り訂正が行われた場合には、誤り訂正後のデータを用いて再演算を行うため、信頼性が低下するおそれはない。 As described above, the processor core 2 determines whether or not the calculation is valid based on the result of the error correction process. If the calculation is not valid, the processor core 2 uses the data after error correction by the error correction process. The recalculation is executed in step S1, and if the calculation is valid, the calculation value obtained by the calculation is stored in the register. That is, in the processor system 1 according to the first embodiment, speculation is performed using this cache data in parallel with performing error correction processing on the cache data read in response to a read request from the processor core 2. If it is found that there is no error, the operation value by the speculative operation is regarded as valid and committed. As a result, the calculation time can be greatly reduced and the processing performance of the processor can be improved as compared with the case where the calculation is started after the result of the error correction processing is obtained. Note that when an error is detected by the error correction circuit 4 and error correction is performed, recalculation is performed using the data after error correction, so there is no possibility that the reliability will be lowered.
　（第２の実施形態）
　以下に説明する第２の実施形態は、誤り訂正回路４をキャッシュメモリ３内に設けるものである。 (Second Embodiment)
In the second embodiment described below, the error correction circuit 4 is provided in the cache memory 3.
　図３は第２の実施形態によるプロセッサシステム１の概略構成を示すブロック図である。図３では、図１と共通する構成部分には同一符号を付しており、以下では相違点を中心に説明する。 FIG. 3 is a block diagram showing a schematic configuration of the processor system 1 according to the second embodiment. In FIG. 3, the same reference numerals are given to components common to FIG. 1, and different points will be mainly described below.
　図３のプロセッサシステム１は、誤り訂正回路４を内蔵した拡張キャッシュコントローラ７ａを有する。この拡張キャッシュコントローラ７ａは、図１のキャッシュコントローラ７と同様にヒット／ミス判定とキャッシュメモリ３のアクセス制御とを行うととともに、誤り訂正処理を行う。 The processor system 1 of FIG. 3 has an extended cache controller 7a with a built-in error correction circuit 4. The extended cache controller 7a performs hit / miss determination and access control of the cache memory 3 as well as the cache controller 7 of FIG. 1, and performs error correction processing.
　図４は拡張キャッシュコントローラ７ａの内部構成の一例を示すブロック図である。図４の拡張キャッシュコントローラ７ａは、キャッシュロジック８と誤り訂正回路４とを有する。 FIG. 4 is a block diagram showing an example of the internal configuration of the extended cache controller 7a. The extended cache controller 7 a in FIG. 4 has a cache logic 8 and an error correction circuit 4.
　図４のキャッシュロジック８は、図１のキャッシュコントローラ７と同様に動作する。また、図４の誤り訂正回路４は、図１の誤り訂正回路４と同様に動作する。キャッシュロジック８は、タグデータを用いてヒット／ミス判定を行い、ヒットしたキャッシュデータをプロセッサコア２に伝送するとともに、誤り訂正回路４にも伝送する。誤り訂正回路４は、キャッシュデータに対して誤り訂正処理を行い、エラー信号の論理すなわち誤りの有無を決定するとともに、訂正後のデータをプロセッサコア２に伝送する。 4 operates in the same manner as the cache controller 7 in FIG. 4 operates in the same manner as the error correction circuit 4 of FIG. The cache logic 8 performs hit / miss determination using the tag data, and transmits the hit cache data to the processor core 2 and also to the error correction circuit 4. The error correction circuit 4 performs error correction processing on the cache data, determines the logic of the error signal, that is, the presence or absence of an error, and transmits the corrected data to the processor core 2.
　図４の誤り訂正回路４は、キャッシュデータ記憶部６から読み出したキャッシュデータのみについて誤り訂正処理を行っていたが、タグ記憶部５から読み出したタグデータについても誤り訂正処理を行ってもよい。この場合の拡張キャッシュコントローラ７ｂの内部構成は図５のようなブロック図で表される。 The error correction circuit 4 in FIG. 4 performs the error correction process only on the cache data read from the cache data storage unit 6, but the error correction process may also be performed on the tag data read from the tag storage unit 5. The internal configuration of the extended cache controller 7b in this case is represented by a block diagram as shown in FIG.
　図５の拡張キャッシュコントローラ７ｂは、図４と比べて、誤り訂正回路（第２誤り訂正部）４の他に、タグデータ用の誤り訂正回路（第１誤り訂正部）４ａが追加されている。タグデータ用の誤り訂正回路４ａは、タグ記憶部５とキャッシュロジック８との間に設けられている。タグ記憶部５から読み出されたタグデータは、誤り訂正回路４ａで誤り訂正処理が施される。そして、誤り訂正されたタグデータがキャッシュロジック８に入力される。よって、キャッシュロジック８は、誤り訂正されたタグデータを用いてヒット／ミス判定を行うことにより、ヒット／ミス判定の精度を向上できる。 Compared to FIG. 4, the extended cache controller 7 b of FIG. 5 includes an error correction circuit (first error correction unit) 4 a for tag data in addition to the error correction circuit (second error correction unit) 4. . The tag data error correction circuit 4 a is provided between the tag storage unit 5 and the cache logic 8. The tag data read from the tag storage unit 5 is subjected to error correction processing by the error correction circuit 4a. Then, the error-corrected tag data is input to the cache logic 8. Therefore, the cache logic 8 can improve the accuracy of the hit / miss determination by performing the hit / miss determination using the error-corrected tag data.
　このように、図５の拡張キャッシュコントローラ７ｂは、キャッシュデータ記憶部６から読み出されたキャッシュデータについては、誤り訂正処理を行っている間に投機的な演算を行うが、タグデータについては、誤り訂正がなされた後にヒット／ミス判定を行う。このように、タグデータについて、投機的な処理を行わない理由は、タグデータの誤りは、アクセスすべきデータのアドレスの誤りを意味し、データの誤りに比べて、投機的な処理が非常に複雑になるためである。 As described above, the extended cache controller 7b shown in FIG. 5 performs speculative computation for the cache data read from the cache data storage unit 6 while performing the error correction process. After error correction is performed, hit / miss determination is performed. As described above, the reason for not performing speculative processing for tag data is that an error in tag data means an error in the address of data to be accessed, and speculative processing is much more difficult than data errors. This is because it becomes complicated.
　タグデータについても誤り訂正処理を行うか否かは、以下のことを考慮に入れて決めればよい。プロセッサシステム１を低電圧駆動すると、消費電力を低減できるが、データの信頼性は低下し、誤りが生じやすくなる。消費電力の低減を念頭に置かなくてよい場合は、タグデータの信頼性が確保できる程度の電源電圧レベルに設定して、図３のようなタグデータの誤り訂正なしのプロセッサシステム１の構成を選択すればよい。一方、消費電力を低減したい場合は、電源電圧レベルを下げるとともに、図５のようなタグデータの誤り訂正を行うプロセッサシステム１の構成を選択すればよい。 Whether or not to perform error correction processing for tag data may be determined in consideration of the following. When the processor system 1 is driven at a low voltage, the power consumption can be reduced, but the reliability of the data is lowered and errors are likely to occur. When it is not necessary to keep power consumption reduction in mind, the power supply voltage level is set to a level that can ensure the reliability of the tag data, and the configuration of the processor system 1 without error correction of the tag data as shown in FIG. Just choose. On the other hand, in order to reduce power consumption, the power supply voltage level is lowered and the configuration of the processor system 1 that performs error correction of tag data as shown in FIG. 5 may be selected.
　このように、第２の実施形態では、誤り訂正回路４をキャッシュメモリ３内に設けるため、キャッシュメモリ３とプロセッサコア２との他に誤り訂正回路４を設ける必要がなくなり、プロセッサシステム１の実装形態を簡略化できる。また、誤り訂正回路４をキャッシュメモリ３に内蔵することで、データキャッシュ記憶部、タグ記憶部５、キャッシュロジック８および誤り訂正回路４間のデータの送受を高速化できる。 As described above, in the second embodiment, since the error correction circuit 4 is provided in the cache memory 3, it is not necessary to provide the error correction circuit 4 in addition to the cache memory 3 and the processor core 2. The form can be simplified. In addition, by incorporating the error correction circuit 4 in the cache memory 3, it is possible to speed up data transmission / reception among the data cache storage unit, the tag storage unit 5, the cache logic 8, and the error correction circuit 4.
　（第３の実施形態）
　以下に説明する第３の実施形態は、第２の実施形態とは逆に、プロセッサコア２の内部に誤り訂正回路４を設けるものである。 (Third embodiment)
In the third embodiment described below, an error correction circuit 4 is provided inside the processor core 2, contrary to the second embodiment.
　図６は第３の実施形態によるプロセッサシステム１の概略構成を示すブロック図である。図６のプロセッサシステム１は、誤り訂正回路４を内蔵したプロセッサコア２を有する。近年のプロセッサコア２のクロック信号は、他の回路ブロックのクロック信号よりも高速であることが多い。よって、プロセッサコア２の内部に誤り訂正回路４を設けると、プロセッサコア２の外部に誤り訂正回路４を設けた場合と比べて、誤り訂正処理を高速に行える可能性が高い。 FIG. 6 is a block diagram showing a schematic configuration of the processor system 1 according to the third embodiment. The processor system 1 shown in FIG. 6 has a processor core 2 with a built-in error correction circuit 4. In recent years, the clock signal of the processor core 2 is often faster than the clock signals of other circuit blocks. Therefore, when the error correction circuit 4 is provided inside the processor core 2, there is a high possibility that error correction processing can be performed at a higher speed than when the error correction circuit 4 is provided outside the processor core 2.
　その一方で、誤り訂正回路４で誤りが検出されると、訂正済のデータをキャッシュメモリ３に書き戻す際に、プロセッサコア２とキャッシュメモリ３間のバスを占有してしまう。誤り率が高い場合には、バスの占有率も高くなるため、キャッシュメモリ３からプロセッサコア２にバスを介して伝送されるデータ量が減るおそれがある。 On the other hand, if an error is detected by the error correction circuit 4, the bus between the processor core 2 and the cache memory 3 is occupied when the corrected data is written back to the cache memory 3. When the error rate is high, the occupancy rate of the bus also increases, so that the amount of data transmitted from the cache memory 3 to the processor core 2 via the bus may be reduced.
　よって、誤り率が低い場合には、図６の構成を採用することで、誤り訂正処理の高速化を図ることができる。 Therefore, when the error rate is low, the speed of error correction processing can be increased by adopting the configuration of FIG.
　このように、第３の実施形態では、プロセッサコア２の内部に誤り訂正回路４を設けるため、誤り訂正回路４から出力されるエラー信号と訂正済のデータとをいち早く取得できる。よって、投機的な演算が有効か否かの判断を迅速に行えるとともに、投機的な演算が無効であったことも迅速に判断でき、再演算のタイミングを早めることができる。 Thus, in the third embodiment, since the error correction circuit 4 is provided in the processor core 2, the error signal output from the error correction circuit 4 and the corrected data can be acquired quickly. Therefore, it is possible to quickly determine whether or not the speculative calculation is valid, it is also possible to quickly determine that the speculative calculation is invalid, and to advance the timing of the recalculation.
　上述した第１～第３の実施形態によるプロセッサシステム１のどれを採用するかは、キャッシュメモリ３の誤り発生率、プロセッサコア２によるバスの占有率、およびバス幅などを考慮に入れて決定するのが望ましい。 Which of the processor systems 1 according to the first to third embodiments described above is adopted is determined in consideration of the error occurrence rate of the cache memory 3, the bus occupation rate by the processor core 2, the bus width, and the like. Is desirable.
　（第４の実施形態）
　以下に説明する第４の実施形態は、上述した第１～第３の実施形態におけるプロセッサコア２の内部構成を具体化したものである。 (Fourth embodiment)
The fourth embodiment described below embodies the internal configuration of the processor core 2 in the first to third embodiments described above.
　図７は第４の実施形態によるプロセッサシステム１のプロセッサコア２の内部構成を示すブロック図である。図７のプロセッサコア２は、Ｌ１データキャッシュ１１と、Ｌ１データキャッシュコントローラ１２と、命令キャッシュ１３と、命令キャッシュコントローラ１４と、命令発行ユニット１５と、命令キュー（命令記憶部）１６と、拡張リオーダ・バッファ（Reorder Buffer）１７と、レジスタ１８と、リザベーション・ステーション（Reservation Stations）１９と、演算器２０とを有する。 FIG. 7 is a block diagram showing an internal configuration of the processor core 2 of the processor system 1 according to the fourth embodiment. 7 includes an L1 data cache 11, an L1 data cache controller 12, an instruction cache 13, an instruction cache controller 14, an instruction issuing unit 15, an instruction queue (instruction storage unit) 16, an extended reorder A buffer (Reorder Buffer) 17, a register 18, a reservation station (Reservation Stations) 19, and an arithmetic unit 20 are included.
　拡張リオーダ・バッファ１７とリザザーション・ステーション１９は演算制御部に対応し、拡張リオーダ・バッファ１７は第１記憶部に対応し、リザベーション・ステーション１９は第２記憶部に対応する。 The extended reorder buffer 17 and the reservation station 19 correspond to the calculation control unit, the extended reorder buffer 17 corresponds to the first storage unit, and the reservation station 19 corresponds to the second storage unit.
　Ｌ１データキャッシュ１１は、プロセッサコア２がアクセス要求をしたデータを記憶する。図７では、省略しているが、Ｌ１データキャッシュ１１に入りきれないデータは、Ｌ２キャッシュ３以降の高次のキャッシュメモリ３かメインメモリに格納される。 The L1 data cache 11 stores data requested by the processor core 2 for access. Although omitted in FIG. 7, data that cannot be stored in the L1 data cache 11 is stored in the higher-order cache memory 3 or the main memory after the L2 cache 3.
　Ｌ１データキャッシュコントローラ１２は、プロセッサコア２がアクセス要求をしたデータがＬ１データキャッシュ１１に格納されているか否かのヒット／ミス判定と、Ｌ１データキャッシュ１１に対するアクセス制御と、Ｌ１データキャッシュ１１にデータが格納されていない場合にＬ２キャッシュ３にアクセスする制御とを行う。 The L1 data cache controller 12 determines the hit / miss of whether or not the data requested by the processor core 2 is stored in the L1 data cache 11, the access control for the L1 data cache 11, and the data in the L1 data cache 11. Is not stored, control to access the L2 cache 3 is performed.
　Ｌ１データキャッシュコントローラ１２は、Ｌ２キャッシュ３からのデータを受け取ると、このデータを拡張リオーダ・バッファ１７に伝送する。この時点では、このデータに誤りがあるか否かがわからないため、拡張リオーダ・バッファ１７には、誤り訂正待ちであることを示すフラグ情報Ｗ(wait)が記憶される。Ｌ２キャッシュ３からのデータに誤りがあるか否かは、Ｌ２キャッシュ３の誤り訂正回路４からのエラー信号の論理により判断される。Ｌ１データキャッシュコントローラ１２は、エラー信号により、Ｌ２キャッシュ３からのデータに誤りがないと判断すると、そのデータをＬ１データキャッシュ１１に記憶する。これにより、Ｌ１データキャッシュ１１には、誤りのないデータを記憶することができる。 When the data from the L2 cache 3 is received, the L1 data cache controller 12 transmits this data to the extended reorder buffer 17. At this point, since it is not known whether or not there is an error in this data, the extended reorder buffer 17 stores flag information W (wait) indicating that it is waiting for error correction. Whether there is an error in the data from the L2 cache 3 is determined by the logic of the error signal from the error correction circuit 4 of the L2 cache 3. When the L1 data cache controller 12 determines that there is no error in the data from the L2 cache 3 based on the error signal, the L1 data cache controller 12 stores the data in the L1 data cache 11. As a result, data with no error can be stored in the L1 data cache 11.
　命令キャッシュコントローラ１４は、Ｌ２キャッシュ３から命令が送られてくると、命令発行ユニット１５を介して命令キュー１６にその命令を記憶する。この時点では、この命令に誤りがあるか否かがわからないため、誤り訂正待ちであることを示すフラグ情報Ｗ(wait)が命令キュー１６に記憶される。その後、Ｌ２キャッシュ３からのエラー信号により、命令に誤りがないことがわかると、フラグ情報はＶ(valid)に変更される。一方、エラー信号により、命令に誤りがあることがわかると、Ｌ２キャッシュ３の誤り訂正回路４で誤り訂正した命令が命令キュー１６に伝送され、フラグ情報はＶ(valid)に変更される。 When the instruction cache controller 14 receives an instruction from the L2 cache 3, the instruction cache controller 14 stores the instruction in the instruction queue 16 via the instruction issue unit 15. At this point, since it is not known whether or not there is an error in this instruction, flag information W (wait) indicating that it is waiting for error correction is stored in the instruction queue 16. Thereafter, when it is found from the error signal from the L2 cache 3 that the instruction has no error, the flag information is changed to V (valid). On the other hand, if the error signal indicates that there is an error in the instruction, the error corrected by the error correction circuit 4 of the L2 cache 3 is transmitted to the instruction queue 16 and the flag information is changed to V (valid).
　命令キュー１６は、複数のエントリを有し、各エントリには、命令発行ユニット１５が発行した命令と、対応する命令のフラグ情報１６ａとが格納される。フラグ情報１６ａは、対応する命令が誤り訂正待ちであることを示すＷ(wait)情報と、対応する命令が有効であることを示すＶ(valid)情報とを含んでいる。 The instruction queue 16 has a plurality of entries, and each entry stores an instruction issued by the instruction issuing unit 15 and flag information 16a of the corresponding instruction. The flag information 16a includes W (wait) information indicating that the corresponding instruction is waiting for error correction, and V (valid) information indicating that the corresponding instruction is valid.
　命令キュー１６から発行された命令は順にリザベーション・ステーション１９に送られる。リザベーション・ステーション１９は、命令キュー１６からの命令を受け取ると、その命令に対応するオペランドをレジスタ１８から取得する。リザベーション・ステーション１９は、命令とオペランドとを一つのエントリとして対応づけて、複数のエントリ分を記憶可能である。そして、リザベーション・ステーション１９は、命令とオペランドが揃ったエントリから優先して、そのエントリの情報を演算器２０に伝送し、演算器２０での演算が実行される。演算器２０で演算された演算値は、拡張リオーダ・バッファ１７に記憶される。 Instructions issued from the instruction queue 16 are sequentially sent to the reservation station 19. When the reservation station 19 receives an instruction from the instruction queue 16, the reservation station 19 acquires an operand corresponding to the instruction from the register 18. The reservation station 19 can store a plurality of entries by associating instructions and operands as one entry. Then, the reservation station 19 gives priority to the entry having the instructions and operands, transmits the information of the entry to the computing unit 20, and the computation in the computing unit 20 is executed. The calculated value calculated by the calculator 20 is stored in the extended reorder buffer 17.
　図７のリザベーション・ステーション１９は、命令と２つのオペランドとを対応づけているが、一つのエントリに対応づけられるオペランドの数には特に制限はない。 Although the reservation station 19 in FIG. 7 associates an instruction with two operands, the number of operands associated with one entry is not particularly limited.
　命令キュー１６から発行された命令は、拡張リオーダ・バッファ１７にも送られる。拡張リオーダ・バッファ１７に送られた命令は、命令キュー１６から削除される。拡張リオーダ・バッファ１７は、命令に誤りがあった場合は、誤り訂正後の命令を記憶するとともに、後続のエントリを削除（フラッシュ）する。後続のエントリを削除するのは、間違った命令以降の演算結果は、正しいという保証が得られないためである。 The instruction issued from the instruction queue 16 is also sent to the extended reorder buffer 17. The instruction sent to the extended reorder buffer 17 is deleted from the instruction queue 16. If there is an error in the instruction, the extended reorder buffer 17 stores the error-corrected instruction and deletes (flushes) subsequent entries. The subsequent entry is deleted because there is no guarantee that the operation result after the wrong instruction is correct.
　図８は拡張リオーダ・バッファ１７のデータ構成の一例を示す図である。図示のように、拡張リオーダ・バッファ１７は、エントリ番号（Entry）と、ビジー情報（Busy）と、命令（Instruction）と、命令のフラグ情報と、オペランド１と、オペランド１のフラグ情報と、オペランド２と、オペランド２のフラグ情報と、保存先（Destination）と、保存先のフラグ情報と、演算値（Value）と、各エントリの状態（State）とを、一つのエントリとして対応づけて、複数エントリ分を記憶している。 FIG. 8 is a diagram showing an example of the data configuration of the extended reorder buffer 17. As shown, the extended reorder buffer 17 includes an entry number (Entry), busy information (Busy), an instruction (Instruction), instruction flag information, operand 1, operand 1 flag information, and operand. 2, operand 2 flag information, storage destination (Destination), storage destination flag information, operation value (Value), and state (State) of each entry are associated with each other as a single entry. The entry is memorized.
　拡張リオーダ・バッファ１７に記憶される各情報は、Ｌ２キャッシュ３、データキャッシュコントローラ７または命令キュー１６から伝送される。命令、オペランド１、オペランド２および保存先の各情報は、拡張リオーダ・バッファ１７に記憶された時点では、誤り訂正結果がまだ得られていないため、フラグ情報はＷ(wait)に設定される。リザベーション・ステーション１９から拡張リオーダ・バッファ１７に転送要求があった場合には、拡張リオーダ・バッファ１７は命令、オペランド１およびオペランド２の各情報を組にしてリザベーション・ステーション１９に伝送する。拡張リオーダ・バッファ１７は、これらの情報を用いて演算器２０が演算を行った演算値を記憶する。 Each information stored in the extended reorder buffer 17 is transmitted from the L2 cache 3, the data cache controller 7 or the instruction queue 16. Since the instruction, operand 1, operand 2 and storage destination information are stored in the extended reorder buffer 17, an error correction result has not yet been obtained, so the flag information is set to W (wait). When there is a transfer request from the reservation station 19 to the extended reorder buffer 17, the extended reorder buffer 17 transmits the instruction, operand 1 and operand 2 information as a set to the reservation station 19. The extended reorder buffer 17 stores the calculation value calculated by the calculator 20 using these pieces of information.
　また、誤り訂正回路４が出力したエラー信号が拡張リオーダ・バッファ１７に入力されると、エラー信号の論理により、対応する情報に誤りがないことがわかると、Ｖ(valid)のフラグ情報が設定される。エラー信号の論理により、対応する情報に誤りがあることがわかると、対応するエントリ以降のすべての情報が削除（フラッシュ）される。例えば、拡張リオーダ・バッファ１７内の命令をフラッシュした後は、命令発行ユニット１５が新たな命令をフェッチして演算を継続して行ってもよいし、拡張リオーダ・バッファ１７のエントリを命令キュー１６に書き戻して演算を継続して行ってもよい。 When the error signal output from the error correction circuit 4 is input to the extended reorder buffer 17, if the error signal logic indicates that there is no error in the corresponding information, the flag information of V (valid) is set. Is done. If the logic of the error signal indicates that there is an error in the corresponding information, all information after the corresponding entry is deleted (flashed). For example, after the instruction in the extended reorder buffer 17 is flushed, the instruction issuing unit 15 may continue to perform the operation by fetching a new instruction, or the entry in the extended reorder buffer 17 may be stored in the instruction queue 16. The calculation may be continued by writing back to.
　演算が実行中のエントリのビジー情報はyesとセットされ、演算が終了するとnoとセットされる。命令、オペランド１、オペランド２、および保存先のすべてのフラグ情報がvalidになり、かつビジー情報がnoの時、各エントリの状態はCommitになる。Commitになると、そのエントリの演算値がレジスタ１８に保存される。 The busy information of the entry where the operation is being executed is set to yes, and set to no when the operation is completed. When all the flag information of the instruction, operand 1, operand 2, and save destination is valid and the busy information is no, the state of each entry is Commit. When Commit is reached, the operation value of the entry is stored in the register 18.
　本実施形態では、上述した第１～第３の実施形態と同様に、Ｌ２キャッシュ３等の高次のキャッシュメモリ３から読み出されたキャッシュデータに対して誤り訂正処理を行うのに並行して、このキャッシュデータを用いて投機的な演算を行う。投機的な演算を行っている最中は、命令、オペランド、および保存先に対応する各フラグ情報はwaitに設定される。この状態で投機的な演算を行って得られた演算値は、拡張リオーダ・バッファ１７に格納され、その演算値に対応するエントリの状態はやはりＷ(wait)に設定される。 In the present embodiment, as in the first to third embodiments described above, the error correction process is performed in parallel on the cache data read from the higher-level cache memory 3 such as the L2 cache 3. Then, speculative calculation is performed using this cache data. During speculative computation, each flag information corresponding to the instruction, operand, and storage destination is set to wait. The calculated value obtained by performing speculative calculation in this state is stored in the extended reorder buffer 17, and the state of the entry corresponding to the calculated value is also set to W (wait).
　誤り訂正回路４からのエラー信号により、命令、オペランド、および保存先に誤りがないことがわかり、かつビジー情報がnoの時、拡張リオーダ・バッファ１７は、対応するエントリの状態をCommitに設定して、投機的な演算により得られた演算値をレジスタ１８に書き込む。 When the error signal from the error correction circuit 4 indicates that there is no error in the instruction, operand, and storage destination, and the busy information is no, the extended reorder buffer 17 sets the state of the corresponding entry to Commit. Thus, the operation value obtained by speculative operation is written into the register 18.
　逆に、誤り訂正回路４からのエラー信号により、拡張リオーダ・バッファ１７内の命令、オペランド、および保存先の少なくとも一つに誤りがあることがわかると、その誤りのあるエントリ以降のすべてのエントリが無効となり、削除（フラッシュ）される。 Conversely, if it is found from the error signal from the error correction circuit 4 that there is an error in at least one of the instruction, operand, and storage destination in the extended reorder buffer 17, all entries after the erroneous entry Becomes invalid and is deleted (flushed).
　このように、第４の実施形態によるプロセッサコア２は、命令キュー１６に各命令に対応したフラグ情報１６ａを設けるため、命令キュー１６内の各エントリの命令に誤りがあるか否かを把握できる。命令キュー１６は、命令に誤りがある場合は、その命令以降のエントリをすべて削除するため、命令の投機的な実行を行った場合でも、誤りのある命令の実行による演算結果がレジスタ１８に書き込まれるおそれはない。 As described above, since the processor core 2 according to the fourth embodiment provides the instruction queue 16 with the flag information 16a corresponding to each instruction, it can grasp whether or not there is an error in the instruction of each entry in the instruction queue 16. . When there is an error in the instruction, the instruction queue 16 deletes all entries after the instruction. Therefore, even when the instruction is speculatively executed, the calculation result of the execution of the erroneous instruction is written in the register 18. There is no fear.
　（第５の実施形態）
　以下に説明する第５の実施形態は、第４の実施形態とはレジスタ１８の内部構成が異なるものである。 (Fifth embodiment)
The fifth embodiment described below is different from the fourth embodiment in the internal configuration of the register 18.
　図９は第５の実施形態によるプロセッサシステム１のプロセッサコア２の内部構成を示すブロック図である。図９のプロセッサコア２は、リザベーション・ステーション１９のデータ構成が図７と異なる他は、図７と共通する。図９のリザベーション・ステーション１９は、命令、オペランド１、オペランド２の各情報に対応するフラグ情報１９ａを有する。これらのフラグ情報１９ａは、命令キュー１６と拡張リオーダ・バッファ１７に記憶されているフラグ情報に基づいて設定される。 FIG. 9 is a block diagram showing an internal configuration of the processor core 2 of the processor system 1 according to the fifth embodiment. The processor core 2 of FIG. 9 is common to FIG. 7 except that the data structure of the reservation station 19 is different from that of FIG. The reservation station 19 of FIG. 9 has flag information 19a corresponding to each information of instruction, operand 1 and operand 2. The flag information 19a is set based on the flag information stored in the instruction queue 16 and the extended reorder buffer 17.
　演算器２０は、リザベーション・ステーション１９の各エントリの中で、Ｖ(valid)のフラグ情報を有する命令を優先して選択して演算を実行する。これにより、演算器２０は、正しいデータのみを用いて演算を行うことができ、演算値が有効である確率を上げることができ、プロセッサの処理能力を向上できる。 The calculator 20 preferentially selects an instruction having V (valid) flag information from each entry of the reservation station 19 and executes the calculation. Thereby, the computing unit 20 can perform computation using only correct data, can increase the probability that the computed value is valid, and can improve the processing capability of the processor.
　このように、第５の実施形態では、リザベーション・ステーション１９内にフラグ情報１９ａを設けるため、このフラグ情報１９ａを参照して、演算器２０は演算順序を決定でき、演算器２０で演算した演算値が有効である確率を向上できる。 As described above, in the fifth embodiment, since the flag information 19a is provided in the reservation station 19, the computing unit 20 can determine the computation order with reference to the flag information 19a, and the computation performed by the computing unit 20 can be performed. The probability that the value is valid can be improved.
　（第６の実施形態）
　図１０は第６の実施形態によるプロセッサシステム１のプロセッサコア２の内部構成を示すブロック図である。図９のプロセッサコア２は、バックアップレジスタ２１を有し、またレジスタ１８のデータ構成が図７と異なっている。これ以外は、図７と共通する。 (Sixth embodiment)
FIG. 10 is a block diagram showing an internal configuration of the processor core 2 of the processor system 1 according to the sixth embodiment. The processor core 2 in FIG. 9 has a backup register 21 and the data configuration of the register 18 is different from that in FIG. The rest is the same as FIG.
　図１０のレジスタ１８は、各エントリごとにフラグ情報１８ａを有する。このフラグ情報１８ａは、誤り訂正回路４から送られて来るエラー信号や拡張リオーダ・バッファ１７により設定される。 10 has flag information 18a for each entry. The flag information 18 a is set by an error signal sent from the error correction circuit 4 or the extended reorder buffer 17.
　バックアップレジスタ２１は、レジスタ１８の各エントリにデータを記憶する際に、このエントリに今まで記憶されていたデータを記憶する。バックアップレジスタ２１を設ける理由は、レジスタ１８に新たに記憶したデータが誤りであった場合に、元のデータに戻せるようにするためである。バックアップレジスタ２１には、バックアップしたデータが誤り訂正前か後かを区別するために、すなわちバックアップしたデータが有効か否かを示すフラグ情報２１ａも保存される。 When the backup register 21 stores data in each entry of the register 18, the backup register 21 stores the data stored so far in this entry. The reason why the backup register 21 is provided is to allow the data newly stored in the register 18 to be restored to the original data when there is an error. The backup register 21 also stores flag information 21a indicating whether the backed up data is before or after error correction, that is, whether the backed up data is valid.
　図７では、レジスタ１８に記憶されるデータは拡張リオーダ・バッファ１７からレジスタ１８に伝送されたが、図１０では、Ｌ２キャッシュ３から直接レジスタ１８にデータを記憶できるようにしている。これにより、レジスタ１８へのデータ転送を高速化でき、ひいては演算器２０へのデータ転送を高速化できる。 7, the data stored in the register 18 is transmitted from the extended reorder buffer 17 to the register 18, but in FIG. 10, the data can be directly stored in the register 18 from the L2 cache 3. Thereby, the data transfer to the register 18 can be speeded up, and the data transfer to the arithmetic unit 20 can be speeded up.
　（第７の実施形態）
　図１１は第７の実施形態によるプロセッサシステム１のプロセッサコア２の内部構成を示すブロック図である。図１１のプロセッサコア２は、図１０のリザベーション・ステーション１９に、図９と同様にフラグ情報１９ａを設けており、これ以外は図１０のプロセッサコア２と共通する。 (Seventh embodiment)
FIG. 11 is a block diagram showing an internal configuration of the processor core 2 of the processor system 1 according to the seventh embodiment. The processor core 2 in FIG. 11 is provided with flag information 19a in the reservation station 19 in FIG. 10 in the same manner as in FIG. 9, and the rest is common to the processor core 2 in FIG.
　図１１のプロセッサコア２では、リザベーション・ステーション１９内にフラグ情報１９ａを設けるため、このフラグ情報１９ａを参照して、演算器２０は演算順序を決定でき、演算器２０で演算した演算値が有効である確率を向上でき、プロセッサの処理性能の向上が図れる。 In the processor core 2 of FIG. 11, since the flag information 19a is provided in the reservation station 19, the calculator 20 can determine the calculation order with reference to the flag information 19a, and the calculation value calculated by the calculator 20 is valid. And the processing performance of the processor can be improved.
　（第８の実施形態）
　図１２は第８の実施形態によるプロセッサシステム１のプロセッサコア２の内部構成を示すブロック図である。図１２のプロセッサコア２は、レジスタ１８のデータ構成が図７と異なっている。これ以外は、図７と共通する。 (Eighth embodiment)
FIG. 12 is a block diagram showing an internal configuration of the processor core 2 of the processor system 1 according to the eighth embodiment. The processor core 2 in FIG. 12 is different from that in FIG. 7 in the data configuration of the register 18. The rest is the same as FIG.
　図１２のレジスタ１８は、各エントリごとに、レジスタ・フィールド（第１フィールド）１８ｂと、バックアップ・フィールド１８ｃ（第２フィールド）と、レジスタ・フィールド１８ｂ内のデータのフラグ情報１８ａ（第３フィールド）と、バックアップ・フィールド１８ｃのデータのフラグ情報１８ｄ（第４フィールド）とを有する。レジスタ・フィールド１８ｂには、レジスタ１８に記憶されるべき本来のデータが記憶される。バックアップ・フィールド１８ｃには、対応するレジスタ・フィールド１８ｂ内のデータを更新する際に、このレジスタ・フィールド１８ｂに今まで記憶されていたデータが記憶され、そのデータが誤り訂正前か後か、すなわち有効か否かを示すフラグ情報１８ｄが記憶される。 The register 18 shown in FIG. 12 includes a register field (first field) 18b, a backup field 18c (second field), and flag information 18a (third field) of data in the register field 18b for each entry. And flag information 18d (fourth field) of data in the backup field 18c. The register field 18b stores original data to be stored in the register 18. When the data in the corresponding register field 18b is updated, the data stored in the register field 18b is stored in the backup field 18c, and the data is stored before or after error correction. Flag information 18d indicating whether or not it is valid is stored.
　レジスタ１８内のフラグ情報は、誤り訂正回路４から送られて来るエラー信号や拡張リオーダ・バッファ１７により設定される。バックアップ・フィールド１８ｃは、図１０のバックアップレジスタ２１と同様の目的で用いられるが、バックアップ・フィールド１８ｃはレジスタ１８の各エントリごとに設けられるため、誤りが多い場合であっても、バックアップ・フィールド１８ｃが不足するおそれは少ない。よって、バックアップ・フィールド１８ｃを有効活用して、投機演算を行うことができる。 The flag information in the register 18 is set by an error signal sent from the error correction circuit 4 or the extended reorder buffer 17. The backup field 18c is used for the same purpose as the backup register 21 of FIG. 10, but since the backup field 18c is provided for each entry of the register 18, even if there are many errors, the backup field 18c. There is little risk of shortage. Therefore, it is possible to perform speculative calculation by effectively using the backup field 18c.
　（第９の実施形態）
　図１３は第７の実施形態によるプロセッサシステム１のプロセッサコア２の内部構成を示すブロック図である。図１３のプロセッサコア２は、図１２のリザベーション・ステーション１９に、図９と同様にフラグ情報１９ａを設けており、これ以外は図１２のプロセッサコア２と共通する。 (Ninth embodiment)
FIG. 13 is a block diagram showing an internal configuration of the processor core 2 of the processor system 1 according to the seventh embodiment. The processor core 2 in FIG. 13 is provided with flag information 19a in the reservation station 19 in FIG. 12 in the same manner as in FIG. 9, and the rest is common to the processor core 2 in FIG.
　図１３のプロセッサコア２では、リザベーション・ステーション１９内にフラグ情報１９ａを設けるため、このフラグ情報１９ａを参照して、演算器２０は演算順序を決定でき、演算器２０で演算した演算値が有効である確率を向上でき、プロセッサの処理性能の向上が図れる。 In the processor core 2 of FIG. 13, since flag information 19a is provided in the reservation station 19, the arithmetic unit 20 can determine the arithmetic order with reference to the flag information 19a, and the arithmetic value calculated by the arithmetic unit 20 is valid. And the processing performance of the processor can be improved.
　本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。 Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

Claims (15)

  1. 　メモリから読み出されたデータの誤り訂正処理に並行して、誤り訂正前のデータを用いて演算を実行する演算器と、
    　前記演算器にて演算された演算値を記憶するレジスタと、
    　前記誤り訂正処理の結果に基づいて前記演算が有効か否かを判断するとともに、前記演算が有効でない場合には、前記誤り訂正処理による誤り訂正後のデータを用いて前記演算器にて再演算を実行させ、前記演算が有効な場合には、前記演算による演算値を前記レジスタに記憶する演算制御部と、を備えるプロセッサ。     In parallel with the error correction processing of the data read from the memory, an arithmetic unit that performs an operation using the data before error correction,
    A register for storing a calculation value calculated by the calculator;
    Based on the result of the error correction process, it is determined whether or not the calculation is valid. If the calculation is not valid, recalculation is performed by the computing unit using data after error correction by the error correction process. And a calculation control unit that stores a calculation value obtained by the calculation in the register when the calculation is valid.
  2. 　命令を発行する命令発行ユニットと、
    　前記命令発行ユニットが発行した命令を、当該命令が有効か否かを示すフラグ情報と対応づけて記憶する命令記憶部と、を備える請求項１に記載のプロセッサ。     An instruction issuing unit for issuing instructions;
    The processor according to claim 1, further comprising: an instruction storage unit that stores an instruction issued by the instruction issuing unit in association with flag information indicating whether the instruction is valid.
  3. 　前記演算制御部は、
    　前記命令記憶部から読み出された命令と、当該命令に対応するフラグ情報と、当該命令に対応するオペランド情報と、当該命令に対応する演算結果保存先情報と、前記演算器による演算値情報と、を対応づけて記憶する第１記憶部と、
    　前記命令記憶部から読み出された命令を前記演算器に対応づけて記憶する第２記憶部と、を有し、
    　前記演算器は、前記第２記憶部に記憶された命令に基づいて演算を行い、
    　前記第１記憶部は、前記演算器が演算した演算値を記憶する請求項２に記載のプロセッサ。     The arithmetic control unit is
    An instruction read from the instruction storage unit, flag information corresponding to the instruction, operand information corresponding to the instruction, operation result storage destination information corresponding to the instruction, and operation value information by the operator; , And a first storage unit that stores the information in association with each other,
    A second storage unit that stores an instruction read from the instruction storage unit in association with the arithmetic unit;
    The arithmetic unit performs an operation based on an instruction stored in the second storage unit,
    The processor according to claim 2, wherein the first storage unit stores a calculation value calculated by the calculator.
  4. 　前記第１記憶部内の前記命令記憶部から読み出された命令は、前記演算器にて演算を行うべき命令であり、
    　前記フラグ情報は、前記命令記憶部から読み出された命令が有効か否かを示す情報であり、
    　前記オペランド情報は、前記命令記憶部から読み出された命令に対応するオペランドと、前記オペランドが有効か否かを示す情報と、を含み、
    　前記演算結果保存先情報は、前記命令記憶部から読み出された命令に対応する前記演算器で演算された演算値の保存先と、当該保存先が有効か否かを示す情報と、を含んでおり、
    　前記演算値情報は、前記演算値と、前記演算値が有効か否かを示す情報と、を含む請求項３に記載のプロセッサ。     The instruction read from the instruction storage unit in the first storage unit is an instruction to be operated by the computing unit,
    The flag information is information indicating whether or not the instruction read from the instruction storage unit is valid,
    The operand information includes an operand corresponding to an instruction read from the instruction storage unit, and information indicating whether the operand is valid,
    The calculation result storage destination information includes a storage destination of a calculation value calculated by the calculator corresponding to the instruction read from the instruction storage unit, and information indicating whether or not the storage destination is valid. And
    The processor according to claim 3, wherein the calculated value information includes the calculated value and information indicating whether the calculated value is valid.
  5. 　前記第２記憶部内の前記命令記憶部から読み出された命令は、前記演算器にて演算を行うべき命令であり、
    　前記第２記憶部は、前記演算器にて実行されるべき命令の他に、当該命令が有効か否かを示す情報と、当該命令に対応するオペランドと、当該オペランドが有効か否かを示す情報と、を記憶する請求項３に記載のプロセッサ。     The instruction read from the instruction storage unit in the second storage unit is an instruction to be operated by the computing unit,
    In addition to the instruction to be executed by the computing unit, the second storage unit indicates information indicating whether the instruction is valid, an operand corresponding to the instruction, and whether the operand is valid. The processor according to claim 3, wherein information is stored.
  6. 　前記演算器は、前記第２記憶部に記憶された命令のうち、対応する命令およびオペランドがともに有効な命令を優先して実行する請求項５に記載のプロセッサ。 The processor according to claim 5, wherein the arithmetic unit preferentially executes an instruction having a valid corresponding instruction and operand among instructions stored in the second storage unit.
  7. 　前記レジスタの任意のエントリに有効か否かが不明のデータを記憶する際に、当該エントリに記憶されていた元データを記憶するバックアップレジスタを備え、
    　前記レジスタおよび前記バックアップレジスタはそれぞれ、各エントリごとに、各エントリのデータが有効か否かを示すフラグ情報を記憶する請求項１に記載のプロセッサ。     A backup register for storing the original data stored in the entry when storing data for which it is unknown whether or not it is valid for an arbitrary entry of the register;
    The processor according to claim 1, wherein each of the register and the backup register stores flag information indicating whether data of each entry is valid for each entry.
  8. 　前記レジスタは、エントリごとに、データを記憶する第１フィールドと、前記第１フィールドのデータを更新する際に前記第１フィールドに記憶されていた元データを記憶する第２フィールドと、前記第１フィールドに記憶されたデータが有効か否かを示すフラグ情報を記憶する第３フィールドと、前記第２フィールド内の前記第１フィールドに記憶されていた元データが有効か否かを示すフラグ情報を記憶する第４フィールドと、を有する請求項１に記載のプロセッサ。 The register includes, for each entry, a first field for storing data, a second field for storing original data stored in the first field when the data in the first field is updated, and the first field A third field for storing flag information indicating whether the data stored in the field is valid; and flag information indicating whether the original data stored in the first field in the second field is valid. The processor according to claim 1, further comprising a fourth field to be stored.
  9. 　前記誤り訂正処理を行う誤り訂正回路を備える請求項１に記載のプロセッサ。 The processor according to claim 1, further comprising an error correction circuit that performs the error correction processing.
  10. 　メモリと、
    　前記メモリから読み出されたデータの誤り訂正処理を行う誤り訂正回路と、
    　前記誤り訂正処理に並行して、誤り訂正前のデータを用いて演算を実行し、前記誤り訂正処理の結果に基づいて、前記演算が有効か否かを判断するとともに、前記演算が有効でない場合には、前記誤り訂正処理による誤り訂正後のデータを用いて前記演算器にて再演算を実行させ、前記演算が有効な場合には、前記演算による演算値をレジスタに記憶するプロセッサコアと、を備えるプロセッサシステム。     Memory,
    An error correction circuit for performing an error correction process on the data read from the memory;
    In parallel with the error correction process, an operation is performed using data before error correction, and based on the result of the error correction process, it is determined whether or not the operation is valid. A processor core for performing recalculation in the computing unit using data after error correction by the error correction processing, and storing the computed value of the computation in a register when the computation is valid; A processor system comprising:
  11. 　前記誤り訂正回路は、前記メモリに内蔵されるか、前記メモリと前記プロセッサコアとの間に設けられるか、あるいは前記プロセッサコアに内蔵される請求項１０に記載のプロセッサシステム。 The processor system according to claim 10, wherein the error correction circuit is built in the memory, is provided between the memory and the processor core, or is built in the processor core.
  12. 　前記メモリは、
    　タグデータを記憶するタグ記憶部と、
    　前記タグデータに対応するデータを記憶するデータ記憶部と、
    　前記プロセッサコアからアクセス要求のあったアドレスが前記タグ記憶部に記憶されたタグデータに一致するか否かのヒット／ミス判定を行うヒット／ミス判定部と、を有し、
    　前記誤り訂正回路は、前記データ記憶部に記憶された前記データに対して前記誤り訂正処理を行う請求項１０に記載のプロセッサシステム。     The memory is
    A tag storage unit for storing tag data;
    A data storage unit for storing data corresponding to the tag data;
    A hit / miss determination unit that performs a hit / miss determination as to whether or not the address requested to be accessed from the processor core matches the tag data stored in the tag storage unit,
    The processor system according to claim 10, wherein the error correction circuit performs the error correction processing on the data stored in the data storage unit.
  13. 　前記メモリは、
    　タグデータを記憶するタグ記憶部と、
    　前記タグデータに対応するデータを記憶するデータ記憶部と、
    　前記プロセッサコアからアクセス要求のあったアドレスが前記タグ記憶部に記憶されたタグデータに一致するか否かのヒット／ミス判定を行うヒット／ミス判定部と、を有し、
    　前記誤り訂正回路は、
    　前記タグ記憶部から読み出されたタグデータの誤り訂正を行う第１誤り訂正部と、
    　前記データ記憶部から読み出されたデータの誤り訂正を行う第２誤り訂正部と、を有し、
    　前記ヒット／ミス判定部は、前記第１誤り訂正部で誤り訂正を行った後のタグデータを用いて前記ヒット／ミス判定を行う請求項１０に記載のプロセッサシステム。     The memory is
    A tag storage unit for storing tag data;
    A data storage unit for storing data corresponding to the tag data;
    A hit / miss determination unit that performs a hit / miss determination as to whether or not the address requested to be accessed from the processor core matches the tag data stored in the tag storage unit,
    The error correction circuit is
    A first error correction unit that performs error correction of tag data read from the tag storage unit;
    A second error correction unit that performs error correction of data read from the data storage unit,
    The processor system according to claim 10, wherein the hit / miss determination unit performs the hit / miss determination using tag data after error correction is performed by the first error correction unit.
  14. 　前記プロセッサコアは、１次キャッシュメモリを含み、
    　前記メモリは、２次以上の高次のキャッシュメモリを含む請求項１０に記載のプロセッサシステム。     The processor core includes a primary cache memory,
    The processor system according to claim 10, wherein the memory includes a secondary or higher-order cache memory.
  15. 　前記メモリは、ＭＲＡＭ（Magnetoresistive RAM）を含む請求項１０に記載のプロセッサシステム。 The processor system according to claim 10, wherein the memory includes an MRAM (Magnetoresistive RAM).
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