WO2016003638A1 - Methods of making three dimensional nand devices - Google Patents

Methods of making three dimensional nand devices Download PDF

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Publication number
WO2016003638A1
WO2016003638A1 PCT/US2015/035961 US2015035961W WO2016003638A1 WO 2016003638 A1 WO2016003638 A1 WO 2016003638A1 US 2015035961 W US2015035961 W US 2015035961W WO 2016003638 A1 WO2016003638 A1 WO 2016003638A1
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Prior art keywords
back side
layer
forming
charge storage
side recesses
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Raghuveer S. Makala
Yao-Sheng Lee
Senaka Krishna Kanakamedala
Yanli Zhang
George Matamis
Johann Alsmeier
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SanDisk Technologies LLC
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SanDisk Technologies LLC
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    • H—ELECTRICITY
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/63—Vertical IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/418—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials the conductive layers comprising transition metals
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/6903—Inorganic materials containing silicon
    • H—ELECTRICITY
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6938—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides
    • H10P14/6939—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal
    • H10P14/69394—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses the material containing at least one metal element, e.g. metal oxides, metal oxynitrides or metal oxycarbides characterised by the metal the material containing titanium, e.g. TiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz

Definitions

  • the present invention relates generally to the field of semiconductor devices and specifically to three dimensional vertical NAND strings and other three dimensional devices and methods of making thereof.
  • S-SGT Structured Cell
  • IEDM Proc. (2001) 33-36 IEDM Proc.
  • this NAND string provides only one bit per cell.
  • the active regions of the NAND string is formed by a relatively difficult and time consuming process involving repeated formation of sidewall spacers and etching of a portion of the substrate, which results in a roughly conical active region shape.
  • An embodiment relates to a method of making a three dimensional NAND string including providing a stack of alternating first material layers and second material layers over a substrate.
  • the first material layers include an insulating material and the second material layers include sacrificial layers.
  • the method further includes forming a front side opening in the stack, forming a tunnel dielectric in the front side opening, forming a semiconductor channel in the front side opening over the tunnel dielectric and forming a back side opening in the stack.
  • the method also includes selectively removing the second material layers through the back side opening to form back side recesses between adjacent first material layers, forming a metal charge storage layer in the back side opening and in the back side recesses and forming discrete charge storage regions in the back side recesses by removing the metal charge storage layer from the back side opening and selectively recessing the metal charge storage layer in the back side recesses.
  • Another embodiment relates to a monolithic three dimensional N AND string including a semiconductor channel with at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate.
  • the NAND string also includes a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate.
  • the plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level.
  • the NAND string also includes a blocking dielectric located in contact with the plurality of control gate electrodes, a tunnel dielectric in contact with the
  • Each floating gate includes a tungsten portion located between a first nitride layer and a second nitride layer.
  • Another embodiment relates to a monolithic, three dimensional array of memory devices located over a silicon substrate including an array of vertically oriented NAND strings in which at least one memory cell in a first device level of the array is located over another memory cell in a second device level and an integrated circuit including a driver circuit for the array of memory devices located on the silicon substrate.
  • At least one vertically oriented NAND string of the array of vertically oriented NAND strings includes: a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate.
  • the plurality of control gate electrodes include at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level located over the major surface of the substrate and below the first device level.
  • the NAND strings also include a blocking dielectric located in contact with the plurality of control gate electrodes, a tunnel dielectric in contact with the semiconductor channel and a plurality of vertically spaced apart floating gates located between the blocking dielectric and the tunnel dielectric.
  • Each floating gate includes a tungsten portion located between a first nitride layer and a second nitride layer.
  • FIGs. 1 A and IB are respectively side cross sectional and top cross sectional views of a conventional NAND string.
  • Figure 1 A is a side cross sectional view of the device along line Y-Y' in Figure IB
  • Figure IB is a side cross sectional view of the device along line X-X' in Figure 1 A.
  • FIGs. 2A and 2B are respectively side cross sectional and top cross sectional views of another conventional NAND string.
  • Figure 2 A is a side cross sectional view of the device along line Y-Y' in Figure 2B
  • Figure 2B is a side cross sectional view of the device along line X-X' in Figure 2A.
  • FIG. 3 A is a side cross sectional view of a conventional NAND string of an embodiment with a U-shaped channel.
  • Fig. 3B is a side cross sectional view of another conventional NAND string.
  • FIG. 4 is a top schematic view of a portion of a conventional memory device comprising NAND strings.
  • Figs. 5A-5E illustrate a method of making a NAND string according to an embodiment.
  • Figs. 6A-6E illustrate a method of making a NAND string according to an embodiment.
  • Figs. 7A-7E illustrate a method of making a NAND string according to an embodiment.
  • the inventors have developed methods that allow for the fabrication of metal (e.g., pure metal, such as tungsten, and/or electrically conductive metal alloy, such as tungsten nitride or titanium nitride) floating gate NAND devices.
  • metal e.g., pure metal, such as tungsten, and/or electrically conductive metal alloy, such as tungsten nitride or titanium nitride
  • a sequential deposition-etch sequence is used for selective formation of floating gates in the recesses in sidewalls of a high-aspect ratio three dimensional NAND structure.
  • An advantage of the methods is that the thermal budget constraints used to fabricate floating gates allows a different order of fabrication steps which does not require an additional high temperature annealing typically used in fabricating the tunnel dielectric and polysilicon channel. The additional high temperature anneal tends to lead to poor tunnel dielectric quality which degrades the device program/erase speed.
  • the floating gates are formed after annealing the tunnel dielectric and the polysilicon channel.
  • An additional advantage is that the NAND strings may be fabricated by only forming recesses from the back side opening (slit trench) rather than forming recesses from both the back side opening and the front side (memory hole) openings.
  • the back side recesses are typically deeper (e.g. 100-500 nm deep) than the shallow front side recesses (e.g. 3-10 nm deep) which improves the ease of forming the metal floating gates through the high aspect ratio openings.
  • a monolithic three dimensional memory array is one in which multiple memory levels are formed above a single substrate, such as a semiconductor wafer, with no
  • non-monolithic stacked memories have been constructed by forming memory levels on separate substrates and adhering the memory levels atop each other, as in Leedy, U.S. Pat. No. 5,915,167, titled “Three Dimensional Structure Memory.” The substrates may be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not true monolithic three dimensional memory arrays.
  • the monolithic three dimensional NAND string 180 comprises a semiconductor channel 1 having at least one end portion extending substantially perpendicular to a major surface 100a of a substrate 100, as shown in Figures 1 A, 2A and 3B.
  • “Substantially perpendicular to” means within 0-10°.
  • the semiconductor channel 1 may have a pillar shape and the entire pillar-shaped semiconductor channel extends substantially perpendicularly to the major surface of the substrate 100, as shown in Figures 1 A, 2A and 3B.
  • the source/drain electrodes of the device can include a lower electrode 102 provided below the semiconductor channel 1 and an upper electrode 202 formed over the semiconductor channel 1, as shown in Figures lA and 2A.
  • the semiconductor channel 1 may have a U-shaped pipe shape, as shown in Figure 3A. The two wing portions la and lb of the U-shaped pipe shape
  • semiconductor channel may extend substantially perpendicular to the major surface 100a of the substrate 100, and a connecting portion lc of the U-shaped pipe shape semiconductor channel 1 connects the two wing portions la, lb extends substantially parallel to the major surface 100a of the substrate 100.
  • one of the source or drain electrodes 2021 contacts the first wing portion of the semiconductor channel from above, and another one of a source or drain electrodes 202 2 contacts the second wing portion of the semiconductor channel 1 from above.
  • An optional body contact electrode (not shown) may be disposed in the substrate 100 to provide body contact to the connecting portion of the semiconductor channel 1 from below.
  • the NAND string's select or access transistors are not shown in Figures 1-3B for clarity.
  • the semiconductor channel 1 may be a filled feature, as shown in Figures 2A, 2B, 3A and 3B.
  • the semiconductor channel 1 may be hollow, for example a hollow cylinder filled with an insulating fill material 2, as shown in Figures 1 A- IB.
  • an insulating fill material 2 may be formed to fill the hollow part surrounded by the semiconductor channel 1.
  • the U-shaped pipe shape semiconductor channel 1 shown in Figure 3 A and or the channel 1 shown in Figure 3B may alternatively be a hollow cylinder filled with an insulating fill material 2, shown in Figures 1A-1B.
  • the substrate 100 can be any semiconducting substrate known in the art, such as monocrystalline silicon, IV-IV compounds such as silicon-germanium or silicon-germanium- carbon, III-V compounds, II- VI compounds, epitaxial layers over such substrates, or any other semiconducting or non-semiconducting material, such as silicon oxide, glass, plastic, metal or ceramic substrate.
  • the substrate 100 may include integrated circuits fabricated thereon, such as driver circuits for a memory device.
  • semiconductor channel 1 Any suitable semiconductor materials can be used for semiconductor channel 1 , for example silicon, germanium, silicon germanium, or other compound semiconductor materials, such as III-V, II- VI, or conductive or semiconductive oxides, etc.
  • semiconductor materials for example silicon, germanium, silicon germanium, or other compound semiconductor materials, such as III-V, II- VI, or conductive or semiconductive oxides, etc.
  • semiconductor material may be amorphous, polycrystalline or single crystal.
  • the semiconductor channel material may be formed by any suitable deposition methods.
  • the semiconductor channel material is deposited by low pressure chemical vapor deposition (LPCVD).
  • LPCVD low pressure chemical vapor deposition
  • semiconductor channel material may be a recrystallized polycrystalline semiconductor material formed by recrystallizing an initially deposited amorphous semiconductor material.
  • the insulating fill material 2 may comprise any electrically insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or other high-k insulating materials.
  • the monolithic three dimensional NAND string further comprise a plurality of control gate electrodes 3, as shown in Figures 1 A- IB, 2A-2B, 3 A and 3B.
  • the control gate electrodes 3 may comprise a portion having a strip shape extending substantially parallel to the major surface 100a of the substrate 100.
  • the plurality of control gate electrodes 3 comprise at least a first control gate electrode 3a located in a first device level (e.g., device level A) and a second control gate electrode 3b located in a second device level (e.g., device level B) located over the major surface 100a of the substrate 100 and below the device level A.
  • the control gate material may comprise any one or more suitable conductive or semiconductor control gate material known in the art, such as doped polysilicon, tungsten, tungsten nitride, copper, aluminum, tantalum, titanium, cobalt, titanium nitride or alloys thereof.
  • the control gate material in Figures 1 A, 2 A and 3 A may comprise a conductive metal or metal alloy, such as tungsten and/or titanium nitride, while the control gate material in Figure 3B may comprise doped polysilicon.
  • a blocking dielectric 7 is located adjacent to the control gate(s) 3 and may surround the control gate electrodes 3, as shown in Figures 1 A, 2A and 3A.
  • a straight blocking dielectric layer 7 may be located only adjacent to an edge (i.e., minor surface) of each control gate electrode 3, as shown in Figure 3B.
  • the blocking dielectric 7 may comprise a layer having plurality of blocking dielectric segments located in contact with a respective one of the plurality of control gate electrodes 3, for example a first blocking dielectric segment 7a located in device level A and a second blocking dielectric segment 7b located in device level B are in contact with control electrodes 3 a and 3b, respectively, as shown in Figure 3A.
  • the blocking dielectric 7 may be a straight, continuous layer, as shown in Figure 3B, similar to the device described in U.S. Patent Number
  • the monolithic three dimensional NAND string also comprise a charge storage region 9.
  • the charge storage region 9 may comprise one or more continuous layers which extend the entire length of the memory cell portion of the NAND string, as shown in Figure 3B.
  • the charge storage region 9 may comprise an insulating charge trapping material, such as a silicon nitride layer.
  • the charge storage region may comprise a plurality of discrete charge storage regions 9, as shown in Figures 1 A, 2 A and 3 A.
  • the plurality of discrete charge storage regions 9 comprise at least a first discrete charge storage region 9a located in the device level A and a second discrete charge storage region 9b located in the device level B, as shown in Figure 3 A.
  • the discrete charge storage regions 9 may comprise a plurality of vertically spaced apart, conductive (e.g., metal such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or a metal silicide such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or a combination thereof), or semiconductor (e.g., polysilicon) floating gates.
  • the discrete charge storage regions 9 may comprise an insulating charge trapping material, such as silicon nitride segments.
  • the tunnel dielectric 11 of the monolithic three dimensional NAND string is located between charge storage region 9 and the semiconductor channel 1.
  • the blocking dielectric 7 and the tunnel dielectric 11 may be independently selected from any one or more same or different electrically insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, or other insulating materials.
  • the blocking dielectric 7 and/or the tunnel dielectric 1 may include multiple layers of silicon oxide, silicon nitride and/or silicon oxynitride (e.g., ONO layers) or high-k materials such as aluminum oxide, hafnium oxide or combinations thereof.
  • FIG 4 is a top schematic view illustrating a portion of a conventional memory device comprising NAND strings 180.
  • the front side openings (e.g. memory holes) 81 are circular, thereby resulting in cylindrical pillar shaped NAND strings 180.
  • the tunnel dielectric 11, charge storage region 9 and blocking dielectric form concentric rings around the channel 1.
  • the control gate electrode 3 in each device level is generally slab shaped.
  • a back side opening 84 such as a trench, electrically separates adjacent NAND strings 180 from each other. As discussed in more detail below, the back side opening 84 may be used in the manufacture of NAND strings 180 according to some embodiments.
  • FIG. 5A-5E A first embodiment of making a monolithic three dimensional NAND string 180 is illustrated in Figures 5A-5E.
  • a stack 120 of alternating first material layers 121 and second material layers 122 is provided over a major surface 100a of a substrate 100.
  • the first material layers 121 comprise an insulating material and the second material layers 122 comprise sacrificial layers.
  • the first material layers 121 comprise silicon oxide and the second material layers 122 comprise polysilicon or amorphous silicon.
  • the first material layers 121 comprise silicon oxide and the second material layers 122 comprise silicon nitride.
  • the stack 120 comprises a back side opening 84 (e.g. the slit trench shown in Figure 4) and a front side opening 81 (e.g. a cylindrical memory hole as shown in Figures IB and 2B).
  • the method includes forming the front side opening 81 followed by forming a tunnel dielectric 11 and a semiconductor channel 1 in the front side opening 81.
  • an insulating fill material 2 may be provided to fill any remaining space in the front side opening 81 after forming the semiconductor channel 1.
  • the back side opening 84 is then formed in the stack 120 following formation of the channel 1 and the optional insulating fill material 2.
  • the method includes selectively removing (e.g.
  • the method includes forming a metal charge storage layer 99 in the back side opening 84 and in the back side recesses 64.
  • the metal charge storage layer 99 comprises a tungsten layer.
  • the tungsten layer is formed by atomic layer deposition with fluorine-free precursors.
  • the tungsten layer is formed by atomic layer deposition with chlorine based precursors, such as WC1 6 , or with organometallic precursors, such as W(CH 3 ) 6 , or MOCVD precursors such as tungsten carbonyl, WCl 2 (Nt-Bu) 2 py2, W(Nt-Bu) 2 CI ⁇ (Ni-Pr) 2 CNi-Pr 2 ⁇ , W(Nt-Bu) 2 Cl ⁇ (Ni-Pr) CNMe 2 ⁇ , W(Nt-Bu) 2 Cl ⁇ (Ni-Pr) 2 CNEt 2 ⁇ , W(Nt-Bu) 2 Cl ⁇ (NCy) 2 CNEt 2 ⁇ , W(Nt-Bu)
  • the method includes a step of forming discrete charge storage regions 9, such as discrete metal floating gates, in the back side recesses 64 by removing the metal charge storage layer 99 from the back side opening 84 and selectively recessing the metal charge storage layer 99 in the back side recesses 64.
  • the removing and/or recessing steps may be performed in one combined or two discrete selective dry and/or wet etching steps.
  • the discreet charge storage regions 9 comprise tungsten floating gates.
  • the method includes a step of forming a blocking dielectric layer 7 in the back side opening 84 and the back side recesses 64 after forming the discrete charge storage regions 9.
  • Portions of the blocking dielectric 7 in each of the back side recesses 64 have a clam shape with a vertical portion 7c adjacent to the discrete charge storage regions 9 and horizontal portions 7a, 7b adjacent to the first material layers 121.
  • the method includes forming a conductive liner layer 4 (e.g. a titanium nitride or tungsten nitride layer) on the blocking dielectric 7 in the back side opening 84 and in the back side recesses 64. Similar to the blocking dielectric 7, portions of the liner layer 4 in each of the back side recesses 64 have a clam shape with a vertical portion 4c adjacent the discrete charge storage regions 9 and horizontal portions 4a, 4b adjacent the first material layers 121.
  • a conductive liner layer 4 e.g. a titanium nitride or tungsten nitrid
  • the method also includes a step of forming a plurality of control gates 3 in the respective clam shell shaped regions of the blocking dielectric 7 or clam shell shaped regions of the optional liner 4 in the back side recesses 64.
  • the blocking dielectric 7, the liner layer 4 and the control gate layer are removed from the back side opening 84 to form the plurality of control gates 3 in the respective clam shell shaped regions of the blocking dielectric 7 or liner layer 4 in the back side recesses 64.
  • the plurality of control gates 3 comprise tungsten control gates
  • the liner layer 4 comprises a tungsten nitride or titanium nitride layer
  • the first material layers 121 comprise silicon oxide layers
  • the sacrificial layers comprise amorphous silicon, polysilicon or silicon nitride layers.
  • selectively removing the second material layers 121 to form back side recesses 64 between adjacent first material layers 121 comprises completely removing the second material layers 122 to expose the tunnel dielectric 11 in the back side recesses 64.
  • the metal charge storage layer 99 contacts the tunnel dielectric 11 in the back side recesses 64.
  • the front side opening 81 does not have front side recesses between the first material layers 121.
  • the substrate comprises a silicon substrate.
  • the NAND string 180 is located in a monolithic, three dimensional array of NAND strings 180 located over the silicon substrate 100. At least one memory cell in the first device level of the three dimensional array of NAND strings 180 is located over another memory cell in the second device level of the three dimensional array of NAND strings 180.
  • the silicon substrate 100 contains an integrated circuit comprising a driver circuit for the memory device located thereon.
  • Figures 6A-6E illustrate a second embodiment of making a monolithic three dimensional NAND string 180.
  • the NAND string 180 is a hybrid AND string 180. That is, the NAND string of this embodiment includes both metal discrete charge storage regions 9 and a charge storage dielectric layer 59.
  • a stack 120 of alternating first material layers 121 and second material layers 122 is provided over a major surface 100a of a substrate 100.
  • the first material layers 121 comprise an insulating material and the second material layers 122 comprise sacrificial layers.
  • the stack 120 comprises a back side opening 84 and a front side opening 81.
  • the method according to this embodiment includes a step of forming a charge storage dielectric layer 59, such as a silicon nitride layer, in the front side opening 81 before forming the tunnel dielectric 11 and the semiconductor channel 1.
  • a charge storage dielectric layer 59 such as a silicon nitride layer
  • an insulating fill material 2 may be provided to fill any remaining space in the front side opening 81 after forming the semiconductor channel 1.
  • the method includes selectively removing the second material layers 122 through the back side opening 84 to form back side recesses 64 between adjacent first material layers 121.
  • the method includes a step of forming a metal charge storage layer 99 in the back side opening 84 and in the back side recesses 64.
  • selectively removing the second material layers 122 to form back side recesses 64 between adjacent first material layers 121 comprises completely removing the second material layers 122 to expose the charge storage dielectric layer 59 in the back side recesses 64.
  • the metal charge storage layer 99 contacts the charge storage dielectric layer 59 in the back side recesses 64 to form a hybrid device.
  • the method includes a step of forming discrete charge storage regions 9, such as discrete floating gates, in the back side recesses 64 by removing the metal charge storage layer 99 from the back side opening 84 and selectively recessing the metal charge storage layer 99 in the back side recesses 64.
  • the method includes a step of forming a blocking dielectric layer 7 in the back side opening 84 and the back side recesses 64 after forming the discrete charge storage regions 9.
  • portions of the blocking dielectric 7 in each of the back side recesses 64 have a clam shape with a vertical portion 7c adjacent the discrete charge storage regions 9 and horizontal portions 7a, 7b adjacent the first material layers 121.
  • the method includes forming a liner layer 4 on the blocking dielectric 7 in the back side opening 84 and in the back side recesses 64. Similar to the blocking dielectric 7, portions of the liner layer 4 in each of the back side recesses 64 have a clam shape with a vertical portion 4c adjacent the discrete charge storage regions 9 and horizontal portions 4a, 4b adjacent the first material layers 121.
  • the method also includes a step of forming a plurality of control gates 3 in the respective clam shell shaped regions of the blocking dielectric 7 or clam shell shaped regions of the optional liner 4 in the back side recesses 64.
  • the blocking dielectric 7, the liner layer 4 and the control gate layer are removed from the back side opening 84 to form the plurality of control gates 3 in the respective clam shell shaped regions of the blocking dielectric 7 or liner layer 4 in the back side recesses 64.
  • FIG. 7A-7E A third embodiment of making a monolithic three dimensional NAND string 180 is illustrated in Figures 7A-7E. This embodiment is similar to the first embodiment.
  • a barrier layer 16 is formed in the back side recesses 64 prior to forming the control gate layer 99.
  • a second barrier layer 16d is formed over an exposed back surface of the discrete charge storage regions 9 in the back side recesses 64 after forming the discrete charge storage regions 9.
  • a stack 120 of alternating first material layers 121 and second material layers 122 is provided over a major surface 100a of a substrate 100.
  • the first material layers 121 comprise an insulating material and the second material layers 122 comprise sacrificial layers.
  • the first material layers 121 comprise silicon oxide and the second material layers comprise polysilicon or amorphous silicon.
  • the first material layers 121 comprise silicon oxide and the second material layers comprise silicon nitride.
  • the stack 120 comprises a back side opening 84 and a front side opening 81.
  • the front side opening 81 includes a tunnel dielectric 11 and a semiconductor channel 1 formed thereon.
  • an insulating fill material 2 may be provided to fill any remaining space in the front side opening 81 after forming the semiconductor channel 1.
  • the charge storage dielectric layer 59 may also be formed in the opening 81 as described above if a hybrid device is to be formed.
  • the method includes selectively removing the second material layers 122 through the back side opening 84 to form back side recesses 64 between adjacent first material layers 121. Then, in this embodiment, a first barrier layer 6 is formed in the back side opening 84 and in the back side recesses 64.
  • the first barrier layer may comprise a tungsten nitride barrier layer.
  • Portions 16 of the first barrier layer 6 in each of the back side recesses 64 have a clam shape with a vertical portion 16c adjacent to the tunnel dielectric 11 (or the charge storage dielectric layer 59, if present) and horizontal portions 16a, 16b adjacent to the first material layers 121.
  • the metal charge storage layer 99 is then formed on the first barrier layer 6 in the back side opening 84 and in the back side recesses 64. Due to the presence of the barrier layer, the metal charge storage layer 99 may be formed using ALD or CVD with fluorine containing precursors, such as WF6, which typically attacks the thin S1O2 tunnel dielectric 11.
  • the method includes a step of forming discrete charge storage regions 9, such as discrete floating gates, in the back side recesses 64 by removing the metal charge storage layer 99 from the back side opening 84 and selectively recessing the metal charge storage layer 99 in the back side recesses 64.
  • the first barrier layer 6 is also removed, from the back side opening 84 and selectively recessed in the back side recesses 64 in the same or different removal and or recess step(s) as those for metal charge storage layer 99.
  • the first barrier layer 6 has a smaller clam shape with recessed (i.e.
  • the discrete charge storage regions comprise tungsten floating gates 9 located in clam shaped first barrier layer 6 portions 16.
  • a second barrier layer 16d may be formed over an exposed back surface of the discrete charge storage regions 9 in the back side recesses 64.
  • the second barrier layer may be formed, for example, by nitriding the exposed back surface of the discrete charge storage regions 9 by exposing the regions to a nitrogen containing ambient (e.g. a nitrogen containing plasma or high temperature annealing in a nitrogen containing atmosphere).
  • a nitrogen containing ambient e.g. a nitrogen containing plasma or high temperature annealing in a nitrogen containing atmosphere.
  • the discrete charge storage regions 9 are tungsten floating gates and the second barrier layer 16d is tungsten nitride.
  • layer 16d may be formed by depositing a barrier layer into the back side opening 84 and the back side recesses 64 followed by removing and recessing the layer from the respective back side opening 84 and back side recesses 64.
  • the second barrier layer 16d may also comprise tungsten nitride.
  • the discrete charge storage regions 9 comprise tungsten floating gates located between the first 6 and the second 16d tungsten nitride barrier layers.
  • the method includes a step of forming a blocking dielectric layer 7 in the back side opening 84 and the back side recesses 64 after forming the discrete charge storage regions 9.
  • portions of the blocking dielectric 7 in each of the back side recesses 64 have a clam shape with a vertical portion 7c adjacent the discrete charge storage regions 9 and horizontal portions 7a, 7b adjacent the exposed back side horizontal portions of the first material layers 121.
  • the method includes forming a liner layer 4 on the blocking dielectric 7 in the back side opening 84 and in the back side recesses 64.
  • portions of the liner layer 4 in each of the back side recesses 64 have a clam shape with a vertical portion 4c adjacent the discrete charge storage regions 9 or to the optional second barrier layer 16d and horizontal portions 4a, 4b adjacent the first material layers 121.
  • the method also includes a step of forming a plurality of control gates 3 in the respective clam shell shaped regions of the blocking dielectric 7 or clam shell shaped regions of the optional liner 4 in the back side recesses 64.
  • the blocking dielectric 7, the liner layer 4 and the control gate layer are removed from the back side opening 84.
  • the second and third embodiments of the invention form NAND strings 180 shown in Figures 6E and 7E and memory devices comprising a monolithic, three dimensional array of memory devices.
  • the monolithic three dimensional NAND string includes the semiconductor channel 1, at least one end portion of the semiconductor channel 1 extending substantially perpendicular to a major surface 100a of the substrate 100.
  • the string further also includes a plurality of control gate electrodes 3 extending substantially parallel to the major surface 100 of the substrate 100.
  • the plurality of control gate electrodes 3 comprise at least a first control gate electrode 3a located in a first device level and a second control gate electrode 3b located in a second device level located over the major surface 100a of the substrate 100 and below the first device level.
  • the NAND string includes a blocking dielectric 7 located in contact with the plurality of control gate electrodes 3, a tunnel dielectric 11 in contact with the semiconductor channel 1 and a plurality of vertically spaced apart floating gates 9 located between the blocking dielectric 7 and the tunnel dielectric 11.
  • Each floating gate comprises a tungsten portion located between a first nitride layer and a second nitride layer.
  • the first nitride layer comprises a continuous silicon nitride charge storage dielectric layer 59 and the NAND string comprises a hybrid NAND string.
  • the first nitride layer comprises a first tungsten nitride barrier layer 6 having clam shaped portions 16 and the second nitride layer comprises a second tungsten nitride barrier layer 16d.
  • a three dimensional array of memory devices is located over a silicon substrate 100.
  • the array of memory devices comprises an array of vertically oriented NAND strings 180 described above with respect to the prior embodiments in which at least one memory cell in a first device level of the array is located over another memory cell in a second device level and an integrated circuit comprising a driver circuit for the array of memory devices is located on the silicon substrate.

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Abstract

A method of making a three dimensional NAND string includes providing a stack of alternating first material layers and second material layers over a substrate. The method further includes forming a front opening in the stack, forming a tunnel dielectric in the front side opening, forming a semiconductor channel in the front side opening over the tunnel dielectric and forming a back side opening in the stack. The method also includes selectively removing the second material layers through the back side opening to form back side recesses between adjacent first material layers, forming a metal charge storage layer in the back side opening and in the back side recesses and forming discrete charge storage regions in the back side recesses by removing the metal charge storage layer from the back side opening and selectively recessing the metal charge storage layer in the back side recesses.

Description

METHODS OF MAKING THREE DIMENSIONAL NAND DEVICES
FIELD
[0001] The present invention relates generally to the field of semiconductor devices and specifically to three dimensional vertical NAND strings and other three dimensional devices and methods of making thereof.
BACKGROUND
[0002] Three dimensional vertical NAND strings are disclosed in an article by T. Endoh, et. al., titled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate
Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36. However, this NAND string provides only one bit per cell. Furthermore, the active regions of the NAND string is formed by a relatively difficult and time consuming process involving repeated formation of sidewall spacers and etching of a portion of the substrate, which results in a roughly conical active region shape.
SUMMARY
[0003] An embodiment relates to a method of making a three dimensional NAND string including providing a stack of alternating first material layers and second material layers over a substrate. The first material layers include an insulating material and the second material layers include sacrificial layers. The method further includes forming a front side opening in the stack, forming a tunnel dielectric in the front side opening, forming a semiconductor channel in the front side opening over the tunnel dielectric and forming a back side opening in the stack. The method also includes selectively removing the second material layers through the back side opening to form back side recesses between adjacent first material layers, forming a metal charge storage layer in the back side opening and in the back side recesses and forming discrete charge storage regions in the back side recesses by removing the metal charge storage layer from the back side opening and selectively recessing the metal charge storage layer in the back side recesses.
[0004] Another embodiment relates to a monolithic three dimensional N AND string including a semiconductor channel with at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate. The NAND string also includes a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level. The NAND string also includes a blocking dielectric located in contact with the plurality of control gate electrodes, a tunnel dielectric in contact with the
semiconductor channel and a plurality of vertically spaced apart floating gates located between the blocking dielectric and the tunnel dielectric. Each floating gate includes a tungsten portion located between a first nitride layer and a second nitride layer.
[0005] Another embodiment relates to a monolithic, three dimensional array of memory devices located over a silicon substrate including an array of vertically oriented NAND strings in which at least one memory cell in a first device level of the array is located over another memory cell in a second device level and an integrated circuit including a driver circuit for the array of memory devices located on the silicon substrate. At least one vertically oriented NAND string of the array of vertically oriented NAND strings includes: a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate. The plurality of control gate electrodes include at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level located over the major surface of the substrate and below the first device level. The NAND strings also include a blocking dielectric located in contact with the plurality of control gate electrodes, a tunnel dielectric in contact with the semiconductor channel and a plurality of vertically spaced apart floating gates located between the blocking dielectric and the tunnel dielectric. Each floating gate includes a tungsten portion located between a first nitride layer and a second nitride layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figs. 1 A and IB are respectively side cross sectional and top cross sectional views of a conventional NAND string. Figure 1 A is a side cross sectional view of the device along line Y-Y' in Figure IB, while Figure IB is a side cross sectional view of the device along line X-X' in Figure 1 A.
[0007] Figs. 2A and 2B are respectively side cross sectional and top cross sectional views of another conventional NAND string. Figure 2 A is a side cross sectional view of the device along line Y-Y' in Figure 2B, while Figure 2B is a side cross sectional view of the device along line X-X' in Figure 2A.
[0008] Fig. 3 A is a side cross sectional view of a conventional NAND string of an embodiment with a U-shaped channel. Fig. 3B is a side cross sectional view of another conventional NAND string.
[0009] Fig. 4 is a top schematic view of a portion of a conventional memory device comprising NAND strings.
[0010] Figs. 5A-5E illustrate a method of making a NAND string according to an embodiment. [0011] Figs. 6A-6E illustrate a method of making a NAND string according to an embodiment.
[0012] Figs. 7A-7E illustrate a method of making a NAND string according to an embodiment.
DETAILED DESCRIPTION
[0013] Many conventional three dimensional NAND memories store charge in silicon nitride charge storage dielectric layers. The conventional devices suffer from slower erase times, less than desirable data retention and charge spreading. The inventors have realized that low work function conducting floating gates provide better performance than charge storage silicon nitride dielectric layers.
[0014] The inventors have developed methods that allow for the fabrication of metal (e.g., pure metal, such as tungsten, and/or electrically conductive metal alloy, such as tungsten nitride or titanium nitride) floating gate NAND devices. In an embodiment, a sequential deposition-etch sequence is used for selective formation of floating gates in the recesses in sidewalls of a high-aspect ratio three dimensional NAND structure. An advantage of the methods is that the thermal budget constraints used to fabricate floating gates allows a different order of fabrication steps which does not require an additional high temperature annealing typically used in fabricating the tunnel dielectric and polysilicon channel. The additional high temperature anneal tends to lead to poor tunnel dielectric quality which degrades the device program/erase speed. Further, incomplete crystallization of channel causes low drive currents. In the methods discussed below, the floating gates are formed after annealing the tunnel dielectric and the polysilicon channel. An additional advantage is that the NAND strings may be fabricated by only forming recesses from the back side opening (slit trench) rather than forming recesses from both the back side opening and the front side (memory hole) openings. Furthermore, the back side recesses are typically deeper (e.g. 100-500 nm deep) than the shallow front side recesses (e.g. 3-10 nm deep) which improves the ease of forming the metal floating gates through the high aspect ratio openings.
[0015] A monolithic three dimensional memory array is one in which multiple memory levels are formed above a single substrate, such as a semiconductor wafer, with no
intervening substrates. The term "monolithic" means that layers of each level of the array are directly deposited on the layers of each underlying level of the array. In contrast, two dimensional arrays may be formed separately and then packaged together to form a non- monolithic memory device. For example, non-monolithic stacked memories have been constructed by forming memory levels on separate substrates and adhering the memory levels atop each other, as in Leedy, U.S. Pat. No. 5,915,167, titled "Three Dimensional Structure Memory." The substrates may be thinned or removed from the memory levels before bonding, but as the memory levels are initially formed over separate substrates, such memories are not true monolithic three dimensional memory arrays.
[0016] In some embodiments, the monolithic three dimensional NAND string 180 comprises a semiconductor channel 1 having at least one end portion extending substantially perpendicular to a major surface 100a of a substrate 100, as shown in Figures 1 A, 2A and 3B. "Substantially perpendicular to" (or "substantially parallel to") means within 0-10°. For example, the semiconductor channel 1 may have a pillar shape and the entire pillar-shaped semiconductor channel extends substantially perpendicularly to the major surface of the substrate 100, as shown in Figures 1 A, 2A and 3B. In these embodiments, the source/drain electrodes of the device can include a lower electrode 102 provided below the semiconductor channel 1 and an upper electrode 202 formed over the semiconductor channel 1, as shown in Figures lA and 2A. [0017] Alternatively, the semiconductor channel 1 may have a U-shaped pipe shape, as shown in Figure 3A. The two wing portions la and lb of the U-shaped pipe shape
semiconductor channel may extend substantially perpendicular to the major surface 100a of the substrate 100, and a connecting portion lc of the U-shaped pipe shape semiconductor channel 1 connects the two wing portions la, lb extends substantially parallel to the major surface 100a of the substrate 100. In these embodiments, one of the source or drain electrodes 2021 contacts the first wing portion of the semiconductor channel from above, and another one of a source or drain electrodes 2022 contacts the second wing portion of the semiconductor channel 1 from above. An optional body contact electrode (not shown) may be disposed in the substrate 100 to provide body contact to the connecting portion of the semiconductor channel 1 from below. The NAND string's select or access transistors are not shown in Figures 1-3B for clarity.
[0018] In some embodiments, the semiconductor channel 1 may be a filled feature, as shown in Figures 2A, 2B, 3A and 3B. In some other embodiments, the semiconductor channel 1 may be hollow, for example a hollow cylinder filled with an insulating fill material 2, as shown in Figures 1 A- IB. In these embodiments, an insulating fill material 2 may be formed to fill the hollow part surrounded by the semiconductor channel 1. The U-shaped pipe shape semiconductor channel 1 shown in Figure 3 A and or the channel 1 shown in Figure 3B may alternatively be a hollow cylinder filled with an insulating fill material 2, shown in Figures 1A-1B.
[0019] The substrate 100 can be any semiconducting substrate known in the art, such as monocrystalline silicon, IV-IV compounds such as silicon-germanium or silicon-germanium- carbon, III-V compounds, II- VI compounds, epitaxial layers over such substrates, or any other semiconducting or non-semiconducting material, such as silicon oxide, glass, plastic, metal or ceramic substrate. The substrate 100 may include integrated circuits fabricated thereon, such as driver circuits for a memory device.
[0020] Any suitable semiconductor materials can be used for semiconductor channel 1 , for example silicon, germanium, silicon germanium, or other compound semiconductor materials, such as III-V, II- VI, or conductive or semiconductive oxides, etc. The
semiconductor material may be amorphous, polycrystalline or single crystal. The semiconductor channel material may be formed by any suitable deposition methods. For example, in one embodiment, the semiconductor channel material is deposited by low pressure chemical vapor deposition (LPCVD). In some other embodiments, the
semiconductor channel material may be a recrystallized polycrystalline semiconductor material formed by recrystallizing an initially deposited amorphous semiconductor material.
[0021] The insulating fill material 2 may comprise any electrically insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, or other high-k insulating materials.
[0022] The monolithic three dimensional NAND string further comprise a plurality of control gate electrodes 3, as shown in Figures 1 A- IB, 2A-2B, 3 A and 3B. The control gate electrodes 3 may comprise a portion having a strip shape extending substantially parallel to the major surface 100a of the substrate 100. The plurality of control gate electrodes 3 comprise at least a first control gate electrode 3a located in a first device level (e.g., device level A) and a second control gate electrode 3b located in a second device level (e.g., device level B) located over the major surface 100a of the substrate 100 and below the device level A. The control gate material may comprise any one or more suitable conductive or semiconductor control gate material known in the art, such as doped polysilicon, tungsten, tungsten nitride, copper, aluminum, tantalum, titanium, cobalt, titanium nitride or alloys thereof. For example, the control gate material in Figures 1 A, 2 A and 3 A may comprise a conductive metal or metal alloy, such as tungsten and/or titanium nitride, while the control gate material in Figure 3B may comprise doped polysilicon.
[0023] A blocking dielectric 7 is located adjacent to the control gate(s) 3 and may surround the control gate electrodes 3, as shown in Figures 1 A, 2A and 3A. Alternatively, a straight blocking dielectric layer 7 may be located only adjacent to an edge (i.e., minor surface) of each control gate electrode 3, as shown in Figure 3B. The blocking dielectric 7 may comprise a layer having plurality of blocking dielectric segments located in contact with a respective one of the plurality of control gate electrodes 3, for example a first blocking dielectric segment 7a located in device level A and a second blocking dielectric segment 7b located in device level B are in contact with control electrodes 3 a and 3b, respectively, as shown in Figure 3A. Alternatively, the blocking dielectric 7 may be a straight, continuous layer, as shown in Figure 3B, similar to the device described in U.S. Patent Number
8,349,681 issued on January 8, 2013 and incorporated herein by reference in its entirety.
[0024] The monolithic three dimensional NAND string also comprise a charge storage region 9. The charge storage region 9 may comprise one or more continuous layers which extend the entire length of the memory cell portion of the NAND string, as shown in Figure 3B. For example, the charge storage region 9 may comprise an insulating charge trapping material, such as a silicon nitride layer.
[0025] Alternatively, the charge storage region may comprise a plurality of discrete charge storage regions 9, as shown in Figures 1 A, 2 A and 3 A. The plurality of discrete charge storage regions 9 comprise at least a first discrete charge storage region 9a located in the device level A and a second discrete charge storage region 9b located in the device level B, as shown in Figure 3 A. The discrete charge storage regions 9 may comprise a plurality of vertically spaced apart, conductive (e.g., metal such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or a metal silicide such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or a combination thereof), or semiconductor (e.g., polysilicon) floating gates. Alternatively, the discrete charge storage regions 9 may comprise an insulating charge trapping material, such as silicon nitride segments.
[0026] The tunnel dielectric 11 of the monolithic three dimensional NAND string is located between charge storage region 9 and the semiconductor channel 1.
[0027] The blocking dielectric 7 and the tunnel dielectric 11 may be independently selected from any one or more same or different electrically insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, or other insulating materials. The blocking dielectric 7 and/or the tunnel dielectric 1 may include multiple layers of silicon oxide, silicon nitride and/or silicon oxynitride (e.g., ONO layers) or high-k materials such as aluminum oxide, hafnium oxide or combinations thereof.
[0028] Figure 4 is a top schematic view illustrating a portion of a conventional memory device comprising NAND strings 180. In this device, the front side openings (e.g. memory holes) 81 are circular, thereby resulting in cylindrical pillar shaped NAND strings 180. From the view, the tunnel dielectric 11, charge storage region 9 and blocking dielectric form concentric rings around the channel 1. The control gate electrode 3 in each device level is generally slab shaped. A back side opening 84, such as a trench, electrically separates adjacent NAND strings 180 from each other. As discussed in more detail below, the back side opening 84 may be used in the manufacture of NAND strings 180 according to some embodiments.
[0029] A first embodiment of making a monolithic three dimensional NAND string 180 is illustrated in Figures 5A-5E. As illustrated in Figure 5 A, a stack 120 of alternating first material layers 121 and second material layers 122 is provided over a major surface 100a of a substrate 100. The first material layers 121 comprise an insulating material and the second material layers 122 comprise sacrificial layers. In an embodiment, the first material layers 121 comprise silicon oxide and the second material layers 122 comprise polysilicon or amorphous silicon. In an alternative embodiment, the first material layers 121 comprise silicon oxide and the second material layers 122 comprise silicon nitride.
[0030] The stack 120 comprises a back side opening 84 (e.g. the slit trench shown in Figure 4) and a front side opening 81 (e.g. a cylindrical memory hole as shown in Figures IB and 2B). The method includes forming the front side opening 81 followed by forming a tunnel dielectric 11 and a semiconductor channel 1 in the front side opening 81. Optionally, an insulating fill material 2 may be provided to fill any remaining space in the front side opening 81 after forming the semiconductor channel 1. The back side opening 84 is then formed in the stack 120 following formation of the channel 1 and the optional insulating fill material 2.
[0031] As illustrated in Figure 5B, the method includes selectively removing (e.g.
selectively etching) the second material layers 122 through the back side opening 84 to form back side recesses 64 between adjacent first material layers 121. Next, as illustrated in Figure 5C, the method includes forming a metal charge storage layer 99 in the back side opening 84 and in the back side recesses 64. In an embodiment, the metal charge storage layer 99 comprises a tungsten layer. In one embodiment, the tungsten layer is formed by atomic layer deposition with fluorine-free precursors. For example, the tungsten layer is formed by atomic layer deposition with chlorine based precursors, such as WC16, or with organometallic precursors, such as W(CH3)6, or MOCVD precursors such as tungsten carbonyl, WCl2(Nt-Bu)2py2, W(Nt-Bu)2CI{(Ni-Pr)2CNi-Pr2}, W(Nt-Bu) 2Cl{(Ni-Pr) CNMe2}, W(Nt-Bu) 2Cl{(Ni-Pr) 2CNEt2}, W(Nt-Bu) 2Cl{(NCy) 2CNEt2}, W(Nt-Bu)
2NMe2{(Ni-Pr) 2CNi-Pr2}, W(Nt-Bu) 2(NMe2){(Ni-Pr) 2CNMe2}, W(Nt-Bu) 2(N3){(Ni-Pr) 2CNi-Pr2}, W(Nt-Bu) 2{(Ni-Pr)2CNMe2}, [W(Nt-Bu)2Cl{NC(NMe2)2}]2, W(Nt-Bu)
2(N3){NC(NMe2)2}2, [(W(Nt-Bu) 2
Figure imgf000013_0001
2 or other precursors. In this embodiment, preferably no barrier layer formation step (discussed in more detail below in regards to Figures 7A-7E) is needed between forming the back side recesses 64 and forming the tungsten layer because chlorine and organometallic precursors do not attack the Si02 tunnel dielectric 11.
[0032] Then, as illustrated in Figure 5D, the method includes a step of forming discrete charge storage regions 9, such as discrete metal floating gates, in the back side recesses 64 by removing the metal charge storage layer 99 from the back side opening 84 and selectively recessing the metal charge storage layer 99 in the back side recesses 64. The removing and/or recessing steps may be performed in one combined or two discrete selective dry and/or wet etching steps. In an embodiment, the discreet charge storage regions 9 comprise tungsten floating gates.
[0033] Next, as illustrated in Figure 5E, the method includes a step of forming a blocking dielectric layer 7 in the back side opening 84 and the back side recesses 64 after forming the discrete charge storage regions 9. Portions of the blocking dielectric 7 in each of the back side recesses 64 have a clam shape with a vertical portion 7c adjacent to the discrete charge storage regions 9 and horizontal portions 7a, 7b adjacent to the first material layers 121. Optionally, the method includes forming a conductive liner layer 4 (e.g. a titanium nitride or tungsten nitride layer) on the blocking dielectric 7 in the back side opening 84 and in the back side recesses 64. Similar to the blocking dielectric 7, portions of the liner layer 4 in each of the back side recesses 64 have a clam shape with a vertical portion 4c adjacent the discrete charge storage regions 9 and horizontal portions 4a, 4b adjacent the first material layers 121.
[0034] The method also includes a step of forming a plurality of control gates 3 in the respective clam shell shaped regions of the blocking dielectric 7 or clam shell shaped regions of the optional liner 4 in the back side recesses 64. In an embodiment, the blocking dielectric 7, the liner layer 4 and the control gate layer are removed from the back side opening 84 to form the plurality of control gates 3 in the respective clam shell shaped regions of the blocking dielectric 7 or liner layer 4 in the back side recesses 64.
[0035] In an embodiment, the plurality of control gates 3 comprise tungsten control gates, the liner layer 4 comprises a tungsten nitride or titanium nitride layer, the first material layers 121 comprise silicon oxide layers, and the sacrificial layers comprise amorphous silicon, polysilicon or silicon nitride layers. In an embodiment, selectively removing the second material layers 121 to form back side recesses 64 between adjacent first material layers 121 comprises completely removing the second material layers 122 to expose the tunnel dielectric 11 in the back side recesses 64. In this embodiment, the metal charge storage layer 99 contacts the tunnel dielectric 11 in the back side recesses 64. In an embodiment, the front side opening 81 does not have front side recesses between the first material layers 121.
[0036] In an embodiment, the substrate comprises a silicon substrate. The NAND string 180 is located in a monolithic, three dimensional array of NAND strings 180 located over the silicon substrate 100. At least one memory cell in the first device level of the three dimensional array of NAND strings 180 is located over another memory cell in the second device level of the three dimensional array of NAND strings 180. The silicon substrate 100 contains an integrated circuit comprising a driver circuit for the memory device located thereon.
[0037] Figures 6A-6E illustrate a second embodiment of making a monolithic three dimensional NAND string 180. In this embodiment, the NAND string 180 is a hybrid AND string 180. That is, the NAND string of this embodiment includes both metal discrete charge storage regions 9 and a charge storage dielectric layer 59.
[0038] As illustrated in Figure 6A and similar to the previous embodiment, a stack 120 of alternating first material layers 121 and second material layers 122 is provided over a major surface 100a of a substrate 100. The first material layers 121 comprise an insulating material and the second material layers 122 comprise sacrificial layers.
[0039] As in the previous embodiment, the stack 120 comprises a back side opening 84 and a front side opening 81. In contrast to the previous embodiment, the method according to this embodiment includes a step of forming a charge storage dielectric layer 59, such as a silicon nitride layer, in the front side opening 81 before forming the tunnel dielectric 11 and the semiconductor channel 1. Optionally, as in the previous embodiment, an insulating fill material 2 may be provided to fill any remaining space in the front side opening 81 after forming the semiconductor channel 1.
[0040] The remaining steps of the method are the same as in the previous embodiment. That is, as illustrated in Figure 6B, the method includes selectively removing the second material layers 122 through the back side opening 84 to form back side recesses 64 between adjacent first material layers 121. Then, as illustrated in Figure 6C, the method includes a step of forming a metal charge storage layer 99 in the back side opening 84 and in the back side recesses 64. In an embodiment, selectively removing the second material layers 122 to form back side recesses 64 between adjacent first material layers 121 comprises completely removing the second material layers 122 to expose the charge storage dielectric layer 59 in the back side recesses 64. In this embodiment, the metal charge storage layer 99 contacts the charge storage dielectric layer 59 in the back side recesses 64 to form a hybrid device. [0041] Then, as illustrated in Figure 6D, the method includes a step of forming discrete charge storage regions 9, such as discrete floating gates, in the back side recesses 64 by removing the metal charge storage layer 99 from the back side opening 84 and selectively recessing the metal charge storage layer 99 in the back side recesses 64.
[0042] Next, as illustrated in Figure 6E, the method includes a step of forming a blocking dielectric layer 7 in the back side opening 84 and the back side recesses 64 after forming the discrete charge storage regions 9. As in the previous embodiment, portions of the blocking dielectric 7 in each of the back side recesses 64 have a clam shape with a vertical portion 7c adjacent the discrete charge storage regions 9 and horizontal portions 7a, 7b adjacent the first material layers 121. Optionally, the method includes forming a liner layer 4 on the blocking dielectric 7 in the back side opening 84 and in the back side recesses 64. Similar to the blocking dielectric 7, portions of the liner layer 4 in each of the back side recesses 64 have a clam shape with a vertical portion 4c adjacent the discrete charge storage regions 9 and horizontal portions 4a, 4b adjacent the first material layers 121.
[0043] The method also includes a step of forming a plurality of control gates 3 in the respective clam shell shaped regions of the blocking dielectric 7 or clam shell shaped regions of the optional liner 4 in the back side recesses 64. Preferably, the blocking dielectric 7, the liner layer 4 and the control gate layer are removed from the back side opening 84 to form the plurality of control gates 3 in the respective clam shell shaped regions of the blocking dielectric 7 or liner layer 4 in the back side recesses 64.
[0044] A third embodiment of making a monolithic three dimensional NAND string 180 is illustrated in Figures 7A-7E. This embodiment is similar to the first embodiment.
However, in this embodiment, a barrier layer 16 is formed in the back side recesses 64 prior to forming the control gate layer 99. In another embodiment (discussed in more detail below), a second barrier layer 16d is formed over an exposed back surface of the discrete charge storage regions 9 in the back side recesses 64 after forming the discrete charge storage regions 9.
[0045] As illustrated in Figure 7A, a stack 120 of alternating first material layers 121 and second material layers 122 is provided over a major surface 100a of a substrate 100. As in the previous embodiments, the first material layers 121 comprise an insulating material and the second material layers 122 comprise sacrificial layers. In an embodiment, the first material layers 121 comprise silicon oxide and the second material layers comprise polysilicon or amorphous silicon. In an alternative embodiment, the first material layers 121 comprise silicon oxide and the second material layers comprise silicon nitride.
[0046] The stack 120 comprises a back side opening 84 and a front side opening 81. As in the embodiment illustrated in Figures 5A-5E, the front side opening 81 includes a tunnel dielectric 11 and a semiconductor channel 1 formed thereon. Optionally, an insulating fill material 2 may be provided to fill any remaining space in the front side opening 81 after forming the semiconductor channel 1. Optionally, the charge storage dielectric layer 59 may also be formed in the opening 81 as described above if a hybrid device is to be formed.
[0047] As illustrated in Figure 7B, the method includes selectively removing the second material layers 122 through the back side opening 84 to form back side recesses 64 between adjacent first material layers 121. Then, in this embodiment, a first barrier layer 6 is formed in the back side opening 84 and in the back side recesses 64. The first barrier layer may comprise a tungsten nitride barrier layer. Portions 16 of the first barrier layer 6 in each of the back side recesses 64 have a clam shape with a vertical portion 16c adjacent to the tunnel dielectric 11 (or the charge storage dielectric layer 59, if present) and horizontal portions 16a, 16b adjacent to the first material layers 121. The metal charge storage layer 99 is then formed on the first barrier layer 6 in the back side opening 84 and in the back side recesses 64. Due to the presence of the barrier layer, the metal charge storage layer 99 may be formed using ALD or CVD with fluorine containing precursors, such as WF6, which typically attacks the thin S1O2 tunnel dielectric 11.
[0048] Then, as illustrated in Figure 7C, the method includes a step of forming discrete charge storage regions 9, such as discrete floating gates, in the back side recesses 64 by removing the metal charge storage layer 99 from the back side opening 84 and selectively recessing the metal charge storage layer 99 in the back side recesses 64. In an embodiment, the first barrier layer 6 is also removed, from the back side opening 84 and selectively recessed in the back side recesses 64 in the same or different removal and or recess step(s) as those for metal charge storage layer 99. After the step of recessing the first barrier layer 6, the first barrier layer 6 has a smaller clam shape with recessed (i.e. shortened) horizontal portions 16a', 16b' adjacent to the front side of the first material layers 121 while the back horizontal sides of the layers 121 in the recesses are exposed. In an embodiment, the discrete charge storage regions comprise tungsten floating gates 9 located in clam shaped first barrier layer 6 portions 16.
[0049] Optionally, as illustrated in Figure 7D, a second barrier layer 16d may be formed over an exposed back surface of the discrete charge storage regions 9 in the back side recesses 64. The second barrier layer may be formed, for example, by nitriding the exposed back surface of the discrete charge storage regions 9 by exposing the regions to a nitrogen containing ambient (e.g. a nitrogen containing plasma or high temperature annealing in a nitrogen containing atmosphere). In an embodiment, the discrete charge storage regions 9 are tungsten floating gates and the second barrier layer 16d is tungsten nitride. Alternatively, layer 16d may be formed by depositing a barrier layer into the back side opening 84 and the back side recesses 64 followed by removing and recessing the layer from the respective back side opening 84 and back side recesses 64. The second barrier layer 16d may also comprise tungsten nitride. In an embodiment, the discrete charge storage regions 9 comprise tungsten floating gates located between the first 6 and the second 16d tungsten nitride barrier layers.
[0050] Next, as illustrated in Figure 7E, the method includes a step of forming a blocking dielectric layer 7 in the back side opening 84 and the back side recesses 64 after forming the discrete charge storage regions 9. As in the previous embodiments, portions of the blocking dielectric 7 in each of the back side recesses 64 have a clam shape with a vertical portion 7c adjacent the discrete charge storage regions 9 and horizontal portions 7a, 7b adjacent the exposed back side horizontal portions of the first material layers 121. Optionally, as in the previous embodiments, the method includes forming a liner layer 4 on the blocking dielectric 7 in the back side opening 84 and in the back side recesses 64. Similar to the blocking dielectric 7, portions of the liner layer 4 in each of the back side recesses 64 have a clam shape with a vertical portion 4c adjacent the discrete charge storage regions 9 or to the optional second barrier layer 16d and horizontal portions 4a, 4b adjacent the first material layers 121.
[0051] The method also includes a step of forming a plurality of control gates 3 in the respective clam shell shaped regions of the blocking dielectric 7 or clam shell shaped regions of the optional liner 4 in the back side recesses 64. Preferably, the blocking dielectric 7, the liner layer 4 and the control gate layer are removed from the back side opening 84.
[0052] The second and third embodiments of the invention form NAND strings 180 shown in Figures 6E and 7E and memory devices comprising a monolithic, three dimensional array of memory devices. The monolithic three dimensional NAND string includes the semiconductor channel 1, at least one end portion of the semiconductor channel 1 extending substantially perpendicular to a major surface 100a of the substrate 100. The string further also includes a plurality of control gate electrodes 3 extending substantially parallel to the major surface 100 of the substrate 100. The plurality of control gate electrodes 3 comprise at least a first control gate electrode 3a located in a first device level and a second control gate electrode 3b located in a second device level located over the major surface 100a of the substrate 100 and below the first device level. The NAND string includes a blocking dielectric 7 located in contact with the plurality of control gate electrodes 3, a tunnel dielectric 11 in contact with the semiconductor channel 1 and a plurality of vertically spaced apart floating gates 9 located between the blocking dielectric 7 and the tunnel dielectric 11. Each floating gate comprises a tungsten portion located between a first nitride layer and a second nitride layer.
(0053] In the second embodiment shown in Figure 6E, the first nitride layer comprises a continuous silicon nitride charge storage dielectric layer 59 and the NAND string comprises a hybrid NAND string. In the third embodiment shown in Figure 7E, the first nitride layer comprises a first tungsten nitride barrier layer 6 having clam shaped portions 16 and the second nitride layer comprises a second tungsten nitride barrier layer 16d.
[0054] In another embodiment, a three dimensional array of memory devices is located over a silicon substrate 100. The array of memory devices comprises an array of vertically oriented NAND strings 180 described above with respect to the prior embodiments in which at least one memory cell in a first device level of the array is located over another memory cell in a second device level and an integrated circuit comprising a driver circuit for the array of memory devices is located on the silicon substrate.
[0055] Although the foregoing refers to particular preferred embodiments, it will be understood that the invention is not so limited. It will occur to those of ordinary skill in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the invention. All of the publications, patent applications and patents cited herein are incorporated herein by reference in their entirety.

Claims

WHAT IS CLAIMED IS: Claims:
1. A method of making a three dimensional NAND string, comprising:
providing a stack of alternating first material layers and second material layers over a substrate, wherein the first material layers comprise an insulating material and the second material layers comprise sacrificial layers;
forming a front side opening in the stack;
forming a tunnel dielectric in the front side opening;
forming a semiconductor channel in the front side opening over the tunnel dielectric; forming a back side opening in the stack;
selectively removing the second material layers through the back side opening to form back side recesses between adjacent first material layers;
forming a metal charge storage layer in the back side opening and in the back side recesses; and
forming discrete charge storage regions in the back side recesses by removing the metal charge storage layer from the back side opening and selectively recessing the metal charge storage layer in the back side recesses.
2. The method of claim 1 , wherein the metal charge storage layer comprises a tungsten layer and the discreet charge storage regions comprise tungsten floating gates.
3. The method of claim 2, wherein the tungsten layer is formed by atomic layer deposition with fluorine-free precursors.
4. The method of claim 3, wherein the tungsten layer is formed by atomic layer deposition with chlorine based precursors or with organometallic precursors, and wherein no barrier layer formation step occurs between forming the back side recesses and forming the tungsten layer.
5. The method of claim 1, further comprising: forming a blocking dielectric in the back side opening and in the back side recesses after forming the discrete charge storage regions, wherein the blocking dielectric has clam shell shaped regions inside the back side recesses; and
forming a plurality of control gates in the respective clam shell shaped regions of the blocking dielectric in the back side recesses.
6. The method of claim 5, further comprising:
forming a liner layer on the blocking dielectric in the back side opening and in the back side recesses;
forming a control gate layer over the liner layer in the back side opening and in the back side recesses; and
removing the blocking dielectric, the liner layer and the control gate layer from the back side opening to form the plurality of control gates in the respective clam shell shaped regions of the blocking dielectric in the back side recesses.
7. The method of claim 6, wherein the plurality of control gates comprise tungsten control gates, the liner layer comprises a tungsten nitride or titanium nitride layer, the first material layers comprise silicon oxide layers, and the sacrificial layers comprise amorphous silicon, polysilicon or silicon nitride layers.
8. The method of claim 1, wherein selectively removing the second material layers to form back side recesses between adjacent first material layers comprises completely removing the second material layers to expose the tunnel dielectric in the back side recesses, and wherein the metal charge storage layer contacts the tunnel dielectric in the back side recesses.
9. The method of claim 1 , further comprising forming a charge storage dielectric layer in the front side opening prior to forming the tunneling dielectric, such that the tunneling dielectric is located over the charge storage dielectric layer.
10. The method of claim 9, wherein selectively removing the second material layers to form back side recesses between adjacent first material layers comprises completely removing the second material layers to expose the charge storage dielectric layer in the back side recesses, and wherein the metal charge storage layer contacts the charge storage dielectric layer in the back side recesses to form a hybrid device.
11. The method of claim 2, further comprising forming a first barrier layer in the back side recesses prior to forming the metal charge storage layer.
12. The method of claim 11 , wherein:
the first barrier layer comprises a tungsten nitride barrier layer;
forming the discrete charge storage regions in the back side recesses further comprises removing the first barrier layer from the back side opening and selectively recessing the first barrier layer in the back side recesses; and
the discrete charge storage regions comprise tungsten nitride and tungsten floating gates.
13. The method of claim 12, further comprising forming a second barrier layer over an exposed back surface of the tungsten floating gates in the back side recesses.
14. The method of claim 13, wherein:
the second barrier layer is formed by nitriding the exposed back surface of the tungsten floating gates;
the second barrier layer comprises a tungsten nitride barrier layer; and
the discrete charge storage regions comprise tungsten floating gates located between the first and the second tungsten nitride barrier layers.
15. The method of claim 13 , further comprising:
forming a blocking dielectric in the back side opening and in the back side recesses after forming the discrete charge storage regions, wherein the blocking dielectric has clam shell shaped regions inside the back side recesses; and forming a liner layer on the blocking dielectric in the back side opening and in the back side recesses;
forming a control gate layer over the liner layer in the back side opening and in the back side recesses; and
removing the blocking dielectric, the liner layer and the control gate layer from the back side opening to form a plurality of control gates in the respective clam shell shaped regions of the blocking dielectric in the back side recesses.
16. The method of claim 1 , wherein the front side opening does not have front side recesses between the first material layers.
17. The method of claim 1, wherein:
the substrate comprises a silicon substrate;
the NAND string is located in a monolithic, three dimensional array of NAND strings located over the silicon substrate;
at least one memory cell in the first device level of the three dimensional array of NAND strings is located over another memory cell in the second device level of the three dimensional array of NAND strings; and
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon.
18. A monolithic three dimensional NAND string, comprising:
a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate;
a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level located over the major surface of the substrate and below the first device level;
a blocking dielectric located in contact with the plurality of control gate electrodes; a tunnel dielectric in contact with the semiconductor channel; and a plurality of vertically spaced apart floating gates located between the blocking dielectric and the tunnel dielectric;
wherein each floating gate comprises a tungsten portion located between a first nitride layer and a second nitride layer.
19. The monolithic three dimensional NAND string of claim 18, wherein the first nitride layer comprises a continuous silicon nitride charge storage dielectric layer and the NAND string comprises a hybrid NAND string.
20. The monolithic three dimensional NAND string of claim 18, wherein the first nitride layer comprises a first tungsten nitride barrier layer and the second nitride layer comprises a second tungsten nitride barrier layer.
21. A monolithic, three dimensional array of memory devices located over a silicon substrate, comprising an array of vertically oriented NAND strings in which at least one memory cell in a first device level of the array is located over another memory cell in a second device level and an integrated circuit comprising a driver circuit for the array of memory devices located on the silicon substrate, wherein at least one vertically oriented NAND string of the array of vertically oriented NAND strings comprises:
a semiconductor channel, at least one end portion of the semiconductor channel extending substantially perpendicular to a major surface of a substrate;
a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, wherein the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level located over the major surface of the substrate and below the first device level;
a blocking dielectric located in contact with the plurality of control gate electrodes; a tunnel dielectric in contact with the semiconductor channel; and
a plurality of vertically spaced apart floating gates located between the blocking dielectric and the tunnel dielectric; wherein each floating gate comprises a tungsten portion located between a first nitride layer and a second nitride layer.
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