WO2015194817A1 - Transfer impedance amplifier - Google Patents

Abstract

A transfer impedance amplifier, according to the present embodiment, comprises: an inverter having a feedback resistance and amplifying a signal provided to an input side; and a common gate amplifier cascade connected to the inverter so as to amplify an output of the inverter, wherein the signal provided to the input side is feed-forwarded to a gate of the common gate amplifier by interposing a gate resistance.

Description

Transfer impedance amplifier

The present invention relates to a transfer impedance amplifier.

The transfer impedance amplifier refers to an amplifier that converts, amplifies, and outputs a current signal provided as an input to a voltage signal using a transfer impedance of the amplifier. In the conventional transfer impedance amplifier, a trade-off relationship must be sacrificed in order to obtain a high gain, and a gain must be sacrificed when implementing an amplifier operating in a wide bandwidth. Was present. Prior arts of a conventional transfer impedance amplifier include Korean Patent Publication No. 2006-0064981.

This embodiment is to solve the disadvantages of the conventional transfer impedance amplifier described above, it is one of the objects of the present invention to provide a transfer impedance amplifier having a high gain while having a sufficient bandwidth to operate at a high speed.

One of the objectives of this embodiment is to provide a transfer impedance amplifier which is not sensitive to noise coming from the power source.

One of the objectives of this embodiment is to provide a transfer impedance amplifier that maintains high gain without reducing bandwidth and has excellent noise characteristics.

The transfer impedance amplifier according to the present embodiment has a feedback resistor, and includes an inverter for amplifying a signal provided to an input side and a common gate amplifier cascaded with the inverter to amplify the output of the inverter. However, the signal provided to the input side is fed forward to the gate of the common gate amplifier via the gate resistor.

The transfer impedance amplifier according to the present embodiment has a feedback resistor, and includes an inverter for amplifying an input signal and a common source amplifier for amplifying the input signal, wherein the input signal is interposed with a gate resistor. The output signal of the inverter and the output signal of the common source are added at the same node.

According to the present embodiment, both the high gain of the inverter and the wide operating bandwidth of the common gate amplifier can be obtained by the configuration in which the inverter, the common gate amplifier, and the input signal are fed forward. In addition, a low noise sensitivity characteristic can be obtained by the above-described configuration.

According to the present embodiment, it is possible to add signals amplified by the inverter and the common source amplifier, respectively, to obtain high gain, and to obtain good noise characteristics because noise intervening in the input signal is canceled in the output signal. Provided at the same time.

1 is a schematic circuit diagram of a transfer impedance amplifier according to the present embodiment.

2 is a block diagram showing an outline of a transfer impedance amplifier according to the present embodiment.

3 is a schematic circuit diagram of an inverter and a common source amplifier of an embodiment.

4 (a) is a view schematically showing the components of the signal provided to the inverter and the common source amplifier according to the present embodiment, Figure 4 (b) is a signal that the inverter receives the input signal and outputs, 4 (c) is a signal that the common source amplifier receives and outputs an input signal, and FIG. 4 (d) shows a shape of an output signal formed by combining the signals output from the common source amplifier and the inverter.

5 is a diagram comparing the frequency response of the transfer impedance amplifier according to the present embodiment and the conventional transfer impedance amplifier.

6 is a diagram comparing noise sensitivity of a transfer impedance amplifier according to the present embodiment and a conventional transfer impedance amplifier.

7 is a diagram comparing eye diagrams of a transfer impedance amplifier according to the present embodiment and a conventional transfer impedance amplifier.

8 is a diagram comparing the pulse response of the transfer impedance amplifier according to the present embodiment and the conventional transfer impedance amplifier.

Fig. 9 shows the simulation results of the frequency-gain relationship between the transfer impedance amplifier according to the prior art and the transfer impedance amplifier according to the second embodiment.

10 is a noise simulation result of the transfer impedance amplifier according to the prior art and the transfer impedance amplifier according to the second embodiment.

FIG. 11 (a) shows the result of measuring the frequency response by implementing the transfer impedance amplifier according to the second embodiment, and FIG. 11 (b) shows the noise by implementing the transfer impedance amplifier according to the second embodiment as an actual chip. It is a figure which shows a measurement result.

12 (a) is an eye diagram measurement result of chips classified by operation speed, and FIG. 12 (b) is an eye diagram measurement result of chips classified by input current.

Description of the present invention is only an embodiment for structural or functional description, the scope of the present invention should not be construed as limited by the embodiments described in the text. That is, since the embodiments may be variously modified and may have various forms, the scope of the present invention should be understood to include equivalents capable of realizing the technical idea.

On the other hand, the meaning of the terms described in the present application should be understood as follows.

Terms such as "first" and "second" are intended to distinguish one component from another component, and the scope of rights should not be limited by these terms. For example, the first component may be named a second component, and similarly, the second component may also be named a first component.

When a component is referred to as being "above" or "on" another component, it should be understood that another component may be present, although it may be directly above the other component. On the other hand, when a component is said to be "in contact" with another component, it should be understood that there is no other component in between. On the other hand, other expressions describing the relationship between the components, such as "between" and "immediately through", "between" and "immediately between" or "neighboring to" and "on" Direct neighbor "and so on.

Singular expressions should be understood to include plural expressions unless the context clearly indicates otherwise, and terms such as "include" or "have" refer to features, numbers, steps, operations, components, parts, or parts thereof described. It is to be understood that the combination is intended to be present, but not to exclude in advance the possibility of the presence or addition of one or more other features or numbers, steps, operations, components, parts or combinations thereof.

Each step may occur differently from the stated order unless the context clearly dictates the specific order. That is, each step may occur in the same order as specified, may be performed substantially simultaneously, or may be performed in the reverse order.

The drawings referred to for describing the embodiments of the present disclosure are intentionally exaggerated in size, height, thickness, etc. for ease of explanation and easy understanding, and are not to be enlarged or reduced in proportion. In addition, any component illustrated in the drawings may be intentionally reduced in size, and other components may be intentionally enlarged in size.

All terms used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. Terms such as those defined in the commonly used dictionaries should be construed to be consistent with the meanings in the context of the related art and should not be construed as having ideal or overly formal meanings unless expressly defined in this application. .

First embodiment

Hereinafter, with reference to the accompanying drawings will be described a first embodiment of the present invention. 1 is a schematic circuit diagram of a transfer impedance amplifier according to the present embodiment. Referring to FIG. 1, the transfer impedance amplifier according to the present embodiment includes an inverter 100 and a common gate amplifier 200, and the inverter and the common gate amplifier are cascaded and connected to an input signal input to the inverter. (i _in ) is fed through the gate resistor Rg to the gate of the NMOS Q3 of the amplifier of the common gate. For example, the input signal input to the inverter _(in i) may be a signal provided by the photodiode, a laser diode that detects a light signal, a laser signal output corresponding to the current thereto.

The inverter 100 is connected to an output terminal having a PMOS transistor Q1 having a source connected to a supply power supply (Vdd) and an output terminal having drains of NMOS transistors Q2 and Q1 and Q2 having a source connected to a ground power source, and an input terminal having a gate of Q1 and Q2 connected thereto. It includes a feedback resistor (Rf) is connected to the other end.

If the voltage gain, which is the ratio of the output voltage to the input voltage in the inverter not including the feedback resistor Rf, is -A (A >> 1), the inverter including the feedback resistor Rf is applied to the input current i _in . The ratio of the output voltage vo is approximated by the following equation. Therefore, in the inverter having a feedback resistor, the output voltage gain with respect to the input current can be controlled by adjusting the feedback resistor value Rf.

The common gate amplifier 200 is connected to the inverter 100 and the cascade (cascade) receives the output signal of the inverter is applied to the source of the transistor Q3, and outputs a voltage signal (v _out) as the drain of Q3. In addition, the current signal i _in is feed-forwarded through the gate resistor Rg to the gate of Q3.

Gate resistance Rg reduces parasitic ringing due to input current. The parasitic oscillation may occur due to the gate capacitance of Q3 and the inductance of the wiring line.When the parasitic oscillation occurs, the transistor is not turned on or off quickly, so it is difficult to secure a sufficient operating speed, and additional current is caused by the current flowing between the drain sources. Power consumption occurs. The parasitic oscillation can be attenuated by placing a gate resistance (Rg) of several ohms to several hundred ohms, so it can be turned on / off at a higher speed than when the gate resistor is not disposed, thereby obtaining a high operating frequency and a large bandwidth. Can be.

Since the common gate amplifier according to the present embodiment can operate at a high speed and has a wide bandwidth, the tradeoff between the gain and the bandwidth of the inverter being cascaded with the inverter can be solved, thereby increasing the gain and increasing the bandwidth. As can be seen in the simulation examples described later, the noise sensitivity is not significantly different from that of the conventional inverter transfer impedance amplifier.

Second embodiment

2 is a block diagram showing an outline of a transfer impedance amplifier according to the present embodiment. In describing the present embodiment, the same or similar parts as the first embodiment may be omitted for the sake of brevity and clarity.

Referring to FIG. 2, the transfer impedance amplifier according to the present embodiment has a feedback resistor Rf, an inverter 100 that amplifies an input signal, and a common source amplifier 300 that amplifies the input signal. Wherein, the input signal is provided to the gate of the common source amplifier via the gate resistor (Rg), the output signal of the inverter and the output signal of the common source amplifier is added at the same node (n).

Passing the input signal _(in i) provided in the amplifier may be a signal provided to detect the light of the photodiode, a certain wavelength band, a laser diode, such as the above-described first example of the current. Inverter 100 is similar to the inverter of the first embodiment described above. Therefore, description of overlapping portions will be omitted for the sake of brevity of the present embodiment.

The transfer impedance amplifier is supplied with a single ended output signal, and has a low pass filter (LPF) and single ended output signal and a single ended output that pass only low-frequency signals of a single ended output signal. and a differential amplification stage 400 including a differential amplifier 410 that receives a single ended output signal and provides a differential signal (v _o +, v _o- ) that amplifies the difference between the two signals. .

The single-ended output signal is vulnerable to noise, but the differential signal suppresses amplification of the noise flowing into the common mode and amplifies the differential signal component through the differential amplification process. The differential signal output from the differential amplification stage _{(400) (v o +,} v o -) to which is advantageous in that the noise terms to perform the subsequent signal processing.

Differential amplifier 400 may utilize a variety of configurations, such as a differential amplifier having a common source amplifier pair connected to the source, a differential amplifier using one or more operational amplifier (OP AMP). In addition, in the differential amplification stage 400 of the present embodiment, there is no limitation in using other differential amplifiers not illustrated.

3 is a schematic circuit diagram of an inverter 100 and a common source amplifier 300 of an embodiment. Referring to FIG. 3, the configuration of the inverter 100 is the same as that shown in FIG. 1, and thus a detailed description thereof will be omitted.

The common source amplifier 300 has an input signal i _in through a load resistor R _L connected at one end to a supply potential Vdd and at the other end connected to a drain of the NMOS transistor Q3, and a gate resistor Rg. Has an NMOS transistor Q3 having a gate and a source electrically connected to a ground potential, and an output node of the inverter 100 and an output node of the common source amplifier 300 are electrically connected.

The common source amplifier 300 receives an input signal through the gate resistor Rg to suppress parasitic oscillation as described above. Transistor Q3 is controlled by conducting a signal provided to its gate, thereby controlling the current flowing through the load resistor R _L. The common source amplifier 300 provides a voltage formed across the load resistor R _L as an output voltage. The gain (-A2) of the common source amplifier 300 may be set by adjusting the load resistance value, and the gain increases as the load resistance value increases.

FIG. 4A is a diagram schematically showing components of signals provided to the inverter 100 and the common source amplifier according to the present embodiment. Referring to Fig. 4A, the signal s is a signal for the purpose of amplification. The signal n is a noise component included _{in the} input signal i _in . The noise component n shown in this figure is for illustrating the noise in outline, and is not a periodic signal as shown, and the actual noise has a characteristic that its amplitude and frequency are random.

4B is a signal that the inverter 100 receives and outputs the input signal shown in FIG. 4A. Referring to FIG. 4B, an inverter having a feedback resistor Rf amplifies an input signal with a preset gain −A1. The output signal S _I of the inverter has a phase difference of 180 degrees with the phase of the input signal s, so the minus sign is indicated in the gain. Inverter 100 forms a signal having a signal component S _I (s) and the opposite phase amplifies the signal component (s) that are the object of amplification of the input signal. However, the inverter 100 amplifies the noise component (n) included in the input signal to form a N _I signal, but the N _I signal is in phase with the noise component (n) of the input signal (i _in ) because the phase is not reversed. relationship in phase.

4 (c) is a signal that the common source amplifier 300 receives and outputs the input signal shown in FIG. 4 (a). Referring to FIG. 4C, the common source amplifier amplifies the input signal with a preset gain, -A2. The output signal of the common source amplifier has a phase difference of 180 degrees from the phase of the input signal, so the minus sign is indicated in the gain. Accordingly, the common source amplifier 300 amplifies the signal component s, which is the purpose of amplification, from the input signal to form an S _S signal having an opposite phase to the signal component s. The common source amplifier 300 amplifies the noise component included in the signal to form a signal _S N, _S N signal, unlike the inverter 100 does not phase inversion. Therefore, the phase of the N _S signal is 180 degrees out of phase with the phase of the noise component n of the input signal i _in .

FIG. 4D is a diagram illustrating a modified form of an output signal Vout formed by adding signals output from the common source amplifier 300 and the inverter 100. Inverter 100 is amplified by the formation of a by the signal component S _I and the common source amplifier 300 amplifies the signal component S _S formed has no phase difference with each other. Therefore, when the output node of the common source amplifier 300 and the output node of the inverter 100 are formed as a single node, the two signal components are combined to form an S component.

The noise component N _I formed by amplifying the inverter 100 and the signal component N _S formed by amplifying the common source amplifier 300 are out of phase with a 180 degree phase difference from each other. After amplifying the noise components n included _{in the} input signal i _in with a predetermined gain, and then combining the output signals including them at the same node, the two signals N _I and N _S cancel each other out. Therefore, the noise component is canceled and only the signal component s is amplified in the output signal of the transfer impedance amplifier according to the present embodiment as shown in Fig. 4 (d).

As described above the gain of the common source amplifier 300 can be controlled by adjusting the load resistance R _L value, and the gain of the inverter 100 is the resistance value of the feedback resistor (Rf), as described in equation (1) Can be controlled by adjusting. In an ideal case, if the gain value of the common source amplifier 300 and the gain value of the inverter 100 are controlled to be the same, noise components included in the output signal Vout may be removed, and the inverter 100 and the common source amplifier 300 may be removed. Each gain is summed up to a gain of + 6dB.

According to the present embodiment, as shown in FIG. 4, the noise component can be removed, thereby reducing noise sensitivity at an input terminal of an optical communication circuit or a laser radar in which the transfer impedance amplifier according to the present embodiment is used. Furthermore, according to the present embodiment, not only can the noise component be canceled, but also the signal component is amplified by the inverter and the common source amplifier and then summed at the output node, so that it is further amplified by about twice the gain (+6 dB). .

The transfer impedance amplifier according to the embodiments described above may be used at a receiving end of an optical communication, a laser radar, or the like in which a conventional transfer impedance is utilized.

Simulation and Experimental Example

5 is a diagram comparing the frequency response of the transfer impedance amplifier according to the first embodiment and the conventional transfer impedance amplifier. As shown in FIG. 5, the gain of the transfer impedance amplifier according to the present embodiment is 79.79db, which is approximately 4db increased compared to the gain of the conventional transfer impedance amplifier 75.8db, and the -3db cutoff frequency is also increased to the existing 892MHz. It can be seen that it is 1.04 GHz which is increased by approximately 150 MHz. That is, it can be seen that the transfer impedance amplifier according to the present embodiment has improved bandwidth characteristics and improved gain as compared with the conventional transfer impedance amplifier.

6 is a diagram comparing noise sensitivity of a transfer impedance amplifier according to the present embodiment and a conventional transfer impedance amplifier. As shown in FIG. 6, the noise sensitivity curve of the transfer impedance amplifier according to the related art and the noise sensitivity curve of the transfer impedance amplifier according to the present embodiment are not significantly different as shown. As shown in the square box, the noise sensitivity characteristic of the conventional transmission impedance amplifier in the constant frequency band is -26.2dbm, but the noise sensitivity characteristic of the transmission impedance amplifier according to the present embodiment is -26.5dbm, and the difference is only 0.5dbm. It can be seen that the noise sensitivity characteristic of the transfer impedance amplifier according to the present embodiment does not significantly deteriorate.

7 is a diagram comparing eye diagrams of a transfer impedance amplifier and a conventional transfer impedance amplifier according to the present embodiment, and FIG. 8 is a view comparing pulse response of the transfer impedance amplifier and the conventional transfer impedance amplifier according to the present embodiment. 8A illustrates a response to a pulse having a separation period of 2 ns and a pulse width of 2 ns, and FIG. 8B illustrates a response to a pulse having a separation period of 2 ns and a pulse width of 2 ns.

Referring to FIG. 7, when looking at the eye diagram of the conventional transfer impedance amplifier illustrated in FIG. 7, it can be seen that an overshoot occurs as shown by a circle during data transition. However, in the eye diagram of the transfer impedance amplifier according to the present embodiment shown below, the overshoot does not occur, and it can be confirmed that the opening diagram has a larger opening area than the eye diagram of the conventional transfer impedance amplifier.

In addition, when a pulse input is applied as shown at the top of Figs. 8A and 8B, the conventional transfer impedance amplifier is overshooted as shown in a circle. However, the transfer impedance amplifier according to the present embodiment can be seen that the overshoot is significantly reduced as shown below.

As described above, it can be seen that the transfer impedance amplifier according to the present embodiment improves gain characteristics and bandwidth characteristics while maintaining similar noise sensitivity compared to the prior art, as can be seen in the eye diagram and the pulse response curve. We can see that the overshoot for the response is significantly reduced.

9 is a diagram showing a simulation result of the frequency-gain relationship between the transfer impedance amplifier according to the prior art and the transfer impedance amplifier according to the second embodiment. The gain change according to the frequency change of the conventional transfer impedance amplifier is the following curve, and the result according to the present embodiment is the above curve. As shown, although the transfer impedance amplifier according to the present embodiment has a 20 MHz wider bandwidth than the 700 MHz bandwidth of the transfer impedance amplifier according to the prior art, it can be seen that there is a gain increase of 6 dB compared with the prior art.

10 is a noise simulation result of a transfer impedance amplifier according to the related art and a transfer impedance amplifier according to a second embodiment. The spectral density of the noise current of the conventional transfer impedance amplifier is illustrated by connecting black spots, and the result of the present example is illustrated by connecting white rhombuses. As shown, the spectral density of the noise current of the transfer impedance amplifier according to the present embodiment is lower than the spectral density of the noise current of the prior art in all frequency bands, and thus it is confirmed that the noise characteristics are superior to those of the prior art.

FIG. 11 (a) shows the result of measuring the frequency response by implementing the transfer impedance amplifier according to the second embodiment, and FIG. 11 (b) shows the noise by implementing the transfer impedance amplifier according to the second embodiment as an actual chip. It is a figure which shows a measurement result. 11 (a) and 11 (b) demonstrate the simulation results. In particular, it can be seen from Figure 11 (b) that the noise spectral density measurement results in excellent noise performance of 6.4pA / sqrt (Hz), which is expected when the optical response of 10-12 BER and 0.9A / W, It can be seen that it has a very high sensitivity of -28.7 dBm.

12 (a) and 12 (b) are the eye diagrams (eye-diagram) measured using the actual chip implemented, Figure 12 (a) is the eye diagram measurement results of chips classified by operation speed 12 (b) is an eye diagram measurement result of chips classified by input current. 12 (a) and 12 (b), the chip implemented according to the present embodiment shows a high operating speed up to 1.3 Gb / s and has a wide dynamic range characteristic of an input current of 5uApp to 100uApp. Can be.

Although described with reference to the embodiments shown in the drawings to aid the understanding of the present invention, this is an embodiment for the implementation, it is merely exemplary, those skilled in the art from various modifications and equivalents therefrom It will be appreciated that other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the appended claims.

Included above

Claims (15)

1. An inverter having a feedback resistor and amplifying the signal provided to the input side; And

   A common gate amplifier cascaded with the inverter to amplify the output of the inverter;

   And a signal provided to the input side is fed forward to a gate of the common gate amplifier via a gate resistor.
2. The method of claim 1,

   The transfer impedance amplifier,

   A transfer impedance amplifier that outputs a voltage signal by receiving a photocurrent as an input.
3. The method of claim 1,

   The gate resistor attenuates parasitic oscillations at the gate of the common gate amplifier.
4. The method of claim 1,

   The inverter,

   A P type metal oxide semiconductor field effect transistor (P MOS FET) having a source connected to the supply and a N type MOS FET having a source connected to the reference supply,

   And the feedback resistor is electrically connected at one end to the drain of the P-type MOSFET and the drain of the N-type MOSFET, and electrically connected at the other end to the gate of the P-type MOSFET and the gate of the N-type MOSFET.
5. The method of claim 1,

   The common gate amplifier includes an NMOS transistor,

   The NMOS transistor

   A source receiving the output from the inverter,

   A drain providing an output signal, and

   A transfer impedance amplifier comprising a gate that receives a signal forwarded through a gate resistor.
6. The method of claim 1,

   The transfer impedance amplifier is disposed at an input terminal of an optical communication circuit and an input terminal of a laser radar.
7. An inverter having a feedback resistor and amplifying the input signal; And

   Including a common source amplifier (common source 7mplifier) for amplifying the input signal,

   And the input signal is provided to a gate of the common source amplifier via a gate resistor, and the output signal of the inverter and the output signal of the common source are added at the same node.
8. The method of claim 7, wherein

   The transfer impedance is

   And a gain of the inverter plus a gain of the common source amplifier.
9. The method of claim 7, wherein

   The output signal of the inverter is:

   A component in which the input signal is phase inverted and amplified, and a component in which noise intervening in the input signal is amplified without phase inversion,

   The output signal of the common source amplifier is:

   And a component amplified by the phase signal inverted and amplified by the phase inverted noise.
10. The method of claim 9,

    The transfer impedance amplifier,

    And an output signal of the inverter and an output signal of the common source amplifier are added at the same node so that the components due to the noise are mutually canceled.
11. The method of claim 9,

    The transfer impedance amplifier,

    And an output signal of the inverter and an output signal of the common source amplifier are added at the same node so that components of the input signal are added to each other.
12. The method of claim 7, wherein

    The gain of the inverter

    A transfer impedance amplifier, wherein the gains of the common source amplifier are set equal to each other.
13. The method of claim 7, wherein

    The common source amplifier includes a load resistor connected to a supply potential, and an NMOS transistor having one electrode and the other electrode electrically connected to the load resistor and the ground potential, respectively, and the gain of the common source amplifier determines a resistance value of the load resistor. Adjust the settings,

    And a gain of the inverter is set by adjusting the feedback resistance value.
14. The method of claim 7, wherein

    The transfer impedance amplifier further includes an amplification stage for amplifying the output signal of the transfer impedance amplifier,

    The amplification stage is:

    A low pass filter configured to receive the output signal and pass low frequency components;

    Receiving the output signal of the transfer impedance amplifier at one input and receiving the output signal of the low pass filter at another input to amplify a difference between the output signal of the transfer impedance amplifier and the output signal of the low pass filter Transfer impedance amplifiers including differential amplifiers.
15. The method of claim 7, wherein

    The transfer impedance amplifier is disposed at an input terminal of an optical communication circuit and an input terminal of a laser radar.

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