WO2015185017A1 - Storage apparatus, storage system, storage apparatus controlling method - Google Patents

Storage apparatus, storage system, storage apparatus controlling method Download PDF

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Publication number
WO2015185017A1
WO2015185017A1 PCT/CN2015/080891 CN2015080891W WO2015185017A1 WO 2015185017 A1 WO2015185017 A1 WO 2015185017A1 CN 2015080891 W CN2015080891 W CN 2015080891W WO 2015185017 A1 WO2015185017 A1 WO 2015185017A1
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WIPO (PCT)
Prior art keywords
storage apparatus
deep sleep
sleep mode
enter
port
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PCT/CN2015/080891
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French (fr)
Inventor
Li-Chun Tu
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MediaTek Inc
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MediaTek Inc
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Priority to US14/905,971 priority Critical patent/US20160154454A1/en
Priority to CN201580001862.9A priority patent/CN105531681A/en
Publication of WO2015185017A1 publication Critical patent/WO2015185017A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3268—Power saving in hard disk drive
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0625—Power saving in storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G06F3/0634—Configuration or reconfiguration of storage systems by changing the state or mode of one or more devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4418—Suspend and resume; Hibernate and awake
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to a storage apparatus, a storage system and a storage apparatus controlling method, and particularly relates to a storage apparatus, a storage system and a storage apparatus controlling method which can enter a deep sleep mode.
  • a conventional storage apparatus typically has two operation modes: a normal mode and a standby mode.
  • a normal mode data stored in the storage apparatus can be accessed (i.e. read or write) .
  • the standby mode data stored in the storage apparatus is kept but can’t be accessed. If the storage apparatus exits the standby mode, the storage apparatus can immediately enter the normal mode.
  • the storage apparatus in order to control the storage apparatus to immediately enter the normal mode after exits the standby mode, some devices in the storage apparatus must be kept active in the standby mode. Accordingly, the storage apparatus keep consuming power in the standby mode and may cause leakage currents due to the active devices.
  • One objective of the present disclosure is to provide a storage apparatus and a storage system that can suppress the power consumption and the leakage current.
  • Another objective of the present disclosure is to provide a storage apparatus controlling method and a storage system controlling method that can suppress the power consumption and the leakage current.
  • One implementation of the present disclosure provides a storage apparatus, which is configured to receive an enter instruction to enter a deep sleep mode and receive an awaking instruction to enter a normal mode after exiting the deep sleep mode.
  • the storage apparatus keeps data stored therein in the deep sleep mode, and the storage apparatus can be normally accessed in the normal mode. If the storage apparatus is controlled to enter the normal mode while in the deep sleep mode, the storage apparatus enters the normal mode after the storage apparatus exits the deep sleep mode for a recovery time interval.
  • a storage system which comprises: a storage apparatus and a control apparatus configured to control a storage apparatus to enter a deep sleep mode via the control apparatus and configured to control the storage apparatus to enter a normal mode after exiting the deep sleep mode.
  • the storage apparatus keeps data stored therein in the deep sleep mode and the storage apparatus can be normally accessed in the normal mode. If the storage apparatus is controlled to enter a normal mode in the deep sleep mode, the control apparatus controls the storage apparatus to enter the normal mode after the storage apparatus exits the deep sleep mode for a recovery time interval.
  • Storage apparatus controlling methods can be acquired in view of above-mentioned implementations. Detail steps thereof are omitted for brevity here.
  • the storage apparatus can operate in a deep sleep mode that consumes less power and generates less leakage currents than a conventional standby mode. Further, methods for controlling the storage apparatus to the normal mode after exiting the deep sleep mode can ensure that the storage apparatus can be correctly accessed.
  • FIG. 1 is a block diagram illustrating a storage system according to one implementation of the present disclosure.
  • FIG. 2A is a block diagram illustrating detail structures for a storage system according to one implementation of the present disclosure.
  • FIG. 2B is a schematic diagram illustrating signal applied to the storage system depicted in FIG. 2A.
  • FIG. 3-5 are schematic diagrams illustrating methods for controlling the storage apparatus to exit the deep sleep mode and enter the normal mode according to one implementation of the present disclosure.
  • FIG. 6A and FIG. 6B are schematic diagrams illustrating the operation for separating the power up operation and the refresh operation, according to one implementation of the present disclosure.
  • FIG. 1 is a block diagram illustrating a storage system according to one implementation of the present disclosure.
  • the storage system 100 comprises a control apparatus 101 and a storage apparatus 103.
  • the control apparatus 101 controls the storage apparatus 103 to enter a deep sleep mode via an enter instruction. In such deep sleep mode, the storage apparatus keeps information already stored therein. Also, if the storage apparatus 103 is controlled to enter a normal mode while in the deep sleep mode via an awakening instruction from the control apparatus, the storage apparatus 103 enters the normal mode after the storage apparatus 103 exits the deep sleep mode for a recovery time interval. Fewer devices in such storage apparatus are active, since the storage apparatus does not immediately enter the normal mode after exists the deep sleep mode. By this way, less power consumption is needed and the above mentioned leakage current issue can be solved.
  • FIG. 2A is a block diagram illustrating detail structures for a storage system according to one implementation of the present disclosure.
  • the structure of FIG. 2A has been disclosed in above-mentioned earlier US application with application number 14/139951.
  • the processor 201, transceiving interface 203 and the storage apparatus 103 in FIG. 2A of the present disclosure correspond to the processor 102, the media peripheral interface 106 and the peripheral device 104 in FIG. 1 of the earlier US application with application number 14/139951.
  • the control apparatus 101 comprises a processor 201 and a transceiving interface 203.
  • the transceiving interface 203 may be implemented as a hardware module and is coupled between the processor 201 and the storage apparatus 103 for communication therebetween.
  • the processor 201, the storage apparatus 103 and the transceiving interface 203 are enclosed in a single module (or a package) as a system-in-package (but not limited thereto) .
  • the storage apparatus 103 may be a PSRAM, a FLASH memory, and so on.
  • the transceiving interface 203 can be any interface matching the storage apparatus.
  • the storage apparatus 103 and the transceiving interface 203 respectively comprise a clock port CLK, a plurality of data ports (labeled DATA) , a data strobe port DQS, and a data mask signal port DM.
  • FIG. 2B is a schematic diagram illustrating a write operation for the storage system 100, please refer to FIG. 2A and FIG. 2B together to understand the present disclosure for more clear.
  • the clock port CLK is operative to transfer a clock signal (also designated as CLK) to the storage apparatus 103.
  • the data ports (DATA) are provided for command transfer to the storage apparatus 103 and for data transfer to and from the storage apparatus 103.
  • the data strobe port DQS is operative to transfer a data strobe signal (also designated as DQS) to or from the storage apparatus 103 according to an instruction that the processor 201 issues to the storage apparatus 103. For example, a data strobe signal DQS is transferred ‘to’ the storage apparatus 103 when a ‘write’ instruction is issued by processor 201, and, a data strobe signal DQS is transferred ‘from’ the storage apparatus 103 when a ‘read’ instruction is issued by the processor 201.
  • the data mask signal port DM is optional (e.g., depending on the bit number of the data ports DATA) , and operative to transfer a data mask signal (also designated as DM) to the storage apparatus 103 to mask particular transition edges of the data strobe signal DQS accordingly.
  • a data mask signal also designated as DM
  • the command information transferred via the data ports DATA is captured.
  • data transferred via the data ports DATA it is captured according to rising edges and falling edges of the data strobe signal DQS when the data mask signal DM is disabled.
  • the data transferred via the data ports Data is captured according to only particular transition edges (e.g. only H ⁇ L transition edges, or, only L ⁇ H transition edges) of the data strobe signal DQS.
  • the clock port CLK is not limited to providing a single connection terminal.
  • the clock port CLK may provide a differential pair and the clock signal CLK may be a differential signal.
  • the data strobe port DQS is not limited to providing a single connection terminal.
  • the data strobe port DQS may provide a differential pair and the data strobe signal DQS may be a differential signal.
  • the transceiving interface 203 and the storage apparatus 103 can further respectively comprise an access indicating port CE for an access indicating signal (also designated as CE) , which indicates at least one accessing operation will be applied to the storage apparatus 103.
  • an access indicating signal CE comprises a first logic value (high logic value in this implementation) and a second logic value (low logic value in this implementation) . If the access indicating signal CE transits from the first logic value to the second logic value, it means at least one accessing operation will be performed to the storage apparatus 103. Please note, such access indicating signal CE is optional.
  • FIG. 2B is a schematic diagram illustrating a write operation for the storage system 100, and the detail descriptions thereof are disclosed in the earlier US application with application number 14/139951. Additionally, other detail descriptions for the storage system 100 in FIG. 2A are disclosed in the earlier US application with application number 14/139951, thus it is omitted for brevity here. Please note the storage system in FIG. 2A is only an example for explaining. The concept of the present disclosure is not limited to be applied to the storage system in FIG. 2A.
  • the storage apparatus 103 can be controlled by the control apparatus 101 to enter the deep sleep mode. Also, the storage apparatus 103 can be controlled by the control apparatus 101 to exit the deep sleep mode and enters the normal mode.
  • the command for triggering the accessing operation may be wrongly received by the storage apparatus in the deep sleep mode or in the recovery time interval. Therefore, the present disclosure also provides other methods for controlling the storage apparatus to exit the deep sleep mode and to enter the normal mode.
  • FIG. 3-5 are schematic diagrams illustrating methods for controlling the storage apparatus to exit the deep sleep mode and enter the normal mode according to one implementation of the present disclosure.
  • the control apparatus 101 and the storage apparatus 103 respectively comprises an awakening port AW.
  • the control apparatus 101 applies the awakening port AW to transmit an awakening instruction AI to the storage apparatus 103, to control the storage apparatus 103 to exit the deep sleep mode and enter the normal mode. Since specific ports are assigned to transmit or receive the awakening instruction AI, almost all devices in the storage apparatus 103 can be non-active in the deep sleep mode, thus the power consumption and the leakage current for the storage apparatus 103 can be suppressed. Also, via this mechanism, it can be ensured the awakening instruction AI is successfully received by the storage apparatus 103 even if the storage apparatus 103 is in the deep sleep mode.
  • the control apparatus 101 applies the data strobe port DQS to transmit an awakening instruction AI to the storage apparatus 103, to control the storage apparatus 103 to exit the deep sleep mode and enter the normal mode.
  • the control apparatus 101 gives the storage apparatus 103 a enter instruction to enter the deep sleep mode, and uses an awakening instruction AI particularly corresponding to such instruction to exit the deep sleep mode and enter the normal mode.
  • the control apparatus 101 controls the storage apparatus 103 to exit the deep sleep mode and to enter the normal mode after a transiting timing TT for a predetermined time interval PT.
  • the access indicating signal CE transits from the first logic value to the second logic value at the transiting timing TT.
  • the predetermined time interval PT is larger or equals to the recovery time interval.
  • FIG. 4 can be summarized as: wherein the control apparatus 101 performs the accessing operation to the storage apparatus 103 after a transiting timing for a predetermined time interval, wherein a determining step indicates that at least one access operation will be performed to the storage apparatus at the transiting timing.
  • the control apparatus 101 transmits a dummy accessing command signal (in one implementation, a read command signal) to the storage apparatus 103 after the storage apparatus 103 exits the deep sleep mode. After that, the control apparatus 101 does not access the storage apparatus 103 until the control apparatus 101 receives a response corresponding to the dummy accessing command signal, wherein the response is generated by the storage apparatus 103. By this way, it can be ensured that the storage apparatus 103 is accessed in the normal mode, since the storage apparatus 103 cannot respond the dummy accessing command signal if does not normally operate in the normal mode.
  • a dummy accessing command signal in one implementation, a read command signal
  • the storage apparatus 103 may need to be periodic refreshed such that the data can be kept. Before each refresh operation, the storage apparatus 103 need to be powered up first (still in the deep sleep mode) , and then the refresh operation is performed following the power up operation, as depicted in FIG. 6A.
  • the storage apparatus receives the awakening instruction AI during the power up operation, the total wake up time interval (the time interval for leaving the deep sleep mode and to enter the normal mode) is extremely long since it includes power up time interval and refresh time interval. Accordingly, in one implementation, the power up operation and the fresh operation are separated, as depicted in FIG. 6B. In such case, if the storage apparatus 103 receives the awakening instruction AI during the power up operation, the storage apparatus exits the deep sleep mode and enters the normal mode after the power up operation and before the corresponding refresh rate operation, rather than conventionally perform the corresponding refresh operation after the power up operation.
  • the storage apparatus can exit the deep sleep mode and enter the normal mode after the power up operation, even if receive the awakening instruction AI during the power up operation, thus the issue of long wake up time interval can be avoided.
  • a storage apparatus controlling method can be acquired, which comprises the step of: controlling a storage apparatus to enter a deep sleep mode and controlling the storage apparatus to exit the deep sleep mode and to enter a normal mode; wherein the storage apparatus keeps data stored therein in the deep sleep mode; wherein if the storage apparatus is controlled to enter a normal mode while in the deep sleep mode, the storage apparatus enters the normal mode after the storage apparatus exits the deep sleep mode for a recovery time interval , wherein the storage apparatus can be normally accessed in the normal mode.
  • Such method can be performed by a control apparatus as above-mentioned, but can also be performed by other apparatuses.
  • Other detail steps for the storage apparatus controlling method can be acquired based upon above-mentioned implementations, thus are omitted for brevity here.
  • the storage apparatus can operate in a deep sleep mode that consumes less power and generates less leakage currents than a conventional standby mode. Further, methods for controlling the storage apparatus to exit the deep sleep mode and enter the normal mode can ensure that the storage apparatus can be correctly accessed.

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Abstract

A storage apparatus, which is configured to receive an enter instruction to enter a deep sleep mode and configured to receive an awaking instruction to exit the deep sleep mode and to enter a normal mode. The storage apparatus keeps data stored therein in the deep sleep mode, and the storage apparatus can be normally accessed in the normal mode. If the storage apparatus is controlled to enter the normal mode while in the deep sleep mode, the storage apparatus enters the normal mode after the storage apparatus exits the deep sleep mode for a recovery time interval.

Description

STORAGE APPARATUS, STORAGE SYSTEM, STORAGE APPARATUS CONTROLLING METHOD
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of U.S. Provisional Application No. 62/008,091, filed on June 05, 2014 and U.S. Provisional Application No. 62/035,623, filed on August 11, 2014. Also, this application is a continuation-in-part of applicant’s earlier application, Serial No. 14/139,951, filed Dec 24, 2013 and is included herein by reference.
TECHNICAL FIELD
The present disclosure relates to a storage apparatus, a storage system and a storage apparatus controlling method, and particularly relates to a storage apparatus, a storage system and a storage apparatus controlling method which can enter a deep sleep mode.
BACKGROUND
A conventional storage apparatus typically has two operation modes: a normal mode and a standby mode. In the normal mode, data stored in the storage apparatus can be accessed (i.e. read or write) . On the other hand, in the standby mode, data stored in the storage apparatus is kept but can’t be accessed. If the storage apparatus exits the standby mode, the storage apparatus can immediately enter the normal mode.
However, in order to control the storage apparatus to immediately enter the normal mode after exits the standby mode, some devices in the storage apparatus must be kept active in the standby mode. Accordingly, the storage apparatus keep consuming power in the standby mode and may cause leakage currents due to the active devices.
SUMMARY
One objective of the present disclosure is to provide a storage apparatus and a storage system that can suppress the power consumption and the leakage current.
Another objective of the present disclosure is to provide a storage apparatus controlling method and a storage system controlling method that can suppress the power consumption and the leakage current.
One implementation of the present disclosure provides a storage apparatus, which is configured to receive an enter instruction to enter a deep sleep mode and receive an awaking instruction to  enter a normal mode after exiting the deep sleep mode. The storage apparatus keeps data stored therein in the deep sleep mode, and the storage apparatus can be normally accessed in the normal mode. If the storage apparatus is controlled to enter the normal mode while in the deep sleep mode, the storage apparatus enters the normal mode after the storage apparatus exits the deep sleep mode for a recovery time interval.
Another implementation of the present disclosure discloses a storage system, which comprises: a storage apparatus and a control apparatus configured to control a storage apparatus to enter a deep sleep mode via the control apparatus and configured to control the storage apparatus to enter a normal mode after exiting the deep sleep mode. The storage apparatus keeps data stored therein in the deep sleep mode and the storage apparatus can be normally accessed in the normal mode. If the storage apparatus is controlled to enter a normal mode in the deep sleep mode, the control apparatus controls the storage apparatus to enter the normal mode after the storage apparatus exits the deep sleep mode for a recovery time interval.
Storage apparatus controlling methods can be acquired in view of above-mentioned implementations. Detail steps thereof are omitted for brevity here.
In view of above-mentioned implementations, the storage apparatus can operate in a deep sleep mode that consumes less power and generates less leakage currents than a conventional standby mode. Further, methods for controlling the storage apparatus to the normal mode after exiting the deep sleep mode can ensure that the storage apparatus can be correctly accessed.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the embodiments that are illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 is a block diagram illustrating a storage system according to one implementation of the present disclosure.
FIG. 2A is a block diagram illustrating detail structures for a storage system according to one implementation of the present disclosure.
FIG. 2B is a schematic diagram illustrating signal applied to the storage system depicted in FIG. 2A.
FIG. 3-5 are schematic diagrams illustrating methods for controlling the storage apparatus to exit the deep sleep mode and enter the normal mode according to one implementation of the present disclosure.
FIG. 6A and FIG. 6B are schematic diagrams illustrating the operation for separating the power  up operation and the refresh operation, according to one implementation of the present disclosure.
DETAILED DESCRIPTION
FIG. 1 is a block diagram illustrating a storage system according to one implementation of the present disclosure. As shown in FIG. 1, the storage system 100 comprises a control apparatus 101 and a storage apparatus 103. The control apparatus 101 controls the storage apparatus 103 to enter a deep sleep mode via an enter instruction. In such deep sleep mode, the storage apparatus keeps information already stored therein. Also, if the storage apparatus 103 is controlled to enter a normal mode while in the deep sleep mode via an awakening instruction from the control apparatus, the storage apparatus 103 enters the normal mode after the storage apparatus 103 exits the deep sleep mode for a recovery time interval. Fewer devices in such storage apparatus are active, since the storage apparatus does not immediately enter the normal mode after exists the deep sleep mode. By this way, less power consumption is needed and the above mentioned leakage current issue can be solved.
FIG. 2A is a block diagram illustrating detail structures for a storage system according to one implementation of the present disclosure. The structure of FIG. 2A has been disclosed in above-mentioned earlier US application with application number 14/139951. The processor 201, transceiving interface 203 and the storage apparatus 103 in FIG. 2A of the present disclosure correspond to the processor 102, the media peripheral interface 106 and the peripheral device 104 in FIG. 1 of the earlier US application with application number 14/139951.
As illustrated in FIG. 2A, the control apparatus 101 comprises a processor 201 and a transceiving interface 203. The transceiving interface 203 may be implemented as a hardware module and is coupled between the processor 201 and the storage apparatus 103 for communication therebetween. In some exemplary implementations, the processor 201, the storage apparatus 103 and the transceiving interface 203 are enclosed in a single module (or a package) as a system-in-package (but not limited thereto) . The storage apparatus 103 may be a PSRAM, a FLASH memory, and so on. In addition to implementing a PSRAM interface or a FLASH interface, the transceiving interface 203 can be any interface matching the storage apparatus.
As shown in Fig. 2A, the storage apparatus 103 and the transceiving interface 203 respectively comprise a clock port CLK, a plurality of data ports (labeled DATA) , a data strobe port DQS, and a data mask signal port DM. FIG. 2B is a schematic diagram illustrating a write operation for the storage system 100, please refer to FIG. 2A and FIG. 2B together to understand the present disclosure for more clear.
The clock port CLK is operative to transfer a clock signal (also designated as CLK) to the  storage apparatus 103. The data ports (DATA) are provided for command transfer to the storage apparatus 103 and for data transfer to and from the storage apparatus 103. The data strobe port DQS is operative to transfer a data strobe signal (also designated as DQS) to or from the storage apparatus 103 according to an instruction that the processor 201 issues to the storage apparatus 103. For example, a data strobe signal DQS is transferred ‘to’ the storage apparatus 103 when a ‘write’ instruction is issued by processor 201, and, a data strobe signal DQS is transferred ‘from’ the storage apparatus 103 when a ‘read’ instruction is issued by the processor 201. The data mask signal port DM is optional (e.g., depending on the bit number of the data ports DATA) , and operative to transfer a data mask signal (also designated as DM) to the storage apparatus 103 to mask particular transition edges of the data strobe signal DQS accordingly.
According to the clock signal CLK, the command information transferred via the data ports DATA is captured. As data transferred via the data ports DATA, it is captured according to rising edges and falling edges of the data strobe signal DQS when the data mask signal DM is disabled. When the data mask signal DM is enabled, the data transferred via the data ports Data is captured according to only particular transition edges (e.g. only H→L transition edges, or, only L→H transition edges) of the data strobe signal DQS. Note that the clock port CLK is not limited to providing a single connection terminal. In some implementations, the clock port CLK may provide a differential pair and the clock signal CLK may be a differential signal. Further, note that the data strobe port DQS is not limited to providing a single connection terminal. In some implementations, the data strobe port DQS may provide a differential pair and the data strobe signal DQS may be a differential signal.
The transceiving interface 203 and the storage apparatus 103 can further respectively comprise an access indicating port CE for an access indicating signal (also designated as CE) , which indicates at least one accessing operation will be applied to the storage apparatus 103. Such access indicating signal CE comprises a first logic value (high logic value in this implementation) and a second logic value (low logic value in this implementation) . If the access indicating signal CE transits from the first logic value to the second logic value, it means at least one accessing operation will be performed to the storage apparatus 103. Please note, such access indicating signal CE is optional.
Please note, FIG. 2B is a schematic diagram illustrating a write operation for the storage system 100, and the detail descriptions thereof are disclosed in the earlier US application with application number 14/139951. Additionally, other detail descriptions for the storage system 100 in FIG. 2A are disclosed in the earlier US application with application number 14/139951, thus it is omitted for brevity here. Please note the storage system in FIG. 2A is only an example for explaining. The  concept of the present disclosure is not limited to be applied to the storage system in FIG. 2A.
Please refer to FIG. 1 again. As above-mentioned, the storage apparatus 103 can be controlled by the control apparatus 101 to enter the deep sleep mode. Also, the storage apparatus 103 can be controlled by the control apparatus 101 to exit the deep sleep mode and enters the normal mode. However, the command for triggering the accessing operation may be wrongly received by the storage apparatus in the deep sleep mode or in the recovery time interval. Therefore, the present disclosure also provides other methods for controlling the storage apparatus to exit the deep sleep mode and to enter the normal mode.
FIG. 3-5 are schematic diagrams illustrating methods for controlling the storage apparatus to exit the deep sleep mode and enter the normal mode according to one implementation of the present disclosure. In the implementation of FIG. 3, besides the clock port CLK, the data ports DATA and the data strobe port DQS, the control apparatus 101 and the storage apparatus 103 respectively comprises an awakening port AW. The control apparatus 101 applies the awakening port AW to transmit an awakening instruction AI to the storage apparatus 103, to control the storage apparatus 103 to exit the deep sleep mode and enter the normal mode. Since specific ports are assigned to transmit or receive the awakening instruction AI, almost all devices in the storage apparatus 103 can be non-active in the deep sleep mode, thus the power consumption and the leakage current for the storage apparatus 103 can be suppressed. Also, via this mechanism, it can be ensured the awakening instruction AI is successfully received by the storage apparatus 103 even if the storage apparatus 103 is in the deep sleep mode.
In the implementation of FIG. 4, the control apparatus 101 applies the data strobe port DQS to transmit an awakening instruction AI to the storage apparatus 103, to control the storage apparatus 103 to exit the deep sleep mode and enter the normal mode. In one implementation, the control apparatus 101 gives the storage apparatus 103 a enter instruction to enter the deep sleep mode, and uses an awakening instruction AI particularly corresponding to such instruction to exit the deep sleep mode and enter the normal mode.
As above-mentioned, if the access indicating signal CE transits from the first logic value to the second logic value, it indicates at least one access operation will be performed to the storage apparatus 103. In the implementation of FIG. 5, the control apparatus 101 controls the storage apparatus 103 to exit the deep sleep mode and to enter the normal mode after a transiting timing TT for a predetermined time interval PT. The access indicating signal CE transits from the first logic value to the second logic value at the transiting timing TT. The predetermined time interval PT is larger or equals to the recovery time interval. By this way, it can be ensured that the accessing operations are performed after the recovery time interval (i.e. in the normal mode) , thus can be  normally performed. However, please note other mechanisms can be applied to indicate at least one access operation will be performed to the storage apparatus 103 as well. Therefore, the implementation illustrated in FIG. 4 can be summarized as: wherein the control apparatus 101 performs the accessing operation to the storage apparatus 103 after a transiting timing for a predetermined time interval, wherein a determining step indicates that at least one access operation will be performed to the storage apparatus at the transiting timing.
In another implementation, the control apparatus 101 transmits a dummy accessing command signal (in one implementation, a read command signal) to the storage apparatus 103 after the storage apparatus 103 exits the deep sleep mode. After that, the control apparatus 101 does not access the storage apparatus 103 until the control apparatus 101 receives a response corresponding to the dummy accessing command signal, wherein the response is generated by the storage apparatus 103. By this way, it can be ensured that the storage apparatus 103 is accessed in the normal mode, since the storage apparatus 103 cannot respond the dummy accessing command signal if does not normally operate in the normal mode.
Additionally, if the storage apparatus 103 enters the deep sleep mode, the data stored therein may need to be periodic refreshed such that the data can be kept. Before each refresh operation, the storage apparatus 103 need to be powered up first (still in the deep sleep mode) , and then the refresh operation is performed following the power up operation, as depicted in FIG. 6A.
However, if the storage apparatus receives the awakening instruction AI during the power up operation, the total wake up time interval (the time interval for leaving the deep sleep mode and to enter the normal mode) is extremely long since it includes power up time interval and refresh time interval. Accordingly, in one implementation, the power up operation and the fresh operation are separated, as depicted in FIG. 6B. In such case, if the storage apparatus 103 receives the awakening instruction AI during the power up operation, the storage apparatus exits the deep sleep mode and enters the normal mode after the power up operation and before the corresponding refresh rate operation, rather than conventionally perform the corresponding refresh operation after the power up operation.
In view of above-mentioned implementations, the storage apparatus can exit the deep sleep mode and enter the normal mode after the power up operation, even if receive the awakening instruction AI during the power up operation, thus the issue of long wake up time interval can be avoided.
Please note the above-mentioned control apparatus and the storage apparatus can be independently applied to other devices. Also, other methods for exiting the deep sleep mode besides the above-mentioned implementations can be applied if the storage apparatus enters the deep sleep  mode. Accordingly, in view of above-mentioned implementations, a storage apparatus controlling method can be acquired, which comprises the step of: controlling a storage apparatus to enter a deep sleep mode and controlling the storage apparatus to exit the deep sleep mode and to enter a normal mode； wherein the storage apparatus keeps data stored therein in the deep sleep mode； wherein if the storage apparatus is controlled to enter a normal mode while in the deep sleep mode, the storage apparatus enters the normal mode after the storage apparatus exits the deep sleep mode for a recovery time interval , wherein the storage apparatus can be normally accessed in the normal mode. Such method can be performed by a control apparatus as above-mentioned, but can also be performed by other apparatuses. Other detail steps for the storage apparatus controlling method can be acquired based upon above-mentioned implementations, thus are omitted for brevity here.
In view of above-mentioned implementations, the storage apparatus can operate in a deep sleep mode that consumes less power and generates less leakage currents than a conventional standby mode. Further, methods for controlling the storage apparatus to exit the deep sleep mode and enter the normal mode can ensure that the storage apparatus can be correctly accessed.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (24)

  1. A storage apparatus controlling method, comprising:
    (a) controlling a storage apparatus to enter a deep sleep mode, wherein the storage apparatus keeps data stored therein in the deep sleep mode； and
    (b) controlling the storage apparatus to exit the deep sleep mode and to enter a normal mode, wherein the storage apparatus can be normally accessed in the normal mode；
    wherein if the storage apparatus is controlled to enter the normal mode while in the deep sleep mode, the storage apparatus enters the normal mode after the storage apparatus exits the deep sleep mode for a recovery time interval.
  2. The storage apparatus controlling method of claim 1, wherein the storage apparatus comprises a data port, a data strobe port and an awakening port, wherein the step (b) comprises:
    applying the data port to receive data；
    applying the data strobe port to receive or to transmit a data strobe signal； and
    applying the awakening port to receive an awakening instruction, to control the storage apparatus to exit the deep sleep mode and enter the normal mode.
  3. The storage apparatus controlling method of claim 1, wherein the storage apparatus comprises a data port and a data strobe port, wherein the step (b) comprises:
    applying the data port to receive data；
    applying the data strobe port to receive or to transmit a data strobe signal； and
    applying the data strobe port to receive an awakening instruction, to control the storage apparatus to exit the deep sleep mode and enter the normal mode.
  4. The storage apparatus controlling method of claim 1,
    wherein the step (b) comprises performing the accessing operation to the storage apparatus after a transiting timing for a predetermined time interval, wherein a determining step indicates that at least one access operation will be performed to the storage apparatus at the transiting timing；
    wherein the predetermined time interval is larger or equals to the recovery time interval.
  5. The storage apparatus controlling method of claim 1,
    wherein the step (b) comprises:
    controlling the storage apparatus to receive a dummy accessing command signal after the storage apparatus exits the deep sleep mode； and
    not accessing the storage apparatus until the storage apparatus generates a response corresponding to the dummy accessing command signal.
  6. The storage apparatus controlling method of claim 1, further comprising:
    controlling the storage apparatus to exit the deep sleep mode and enter the normal mode after a  power up operation in the deep sleep mode and before a refresh operation corresponding to the power up operation, if the storage apparatus is controlled to exit the deep sleep mode and enter the normal mode during the power up operation.
  7. A storage apparatus controlling method, applied to a control apparatus to control a storage apparatus, comprising:
    (a) controlling a storage apparatus to enter a deep sleep mode via the control apparatus, wherein the storage apparatus keeps data stored therein in the deep sleep mode； and
    (b) controlling the storage apparatus to exit the deep sleep mode and to enter a normal mode via the control apparatus, wherein the storage apparatus can be normally accessed in the normal mode；
    wherein if the storage apparatus is controlled to enter the normal mode in the deep sleep mode, the storage apparatus enters the normal mode after the storage apparatus exits the deep sleep mode for a recovery time interval.
  8. The storage apparatus controlling method of claim 7, wherein the control apparatus comprises a data port, a data strobe port and an awakening port, wherein the step (b) comprises:
    applying the data port to transmit data to the storage apparatus；
    applying the data strobe port to receive a data strobe signal from the storage apparatus or to transmit a data strobe signal to the storage apparatus； and
    applying the awakening port to transmit an awakening instruction to the storage apparatus, to control the storage apparatus to exit the deep sleep mode and enter the normal mode.
  9. The storage apparatus controlling method of claim 7, wherein the control apparatus comprises a data port and a data strobe port, wherein the step (b) comprises:
    applying the data port to transmit data to the storage apparatus；
    applying the data strobe port to receive a data strobe signal from the storage apparatus or to transmit a data strobe signal to the storage apparatus； and
    applying the data strobe port to transmit an awakening instruction to the storage apparatus, to control the storage apparatus to exit the deep sleep mode and enter the normal mode.
  10. The storage apparatus controlling method of claim 7, further comprising:
    wherein the step (b) comprises performing at least one accessing operation to the storage apparatus after a transiting timing for a predetermined time interval, wherein a determining step indicates that at least one access operation will be performed to the storage apparatus at the transiting timing；
    wherein the predetermined time interval is larger or equals to the recovery time interval.
  11. The storage apparatus controlling method of claim 7,
    wherein the step (b) comprises:
    applying the control apparatus to transmit a dummy accessing command signal to the storage apparatus after the storage apparatus exits the deep sleep mode； and
    not accessing the storage apparatus until the control apparatus receives a response corresponding to the dummy accessing command signal, wherein the response is generated by the storage apparatus.
  12. The storage apparatus controlling method of claim 7, further comprising:
    controlling the storage apparatus to exit the deep sleep mode and enter the normal mode after a power up operation in the deep sleep mode and before a refresh operation corresponding to the power up operation, if the storage apparatus is controlled to exit the deep sleep mode and enter the normal mode during the power up operation.
  13. A storage apparatus, configured to receive an enter instruction to enter a deep sleep mode and configured to receive an awaking instruction to exit the deep sleep mode and to enter a normal mode；
    wherein the storage apparatus keeps data stored therein in the deep sleep mode, wherein the storage apparatus can be normally accessed in the normal mode；
    wherein if the storage apparatus is controlled to enter the normal mode while in the deep sleep mode, the storage apparatus enters the normal mode after the storage apparatus exits the deep sleep mode for a recovery time interval.
  14. The storage apparatus of claim 13, wherein the storage apparatus comprises a data port for receiving data, a data strobe port for receiving or transmitting a data strobe signal and an awakening port, wherein the storage apparatus applies the awakening port to receive an awakening instruction to accordingly exit the deep sleep mode and enter the normal mode.
  15. The storage apparatus of claim 13, wherein the storage apparatus comprises a data port for receiving data, a data strobe port for receiving or transmitting a data strobe signal, wherein the storage apparatus applies the data strobe port to receive an awakening instruction, to accordingly control the storage apparatus to exit the deep sleep mode and enter the normal mode.
  16. The storage apparatus of claim 13,
    wherein the storage apparatus transmits or receives data after a transiting timing for a predetermined time interval, wherein a determining step indicates that at least one access operation will be performed to the storage apparatus at the transiting timing；
    wherein the predetermined time interval is larger or equals to the recovery time interval.
  17. The storage apparatus of claim 13, wherein the storage apparatus receives a dummy accessing command signal after the storage apparatus exits the deep sleep mode, and the storage apparatus does not receive or transmit data until the storage apparatus generates a response  corresponding to the dummy accessing command signal.
  18. The storage apparatus of claim 13, wherein the storage apparatus exits the deep sleep mode and enters the normal mode after a power up operation in the deep sleep mode and before a refresh operation corresponding to the power up operation, if the storage apparatus is controlled to exit the deep sleep mode and enter the normal mode during the power up operation.
  19. A storage system, comprising:
    a storage apparatus； and
    a control apparatus, configured to control a storage apparatus to enter a deep sleep mode via the control apparatus, and configured to control the storage apparatus to exit the deep sleep mode and to enter a normal mode；
    wherein the storage apparatus keeps data stored therein in the deep sleep mode, wherein the storage apparatus can be normally accessed in the normal mode；
    wherein if the storage apparatus is controlled to enter the normal mode in the deep sleep mode, the control apparatus controls the storage apparatus to enter the normal mode after the storage apparatus exits the deep sleep mode for a recovery time interval.
  20. The storage system of claim 19, wherein the control apparatus comprises a data port configured to transmit data to the storage apparatus, a data strobe port configured to receive a data strobe signal from the storage apparatus or configured to transmit a data strobe signal to the storage apparatus, and an awakening port to transmit an awakening instruction to the storage apparatus, to control the storage apparatus to exit the deep sleep mode and enter the normal mode.
  21. The storage system of claim 19, wherein the control apparatus comprises a data port for transmitting data to the storage apparatus, a data strobe port configured to receive a data strobe signal from the storage apparatus or configured to transmit a data strobe signal to the storage apparatus, wherein the control apparatus applies the data strobe port to transmit an awakening instruction to the storage apparatus, to control the storage apparatus to exit the deep sleep mode and enter the normal mode.
  22. The storage system of claim 19,
    wherein the control apparatus performs at least one accessing operation to the storage apparatus to enter the normal mode after a transiting timing for a predetermined time interval, wherein a determining step indicates that at least one access operation will be performed to the storage apparatus at the transiting timing；
    wherein the predetermined time interval is larger or equals to the recovery time interval.
  23. The storage system of claim 19, wherein the control apparatus transmits a dummy accessing command signal to the storage apparatus after the storage apparatus exits the deep sleep mode, and  the control apparatus does not access the storage apparatus until the control apparatus receives a response corresponding to the dummy accessing command signal, wherein the response is generated by the storage apparatus.
  24. The storage system of claim 19, wherein control apparatus controls the storage apparatus to exit the deep sleep mode and to enter the normal mode after a power up operation in the deep sleep mode and before a refresh operation corresponding to the power up operation, if the storage apparatus is controlled to exit the deep sleep mode and enter the normal mode during the power up operation.
PCT/CN2015/080891 2013-12-24 2015-06-05 Storage apparatus, storage system, storage apparatus controlling method Ceased WO2015185017A1 (en)

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