WO2015180334A1 - 显示驱动电路、阵列基板及触摸显示装置 - Google Patents

显示驱动电路、阵列基板及触摸显示装置 Download PDF

Info

Publication number
WO2015180334A1
WO2015180334A1 PCT/CN2014/087597 CN2014087597W WO2015180334A1 WO 2015180334 A1 WO2015180334 A1 WO 2015180334A1 CN 2014087597 W CN2014087597 W CN 2014087597W WO 2015180334 A1 WO2015180334 A1 WO 2015180334A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
terminal
sub
transmission gate
circuit
Prior art date
Application number
PCT/CN2014/087597
Other languages
English (en)
French (fr)
Inventor
樊君
李成
孙建
Original Assignee
京东方科技集团股份有限公司
鄂尔多斯市源盛光电有限责任公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 鄂尔多斯市源盛光电有限责任公司 filed Critical 京东方科技集团股份有限公司
Priority to KR1020167030865A priority Critical patent/KR101899228B1/ko
Priority to US14/908,813 priority patent/US9552091B2/en
Priority to EP14893615.6A priority patent/EP3151223B1/en
Priority to JP2016568881A priority patent/JP6594347B2/ja
Publication of WO2015180334A1 publication Critical patent/WO2015180334A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/06—Clock generators producing several clock signals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04166—Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/0418—Control or interface arrangements specially adapted for digitisers for error correction or compensation, e.g. based on parallax, calibration or alignment
    • G06F3/04184—Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management

Definitions

  • the invention relates to a display driving circuit, an array substrate and a touch display device.
  • the traditional OGS (One Glass Solution) touch screen is not suitable for the market due to its thick module, low optical transmittance, complicated structure and high production cost.
  • the thin, simple structure of the in-cell touch display is increasingly referred to as the mainstream of market development.
  • the pixel structure of the conventional structure display panel includes a common electrode and a pixel electrode
  • the conventional structure touch panel includes an X-direction electrode (drive electrode) and a Y-direction electrode (sensing electrode).
  • the in-cell touch screen drives the common electrode of the display screen as a driving electrode of the touch screen.
  • the conventional in-cell capacitive touch screen is directly output by the driving IC because the driving electrode is directly routed.
  • a display driving circuit includes: a touch signal terminal, a first clock terminal, a second clock terminal, a power terminal, a driving signal enable terminal, a driving electrode signal terminal, and a common electrode signal terminal. And a plurality of cascaded sub-circuits, each sub-circuit comprising: a logic unit, a driving unit and a transmission unit, wherein the logic unit is connected to the touch signal terminal, the first clock terminal, the second clock terminal, the power terminal, and the driving signal An enabling end and the driving unit, the driving unit is connected to the transmission unit, and the transmission unit is connected to the driving electrode signal end and the common electrode signal end;
  • the touch signal end is used to input a touch signal
  • the first clock end is used to input a first clock signal
  • the second clock end is used to input a second clock signal
  • the power end end is used to input a power signal
  • the driving signal enable end is used for inputting a driving enable signal
  • the driving electrode signal end is for inputting a driving electrode signal
  • the common electrode signal end is for inputting a common electrode signal
  • each sub-circuit is sequentially connected, and the logic unit is used to control whether to strobe the sub-circuit of the sub-level under the control of the touch signal end, the first clock end and the second clock end, and when strobing, controlling
  • the working period of the common electrode connected to the sub-circuit is a touch period, and the driving enable signal is transmitted to the driving unit; when not strobed, the working period of the common electrode connected to the sub-circuit is Displaying a time period and transmitting the power signal to the driving unit;
  • the driving unit is configured to drive a signal transmitted by the logic unit to reduce a delay generated during signal transmission, and transmit the driven signal to the transmission unit;
  • the transmission unit is configured to output a driving electrode signal or a common electrode signal according to the driven signal, and if the driven signal is a driving enable signal, output a driving electrode signal, and otherwise output a common electrode signal.
  • the logic unit may include: a latch unit, a first transfer gate, a second transfer gate, a first thin film transistor, a second thin film transistor, a first inverter, and a second inverter;
  • the first clock terminal is connected to the first input end of the latch unit of the sub-level circuit, and the second clock end is connected to the first transmission gate of the sub-circuit of the sub-level circuit
  • the input terminal for the logic unit of the even-numbered sub-circuit, the second clock terminal is connected to the first input end of the latch unit of the sub-circuit of the current stage, and the first clock end is connected to the first transmission of the sub-circuit of the sub-level An input end of the gate;
  • the touch signal end is connected to the second input end of the latch unit of the first-stage sub-circuit, and the touch signal is latched by the latch unit of the sub-circuit of the sub-circuit, and then sequentially transmitted to the next stage a second input of the latch unit of the subcircuit;
  • the output end of the latch unit is connected to the input end of the first inverter and the first control end of the first transmission gate, and the output end of the first inverter is connected a second control end of the first transmission gate, an output end of the first transmission gate is connected to an input end of the second inverter and a first control end of the second transmission gate, and an output end of the second inverter Connecting a second control end of the second transmission gate, the driving signal enable end is connected to the input end of the second transmission gate, and the output end of the second transmission gate is connected to the driving unit; the first thin film transistor a gate connected to an output end of the first inverter, a source connected to an output end of the first transmission gate, a drain connected to the power terminal, and a gate of the second thin film transistor being connected to the second An output end of the inverter, a source is connected to an output end of the second transmission gate, and a drain is connected to the power supply end;
  • the latch unit is configured to latch the touch signal under control of a clock terminal connected to a first input terminal thereof, the first thin film transistor is configured to pull an output end of the first transmission gate to the power source a signal; the second thin film transistor is configured to pull an output end of the second transmission gate to the power supply signal, and output the power supply signal to the driving unit.
  • the latch unit is further configured to be latched after being controlled by a clock terminal connected to the first input terminal thereof
  • the touch signal is transmitted to the first control end of the first transmission gate, and the latched touch signal is transmitted to the second control end of the first transmission gate via the first inverter to open the first transmission a first transmission gate for transmitting a clock signal connected thereto to a first control end of the second transmission gate and to a second transmission of the second transmission gate via the second inverter a control end to open the second transmission gate, the drive enable signal is transmitted to the driving unit through the second transmission gate;
  • the first clock signal and the second clock signal are at opposite levels.
  • the driving unit includes: an inverter group composed of at least two inverters connected in series, and a first inverter of the inverter group is connected to an output end of the second transmission gate,
  • the inverter group is used to drive the signal transmitted by the logic unit to reduce the delay of the transmission signal, and the number of inverters in the inverter group is an even number.
  • the transmission unit includes: a third transmission gate and a fourth transmission gate, an input end of the third transmission gate is connected to the signal terminal of the driving electrode, and an output terminal is connected to an output end of the sub-circuit of the current stage, a first control terminal is coupled to an output of a last inverter of the inverter group, a second control terminal is coupled to an input of the last inverter; and an input terminal of the fourth transmission gate is coupled to the common electrode signal
  • the output end is connected to the output end of the sub-circuit of the current stage, the first control end is connected to the input end of the last inverter, and the second control end is connected to the output end of the last inverter;
  • the third transmission gate is configured to output the driving electrode signal when the driving unit outputs a driving enable signal; the fourth transmission gate is configured to: when the driving unit outputs a power signal, the common electrode signal Output.
  • the power signal is opposite to the drive enable signal level.
  • an array substrate is provided, and the display driving circuit described above is disposed on the array substrate.
  • the present disclosure also provides a touch display device including the above array substrate.
  • the display driving circuit realizes common electrode time division multiplexing of an in-cell capacitive touch screen in a narrow bezel display device.
  • FIG. 1 is a schematic diagram of a display driving circuit according to an embodiment of the present disclosure, in which a schematic structural diagram of a primary sub-circuit is shown;
  • FIG. 2 is a schematic diagram showing a cascade structure of N sub-circuits in FIG. 1 (in the case where N is an even number);
  • FIG. 3 is a schematic view showing the specific structure of the transmission door of Figure 1;
  • FIG. 4 is a timing diagram of a display driving circuit of an embodiment of the present disclosure.
  • FIG. 1 schematically shows the structure of a first-level sub-circuit of a display driving circuit of an embodiment of the present disclosure.
  • the circuit includes: a touch signal terminal TSP_IN, a first clock terminal CK, a second clock terminal CKB, a power terminal VGL, a driving signal enable terminal TX_EN, a driving electrode signal terminal TX, and a common electrode signal terminal VCOM.
  • each sub-circuit includes: a logic unit 110, a drive unit 120, and a transmission unit 130.
  • the logic unit 110 is connected to the touch signal terminal TSP_IN, the first clock terminal CK, the second clock terminal CKB, the power terminal VGL, the driving signal enable terminal TX_EN, and the driving unit 120.
  • the drive unit 120 is connected to the transmission unit 130.
  • the transmission unit 130 is connected to the drive electrode signal terminal TX and the common electrode signal terminal VCOM.
  • the touch signal terminal TSP_IN is used for inputting a touch signal
  • the first clock terminal CK is used for inputting the first clock signal
  • the second clock terminal CKB is for inputting the second clock signal
  • the power terminal VGL is used for inputting the power signal
  • the driving signal is used for
  • the enable terminal TX_EN is used to input the drive enable signal
  • the drive electrode signal terminal TX is used to input the drive electrode signal
  • the common electrode signal terminal VCOM is used to input the common electrode signal.
  • Fig. 2 is a view schematically showing a cascade structure of N sub-circuits in the case of Fig. 1 (in the case where N is an even number).
  • the logic unit 110 of each sub-circuit is sequentially connected, and the logic unit 110 is used to control whether the gate is strobed under the control of the touch signal terminal TSP_IN, the first clock terminal CK, and the second clock terminal CKB. Circuit.
  • the working period of the common electrode (the common electrode on the display panel) connected to the sub-circuit is controlled to be a touch period, and the drive enable signal is transmitted to the driving unit 120.
  • the working period of the common electrode connected to the sub-circuit is a display period, and the power signal is transmitted to the driving unit 120.
  • the driving unit 120 is configured to process the signal transmitted by the logic unit 110 (the signal may be a driving enable signal or a power signal) to reduce the signal transmission delay and transmit the processed signal to the transmission unit 130.
  • the transmission unit 130 is configured to output a driving electrode signal or a common electrode signal according to the signal processed by the driving unit 120. If the signal processed by the driving unit 120 is a driving enable signal, the driving electrode signal is output, otherwise the common electrode signal is output.
  • the display driving circuit provided by the embodiment of the present disclosure can be applied to an embedded capacitive touch display screen.
  • the circuit can realize the time-division driving of the driving electrode scanning AC signal used as the touch control and the normal display common electrode DC signal, and finally realize the role of the common electrode as the driving electrode in the touch mode, and realize the touch twice the display refresh frequency.
  • the reporting frequency enables the touch display to have a high signal-to-noise ratio (SNR) characteristic, and at the same time, the compatibility design of the circuit touch and the normal display can be realized.
  • SNR signal-to-noise ratio
  • the traces of the driving electrodes and the common electrodes are connected to the external driving chip, and the corresponding signals are provided to the electrodes through the external driving chip.
  • each trace needs to be relatively wide. Due to the large number of traces, the area that needs to be occupied is large.
  • the display driving circuit provided by the above embodiments of the present disclosure can directly form the display driving circuit on a display substrate (such as an array substrate) in the display device, and only needs to input each input end and each output end (for example, including touch).
  • the signal terminal, the first clock terminal, the second clock terminal, the power terminal, the driving signal enable terminal, the driving electrode signal terminal, and the common electrode signal terminal are connected to the external driving chip, thereby greatly reducing the driving electrodes and the common The footprint of the electrodes is routed, thus enabling a narrow bezel design.
  • the display driving circuit only needs a narrow frame to realize the common electrode time division multiplexing of the embedded capacitive touch screen, and the circuit can realize the high reporting frequency.
  • the drive electrodes can achieve a scan frequency of 120 Hz, thus achieving a higher report frequency.
  • the logic unit 110 includes: a latch unit L, a first transfer gate C1, a second transfer gate C2, a first thin film transistor T1, a second thin film transistor T2, and a first inverter F1 ( Also called the NOT gate) and the second inverter F2.
  • the first clock terminal CK is connected to the latch unit L of the sub-circuit of the current stage, and the second clock terminal CKB is connected to the input of the first transmission gate C1 of the sub-circuit of the current stage. end.
  • the second clock terminal CKB is connected to the latch unit L of the sub-circuit of the current stage, and the first clock terminal CK is connected to the input terminal of the first transmission gate C1 of the sub-circuit of the current stage.
  • the touch signal terminal TSP_IN is connected to the latch unit L of the first-stage sub-circuit, and the touch signal is latched by the latch unit L of the sub-circuit of the current stage and sequentially transmitted to the latch unit L of the next-stage sub-circuit.
  • the latch unit L is connected to the input end of the first inverter F1 and the first control end of the first transmission gate C1, and the output end of the first inverter F1.
  • the output end of the first transmission gate C1 is connected to the input end of the second inverter F2 and the first control end of the second transmission gate C2, and the output of the second inverter F2
  • the terminal is connected to the second control end of the second transmission gate C2.
  • the driving signal enable terminal TX_EN is connected to the input end of the second transmission gate C2, and the second transmission gate
  • the output of C2 is connected to the drive unit 120.
  • the gate of the first thin film transistor T1 in the logic unit 110 is connected to the output end of the first inverter F1, the source is connected to the output end of the first transfer gate C1, the drain is connected to the power supply terminal VGL, and the second thin film transistor T2 is connected.
  • the gate is connected to the output end of the second inverter F2, the source is connected to the output end of the second transfer gate C2, and the drain is connected to the power supply terminal VGL.
  • the latch unit L is configured to latch the touch signal under the control of the clock terminal connected thereto, and when the touch signal is latched, the first thin film transistor T1 is used to pull the output end of the first transmission gate C1 to the power signal ( That is, the output voltage of the power signal is the same; the second thin film transistor T2 is used to pull the output end of the second transmission gate C2 to the power signal (ie, the same as the output voltage of the power signal), and output the power signal to the driving unit 120. .
  • the latch unit L is further configured to transmit the latched touch signal to the first control end of the first transmission gate C1 under the control of the clock terminal connected thereto, and pass the latched touch signal to the first inverter.
  • F1 is transmitted to the second control terminal of the first transmission gate C1 to open the first transmission gate C1.
  • the first transmission gate C1 is configured to transmit a clock signal connected thereto to the first control end of the second transmission gate C2, and to the second control terminal of the second transmission gate C2 via the second inverter F2 to open the Two transmission gates C2.
  • the drive enable signal is transmitted to the drive unit 120 via the second transfer gate C2.
  • the levels of the first clock signal and the second clock signal are opposite.
  • the driving unit 120 includes: an inverter group composed of at least two inverters connected in series. As shown in Figures 1 and 2, the inverter group includes four inverters (F3 to F6), and the first inverter F3 of the inverter group is connected to the output terminal of the second transmission gate C2, the inverter The group is used to process the signals transmitted by the logic unit 110 to reduce the delay of the signals during transmission. Illustratively, in order to ensure that the level of the signal does not change, the number of inverters in the inverter group is an even number.
  • the transmission unit 130 includes: a third transmission gate C3 and a fourth transmission gate C4.
  • the input end of the third transmission gate C3 is connected to the driving electrode signal terminal TX, and the output end is connected to the output end of the sub-circuit of the current stage.
  • the control terminal is connected to the output of the last inverter F6 in the inverter group, and the second control terminal is connected to the input terminal of the last inverter F6.
  • the input end of the fourth transmission gate C4 is connected to the common electrode signal terminal VCOM, the output terminal is connected to the output end of the sub-circuit of the current stage, the first control terminal is connected to the input end of the last inverter F6, and the second control terminal is connected to the last inversion phase. The output of the device F6.
  • the third transmission gate C3 is configured to output the driving electrode signal when the signal output by the driving unit 120 is a driving enable signal; and the fourth transmission gate C4 is configured to output the common electrode signal when the signal output by the driving unit 120 is a power supply signal.
  • the drive is The electrode signal is also the common electrode signal, which can make the power signal and the drive enable signal level opposite.
  • the latch unit L may employ any of the existing two-input latches, and is not limited to the latch unit structure shown in the drawings of the present disclosure.
  • the latch unit in FIGS. 1 and 2 includes a first tri-state gate S1, a second tri-state gate S2, a seventh inverter F7, and an eighth inverter F8.
  • the input end of the seventh inverter F7 is the first input end of the latch unit, and the first input end of the first tri-state gate S1 is the second input end of the latch unit.
  • the output of the eighth inverter F8 is the output of the latch unit.
  • the output of the seventh inverter F7 is connected to the third input of the first tri-state gate S1 and the second input of the second tri-state gate S2.
  • the second input end of the first tri-state gate S1 is connected to the input end of the seventh inverter F7 and the third input end of the second tri-state gate S2, the first tri-state gate S1 output end and the second tri-state gate S2
  • the outputs are connected together and connected to the input of the eighth inverter F8.
  • the output of the eighth inverter F8 is connected to the input of the second tri-state gate S2.
  • Fig. 3 schematically shows the general structure of the transmission door shown in Fig. 1.
  • the transmission gate may be composed of two thin film transistors, the gate of the N-type thin film transistor is the first control terminal I, the gate of the P-type thin film transistor is the second control terminal II, and the N-type and P-type thin film transistors are The sources are connected together to form an input terminal III, and the drains are connected together to form an output terminal IV.
  • Fig. 4 schematically shows a timing chart of the display driving circuit of the present embodiment.
  • the operation principle of the display driving circuit of the present embodiment will be described below with reference to the timing chart shown in FIG. 4 (the description will be made by taking T1 and T2 as N-type thin film transistors as an example).
  • the first stage circuit when the TSP_IN signal and the CK signal are high, the first stage circuit is gated and starts to operate.
  • the high level of the TSP_IN signal is transmitted to the output terminal of the latch unit L (i.e., the input terminal of the first inverter F1) and simultaneously to the input terminal of the latch unit L of the second-stage sub-circuit. Since the levels of the CKB signal and the CK signal are opposite, the latch unit of the second-stage sub-circuit latches the high level of the TSP_IN signal, and of course does not transmit to the next-level sub-circuit.
  • the TSP_IN signal turns on the first transmission gate C1
  • the CKB signal passes through C1 and turns on the second transmission gate C2
  • the drive enable signal TX_EN signal, high level
  • C2 is transmitted to point a.
  • point a is a high level
  • the third transmission gate C3 is opened after passing through four inverters connected in series, so that the driving electrode signal is output.
  • the drive electrode signal (Tx1 in FIG. 4) is output to the common electrode, the common electrode functions as a drive electrode at the time of touch. That is, in a period CK of one CK period and the TSP_IN signal is at a high level, the first-stage sub-circuit is gated, and the common electrode connected to the first-stage sub-circuit operates in the touch phase.
  • the output of the latch unit is in a low state.
  • the transistor T1 is turned on, so the output terminal of the first transfer gate C1 is pulled down to the power supply signal (low level).
  • point a is also pulled low by T2 and remains low after four inverters F3-F6, which causes the fourth transmission gate C4 to open and output the common electrode signal. That is, in the period t1 during one CK period and the TSP_IN signal is low, the common electrode connected to the un-strobed sub-circuit operates in the display phase.
  • CKB and CK have the same duty cycle and are 50%, while the pulse widths of the two clock signals are the same, but the levels are opposite.
  • the pulse width is the sum of the scan time t2 (also referred to as touch time) of the scan drive electrode of the scan display and the normal display time t1 of the branch.
  • the required scan time t2 of a drive electrode can be controlled by the pulse width of the Tx_EN signal.
  • the branch display time t1 can be determined by the number of drive electrodes and the resolution of the screen.
  • An array substrate is also provided in the embodiment of the present disclosure, and the display driving circuit of the above embodiment is disposed on the array substrate.
  • the display driving circuit is disposed on the array substrate according to the embodiment of the present disclosure. Since the display driving circuit can be directly formed on the array substrate, each input terminal and each output terminal (for example, including a touch signal terminal, The first clock terminal, the second clock terminal, the power terminal, the driving signal enable terminal, the driving electrode signal terminal, and the common electrode signal terminal are connected to the external driving chip, thereby greatly reducing the driving electrodes and the common electrodes. The footprint of the line, therefore, allows for a narrow border.
  • a touch display device including the array substrate of the above embodiment, is also provided in the embodiment of the present disclosure.
  • the display device of the embodiment of the present disclosure includes the array substrate of the above embodiment, and a narrow bezel can be realized.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Computer Hardware Design (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种显示驱动电路，包括：触控信号端、第一时钟端、第二时钟端、电源端、驱动信号使能端、驱动电极信号端、公共电极信号端及多个级联的子电路，每个子电路包括：逻辑单元（110），驱动单元（120）和传输单元（130），所述逻辑单元（110）连接所述触控信号端、第一时钟端、第二时钟端、电源端、驱动信号使能端及所述驱动单元（120），所述驱动单元（120）连接所述传输单元（130），所述传输单元（130）连接驱动电极信号端和公共电极信号端。本申请实现了在窄边框显示装置中的内嵌式电容触摸屏的共电极分时复用。

Description

显示驱动电路、阵列基板及触摸显示装置 技术领域
本发明涉及一种显示驱动电路、阵列基板及触摸显示装置。
背景技术
随着移动产品例如：手机，平板电脑等产品越来越轻薄化和精细化，对屏幕分辨率要求越来越高，对屏幕的厚度要求越来越薄。传统的外挂式OGS(One Glass Solution)触摸屏由于模组较厚，光学透过率低，结构复杂，制作成本高等缺点已经不适应市场的需求。轻薄且结构简单的内嵌式触摸显示屏越来越称为市场发展的主流。
传统结构的显示屏的像素结构包括公共电极和像素电极，传统结构的触摸屏包括X向的电极(驱动电极)和Y向的电极(感应电极)。而内嵌式触摸屏将显示屏的公共电极作为触摸屏的驱动电极进行分时驱动。传统的内嵌式电容触摸屏由于驱动电极的走线由驱动IC直接输出，当屏幕尺寸越来越大时，导致驱动电极数量的增多，这样从驱动IC端引出的走线会相应增多，进而实现窄边框变得更为困难。
发明内容
按照本公开的一个方面，提供了一种显示驱动电路，包括：触控信号端、第一时钟端、第二时钟端、电源端、驱动信号使能端、驱动电极信号端、公共电极信号端及多个级联的子电路，每个子电路包括：逻辑单元，驱动单元和传输单元，所述逻辑单元连接所述触控信号端、第一时钟端、第二时钟端、电源端、驱动信号使能端及所述驱动单元，所述驱动单元连接所述传输单元，所述传输单元连接驱动电极信号端和公共电极信号端；
所述触控信号端用于输入触控信号，所述第一时钟端用于输入第一时钟信号，所述第二时钟端用于输入第二时钟信号，所述电源端用于输入电源信号，所述驱动信号使能端用于输入驱动使能信号，所述驱动电极信号端用于输入驱动电极信号，所述公共电极信号端用于输入公共电极信号；
每级子电路的逻辑单元依次连接，所述逻辑单元在所述触控信号端、第一时钟端、第二时钟端的控制下用于控制是否选通本级子电路，选通时，控 制该级子电路连接的公共电极的工作时间段为触摸时段，并将所述驱动使能信号传输至所述驱动单元；未选通时，该级子电路连接的公共电极的工作时间段为显示时段，并将与所述电源信号传输至所述驱动单元；
所述驱动单元用于驱动所述逻辑单元传输过来的信号，以减小信号传输过程中产生的延时，并将驱动后的信号传输至所述传输单元；
所述传输单元用于根据所述驱动后的信号输出驱动电极信号或公共电极信号，若驱动后的信号为驱动使能信号，则输出驱动电极信号，否则输出公共电极信号。
例如，逻辑单元可包括：锁存单元、第一传输门、第二传输门、第一薄膜晶体管、第二薄膜晶体管、第一反相器和第二反相器；
对于奇数级子电路的逻辑单元，所述第一时钟端连接所述本级子电路的锁存单元的第一输入端，所述第二时钟端连接本级子电路的所述第一传输门的输入端，对于偶数级的子电路的逻辑单元，所述第二时钟端连接本级子电路的锁存单元的第一输入端，所述第一时钟端连接本级子电路的第一传输门的输入端；所述触控信号端连接第一级子电路的锁存单元的第二输入端，所述触控信号经过本级子电路的锁存单元锁存后依次传输至下一级子电路的锁存单元的第二输入端；
对于每个子电路的逻辑单元，所述锁存单元的输出端连接所述第一反相器的输入端和第一传输门的第一控制端，所述第一反相器的输出端连接所述第一传输门的第二控制端，所述第一传输门的输出端连接所述第二反相器的输入端和第二传输门的第一控制端，第二反相器的输出端连接所述第二传输门的第二控制端，所述驱动信号使能端连接所述第二传输门的输入端，第二传输门的输出端连接所述驱动单元；所述第一薄膜晶体管的栅极连接所述第一反相器的输出端，源极连接所述第一传输门的输出端，漏极连接所述电源端，所述第二薄膜晶体管的栅极连接所述第二反相器的输出端，源极连接所述第二传输门的输出端，漏极连接所述电源端；
所述锁存单元用于在与其第一输入端连接的时钟端控制下锁存所述触控信号，所述第一薄膜晶体管用于将所述第一传输门的输出端拉至所述电源信号；所述第二薄膜晶体管用于将所述第二传输门的输出端拉至所述电源信号，并将所述电源信号输出至所述驱动单元。
所述锁存单元还用于在与其第一输入端连接的时钟端控制下将锁存后的 触控信号传输至所述第一传输门的第一控制端，将锁存后的触控信号经第一反相器传输至第一传输门的第二控制端，以打开所述第一传输门，所述第一传输门用于将与其连接的时钟信号传输至所述第二传输门的第一控制端，并经过所述第二反相器传输至所述第二传输门的第二控制端，以打开所述第二传输门，所述驱动使能信号经过所述第二传输门传输至所述驱动单元；
所述第一时钟信号和第二时钟信号的电平相反。
可替换地，所述驱动单元包括：至少两个串联的反相器组成的反相器组，所述反相器组的第一个反相器连接所述第二传输门的输出端，所述反相器组用于驱动所述逻辑单元传输过来的信号，以减小传输信号的延时，所述反相器组中反相器个数为偶数个。
可替换地，所述传输单元包括：第三传输门和第四传输门，所述第三传输门的输入端连接所述驱动电极信号端，输出端连接所述本级子电路的输出端，第一控制端连接所述反相器组中最后一个反相器的输出端，第二控制端连接所述最后一个反相器的输入端；第四传输门的输入端连接所述公共电极信号端，输出端连接所述本级子电路的输出端，第一控制端连接所述最后一个反相器的输入端，第二控制端连接所述最后一个反相器的输出端；
所述第三传输门用于在驱动单元输出的为驱动使能信号时将所述驱动电极信号输出；所述第四传输门用于在驱动单元输出的为电源信号时将所述公共电极信号输出。
可替换地，所述电源信号与所述驱动使能信号电平相反。
按照本公开的另一方面还提供了一种阵列基板，所述阵列基板上设置有上述的显示驱动电路。本公开还提供了一种触摸显示装置，包括上述的阵列基板。
按照本公开实施例的显示驱动电路实现了在窄边框显示装置中的内嵌式电容触摸屏的共电极分时复用。
附图说明
图1是本公开实施例的一种显示驱动电路示意图，其中示出了一级子电路的结构示意图；
图2是为图1中N个子电路(图中为N为偶数的情况)的级联结构示意图；
图3是图1中传输门的具体结构示意图；
图4是本公开实施例的显示驱动电路的时序图。
具体实施方式
下面结合附图和实施例，对本公开的具体实施方式作进一步详细描述。以下实施例仅用于说明本公开的原理，但不用来限制本公开的范围。
图1示意性示出了本公开实施例的显示驱动电路的一级子电路的结构。如图1所示，该电路包括：触控信号端TSP_IN、第一时钟端CK、第二时钟端CKB、电源端VGL、驱动信号使能端TX_EN、驱动电极信号端TX、公共电极信号端VCOM及多个级联的子电路。在图1所示实施例中，每个子电路包括：逻辑单元110，驱动单元120和传输单元130。逻辑单元110连接触控信号端TSP_IN、第一时钟端CK、第二时钟端CKB、电源端VGL、驱动信号使能端TX_EN及驱动单元120。驱动单元120连接传输单元130。传输单元130连接驱动电极信号端TX和公共电极信号端VCOM。
触控信号端TSP_IN用于输入触控信号，第一时钟端CK用于输入第一时钟信号，第二时钟端CKB用于输入第二时钟信号，电源端VGL用于输入电源信号，驱动信号使能端TX_EN用于输入驱动使能信号，驱动电极信号端TX用于输入驱动电极信号，公共电极信号端VCOM用于输入公共电极信号。
图2示意性示出图1中N个子电路(图中为N为偶数的情况)的级联结构。如图2所示，每级子电路的逻辑单元110依次连接，逻辑单元110在触控信号端TSP_IN、第一时钟端CK、第二时钟端CKB的控制下用于控制是否选通本级子电路。选通时，控制该级子电路连接的公共电极(显示面板上的公共电极)的工作时间段为触摸时段，并将驱动使能信号传输至驱动单元120。当未选通时，该级子电路连接的公共电极的工作时间段为显示时段，并将电源信号传输至驱动单元120。
驱动单元120用于处理逻辑单元110传输过来的信号(该信号可能是驱动使能信号，也可能是电源信号)，以减小信号传输延时，并将处理后的信号传输至传输单元130。
传输单元130用于根据驱动单元120处理后的信号输出驱动电极信号或公共电极信号，若驱动单元120处理后的信号为驱动使能信号，则输出驱动电极信号，否则输出公共电极信号。
本公开实施例提供的显示驱动电路，可应用于内嵌电容式触摸显示屏， 作为共电极驱动信号扫描电路。该电路可实现用作触控的驱动电极扫描交流信号和正常显示共电极直流信号的分时驱动，最终实现公共电极在触摸模式下作为驱动电极的作用，并实现两倍于显示刷新频率的触摸报点频率，使触摸显示屏具备高的信噪比(SNR)特性，同时可以实现该电路触摸与正常显示的兼容性设计。
此外，现有技术中各驱动电极和各公共电极的走线与外部驱动芯片相连，进而通过外部驱动芯片为各电极提供对应信号。在这种情况下，通常包括几十根驱动电极的走线。为了减小走线造成的信号延迟，各走线需要相对较宽。由于走线数量较多，因此，需要占用的面积大。而本公开上述实施例提供的显示驱动电路，可直接将该显示驱动电路制作在显示装置中的显示基板上(例如阵列基板)，只需将各输入端和各输出端(例如，包括触控信号端、第一时钟端、第二时钟端、电源端、驱动信号使能端、驱动电极信号端、公共电极信号端)与外部驱动芯片相连即可，这样大大减少了各驱动电极和各公共电极的走线的占用面积，因此，可实现窄边框设计。
总之，该显示驱动电路只需要较窄的边框就能实现内嵌式电容触摸屏的共电极分时复用，同时该电路可以实现高报点频率。例如，在60hz的显示扫描频率下，驱动电极可以实现120Hz的扫描频率，因此，实现较高的报点频率。
在图1所示实施例中，逻辑单元110包括：锁存单元L、第一传输门C1、第二传输门C2、第一薄膜晶体管T1、第二薄膜晶体管T2、第一反相器F1(也称非门)和第二反相器F2。
如图2所示，对于奇数级子电路的逻辑单元110，第一时钟端CK连接本级子电路的锁存单元L，第二时钟端CKB连接本级子电路的第一传输门C1的输入端。对于偶数级的子电路的逻辑单元110，第二时钟端CKB连接本级子电路的锁存单元L，第一时钟端CK连接本级子电路的第一传输门C1的输入端。触控信号端TSP_IN连接第一级子电路的锁存单元L，触控信号经过本级子电路的锁存单元L锁存后依次传输至下一级子电路的锁存单元L。
如图1所示，对于每个子电路的逻辑单元110，锁存单元L连接第一反相器F1的输入端和第一传输门C1的第一控制端，第一反相器F1的输出端连接第一传输门C1的第二控制端，第一传输门C1的输出端连接第二反相器F2的输入端和第二传输门C2的第一控制端，第二反相器F2的输出端连接第二传输门C2的第二控制端。驱动信号使能端TX_EN连接第二传输门C2的输入端，第二传输门 C2的输出端连接驱动单元120。此外，逻辑单元110中的第一薄膜晶体管T1的栅极连接第一反相器F1的输出端，源极连接第一传输门C1的输出端，漏极连接电源端VGL，第二薄膜晶体管T2的栅极连接第二反相器F2的输出端，源极连接第二传输门C2的输出端，漏极连接电源端VGL。
锁存单元L用于在与其连接的时钟端控制下锁存触控信号，当触控信号被锁存时，第一薄膜晶体管T1用于将第一传输门C1的输出端拉至电源信号(即和电源信号的输出电压一样)；第二薄膜晶体管T2用于将第二传输门C2的输出端拉至电源信号(即和电源信号的输出电压一样)，并将电源信号输出至驱动单元120。
锁存单元L还用于在与其连接的时钟端控制下将锁存后的触控信号传输至第一传输门C1的第一控制端，将锁存后的触控信号经第一反相器F1传输至第一传输门C1的第二控制端，以打开第一传输门C1。第一传输门C1用于将与其连接的时钟信号传输至第二传输门C2的第一控制端，并经过第二反相器F2传输至第二传输门C2的第二控制端，以打开第二传输门C2。驱动使能信号经过第二传输门C2传输至驱动单元120。
为了控制各级子电路的时序，第一时钟信号和第二时钟信号的电平相反。
本实施例中，驱动单元120包括：至少两个串联的反相器组成的反相器组。如图1和2中所示，反相器组包括4个反相器(F3～F6)，反相器组的第一个反相器F3连接第二传输门C2的输出端，反相器组用于处理逻辑单元110传输过来的信号，以减小传输过程中信号的延时。示例性地，为了保证信号的电平不发生改变，反相器组中反相器个数为偶数个。
本实施例中，传输单元130包括：第三传输门C3和第四传输门C4，第三传输门C3的输入端连接驱动电极信号端TX，输出端连接本级子电路的输出端，第一控制端连接反相器组中最后一个反相器F6的输出端，第二控制端连接最后一个反相器F6的输入端。第四传输门C4的输入端连接公共电极信号端VCOM，输出端连接本级子电路的输出端，第一控制端连接最后一个反相器F6的输入端，第二控制端连接最后一个反相器F6的输出端。
第三传输门C3用于在驱动单元120输出的信号为驱动使能信号时将驱动电极信号输出；第四传输门C4用于在驱动单元120输出的信号为电源信号时将公共电极信号输出。
示例性地，为了能够根据电源信号和驱动使能信号来决定输出的是驱动 电极信号还是公共电极信号，可使电源信号与驱动使能信号电平相反。
本实施例中，锁存单元L可以采用现有的任何一种两输入结构的锁存器，不限于本公开的附图中所示出的锁存单元结构。图1和2中的锁存单元包括：第一三态门S1、第二三态门S2、第七反相器F7和第八反相器F8。第七反相器F7的输入端为该锁存单元的第一输入端，第一三态门S1的第一输入端为该锁存单元的第二输入端。第八反相器F8的输出端为该锁存单元的输出端。第七反相器F7的输出端连接第一三态门S1的第三输入端和第二三态门S2的第二输入端。第一三态门S1的第二输入端连接第七反相器F7的输入端和第二三态门S2的第三输入端，第一三态门S1输出端和第二三态门S2的输出端连接在一起，且连接第八反相器F8的输入端。第八反相器F8的输出端连接第二三态门S2的输入端。
图3示意性地示出了图1中所示传输门的通常结构。如图3所示，上述传输门可以由两个薄膜晶体管组成，N型薄膜晶体管的栅极为第一控制端Ⅰ，P型薄膜晶体管的栅极为第二控制端Ⅱ，N型和P型薄膜晶体管的源极连在一起，形成输入端Ⅲ，漏极连在一起形成输出端Ⅳ。
图4示意性示出了本实施例的显示驱动电路的时序图。以下参照图4所示的时序图，描述本实施例的显示驱动电路的工作原理(以T1和T2为N型薄膜晶体管为例进行说明)。
参考图1及图2中第一级和第二级的子电路，TSP_IN信号和CK信号为高时，第一级电路被选通，开始工作。TSP_IN信号的高电平传输到锁存单元L的输出端(即第一反相器F1的输入端)，同时传输至第二级子电路的锁存单元L的输入端。由于CKB信号和CK信号的电平相反，因此第二级子电路的锁存单元将TSP_IN信号的高电平锁存，当然也不会向下一级子电路传输。对于第一级子电路来说，由于其被选通，TSP_IN信号使第一传输门C1打开，CKB信号通过C1并打开第二传输门C2，驱动使能信号(TX_EN信号，高电平)通过C2传输至a点。此时，a点为高电平，通过4个串联的反相器后打开第三传输门C3，使得驱动电极信号输出。由于是驱动电极信号(图4中Tx1)被输出至公共电极，此时公共电极起到触摸时的驱动电极作用。亦即，在一个CK周期，且TSP_IN信号为高电平的时间段t2内，第一级子电路被选通，与第一级子电路连接的公共电极工作在触摸阶段。
其他级的子电路由于未被选通，锁存单元的输出端处于低电平状态。经 过第一反相器F1后变为高电平，使晶体管T1打开，因此将第一传输门C1的输出端被拉低至电源信号(低电平)。同理，a点也被T2拉至低电平，经过四个反相器F3-F6后仍为低电平，这使得第四传输门C4打开，将公共电极信号输出。即，在一个CK周期内，且TSP_IN信号为低电平的时间段t1内，未被选通的子电路连接的公共电极工作在显示阶段。
示例性地，CKB和CK具有相同的占空比，且为50％，同时两个时钟信号的脉冲宽度相同，只是电平相反。该脉冲宽度的时间为一次停止分行显示扫描的扫描驱动电极的扫描时间t2(也可称为触控时间)和进行分行正常显示时间t1之和。一个驱动电极的所需的扫描时间t2可通过Tx_EN信号的脉冲宽度控制。而分行显示时间t1可由驱动电极的数量和屏幕的分辨率决定。
本公开实施例中还提供了一种阵列基板，所述阵列基板上设置有上述实施例的显示驱动电路。
按照本公开实施例的阵列基板上设置有上述的显示驱动电路，由于可直接将该显示驱动电路制作在阵列基板上，只需将各输入端和各输出端(例如，包括触控信号端、第一时钟端、第二时钟端、电源端、驱动信号使能端、驱动电极信号端、公共电极信号端)与外部驱动芯片相连即可，从而可大大减少各驱动电极和各公共电极的走线的占用面积，因此，可实现窄边框。
本公开实施例中还提供了一种触摸显示装置，包括上述实施例的阵列基板。
本公开实施例的显示装置包括上述实施例的阵列基板，可实现窄边框。
以上实施方式仅用于说明本公开的原理，而并非对本公开技术方案的限制，有关技术领域的普通技术人员，在不脱离本公开的精神和范围的情况下，还可以做出各种变化和变型，因此所有这些变化和变型以及等同的技术方案也属于本公开的范畴，本公开的专利保护范围应由权利要求限定。
本申请要求于2014年5月30日递交的中国专利申请第201410240732.8号的优先权，在此全文引用该中国专利申请公开的内容作为本申请的一部分。

Claims (13)

  1. 一种显示驱动电路，包括：
    触控信号端，用于输入触控信号；
    第一时钟端，用于输入第一时钟信号；
    第二时钟端，输入第二时钟信号；
    电源端，输入电源信号；
    驱动信号使能端，用于输入驱动使能信号；
    驱动电极信号端，用于输入驱动电极信号；
    公共电极信号端，用于输入公共电极信号；以及
    多个级联的子电路，其中每个子电路包括：
    逻辑单元，连接所述触控信号端、第一时钟端、第二时钟端、电源端、驱动信号使能端，用于在所述触控信号、第一时钟信号、第二时钟信号的控制下控制是否选通本级子电路；
    驱动单元，连接所述逻辑单元，用于处理所述逻辑单元传输过来的信号，以减小信号传输过程中产生的延时，并将处理后的信号传输至所述传输单元；以及
    传输单元，连接所述驱动电极信号端和所述公共电极信号端，并连接所述驱动单元，用于根据所述处理后的信号输出驱动电极信号或公共电极信号，若所述处理后的信号为驱动使能信号，则输出驱动电极信号，否则输出公共电极信号，以及
    其中每级子电路的逻辑单元依次连接，在逻辑单元控制选通本级子电路时，控制该级子电路连接的公共电极的工作时间段为触摸时段，并将所述驱动使能信号传输至所述驱动单元；在未选通本级子电路时，该级子电路连接的公共电极的工作时间段为显示时段，并将与所述电源信号传输至所述驱动单元。
  2. 如权利要求1所述的显示驱动电路，其中，所述逻辑单元包括：锁存单元、第一传输门、第二传输门、第一薄膜晶体管、第二薄膜晶体管、第一反相器和第二反相器。
  3. 如权利要求2所述的显示驱动电路，其中，对于奇数级子电路的逻辑单元，所述第一时钟端连接所述本级子电路的锁存单元的第一输入端，所述第 二时钟端连接本级子电路的所述第一传输门的输入端，对于偶数级的子电路的逻辑单元，所述第二时钟端连接本级子电路的锁存单元的第一输入端，所述第一时钟端连接本级子电路的第一传输门的输入端；所述触控信号端连接第一级子电路的锁存单元的第二输入端，所述触控信号经过本级子电路的锁存单元锁存后依次传输至下一级子电路的锁存单元的第二输入端。
  4. 如权利要求2或3所述的显示驱动电路，其中，对于每个子电路的逻辑单元，所述锁存单元的输出端连接所述第一反相器的输入端和第一传输门的第一控制端，所述第一反相器的输出端连接所述第一传输门的第二控制端，所述第一传输门的输出端连接所述第二反相器的输入端和第二传输门的第一控制端，第二反相器的输出端连接所述第二传输门的第二控制端，所述驱动信号使能端连接所述第二传输门的输入端，第二传输门的输出端连接所述驱动单元；所述第一薄膜晶体管的栅极连接所述第一反相器的输出端，源极连接所述第一传输门的输出端，漏极连接所述电源端，所述第二薄膜晶体管的栅极连接所述第二反相器的输出端，源极连接所述第二传输门的输出端，漏极连接所述电源端。
  5. 如权利要求2-4之一所述的显示驱动电路，其中，所述锁存单元用于在与其第一输入端连接的时钟端控制下锁存所述触控信号，所述第一薄膜晶体管用于将所述第一传输门的输出端拉至所述电源信号；所述第二薄膜晶体管用于将所述第二传输门的输出端拉至所述电源信号，并将所述电源信号输出至所述驱动单元。
  6. 如权利要求2-5之一所述的显示驱动电路，其中，所述锁存单元还用于在与其第一输入端连接的时钟端控制下将锁存后的触控信号传输至所述第一传输门的第一控制端，将锁存后的触控信号经第一反相器传输至第一传输门的第二控制端，以打开所述第一传输门，所述第一传输门用于将与其连接的时钟信号传输至所述第二传输门的第一控制端，并经过所述第二反相器传输至所述第二传输门的第二控制端，以打开所述第二传输门，所述驱动使能信号经过所述第二传输门传输至所述驱动单元。
  7. 如权利要求1-6之一所述的显示驱动电路，其中，所述第一时钟信号和第二时钟信号的电平相反。
  8. 如权利要求1-7之一所述的显示驱动电路，其中，所述驱动单元包括： 至少两个串联的反相器组成的反相器组，所述反相器组的第一个反相器连接所述第二传输门的输出端。
  9. 如权利要求8所述的显示驱动电路，其中所述反相器组中反相器个数为偶数个。
  10. 如权利要求1-9之一所述的显示驱动电路，其中，所述传输单元包括：第三传输门和第四传输门，所述第三传输门的输入端连接所述驱动电极信号端，输出端连接所述本级子电路的输出端，第一控制端连接所述反相器组中最后一个反相器的输出端，第二控制端连接所述最后一个反相器的输入端；第四传输门的输入端连接所述公共电极信号端，输出端连接所述本级子电路的输出端，第一控制端连接所述最后一个反相器的输入端，第二控制端连接所述最后一个反相器的输出端；
    所述第三传输门用于在驱动单元输出的为驱动使能信号时将所述驱动电极信号输出；所述第四传输门用于在驱动单元输出的为电源信号时将所述公共电极信号输出。
  11. 如权利要求1-10中任一项所述的显示驱动电路，其中，所述电源信号与所述驱动使能信号电平相反。
  12. 一种阵列基板，所述阵列基板上设置有权利要求1-11中任一项所述的显示驱动电路。
  13. 一种触摸显示装置，包括上述权利要求12所述的阵列基板。
PCT/CN2014/087597 2014-05-30 2014-09-26 显示驱动电路、阵列基板及触摸显示装置 WO2015180334A1 (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020167030865A KR101899228B1 (ko) 2014-05-30 2014-09-26 디스플레이 구동 회로, 어레이 기판, 및 터치 디스플레이 디바이스
US14/908,813 US9552091B2 (en) 2014-05-30 2014-09-26 Display driving circuit, array substrate and touch display apparatus
EP14893615.6A EP3151223B1 (en) 2014-05-30 2014-09-26 Display drive circuit, array substrate and touch display device
JP2016568881A JP6594347B2 (ja) 2014-05-30 2014-09-26 表示駆動回路、アレイ基板及びタッチ表示装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410240732.8 2014-05-30
CN201410240732.8A CN103996371B (zh) 2014-05-30 2014-05-30 显示驱动电路、阵列基板及触摸显示装置

Publications (1)

Publication Number Publication Date
WO2015180334A1 true WO2015180334A1 (zh) 2015-12-03

Family

ID=51310517

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2014/087597 WO2015180334A1 (zh) 2014-05-30 2014-09-26 显示驱动电路、阵列基板及触摸显示装置

Country Status (6)

Country Link
US (1) US9552091B2 (zh)
EP (1) EP3151223B1 (zh)
JP (1) JP6594347B2 (zh)
KR (1) KR101899228B1 (zh)
CN (1) CN103996371B (zh)
WO (1) WO2015180334A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9552091B2 (en) 2014-05-30 2017-01-24 Boe Technology Group Co., Ltd. Display driving circuit, array substrate and touch display apparatus

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9325311B1 (en) * 2014-11-20 2016-04-26 Innolux Corporation Gate driver and display device using the same
CN104503612B (zh) 2014-12-12 2017-11-10 上海天马微电子有限公司 一种触控显示面板和电子设备
CN105373260B (zh) * 2015-12-23 2018-06-01 武汉华星光电技术有限公司 触控驱动电路
CN105654902B (zh) * 2016-03-31 2018-03-27 上海天马微电子有限公司 一种oled显示面板、触控电极驱动电路以及驱动方法
CN105741739B (zh) * 2016-04-22 2018-11-16 京东方科技集团股份有限公司 栅极驱动电路及显示装置
US10217390B2 (en) * 2016-09-20 2019-02-26 Apple Inc. Sensing for compensation of pixel voltages
US10186200B2 (en) * 2016-09-20 2019-01-22 Apple Inc. Sensing for compensation of pixel voltages
CN107908353B (zh) * 2016-09-30 2020-12-18 禾瑞亚科技股份有限公司 电子系统、触控处理装置与其方法
US10133405B2 (en) * 2016-11-11 2018-11-20 Solomon Systech (Shenzhen) Limited Reconfigurable touch sensing for touch-display panel
CN106775119B (zh) * 2017-01-16 2019-09-24 厦门天马微电子有限公司 触控驱动电路、触控显示面板及驱动方法
US10453415B2 (en) * 2017-11-29 2019-10-22 Wuhan China Star Optoelectronics Technology Co., Ltd. GOA circuit and embedded touch display panel
CN108109667B (zh) * 2017-12-15 2021-01-15 京东方科技集团股份有限公司 移位寄存器单元、扫描驱动电路、显示装置、驱动方法
KR102605378B1 (ko) * 2018-07-19 2023-11-24 엘지디스플레이 주식회사 터치 센서를 구비하는 표시장치

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200601347A (en) * 2004-06-24 2006-01-01 Toppoly Optoelectronics Corp Shift register and a shift register
CN202996250U (zh) * 2012-10-23 2013-06-12 京东方科技集团股份有限公司 一种液晶显示器的驱动电路
CN103500551A (zh) * 2013-10-23 2014-01-08 合肥京东方光电科技有限公司 移位寄存器单元、goa电路、阵列基板以及显示装置
CN103700354A (zh) * 2013-12-18 2014-04-02 合肥京东方光电科技有限公司 栅极驱动电路及显示装置
CN103996371A (zh) * 2014-05-30 2014-08-20 京东方科技集团股份有限公司 显示驱动电路、阵列基板及触摸显示装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3513371B2 (ja) * 1996-10-18 2004-03-31 キヤノン株式会社 マトリクス基板と液晶装置とこれらを用いた表示装置
JP3858486B2 (ja) * 1998-11-26 2006-12-13 セイコーエプソン株式会社 シフトレジスタ回路、電気光学装置および電子機器
JP2006005661A (ja) * 2004-06-17 2006-01-05 Matsushita Electric Ind Co Ltd フリップフロップ回路
JP4332652B2 (ja) * 2005-12-12 2009-09-16 独立行政法人 宇宙航空研究開発機構 シングルイベント耐性のラッチ回路及びフリップフロップ回路
JP4650553B2 (ja) * 2008-10-20 2011-03-16 ソニー株式会社 液晶表示パネル
KR101056284B1 (ko) * 2009-10-22 2011-08-11 삼성모바일디스플레이주식회사 센서 스캔 드라이버 및 이를 구비한 터치 스크린 내장형 평판표시장치
JP5501158B2 (ja) * 2010-08-23 2014-05-21 株式会社ジャパンディスプレイ タッチ検出機能付き表示装置、駆動回路、タッチ検出機能付き表示装置の駆動方法、および電子機器
JP5710449B2 (ja) * 2011-04-13 2015-04-30 株式会社ジャパンディスプレイ 表示装置、駆動回路、駆動方法、および電子機器
JP5758825B2 (ja) 2012-03-15 2015-08-05 株式会社ジャパンディスプレイ 表示装置、表示方法、および電子機器
TW201351225A (zh) 2012-06-11 2013-12-16 Giantplus Technology Co Ltd 內嵌式觸控顯示器電路結構
KR101416003B1 (ko) * 2012-06-20 2014-07-08 엘지디스플레이 주식회사 터치스크린 일체형 표시장치 및 그 구동 방법
KR101480314B1 (ko) * 2012-08-16 2015-01-08 엘지디스플레이 주식회사 터치스크린 일체형 표시장치 및 그 구동 방법
KR101628724B1 (ko) * 2012-11-13 2016-06-09 엘지디스플레이 주식회사 터치스크린 일체형 표시장치
JP2014186537A (ja) * 2013-03-22 2014-10-02 Japan Display Inc 表示装置及び電子機器
CN103413521B (zh) * 2013-07-31 2015-06-10 京东方科技集团股份有限公司 有机发光二极管像素电路及其驱动方法、显示装置
JP6162585B2 (ja) 2013-11-22 2017-07-12 株式会社ジャパンディスプレイ タッチ検出機能付き表示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200601347A (en) * 2004-06-24 2006-01-01 Toppoly Optoelectronics Corp Shift register and a shift register
CN202996250U (zh) * 2012-10-23 2013-06-12 京东方科技集团股份有限公司 一种液晶显示器的驱动电路
CN103500551A (zh) * 2013-10-23 2014-01-08 合肥京东方光电科技有限公司 移位寄存器单元、goa电路、阵列基板以及显示装置
CN103700354A (zh) * 2013-12-18 2014-04-02 合肥京东方光电科技有限公司 栅极驱动电路及显示装置
CN103996371A (zh) * 2014-05-30 2014-08-20 京东方科技集团股份有限公司 显示驱动电路、阵列基板及触摸显示装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9552091B2 (en) 2014-05-30 2017-01-24 Boe Technology Group Co., Ltd. Display driving circuit, array substrate and touch display apparatus

Also Published As

Publication number Publication date
EP3151223A4 (en) 2017-12-20
JP6594347B2 (ja) 2019-10-23
JP2017517764A (ja) 2017-06-29
KR101899228B1 (ko) 2018-09-14
US9552091B2 (en) 2017-01-24
EP3151223B1 (en) 2020-08-05
EP3151223A1 (en) 2017-04-05
US20160179258A1 (en) 2016-06-23
CN103996371B (zh) 2016-04-13
KR20160143743A (ko) 2016-12-14
CN103996371A (zh) 2014-08-20

Similar Documents

Publication Publication Date Title
WO2015180334A1 (zh) 显示驱动电路、阵列基板及触摸显示装置
US9864472B2 (en) Touch driving detection circuit, display panel and display device
US9898989B2 (en) Gate driver on array (GOA) circuit and liquid crystal display apparatus having the GOA circuit
US9543040B2 (en) Shift register unit and driving method thereof, gate driver and display device
TWI582739B (zh) 顯示器面板
WO2016119357A1 (zh) 一种goa电路及其驱动方法、显示面板及显示装置
US20160132170A1 (en) Driving Unit for Touch Electrode, Driving Circuit, Touch Panel and Driving Method
US9922589B2 (en) Emission electrode scanning circuit, array substrate and display apparatus
US10120482B2 (en) Driving method for in-cell type touch display panel
TWI578203B (zh) 內嵌式觸控顯示器及其操作方法
US9953555B2 (en) Driving circuit for touch screen, in-cell touch screen and display apparatus
US9880660B2 (en) Touch driving unit, touch panel and display device
US9536623B2 (en) Gate drive circuit and shift register
WO2016180003A1 (zh) 触控电路、触控面板及显示装置
WO2016173197A1 (zh) 扫描驱动电路及其驱动方法、阵列基板、显示装置
WO2017156850A1 (zh) 移位寄存器及驱动方法、驱动电路、阵列基板及显示装置
WO2017133100A1 (zh) 发射电极扫描驱动单元、驱动电路、驱动方法以及阵列基板
CN104393874B (zh) 一种触控扫描电路、触控驱动电路及触摸显示屏
CN109656397A (zh) 触控显示装置
WO2016115797A1 (zh) 触控电路、触控面板及显示装置
CN104376814A (zh) 一种驱动电路及驱动方法、显示面板、显示装置
CN104765504B (zh) 触控显示电路、其驱动方法、触控显示面板及显示装置
WO2017107292A1 (zh) 触控驱动电路
CN108898996B (zh) 栅极驱动单元的下拉电路及显示装置
CN103578437A (zh) 栅极驱动电路的电压下拉电路结构及其显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 14893615

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 14908813

Country of ref document: US

REEP Request for entry into the european phase

Ref document number: 2014893615

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 2014893615

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 20167030865

Country of ref document: KR

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 2016568881

Country of ref document: JP

Kind code of ref document: A

NENP Non-entry into the national phase

Ref country code: DE