WO2015171684A1 - 4 bit nonvolatile flash or variable resistance memory - Google Patents

4 bit nonvolatile flash or variable resistance memory Download PDF

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Publication number
WO2015171684A1
WO2015171684A1 PCT/US2015/029353 US2015029353W WO2015171684A1 WO 2015171684 A1 WO2015171684 A1 WO 2015171684A1 US 2015029353 W US2015029353 W US 2015029353W WO 2015171684 A1 WO2015171684 A1 WO 2015171684A1
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cells
potential
line
data
matrix
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PCT/US2015/029353
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French (fr)
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John Yit FONG
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Fong John Yit
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/005—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line

Definitions

  • the present invention relates to semiconductor memory devices, and particularly to 2 and 3 bit variable resistance (VR) and potential line combination nonvolatile memories and 2 and 3 bit floating gate (FG) potential line combination nonvolatile memories.
  • VR variable resistance
  • FG floating gate
  • DRAM Dynamic random access memory
  • flash memories use electric charge to store data.
  • memory cells scale smaller and smaller into the 45nm region and below, there are serious concerns about the growing electric charge storage errors now occuring in these memories due to charge leakage effects.
  • DRAM and flash memory ... scaling is in jeopardy” [1 p.131]. This is shown in the article by Benjamin C. Lee, et al. entitled “Phase- Change Technology & the Future of Main Memory", IEEE Micro Magazine Jan/Feb 2010 by Stanford University, Carnegie Mellon University, & Microsoft Research, pp. 131 - 141 . See p. 131 , "PCM is closest to realization and imminent deployment”.
  • variable resistance memories like phase change memory (PCM) resistive random access memory (ReRAM) [2], etc. nonvolatilely store data based on the electrical resistance state of a atomic structure of a material.
  • PCM phase change memory
  • ReRAM resistive random access memory
  • the material is a chalcogenide typically Ge2Sb2Te5 (GST) [Lee article p.132] which can be rapidly heated to a high temperature and quickly frozen into an amorphous high resistive state or slowly heated at a much lower temperature for a longer period into a crystalline low resistive state.
  • ReRAMs use a metal oxide that if given a specific reset or set voltage similarly set or reset the atomic structure of a metal oxide to different resistive states This is shown U.S. Patent Publication No. 2011 /0032747 to Hong-Sik Yoon, et. al. (see Fig. 2A and 2B and p.2 col. 2)
  • phase change memory see U.S. Patent N. 3,271 ,591 to Ovshinsky and U.S. Patent No. 8,243,504 to Lui
  • the preferred variable resistive memory of this patent app as a integrated circuit memory technology, verses a CD or DVD optical recording medium, now finally after the last 40 years may be "closest to realization and imminent deployment" [Lee article column 2 p.131 ] due to latest breakthroughs to overcome (1 ) overly intensive electric current requirements to generate sufficient heat that in the past resulted in (a) unacceptable memory cell sizes, and worse in the past (b) electrical current damage to the phase change material's reliability, and (2) unreliable adhesion of phase change material to the underlying substrate, etc.
  • FIG. 1 illustrates a prior art schematic of a group of next store neighbor, resistive variable, cells, preferably in this patent app, phase change memory (PCM) cells which ie. could be a row of variable resistance memory cells, a column of variable resistance, cells, a block of such cells, etc.
  • PCM phase change memory
  • BJT bipolar junction transistor
  • memory cell pass transistors are all electrically shorted or connected to the same ground (GND) supply ie. through a power grid, plate electrode, or substrate.
  • Corrado discusses that phase-change memory (PCM) technology is the only one of the proposed alternative technologies that is demonstrating the capability to enter in the broad NVM market and to become mainstream in the next decade.
  • PCM phase-change memory
  • U.S. Patent No. 4,184,207 to McElroy discloses on NOR floating gate (FG) electrically eraseable programmable read only memories, EEPROM.
  • U.S. Patent No. 4,184,207 to McElroy discloses on NOR floating gate (FG) EEPROM with a series pass transistor.
  • U.S. Patent 7,332,773 to Forbes shows prior art NOR & NAND Flash memory arrays.
  • bit line word line
  • matrix of at least variable resistance (VR) or floating gate (FG) nonvolatile (nv) memory cells In the context of a bit line, word line, matrix of at least variable resistance (VR) or floating gate (FG) nonvolatile (nv) memory cells., generally, a matrix line of at least, M+ N. VR or FG 1 b nv memory cells are combined & improved to store 2b, 3b, or more by each cell being supplied by 1 of at least 2, 4, or more potential lines so "encoding them" with 1 b, 2b, or > potential line combination data.
  • VR variable resistance
  • FG floating gate
  • the VR or FG nonvolatile (NV) data which can be a high resistance or high voltage threshold programmed state can present a problem by blocking out or masking out the potential line combination data from being accessible.
  • a general objective of the invention is to provide a solution to this problem, and an advantage over the prior art, by using the VR or FG nonvolatile (NV) data first and then erases the VR or FG NV memory element to a low resistance or low threshold voltage to access the potential line combination NV data second.
  • NV nonvolatile
  • In another objective of the invention is to provide an alternate solution to this problem by copying any VR or FG NV data to a buffer memory, then erase, then access the potential line combination data next, finally restoring the copied VR or FG NV data at a later date.
  • the key is that a workable combination of VR or FG 1 b or > NV cell + potential line combination encoded NV data of 1 b, 2b, or > nv data is created so that now 2 bits, 3 bits, or more nonvolatile data per cell are stored rather than 1 bit.
  • semiconductor memory devices utilizing 2 and 3 bit variable resistance (VR) and potential line combination nonvolatile memories and 2 and 3 bit floating gate (FG) potential line combination nonvolatile memories.
  • VR variable resistance
  • FG floating gate
  • a variable resistance memory device storing 2 bits or more data.
  • the device includes a plurality of word lines (WL); a plurality of bit lines (BL); a 0 th & 1 st potential line; a said BL said WL matrix of at least Variable Resistance (M+N) (VR) memory cells.
  • WL word lines
  • BL bit lines
  • BL bit lines
  • VR Variable Resistance
  • a 0 th potential line supplies at least, M VR cells
  • a 1 st potential line supplies at least, N VR cells.
  • the 0 th & 1 st potential lines each extend as far in distance to supply at least the M and N matrix of VR cells.
  • the variable resistance memory device can further store 3b or more data.
  • variable resistance memory cells used in the invention are selected from the group consisting of phase change memory (PCM) cells, resistive RAM (ReRAM) cells; conductive bridge RAM cells; and solid electrolyte memories.
  • PCM phase change memory
  • ReRAM resistive RAM
  • conductive bridge RAM cells conductive bridge RAM cells
  • solid electrolyte memories solid electrolyte memories
  • a floating gate memory device storing 2 bits or more data.
  • the floating gate memory device can further store 3b or more data.
  • the floating gate memory cells used in the invention are selected from the group consisting of flash cells and NOR flash cells.
  • variable resistance memory device In both the variable resistance memory device and floating gate memory device embodiments random and structured nonvolatile data patterns are supported. For the random patterns, in both embodiments across the matrix line of cells the potential lines alternately supply the M+ N cells wherein there are at least M+N different 1 bit random-like, potential line combination, nv#s encoded and M+N,1 bit variable resistance (VR) or alternatively floating gate (FG) nv data bits.
  • VR variable resistance
  • FG alternatively floating gate
  • the potential lines separately supply the M+ N cells wherein there are at least M+N different 1 bit structured- like, potential line combination, nv#s encoded and M+N,1 bit variable resistance (VR) or alternatively floating gate (FG) nv data bits.
  • VR variable resistance
  • FG alternatively floating gate
  • the potential lines alternately supply the M+N+P+Q cells, where there are at M+N+P+Q different 2b random-like potential line combination nv#s encoded and M+N+P+Q 1 b variable resistance (VR) or else floating gate (FG) nv data bits.
  • the potential lines separately supply the M+N+P+Q cells, where there are at M+N+P+Q different 2b structured-like potential line combination nv#s encoded and M+N+P+Q 1 b variable resistance (VR) or else floating gate (FG) nv data bits.
  • the M, N, P and Q cells may be consecutive cells across the matrix line.
  • M+N+P+Q # of cells in the matrix line of cells.
  • Criss-crossing potenial lines can encode 1 bit nonvolatile data in a matrix line of DRAM cells too. This can be done by expanding the 1 st potential line to said, N, different said first potential lines; wherein the N cells are now each supplied by each said N first potential lines wherein said, N, said first potential lines criss-cross with said 0 th potential line. Encoding 2 bit nonvolatile data by criss-crossing is also part of the invention.
  • the 2 potential line is expanded to said, P different second potential lines, wherein said 3 rd potential line is expanded to said, Q, different third potential lines, wherein said P and Q cells are now each supplied by each said P and Q second & third potential lines wherein said second and said third potential lines criss-cross with said 0 th & 1 st potential lines.
  • the VR cells or equivalent used in the invention can be core memory array cells, where the core cells are at least 4 cells away from a memory array, matrix, or block border.
  • the "said supplied by said potential lines” is more specifically “connected to said potential lines”; or on a field effect transistor supply terminal; or on a rectifier terminal which is a diode or equivalent; or each said cell supplied by one of at least a plurality of word lines or plurality of bit lines.
  • a potential line source is supplied by an at least 2 logic state output driver.
  • the potential line and/or plurality of potential lines can be shared with a next neighbor matrix line of cells.
  • the potential lines operate as one same supply for the variable resistance (VR) or floating gate (FG) cells, and the cells are rewriteable based on current knowledge and technology.
  • VR variable resistance
  • FG floating gate
  • field effect transistors carbon nanotube (CNT), bipolar junction transistors (BJT), vertical channel field effect transistors Ike FinFET, TriGate and the equivalent, 3 dimensional transistors like surrounding gate transistor (SGT), vertical channel access transistor (VCAT), equivalent; silicon germanium, carbon, can be used in the invention embodiments.
  • CNT carbon nanotube
  • BJT bipolar junction transistors
  • VCAT vertical channel access transistor
  • silicon germanium, carbon can be used in the invention embodiments.
  • variable resistance and floating gate cells may be multi-port cells.
  • a semiconductor memory device including a plurality of word lines (WL); a plurality of bit lines (BL); at least two potential lines, 0 th and 1 st potential line; a said BL said WL matrix line of at least Floating Gate (FG) memory cells or Variable Resistance (VR) memory cells.
  • FG Floating Gate
  • VR Variable Resistance
  • the 0 th potential line supplies at least, M FG cells or M VR cells while the 1 st potential line supplies at least, N FG cells or N VR.
  • the 0 th & 1 st potential lines each extend as far in distance to supply at least said M and said N FG matrix line or said M and said N VR matrix line.
  • FIG. 1 prior art illustrating a phase change memory (PCM) array.
  • PCM phase change memory
  • FIG. 2 illustrates a schematic and drawing symbols of rewriteable, variable resistance (VR) memory cells each also storing 1 bit of potential line combination nonvolatile (NV) data.
  • a floating gate (FG) memory cell also stores 1 bit of potential line combination NV data.
  • FIG.. 3 illustrates a schematic and drawing symbols of rewriteable, variable resistance (VR) memory cells each also storing 2 bits of potential line combination nonvolatile (nv) data.
  • a floating gate (FG) memory cell also stores 2b potential line combination nv data.
  • FIG. 4 shows a flowchart to erase these variable resistance (VR) memory cells to crystalline low resistance state.
  • FIG. 5 shows a flowchart to erase these floating gate (FG) memory cells to low Vthreshold state.
  • FIG. 6 shows a timing diagram to read out potential line combination, nonvolatile, Bit 0 or Bit 1 , data in previous 1 and 2 bit variable resistance (VR) and floating gate (FG) memory cells.
  • VR variable resistance
  • FG floating gate
  • FIG 7 shows a flow chart explaining the FIG. 6 timing diagram periods, T1 to T6.
  • FIG. 8 shows a timing diagram to read out word line combination, nonvolatile, Bit 0 or Bit 1 , data in previous 1 and 2 bit variable resistance (VR) and floating gate (FG) memory cells.
  • VR variable resistance
  • FG floating gate
  • FIG. 12 illustrates a 3D Schematic of a Matrix Line of VR or FG memory cells encoded with nv data by being supplied by a bus 0 tn or 1 st potential line that are crisscrossing.
  • FIG. 13 illustrates a BL WL Matrix with a matrix Line of VR or FG cells, each storing at least 2b of potential line combination, nonvolatile data per VR or FG cell.
  • Each V[3:0] potential line will supply a said matrix line cell at least, N , times each to encode and so store said 2b NV data.
  • Word line (WL), Bit Line (BL), and negative slope lines are matrix line of cells examples given.
  • FIG. 14 shows a negative slope matrix line of 2b potential line combination, NV data VR or FG cells example as illustrated in FIG. 13.
  • FIG. 15 shows a positive slope matrix line of 2b potential line combination, NV data VR or FG cells.
  • FIG. 16 shows a. crisscrossing V[3:2] & V[1 :0] lines for storing 2b potential line combination, NV data in matrix line of VR or FG cells.
  • phase change memories i.e.. like with GST, or like a resistance random access memories (ReRAM) i.e.. a metal oxide, etc.
  • ReRAM resistance random access memories
  • variable resistance memory - is a class of known prior art rewriteable nonvolatile memory elements like phase change memory (PCM), resistive random access memory (ReRAM), conductive bridge memory, solid electrolyte memory, equivalent, or like, etc.
  • PCM phase change memory
  • ReRAM resistive random access memory
  • conductive bridge memory solid electrolyte memory, equivalent, or like, etc.
  • FG Floating Gate transistor - which has known prior art ability to store rewriteable nonvolatile memory by trapping electrons on a transistor with a floating gate. This trapped charged raises the voltage threshold, Vth, of the floating gate transistor substantially verses a lower voltage threshold, Vth, when no charge is trapped.
  • Floating gate transistors or devices are used in EPROM, EEPROM, and Flash memories. These memories can be implemented with NOR and NAND, pass transistor or no pass transistor architectures.
  • known property - phase change memory has the known property of having a "reset state” of high resistance which is its amorphous state and a “set state” of low resistance which is its crystalline state (see Lee article cited earlier and Wong articles]); similar, resistive random access memory (ReRAM) has a "set” state of low resistance and a “reset” state of high resistance using some form of metal oxide (see U.S. Patent Publication No. 2011/0032747)
  • Vreset - is for a variable resistance memory material, best mode, a phase change memory (PCM) material ie. like a GST alloy, (see Wong ariticles) a relatively high voltage we are calling Vreset is applied to a phase change memory material that over a relatively short period of time will rapidly melt and make the PCM material amorphous ie. the atoms are substantially unlinked and so relatively high resistance to electrical current. In the Bedeschi et al. reference discussed earlier, this high resistance can be in the millions of ohms region.
  • This low voltage Vcrystallize pulse is held for a long period to allow time for a substantial number of the PCM atoms to link together in a relatively low resistance state typically called a SET STATE.
  • the high resistance state can range into the Meg ohm range. This Meg ohm high resistance state is a major invention operation concern for its capability to mask out potential line combination nonvolatile data from being accessible.
  • FIG. 2A-C shows various variable resistance (VR) memory cell schematics and symbol implemented with a pass transistor or pass gate rectifier ie. diode.
  • the preferred variable resistance memory for this invention is a rewriteable phase change memory (PCM) element although this applies in scope as well to equivalent and like technologies like Resistive RAM, ReRAM, solid-electrolyte memories, etc.
  • PCM phase change memory
  • the invention is equally applicable to floating gate (FG) memory cells like EPROM, EEPROM, and Flash, as also seen in FIG. 2D-F schematics and symbol. 4F ⁇ and 6F layout styled cells are depicted.
  • FG floating gate
  • FIG. 1 shows a word line (WL), bit line (BL) organized memory matrix, memory array, or memory block at least of rewriteable variable resistance (VR) or floating gate (FG) memory cells.
  • WL word line
  • BL bit line
  • VR rewriteable variable resistance
  • FG floating gate
  • the invention utilizes not one but at least two potential lines along a said matrix line of cells to supply one of a plurality of different potential sources to each said variable resistance (VR) or floating gate (FG) cell. This is so that each said cell is then on encoded with a 1 bit or higher, potential line combination, nonvolatile (NV) number.
  • This nonvolatile data is, in addition, to the already existing VR or FG element nonvolatile data bit.
  • B is the number ( #) of potential line combination NV bit(s) stored in these cells, in addition, to the already nonvolatile value stored by the VR material resistance or FG transistor voltage threshold.
  • VR variable resistance
  • FG floating gate
  • NV nonvolatile
  • NV data within these cells in FIG. 2 and 3 you first start by initializing or erasing the variable resistance (VR) element like RP to ie. a low resistance state or the floating gate (FG) transistor to a low voltage threshold, Vth.
  • VR variable resistance
  • FG floating gate
  • FIG. 4 and 5 illustrate this initialization process. Specifically, next to read out the 1 b or 2b potential line combination, nonvolatile numbers encoded within these VR or FG cells and follow the 1 b or 2b timing diagrams found in FIG. 6 which is illustrated in FIG. 7.
  • WL or BL For diode selected cells, WL or BL, must be sufficient voltage to turn on the selection device.
  • sharing the V, WL, or BL potential lines for storing potential line combination nonvolatile data between adjacent memory cells to save chip area is used.
  • VR variable resistance
  • FG floating gate
  • matrix line of cells encoded with 1 b potential line combination, nonvolatile data and 2b potential line combination, nonvolatile data are illustrated in the following figures.
  • FIG. 9 shows a matrix word line or matrix bit line of 1 b cells.
  • FIG. 10 shows a matrix negative slope of 1 b cells where the slope can vary but must stay negative.
  • FIG. 11 shows a matrix positive slope of 1 b cells where the slope can vary but must stay positive.
  • FIG..12 shows a matrix line of 1 b cells where the supplying potential lines are crisscrossing.
  • FIG. 13 shows a matrix word line or matrix bit line of 2b cells.
  • FIG. 14 shows a matrix negative slope of 2b cells where the slope can vary but must stay negative.
  • FIG. 15 shows a matrix positive slope of 2b cells where the slope can vary but must stay positive
  • FIG. 16 shows a matrix line of 2b cells where the supplying potential lines are crisscrossing.
  • nonvolatile potential line combination data bits in these, M+N, and, M+N+P+Q, matrix line of cells are physically consecutive. In an alternate embodiment they are spaced apart by other cells.
  • this patent further defines the, M+N, and, M+N+P+Q matrix line of cells into whether they are storing (a) random-like, alternating, nonvolatile potential line combination data, or (b)structured-like, separated, nonvolatile potential line combination data.
  • the latter can have relaxed wire spacing from cell to cell due to the ability to share, combine, or merge wiring together due to nv data separated into distinct groupings.
  • An example of random-like, alternating, nonvolatile potential line combination data can be a nonvolatile binary sequence like: 01012.
  • An example of structured-like, separated, nonvolatile potential line combination data can be a nonvolatile binary sequence like: H OO2 .
  • FIG. 9 to FIG. 16 are examples of these random-like and structured-like nonvolatile potential line combination data sequences.
  • variable resistance memory cells and floating gate memory cells
  • other like or equivalent memory cells may be used.

Abstract

A semiconductor memory device including a plurality of word lines; a plurality of bit lines; at least two potential lines, a BL and WL matrix line of at least Floating Gate (FG) or Variable Resistance (VR) M+N memory cells; wherein across the matrix line of cells said M and N FG/VR cells are supplied by potential lines, and are encoded with two different physical representations of at least: B= LOG2(2 said potential lines) = 1 bit of, said FG/VR memory cell/potential line combination, nonvolatile data; wherein encoded and stored across said matrix line of cells there are at least a combined: (said M+N) said different 1f nonvolatile #s of potential line combination data plus (said. M+N) 1b nonvolatile said floating gate/variable resistance data bits; wherein each said M and said N FG/VR cell stores a said combined 2 bits of nonvolatile data.

Description

4 BIT NONVOLATILE FLASH OR VARIABLE RESISTANCE MEMORY
FIELD OF THE INVENTION
The present invention relates to semiconductor memory devices, and particularly to 2 and 3 bit variable resistance (VR) and potential line combination nonvolatile memories and 2 and 3 bit floating gate (FG) potential line combination nonvolatile memories.
BACKGROUND OF THE INVENTION
Dynamic random access memory (DRAM), and flash memories use electric charge to store data. However, as memory cells scale smaller and smaller into the 45nm region and below, there are serious concerns about the growing electric charge storage errors now occuring in these memories due to charge leakage effects. "DRAM and flash memory ... scaling is in jeopardy" [1 p.131]. This is shown in the article by Benjamin C. Lee, et al. entitled "Phase- Change Technology & the Future of Main Memory", IEEE Micro Magazine Jan/Feb 2010 by Stanford University, Carnegie Mellon University, & Microsoft Research, pp. 131 - 141 . See p. 131 , "PCM is closest to realization and imminent deployment".
In contrast, variable resistance memories like phase change memory (PCM) resistive random access memory (ReRAM) [2], etc. nonvolatilely store data based on the electrical resistance state of a atomic structure of a material. This is shown in the article by Lee mentioned above, and an article by H. S. Wong, et al. entitled "Phase Change Memory: a comprehensive and thorough review of PCM technologies...", 2010 Proceedings of the IEEE, Vol. 98, No. 12, pp.2201 -2227, Fig. 2 and p.2202; and another article by Wong et. al. entitled "An Ultra-Low Reset Current Cross-Point Phase Change Memory with Carbon Nanotube Electrodes", IEEE Transactions on Electron Devices, Vol. 59, No. 4, April 2012, research done at Stanford University, pp. 1 155-1 163.
For phase change memory the material is a chalcogenide typically Ge2Sb2Te5 (GST) [Lee article p.132] which can be rapidly heated to a high temperature and quickly frozen into an amorphous high resistive state or slowly heated at a much lower temperature for a longer period into a crystalline low resistive state. ReRAMs use a metal oxide that if given a specific reset or set voltage similarly set or reset the atomic structure of a metal oxide to different resistive states This is shown U.S. Patent Publication No. 2011 /0032747 to Hong-Sik Yoon, et. al. (see Fig. 2A and 2B and p.2 col. 2)
Yet, although conceived of in as early as the late 1960s phase change memory (see U.S. Patent N. 3,271 ,591 to Ovshinsky and U.S. Patent No. 8,243,504 to Lui), the preferred variable resistive memory of this patent app, as a integrated circuit memory technology, verses a CD or DVD optical recording medium, now finally after the last 40 years may be "closest to realization and imminent deployment" [Lee article column 2 p.131 ] due to latest breakthroughs to overcome (1 ) overly intensive electric current requirements to generate sufficient heat that in the past resulted in (a) unacceptable memory cell sizes, and worse in the past (b) electrical current damage to the phase change material's reliability, and (2) unreliable adhesion of phase change material to the underlying substrate, etc. where all such effects, etc. This is disclosed in an article by J. Y. Wu, et al. entitled "A Low Power Phase Change Memory Using a Thermally Confined TaN/TiN Bottom Electrode", 201 1 IEDM, pp. 43-46.
Recently these issues of excessive phase change memory cell current requirements to generate sufficient power to melt the phase change material, plus phase change material reliability issues, etc are currently trying to be solved. Representative of this technology is found in an article by Peter Clarke entitled "ISSCC: Samsung preps 8-Gbit Phase Change Memory", EETimes (11 /29/11 ) where "Samsung is set to reignite debate whether phase change memory is commercially viable. . .. at the 2012 International Solid State Circuits Conference"; an article by Jeff Blagdon, "Micron first to market with mobile phase change memory", (www.theverge.com/users/jeffbladon July 19, 2012) and an article by Micron, "Unleash Your Groundbreaking Designs" 2012 Flier, www.micron.com/pcm.
FIG. 1 illustrates a prior art schematic of a group of next store neighbor, resistive variable, cells, preferably in this patent app, phase change memory (PCM) cells which ie. could be a row of variable resistance memory cells, a column of variable resistance, cells, a block of such cells, etc. Notice that the bipolar junction transistor (BJT) cell selectors, or memory cell pass transistors are all electrically shorted or connected to the same ground (GND) supply ie. through a power grid, plate electrode, or substrate.
In contrast in each of these resistive variable memory cells that are used in the preferred invention mode, PCM cells, due to the at least M=2, programmed resistances within these cells each store: B=LOG2[M], nonvolatile bit or digits of data.
Methods of programming the different resistance states in these PCM cells is known in the art and discussed in detail, and included in its entirety by reference in a reference by Ferdinando Bedeschi, et al. entitled "a Multi-Level-Cell Bipolar-Selected Phase-Change Memory", 2008 ISSCC, pp. 428-429, & 625, (Numonyx Inc.)
Other representative prior art relevant to the invention include the article by Corrado Villa, et. al. entitled "A 45nm 1 Gb 1 .8V Phase-Change Memory", (Numonyx, ISSCC 2010: in particular FIG. 14.8.2: Word Line and Bit Line Biasing schematic, FIG. 14.8.5: Summary of Key Features of Phase Change Memory, FIG. 14.8.6: Chip Die Photo, pp. 270-271 . Corrado discusses that phase-change memory (PCM) technology is the only one of the proposed alternative technologies that is demonstrating the capability to enter in the broad NVM market and to become mainstream in the next decade.
U.S. Patent No. 4,184,207 to McElroy (Texas Instruments) discloses on NOR floating gate (FG) electrically eraseable programmable read only memories, EEPROM. U.S. Patent No. 4,184,207 to McElroy (Texas Instruments) discloses on NOR floating gate (FG) EEPROM with a series pass transistor. U.S. Patent 7,332,773 to Forbes (Micron Technology Inc.) shows prior art NOR & NAND Flash memory arrays.
In the context of a bit line, word line, matrix of at least variable resistance (VR) or floating gate (FG) nonvolatile (nv) memory cells., generally, a matrix line of at least, M+ N. VR or FG 1 b nv memory cells are combined & improved to store 2b, 3b, or more by each cell being supplied by 1 of at least 2, 4, or more potential lines so "encoding them" with 1 b, 2b, or > potential line combination data.
Concerning memory operation, the VR or FG nonvolatile (NV) data which can be a high resistance or high voltage threshold programmed state can present a problem by blocking out or masking out the potential line combination data from being accessible.
A general objective of the invention is to provide a solution to this problem, and an advantage over the prior art, by using the VR or FG nonvolatile (NV) data first and then erases the VR or FG NV memory element to a low resistance or low threshold voltage to access the potential line combination NV data second.
In another objective of the invention is to provide an alternate solution to this problem by copying any VR or FG NV data to a buffer memory, then erase, then access the potential line combination data next, finally restoring the copied VR or FG NV data at a later date. The key is that a workable combination of VR or FG 1 b or > NV cell + potential line combination encoded NV data of 1 b, 2b, or > nv data is created so that now 2 bits, 3 bits, or more nonvolatile data per cell are stored rather than 1 bit.
SUMMARY OF THE INVENTION
In the present invention, these purposes, as well as others, are provided by semiconductor memory devices utilizing 2 and 3 bit variable resistance (VR) and potential line combination nonvolatile memories and 2 and 3 bit floating gate (FG) potential line combination nonvolatile memories.
In one embodiment of the invention is provided a variable resistance memory device storing 2 bits or more data. The device includes a plurality of word lines (WL); a plurality of bit lines (BL); a 0th & 1 st potential line; a said BL said WL matrix of at least Variable Resistance (M+N) (VR) memory cells. Across the same matrix line of at least the VR cells, a 0th potential line supplies at least, M VR cells while a 1 st potential line supplies at least, N VR cells. Across the same matrix line, the 0th & 1st potential lines each extend as far in distance to supply at least the M and N matrix of VR cells. Also across the same matrix line of cells M and N VR cells are supplied by the potential lines, encoded with 2 different physical representations of at least: B= LOG2(2 said potential lines) = 1 bit of, said VR memory cell, potential line combination, nonvolatile (nv) data;
wherein encoded and stored across a said matrix line of cells there are at least a combined: (said M+ said N) said different 1 b nonvolatile #s of potential line combination data plus (said M+ said N) 1 b nonvolatile said variable resistance (VR) data bits, wherein each said M and said N VR cell stores a said combined 2 bits of nonvolatile data.
The variable resistance memory device can further store 3b or more data. The device further includes a 2nd and 3rd said potential line, where across the matrix line, said 2nd potential line supplies at least, P, said VR cells while said 3rd potential line supplies at least, Q said VR cells; wherein across said same matrix line of cells said M, said N, said P , and said Q said VR cells, supplied by said potential lines, are encoded with and so store 4 different physical representations of at least: B= LOG2(4 said potential lines) = 2 bits of, said VR memory cell, potential line combination, nonvolatile (nv) data; wherein encoded and stored across a said matrix line of cells there are at least a combined (said M+ said N+ said P+ said Q) said different 2b nv #s of potential line combination data plus (said M+ said N+ said P+ said Q) 1 b nv said variable resistance (VR) data bits; wherein each said M+ said N+ said P+ said Q said VR cell stores a said combined 3 bits nv data.
The variable resistance memory cells used in the invention are selected from the group consisting of phase change memory (PCM) cells, resistive RAM (ReRAM) cells; conductive bridge RAM cells; and solid electrolyte memories.
In an alternate invention embodiment a floating gate memory device storing 2 bits or more data is provided. The device includes a plurality of word lines (WL); a plurality of bit lines (BL); a 0th & 1 st potential line; a said BL said WL matrix of at least Floating Gate (FG) memory cells; wherein across the same said matrix line of at least said FG cells, said 0th potential line supplies at least, M , said FG cells while said 1 st potential line supplies at least, N , said FG cells; wherein across said same matrix line, said 0th & 1 st potential lines each extend as far in distance to supply at least said M and said N said matrix said at least FG cells; wherein across said same matrix line of cells said M and N FG cells are supplied by said potential lines, and are encoded with two different physical representations of at least: B= LOG2(2 said potential lines) = 1 bit of, said FG memory cell, potential line combination, nonvolatile (nv) data; wherein encoded and stored across a said matrix line of cells there are at least a combined: (said M+ said N ) said different 1f nv #s of potential line combination data plus(said M+ said N ) 1 b nv said floating gate (FG) data bits; wherein each said M and said N FG cell stores a said combined 2 bits of nv data.
The floating gate memory device can further store 3b or more data. The device further includes a 2nd & 3rd said potential line; wherein across the same matrix line, the 2nd potential line supplies at least, P, said FG cells while the 3rd potential line supplies at least, Q, said FG cells; wherein across said same matrix line of cells said M , said N,, said P, and said Q FG cells are supplied by said potential lines, and are encoded with and so store 4 different physical representations of at least: B = LOG2(4 said potential lines) = 2 bits of, said FG memory cell, potential line combination, nonvolatile (nv) data;
wherein encoded and stored across a said matrix line of cells there are at least a combined: (said M + said N+ said P + said Q) different 2b nv #s of potential line combination data plus (said M + said N+ said P + said Q) 1 b nv said floating gate (FG) data bits; wherein each said M, said N, said P and said Q FG cell stores a said combined 3 bits nv data.
The floating gate memory cells used in the invention are selected from the group consisting of flash cells and NOR flash cells.
In both the variable resistance memory device and floating gate memory device embodiments random and structured nonvolatile data patterns are supported. For the random patterns, in both embodiments across the matrix line of cells the potential lines alternately supply the M+ N cells wherein there are at least M+N different 1 bit random-like, potential line combination, nv#s encoded and M+N,1 bit variable resistance (VR) or alternatively floating gate (FG) nv data bits.
For the structured patterns, in both embodiments across the matrix line of cells the potential lines separately supply the M+ N cells wherein there are at least M+N different 1 bit structured- like, potential line combination, nv#s encoded and M+N,1 bit variable resistance (VR) or alternatively floating gate (FG) nv data bits.
In the embodiment where 3b or more data bits are random patterns the potential lines alternately supply the M+N+P+Q cells, where there are at M+N+P+Q different 2b random-like potential line combination nv#s encoded and M+N+P+Q 1 b variable resistance (VR) or else floating gate (FG) nv data bits. For structured patterns, the potential lines separately supply the M+N+P+Q cells, where there are at M+N+P+Q different 2b structured-like potential line combination nv#s encoded and M+N+P+Q 1 b variable resistance (VR) or else floating gate (FG) nv data bits.
In the embodiments, the M, N, P and Q cells may be consecutive cells across the matrix line. In general, M+N+P+Q = # of cells in the matrix line of cells.
Criss-crossing potenial lines can encode 1 bit nonvolatile data in a matrix line of DRAM cells too. This can be done by expanding the 1 st potential line to said, N, different said first potential lines; wherein the N cells are now each supplied by each said N first potential lines wherein said, N, said first potential lines criss-cross with said 0th potential line. Encoding 2 bit nonvolatile data by criss-crossing is also part of the invention. The 2 potential line is expanded to said, P different second potential lines, wherein said 3rd potential line is expanded to said, Q, different third potential lines, wherein said P and Q cells are now each supplied by each said P and Q second & third potential lines wherein said second and said third potential lines criss-cross with said 0th & 1 st potential lines.
In the matrix line of cells M, N, P, Q cells can share the same word line and/or bit line.
When the M, N, P and Q cells form a positive slope cells where a typical matrix word line's dominant direction defines 0 degrees and each cell is on a different word line and bit line.
When the M, N, P and Q cells form a negative slope cells where a typical matrix word line's dominant direction defines 0 degrees and each cell is on a different word line and bit line.
When M=1 middle cell between N=2 next store neighbor cells forming 3 consecutive cells. In other embodiments M=2 and at least N=2, M=3 and at least N=3, M=4 and at least N=4; M=2, at least N=2, at least P=2, and at least Q=2, M=3 and at least N=3 at least P=3, and at least Q=3, M=4, and at least N=4 at least P=4, and at least Q=4.
The VR cells or equivalent used in the invention can be core memory array cells, where the core cells are at least 4 cells away from a memory array, matrix, or block border. The VR cells or equivalent can be <= 8F2 in layout; <= 6F2 in layout or <= 4F^ in layout.
The "said supplied by said potential lines" is more specifically "connected to said potential lines"; or on a field effect transistor supply terminal; or on a rectifier terminal which is a diode or equivalent; or each said cell supplied by one of at least a plurality of word lines or plurality of bit lines.
A potential line source is supplied by an at least 2 logic state output driver.
The potential line and/or plurality of potential lines can be shared with a next neighbor matrix line of cells.
In rewritable embodiments, the potential lines operate as one same supply for the variable resistance (VR) or floating gate (FG) cells, and the cells are rewriteable based on current knowledge and technology.
In addition, field effect transistors, carbon nanotube (CNT), bipolar junction transistors (BJT), vertical channel field effect transistors Ike FinFET, TriGate and the equivalent, 3 dimensional transistors like surrounding gate transistor (SGT), vertical channel access transistor (VCAT), equivalent; silicon germanium, carbon, can be used in the invention embodiments.
The variable resistance and floating gate cells may be multi-port cells.
In another embodiment a semiconductor memory device is provided including a plurality of word lines (WL); a plurality of bit lines (BL); at least two potential lines, 0th and 1 st potential line; a said BL said WL matrix line of at least Floating Gate (FG) memory cells or Variable Resistance (VR) memory cells. Where across the matrix line of at least the FG cells or VR cells, the 0th potential line supplies at least, M FG cells or M VR cells while the 1 st potential line supplies at least, N FG cells or N VR. Where across the matrix line, the 0th & 1 st potential lines each extend as far in distance to supply at least said M and said N FG matrix line or said M and said N VR matrix line. Where across said matrix line of cells the M and N FG cells or M and N VR cells are supplied by the potential lines, and are encoded with two different physical representations of at least: B= LOG2(2 said potential lines) = 1 bit of, said FG memory cell or said VG memory cell, potential line combination, nonvolatile (nv) data; wherein encoded and stored across a said matrix line of cells there are at least a combined: (said M+ said N ) said different 1f nv #s of potential line combination data plus(said M+ said N ) 1 b nv said floating gate (FG) data bits or said variable resistance (VR) data bits; wherein each said M and said N FG cell or said M and said N VR stores a combined 2 bits of nv data or more.
Other objects, features and advantages of the present invention will be apparent when the detailed description of the preferred embodiments of the invention are considered with reference to the drawings, which should be construed in an illustrative and not limiting sense.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 prior art illustrating a phase change memory (PCM) array.
FIG. 2 illustrates a schematic and drawing symbols of rewriteable, variable resistance (VR) memory cells each also storing 1 bit of potential line combination nonvolatile (NV) data. A floating gate (FG) memory cell also stores 1 bit of potential line combination NV data.
FIG.. 3 illustrates a schematic and drawing symbols of rewriteable, variable resistance (VR) memory cells each also storing 2 bits of potential line combination nonvolatile (nv) data. A floating gate (FG) memory cell also stores 2b potential line combination nv data. FIG. 4 shows a flowchart to erase these variable resistance (VR) memory cells to crystalline low resistance state.
FIG. 5 shows a flowchart to erase these floating gate (FG) memory cells to low Vthreshold state.
FIG. 6 shows a timing diagram to read out potential line combination, nonvolatile, Bit 0 or Bit 1 , data in previous 1 and 2 bit variable resistance (VR) and floating gate (FG) memory cells.
FIG 7 shows a flow chart explaining the FIG. 6 timing diagram periods, T1 to T6.
FIG. 8 shows a timing diagram to read out word line combination, nonvolatile, Bit 0 or Bit 1 , data in previous 1 and 2 bit variable resistance (VR) and floating gate (FG) memory cells. The application to sharing potential lines between adjacent cells to save chip area and even use of bit line combination, nonvolatile data are disclosed.
FIG. 9 shows a schematic of a matrix line of at least M=2 & N=2, VR or FG memory cells encoded with NV data by being supplied by a bus 0tn or 1 st potential line.
FIG 10 shows a schematic of a matrix line of cells or, in this case, a negative slope line of cells, with VR or FG cells supplied at least M=2 & N=2 times by each 0th & 1 st potential lines, V0 & V1 .
FIG. 11 illustrates a 3D schematic of a matrix line of cells or, in this case, a positive slope line of cells, with VR or FG cells supplied at least M=2 and N=2 times by each 0tn and 1 st potential lines, V0 and V1 .
FIG. 12 illustrates a 3D Schematic of a Matrix Line of VR or FG memory cells encoded with nv data by being supplied by a bus 0tn or 1 st potential line that are crisscrossing.
FIG. 13 illustrates a BL WL Matrix with a matrix Line of VR or FG cells, each storing at least 2b of potential line combination, nonvolatile data per VR or FG cell. Each V[3:0] potential line will supply a said matrix line cell at least, N , times each to encode and so store said 2b NV data. Word line (WL), Bit Line (BL), and negative slope lines are matrix line of cells examples given.
FIG. 14 shows a negative slope matrix line of 2b potential line combination, NV data VR or FG cells example as illustrated in FIG. 13.
FIG. 15 shows a positive slope matrix line of 2b potential line combination, NV data VR or FG cells.
FIG. 16 shows a. crisscrossing V[3:2] & V[1 :0] lines for storing 2b potential line combination, NV data in matrix line of VR or FG cells. DETAILED DESCRIPTION OF THE INVENTION
The specification, examples and figures used in this detailed description of the invention are to be considered only sample implementations of many possible invention embodiments and are not to be construed as invention limitations or limiting the invention's scope except as defined by the attached claims.
This application claims the benefit of U.S. provisional application no. 61 /994,254 filed May 16, 2014, which is incorporated herein in its entirety by reference.
The Applicants PCT application entitled "DRAM Cells Storing Volatile and Nonvolatile Data" which claims priority of provisional application 61 /989,766 filed May 7, 2014; and PCT application entitled "SRAM With 1 to 10 bits of Single Ended, Nonvolatile Latch Memory" which claims priority of provisional applications 61 /992,741 and 61 /992,773 both filed May 13, 2014; and PCT application entitled "4 bit Nonvolatile Embedded DRAM" which also claims priority of provisional application 61 /994,254 filed May 16, 2014 are all being filed simultaneously with the present application and all three applications are hereby incorporated herein by reference in its entirety.
As used herein the phase change memories (PCM) i.e.. like with GST, or like a resistance random access memories (ReRAM) i.e.. a metal oxide, etc. are merely, sample embodiments of variable resistance memory cells and are not meant to be limited to such.
The following terms and phrases are used throughout the specification and have the meanings assigned thereto, unless otherwise specified.
1.VR = variable resistance memory - is a class of known prior art rewriteable nonvolatile memory elements like phase change memory (PCM), resistive random access memory (ReRAM), conductive bridge memory, solid electrolyte memory, equivalent, or like, etc.
2. FG = Floating Gate transistor - which has known prior art ability to store rewriteable nonvolatile memory by trapping electrons on a transistor with a floating gate. This trapped charged raises the voltage threshold, Vth, of the floating gate transistor substantially verses a lower voltage threshold, Vth, when no charge is trapped. Floating gate transistors or devices are used in EPROM, EEPROM, and Flash memories. These memories can be implemented with NOR and NAND, pass transistor or no pass transistor architectures.
3. known property - phase change memory has the known property of having a "reset state" of high resistance which is its amorphous state and a "set state" of low resistance which is its crystalline state (see Lee article cited earlier and Wong articles]); similar, resistive random access memory (ReRAM) has a "set" state of low resistance and a "reset" state of high resistance using some form of metal oxide (see U.S. Patent Publication No. 2011/0032747)
4. Vreset - is for a variable resistance memory material, best mode, a phase change memory (PCM) material ie. like a GST alloy, (see Wong ariticles) a relatively high voltage we are calling Vreset is applied to a phase change memory material that over a relatively short period of time will rapidly melt and make the PCM material amorphous ie. the atoms are substantially unlinked and so relatively high resistance to electrical current. In the Bedeschi et al. reference discussed earlier, this high resistance can be in the millions of ohms region. This Vreset voltage pulse is quickly ended to freeze the now unlinked atoms in this relatively unlinked high resistance state typically called a RESET STATE. In the invention figures herein, for example purposes only, Vreset = 0.75V is used.
5. Vcrystallize- ie. for a variable resistance memory material, best mode, a phase change memory (PCM) material ie. like a GST alloy, (see Wong et al reference) a relatively low voltage referred to herein as Vcrystallize is applied to a phase change memory material that over a relatively long period of time will slowly heat and substantially crystallize or link together the PCM atoms to create a relatively low resistance to electrical current flow. In the Bedeschi et al. reference this low resistance can be in the 10Kohm or less region. This low voltage Vcrystallize pulse is held for a long period to allow time for a substantial number of the PCM atoms to link together in a relatively low resistance state typically called a SET STATE. The high resistance state can range into the Meg ohm range. This Meg ohm high resistance state is a major invention operation concern for its capability to mask out potential line combination nonvolatile data from being accessible.
FIG. 2A-C shows various variable resistance (VR) memory cell schematics and symbol implemented with a pass transistor or pass gate rectifier ie. diode. The preferred variable resistance memory for this invention is a rewriteable phase change memory (PCM) element although this applies in scope as well to equivalent and like technologies like Resistive RAM, ReRAM, solid-electrolyte memories, etc.
The invention is equally applicable to floating gate (FG) memory cells like EPROM, EEPROM, and Flash, as also seen in FIG. 2D-F schematics and symbol. 4F^ and 6F layout styled cells are depicted.
Variable Resistance (VR) and Floating Gate (FG) Cells
The prior art drawing of FIG. 1 shows a word line (WL), bit line (BL) organized memory matrix, memory array, or memory block at least of rewriteable variable resistance (VR) or floating gate (FG) memory cells. A matrix line of these cells as shown in FIG. 1 , each have their own supply terminal and the ground potential line "all shared" along that said matrix line of cells.
However in FIG. 2 the invention utilizes not one but at least two potential lines along a said matrix line of cells to supply one of a plurality of different potential sources to each said variable resistance (VR) or floating gate (FG) cell. This is so that each said cell is then on encoded with a 1 bit or higher, potential line combination, nonvolatile (NV) number. This nonvolatile data is, in addition, to the already existing VR or FG element nonvolatile data bit.
The mathematical basis is: B=LOG2(#of potential lines); i.e. LOG2(2 lines) = 1 b; LOG2(4 lines) = 2b, etc. where B is the number ( #) of potential line combination NV bit(s) stored in these cells, in addition, to the already nonvolatile value stored by the VR material resistance or FG transistor voltage threshold. The example variable resistance (VR) and floating gate (FG) cells storing 2 bit potential line combination, nonvolatile (NV) numbers are shown with their schematic symbols in FIG. 3.
To read 1 b, 2b, or higher potential line combination nonvolatile (NV) data from these VR or FG cells, one may choose to: (1 ) first save a copy of any existing VR or FG element nv data to another memory like a DRAM or other memory block, then (2) use the potential line combination, NV data within these cells followed by (3) a restore of the original NV data copied data back into these VR or FG cells.
To use the potential line combination, NV data within these cells in FIG. 2 and 3 you first start by initializing or erasing the variable resistance (VR) element like RP to ie. a low resistance state or the floating gate (FG) transistor to a low voltage threshold, Vth.
The flow charts or for next loops shown in FIG. 4 and 5 illustrate this initialization process. Specifically, next to read out the 1 b or 2b potential line combination, nonvolatile numbers encoded within these VR or FG cells and follow the 1 b or 2b timing diagrams found in FIG. 6 which is illustrated in FIG. 7.
In the alternative case that cross point memory cells with diode-like pass gates like FIG. 2C and FIG. 3C are used then, instead, of 1 bit, potential lines V[0] and V[1 ] being used as in FIG. 6A used in their place are 1 bit word lines WL[0] and WL[1 ] or, instead, of 2 bit, potential lines V[00], V[01 ], V[10], and V[11 ] being used as in FIG. 6B we would use in their place, 2 bit word lines WL[00], WL[01 ], WL[10], and WL[11 ]. This is shown in the FIG. 8A and B timing diagrams. This is applicable for a VR cell using a BL[0] and BL[1 ] to encode and store 1 NV bit & for BL[00], BL[01 ], BL[10], and BL[11 ] to encode and store 2 NV bits of bit line combination NV data.
For diode selected cells, WL or BL, must be sufficient voltage to turn on the selection device.
In an alternate embodiment, sharing the V, WL, or BL potential lines for storing potential line combination nonvolatile data between adjacent memory cells to save chip area is used.
As used in the invention a word line, bit line, matrix or block or array of at least variable resistance (VR) or floating gate (FG) cells, a matrix line of VR or FG cells encoded with and so storing at least:
(a) (M+N) =4, 2b #s of ( potential line combination data + VR or FG data ) or
(b) (M+N+P+Q) = 8, 3b #s of (potential line combination data + VR or FG data)
are basis of this invention.
Examples of "matrix line of cells" encoded with 1 b potential line combination, nonvolatile data and 2b potential line combination, nonvolatile data are illustrated in the following figures.
FIG. 9 shows a matrix word line or matrix bit line of 1 b cells.
FIG. 10 shows a matrix negative slope of 1 b cells where the slope can vary but must stay negative.
FIG. 11 shows a matrix positive slope of 1 b cells where the slope can vary but must stay positive. FIG..12 shows a matrix line of 1 b cells where the supplying potential lines are crisscrossing. FIG. 13 shows a matrix word line or matrix bit line of 2b cells.
FIG. 14 shows a matrix negative slope of 2b cells where the slope can vary but must stay negative.
FIG. 15 shows a matrix positive slope of 2b cells where the slope can vary but must stay positive, and
FIG. 16 shows a matrix line of 2b cells where the supplying potential lines are crisscrossing. In one embodiment nonvolatile potential line combination data bits in these, M+N, and, M+N+P+Q, matrix line of cells are physically consecutive. In an alternate embodiment they are spaced apart by other cells.
Furthermore, because encoding of random-like or cell to cell alternating NV potential line combination data can be more difficult on manufacturing due to constant wiring changes from cell to cell, this patent further defines the, M+N, and, M+N+P+Q matrix line of cells into whether they are storing (a) random-like, alternating, nonvolatile potential line combination data, or (b)structured-like, separated, nonvolatile potential line combination data. The latter can have relaxed wire spacing from cell to cell due to the ability to share, combine, or merge wiring together due to nv data separated into distinct groupings.
An example of random-like, alternating, nonvolatile potential line combination data can be a nonvolatile binary sequence like: 01012.
An example of structured-like, separated, nonvolatile potential line combination data can be a nonvolatile binary sequence like: H OO2 .
FIG. 9 to FIG. 16 are examples of these random-like and structured-like nonvolatile potential line combination data sequences.
While the invention is described as preferably using variable resistance memory cells and floating gate memory cells, other like or equivalent memory cells may be used.
The foregoing description of various and preferred embodiments of the present invention has been provided for purposes of illustration only, and it is understood that numerous modifications, variations and alterations may be made without departing from the scope and spirit of the invention as set forth in the following claims

Claims

1 . A variable resistance memory device for storing 2 bits or more data comprising:
a plurality of word lines (WL);
a plurality of bit lines (BL);
a 0th and a 1 st potential line;
a said BL said WL matrix line of at least variable resistance (VR) M + N memory cells; wherein across said matrix line said 0th potential line supplies at least, M said VR cells while said 1 st potential line supplies at least, N said VR cells;
wherein across said matrix line, said 0th & 1 st potential lines each extend as far in distance to supply at least said M and said N VR cells;
wherein across said matrix line of cells said M and said N VR cells are supplied by said potential lines, encoded with 2 different physical representations of at least:
B= LOG2(2 said potential lines) = 1 bit of, said VR memory cell, potential line combination, nonvolatile (nv) data;
wherein encoded and stored across a said matrix line there are at least a combined:(said M+ said N) different 1 b nonvolatile #s of potential line combination data plus (said M+ said N) 1 b nonvolatile said variable resistance (VR) data bits, wherein each said M and said N VR cell stores a combined 2 bits of nonvolatile data.
2. The variable resistance memory device according to Claim 1 , further comprising a 2nd and 3rd potential line and said matrix line includes P and Q VR cells, wherein said 2nd potential line supplies at least said P VR cells and said 3rd potential line supplies at least Q VR cells, such that said M, said N, said P and said Q VR cell stores a combined 3 bits of nonvolatile data.
3. The variable resistance memory device according to Claim 1 , wherein said VR cells are selected from the group consisting of phase change memory (PCM) cells, resistive RAM (ReRAM) cells; conductive bridge RAM cells; and solid electrolyte memories.
4. A floating gate memory device for storing 2 bits or more data comprising:
a plurality of word lines (WL);
a plurality of bit lines (BL);
a 0th & 1 st potential line;
a said BL said WL matrix line of at least Floating Gate (M + N) (FG) memory cells; wherein across matrix line of at least said FG cells, said 0th potential line supplies at least, M FG cells while said 1st potential line supplies at least, N FG cells;
wherein across said matrix line, said 0th & 1st potential lines each extend as far in distance to supply at least said M and said N FG matrix line;
wherein across said matrix line of cells said M and N FG cells are supplied by said potential lines, and are encoded with two different physical representations of at least: B= LOG2(2 said potential lines) = 1 bit of, said FG memory cell, potential line combination, nonvolatile (nv) data; wherein encoded and stored across a said matrix line of cells there are at least a combined: (said M+ said N ) said different 1f nv #s of potential line combination data plus(said M+ said N ) 1 b nv said floating gate (FG) data bits; wherein each said M and said N FG cell stores a said combined 2 bits of nv data.
5. The floating gate memory device according to Claim 4, further comprising a 2nd and 3rd potential line and said matrix line includes P and Q FG cells, wherein said 2nd potential line supplies at least said P FG cells and said 3rd potential line supplies at least Q FG cells, such that said M, said N, said P and said Q FG cell stores a combined 3 bits of nonvolatile data.
6. The floating gate memory device according to Claim 4, wherein said FG cells used in the invention are selected from the group consisting of flash cells and NOR flash cells.
7. A semiconductor memory device comprising
a plurality of word lines (WL);
a plurality of bit lines (BL);
at least two potential lines, 0th and 1 st potential line; a said BL said WL matrix line of at least Floating Gate (FG) memory cells or Variable Resistance (VR) memory cells; wherein across matrix line of at least said FG cells or said VR cells, said 0th potential line supplies at least, M FG cells or M VR cells while said 1 st potential line supplies at least, N FG cells or N VR;
wherein across said matrix line, said 0th & 1st potential lines each extend as far in distance to supply at least said M and said N FG matrix line or said M and said N VR matrix line;
wherein across said matrix line of cells said M and N FG cells or M and N VR cells are supplied by said potential lines, and are encoded with two different physical representations of at least: B= LOG2(2 said potential lines) = 1 bit of, said FG memory cell or said VG memory cell, potential line combination, nonvolatile (nv) data; wherein encoded and stored across a said matrix line of cells there are at least a combined: (said M+ said N ) said different 1f nv #s of potential line combination data plus(said M+ said N ) 1 b nv said floating gate (FG) data bits or said variable resistance (VR) data bits; wherein each said M and said N FG cell or said M and said N VR stores a said combined 2 bits of nv data or more.
PCT/US2015/029353 2014-05-07 2015-05-06 4 bit nonvolatile flash or variable resistance memory WO2015171684A1 (en)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US201461989766P 2014-05-07 2014-05-07
US61/989,766 2014-05-07
US201461992741P 2014-05-13 2014-05-13
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