WO2015146788A1

WO2015146788A1 - Electronic apparatus

Info

Publication number: WO2015146788A1
Application number: PCT/JP2015/058285
Authority: WO
Inventors: 剛史 ▲浜▼川
Original assignee: 京セラドキュメントソリューションズ株式会社
Priority date: 2014-03-28
Filing date: 2015-03-19
Publication date: 2015-10-01

Abstract

With respect to writing of a plurality of programs to non-volatile memory (1): (a1) program information for identifying write positions for the plurality of programs is generated; and (a2) the program information is written to the non-volatile memory (1), merge data which includes a combination of a plurality of programs to be written to the non-volatile memory (1) is continuously written in a predetermined storage region (21) within the non-volatile memory (1), and if there is a bad block in the predetermined storage region (21), the merge data is continuously written so that the bad block is straddled. With respect to reading out a plurality of programs from the non-volatile memory (1) to RAM (2): (b1) program information is read out so as to identify the write positions for the plurality of programs; and (b2) the plurality of programs are read out from the predetermined storage region (21) on the basis of the identified write positions.

Description

Electronics

The present invention relates to an electronic device.

In an electronic device incorporating an embedded system, a plurality of programs are written in advance in a nonvolatile memory such as a NAND flash memory. In such an electronic device, a storage area dedicated to the program is secured in the nonvolatile memory for each program (see, for example, Patent Document 1).

JP 2000-35919 A

FIG. 9 is a diagram for explaining a storage area dedicated to a plurality of programs in the nonvolatile memory. In the nonvolatile memory, there are congenital defective blocks that already exist at the time of manufacture and acquired defective blocks that occur due to use. Therefore, as shown in FIG. 9, unused areas are included in the plurality of storage areas 101a to 101d dedicated to the program so that the program can be written to the storage area dedicated to the program even if a bad block occurs. The size of the storage area dedicated to the program is larger than the size of the program by the size of the unused area.

In this way, the capacity of the non-volatile memory of an electronic device with a built-in system is reduced due to cost requirements, but an unused area is provided for each program. Need to use memory.

The present invention has been made in view of the above problems, and an object of the present invention is to obtain an electronic device in which the size of an area for writing a plurality of programs in a nonvolatile memory can be reduced.

The electronic apparatus according to the present invention includes a processor, a rewritable nonvolatile memory that stores a plurality of programs, and a volatile memory. The processor, when writing a plurality of programs to the nonvolatile memory, (a1) generates program information for specifying a writing position of the plurality of programs, and (a2) stores the program information in the nonvolatile memory. In addition, the merge data including a combination of a plurality of programs to be written to the nonvolatile memory is continuously written in a predetermined storage area in the nonvolatile memory, and a defective block is written in the predetermined storage area. If present, the data is continuously written across the defective block. In addition, when the processor reads the plurality of programs from the nonvolatile memory to the volatile memory, (b1) reads the program information to identify the writing positions of the plurality of programs, and (b2) the The defective block in the predetermined storage area is specified, and (b3) the plurality of programs are read from the predetermined storage area based on the writing position and the position of the specified defective block.

According to the present invention, the size of the area for writing a plurality of programs in the nonvolatile memory of the electronic device can be reduced.

FIG. 1 is a block diagram showing a configuration of an electronic apparatus according to an embodiment of the present invention. FIG. 2 is a flowchart for explaining an operation at the time of program writing of the electronic apparatus according to the first embodiment. FIG. 3 is a diagram for explaining an operation at the time of program writing of the electronic apparatus according to the first embodiment. FIG. 4 is a flowchart for explaining the operation of the electronic device according to Embodiment 1 when reading a program. FIG. 5 is a diagram for explaining an operation at the time of program reading of the electronic device according to the first embodiment. FIG. 6 is a flowchart for explaining the operation at the time of program writing of the electronic apparatus according to the second embodiment. FIG. 7 is a diagram for explaining an operation at the time of program writing of the electronic apparatus according to the second embodiment. FIG. 8 is a diagram for explaining an operation at the time of program reading of the electronic device according to the second embodiment. FIG. 9 is a diagram for explaining storage areas dedicated to a plurality of programs in the nonvolatile memory.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 FIG.

FIG. 1 is a block diagram showing a configuration of an electronic device according to an embodiment of the present invention. The electronic apparatus illustrated in FIG. 1 is, for example, an image forming apparatus such as a printer or a multifunction peripheral, an information terminal apparatus, or the like.

The electronic device shown in FIG. 1 has a built-in system and loads a program stored in a nonvolatile memory 1 such as a NAND flash memory into a RAM (Random Access Memory) 2 which is a volatile memory. , CPU (Central Processing Unit), MPU (Micro Processing Unit), etc.

The electronic device shown in FIG. 1 has a function of writing a plurality of programs in the nonvolatile memory 1 and updating the plurality of programs in the nonvolatile memory 1. Note that the program (new version of the program) used for the update is obtained by reading it from a recording medium through an interface (not shown) or downloading it from a server on the network using a communication device (not shown).

Specifically, when the electronic device shown in FIG. 1 is activated, the boot loader 11 is executed by the processor 3, the system program in the nonvolatile memory 1 is loaded into the RAM 2, and the execution of the system program is started. Thereafter, in accordance with the system program, an application program or the like is loaded from the nonvolatile memory 1 to the RAM 2 and executed as appropriate.

Further, when updating the program in the nonvolatile memory 1, it is executed according to the update program 12, which is one of the programs loaded in the RAM 2.

Next, the operation of the electronic device according to the first embodiment will be described.

(A) Program write operation

FIG. 2 is a flowchart for explaining the operation of the electronic device according to the first embodiment when writing a program. FIG. 3 is a diagram for explaining an operation at the time of program writing of the electronic apparatus according to the first embodiment.

First, the processor 3 acquires a plurality of programs (programs A to D in FIG. 3) to be written in the nonvolatile memory 1 in accordance with the update program 12, holds them on the RAM 2, and obtains header information about the plurality of programs. Generated and held on the RAM 2 (step S1).

The header information includes (a) header identifier (unique identifier indicating header information), (b) header information size, and (c) program information. In the first embodiment, the program information is information for specifying a program writing position and the like. In the first embodiment, for each program, a program identifier (an identifier unique to the program), a program size, and the like. And other attribute information (version information, program compression format, etc.). An end identifier is inserted at the end of the program information of one program, and the program information of a plurality of programs is continued in the same order as the program writing order while being separated by the end identifier.

The header information is generated as one continuous data including program information for a plurality of programs.

Next, the processor 3 combines a plurality of programs to be written in accordance with the update program 12, and generates merge data including the combination (step S2).

In Embodiment 1, for example, as shown in FIG. 3, the program information is continuously combined with a plurality of programs and included in the merge data. In the first embodiment, the program information includes at least the order of the plurality of programs and the size of each of the plurality of programs.

Specifically, in the first embodiment, the merge data is a combination of header information and a plurality of programs. Therefore, the writing position of each program can be specified from the leading writing position of the merge data, the size of the header information, and the size of the program.

Then, according to the update program 12, the processor 3 continuously writes merge data from the top of one predetermined storage area 21 of the nonvolatile memory 1 (step S3). Therefore, in the first embodiment, the header information is continuously written in the nonvolatile memory 1 as one data, and the header information (that is, program information) is written in the predetermined storage area 21.

At this time, for example, as shown in FIG. 3, when the block to be written in the predetermined storage area 21 is a bad block, the processor 3 writes the merge data continuously across the bad block according to the update program 12. Go. That is, the continuation of the program written in the block immediately before the bad block is written from the block next to the bad block. In the example shown in FIG. 3, the program B and the program D are written across the defective blocks.

In this way, it is only necessary to provide one unused area at the end portion of the predetermined storage area 21, and programs are continuously stored in the predetermined storage area 21 without securing an unused area for each of a plurality of programs. Is written to. *

(B) Operation when reading a program

FIG. 4 is a flowchart for explaining the operation of the electronic device according to Embodiment 1 when reading a program. FIG. 5 is a diagram for explaining an operation at the time of program reading of the electronic device according to the first embodiment.

The processor 3 detects the header information stored in the predetermined storage area 21 according to the boot loader 11 or the like based on the header identifier, and reads the header information (that is, program information) (step S11).

The processor 3 identifies the position of the defective block in the predetermined storage area 21 based on the result of the pass / fail check of each block of the nonvolatile memory 1 at the time of startup according to the boot loader 11 or the like (step S12).

Next, in accordance with the boot loader 11 or the like, the processor 3 writes each program write position (that is, a predetermined value) based on the read program information (in particular, the program size in the first embodiment) and the position of the specified defective block. (Offset from the beginning of the storage area 21) is specified, and the program is read from the write position in the predetermined storage area 21 to the RAM 2 while skipping bad blocks (step S13).

Specifically, the processor 3 specifies the program size one by one in order from the top of the program information according to the boot loader 11 and the like, and starts from the current reading position (the initial value is the next address after the end of the header information). Data for the specified size is read as a program from the predetermined storage area 21 to the RAM 2, and after the data, data for the specified size is read from the predetermined storage area 21 to the RAM 2 as the next program.

At this time, for the program divided by the defective block (for example, programs B and D in FIGS. 3 and 5), the part before the defective block and the part after the defective block are respectively read and stored in the RAM 2 so that they are continuous. Stored. In other words, the program divided by the bad block is read from the head to the block immediately before the bad block, and the size of the part before the bad block is subtracted from the program size specified from the program information. Only the size obtained is read from the blocks following the bad block.

As described above, the programs written in the predetermined storage area 21 as described above are individually loaded into the RAM 2 based on the header information (that is, program information).

In the first embodiment, when the program is read, the position information of the bad block and the header information are required to calculate the program write position (the above-described offset) by calculation. It is preferable to read all.

As described above, according to the first embodiment, when the processor 3 writes a plurality of programs in the nonvolatile memory 1, (a1) generates program information for specifying the writing positions of the plurality of programs. (A2) The program information is written in the nonvolatile memory 1 and merge data including a combination of a plurality of programs to be written in the nonvolatile memory 1 is continuously written in the predetermined storage area 21 in the nonvolatile memory 1 In the case where a defective block exists in the predetermined storage area 21, the writing is continuously performed across the defective block. When the processor 3 reads a plurality of programs from the nonvolatile memory 1 to the RAM 2, the processor 3 reads (b1) the program information to identify the writing positions of the plurality of programs, and (b2) a defect in the predetermined storage area 21. A block is specified, and (b3) a plurality of programs are read from the predetermined storage area 21 based on the writing position and the position of the specified defective block.

Thus, it is not necessary to secure an unused area provided for each of the plurality of programs to avoid a shortage of a program writing area caused by a defective block, and the plurality of programs are written in the nonvolatile memory 1. The size of the area can be small.

Embodiment 2. FIG.

In the first embodiment, the header information is stored in the predetermined storage area 21 together with a plurality of programs. In the second embodiment, the header information is stored in a different area from the predetermined storage area in which the plurality of programs are stored. Remembered. Therefore, in the second embodiment, program information is not combined with a plurality of programs and is not included in merge data.

The basic configuration of the electronic device according to the second embodiment is the same as that of the first embodiment (FIG. 1), but operates as follows.

Next, the operation of the electronic device according to the second embodiment will be described.

(A) Program write operation

FIG. 6 is a flowchart for explaining the operation at the time of program writing of the electronic device according to the second embodiment. FIG. 7 is a diagram for explaining an operation at the time of program writing of the electronic apparatus according to the second embodiment.

First, the processor 3 acquires a plurality of programs (programs A to D in FIG. 7) to be written in the nonvolatile memory 1 according to the update program 12, holds them on the RAM 2, combines the plurality of programs to be written, Merge data including the combination is generated (step S21).

Next, the processor 3 writes the merge data continuously from the top of the predetermined storage area 21a of the nonvolatile memory 1 according to the update program 12 (step S22). At this time, for example, as shown in FIG. 7, when the block to be written in the predetermined storage area 21 a is a bad block, the processor 3 writes the merge data continuously across the bad block according to the update program 12. Go.

Then, the processor 3 specifies the writing position of each program after writing the merge data in accordance with the update program 12, generates header information for the plurality of programs, and stores the header information on the RAM 2 (step S23). Writing to another storage area 21b of the memory 1 (step S24).

In the second embodiment, the program information in the header information includes information (for example, an address) that directly indicates the program writing position instead of the program size. That is, in the second embodiment, since the header information is generated after the program is written, the writing position of the program is known when the header information is generated, and the information can be included in the program information.

As described above, the unused area only needs to be provided at the end of the predetermined storage area 21a, and the program is continuously stored in the predetermined storage area 21a without securing an unused area for each of the plurality of programs. Is written to. *

(B) Operation when reading a program

FIG. 8 is a diagram for explaining an operation at the time of reading a program of the electronic device according to the second embodiment.

In the second embodiment, similarly to the first embodiment, the processor 3 detects the header information stored in the storage area 21b according to the boot loader 11 and the like, reads the header information (that is, program information), and reads the header. Based on the program information in the information, the writing position of each program is specified, and the program is read from the writing position in the predetermined storage area 21a to the RAM 2 while skipping the defective block.

As described above, the programs written in the predetermined storage area 21a as described above are individually loaded into the RAM 2 based on the header information (that is, program information).

In the second embodiment, since the program information includes information directly indicating the program writing position, it is not necessary to specify the position of the defective block in the predetermined storage area 21a when reading the program. Absent. Further, it is not necessary to calculate the program writing position (the above-described offset) at the time of program reading.

As described above, since the information on the position of the defective block is not required at the time of reading the program, the information on the position of the defective block obtained at the time of starting is not retained after the completion of the starting process, and a part of a plurality of programs is May be read by the boot loader 11, and the remaining program may be read by the program read by the boot loader 11.

As described above, according to the second embodiment, since the program writing position can be easily specified at the time of reading the program, the time required for reading the program can be shortened.

It should be noted that each of the above-described embodiments is shown for the purpose of illustration and explanation, and this is not all and the invention is not limited to this embodiment.

Various changes and modifications to the above-described embodiment will be apparent to those skilled in the art. Such changes and modifications may be made without departing from the spirit and scope of the subject matter and without diminishing its intended advantages. That is, such changes and modifications are intended to be included in the appended claims.

The present invention can be applied to, for example, an electronic device incorporating a built-in system.

Claims

A processor;
A rewritable nonvolatile memory that stores multiple programs,
With volatile memory,
The processor, when writing a plurality of programs in the nonvolatile memory, (a1) generates program information for specifying a writing position of the plurality of programs, and (a2) stores the program information in the nonvolatile memory. And merge data including a combination of a plurality of programs to be written to the nonvolatile memory is continuously written in a predetermined storage area in the nonvolatile memory, and a defective block exists in the predetermined storage area. In this case, when the plurality of programs are continuously written across the defective blocks and the plurality of programs are read from the nonvolatile memory to the volatile memory, (b1) the program information is read and the writing positions of the plurality of programs are set. (B2) based on the position of the specified writing position, It from the storage area is read out a plurality of programs,
Electronic equipment characterized by
The program information is continuously combined with the plurality of programs and included in the merge data and written to the predetermined storage area,
When the processor reads the plurality of programs from the nonvolatile memory to the volatile memory, the processor identifies the defective block in the predetermined storage area, identifies the identified writing position, and identifies the identified defective block Reading the plurality of programs from the predetermined storage area,
The electronic device according to claim 1.
3. The electronic apparatus according to claim 2, wherein the program information includes at least an order of the plurality of programs and a size of each of the plurality of programs.
The electronic apparatus according to claim 1, wherein the program information is written in an area different from the predetermined storage area.
2. The electronic apparatus according to claim 1, wherein the program information about the plurality of programs is generated as one continuous data and continuously written in the nonvolatile memory.
The electronic device according to claim 1, wherein the nonvolatile memory is a NAND flash memory.