WO2015127124A2 - Imbalanced cross-inhibitory mechanism for spatial target selection - Google Patents

Abstract

A method of selecting a target from among multiple targets includes setting an imbalance for connections in a neural network based on a selection function. The method also includes modifying a relative activation between multiple targets based on the imbalance. The relative activation corresponds to one of the targets.

Description

IMBALANCED CROSS-INHIBITORY MECHANISM FOR

SPATIAL TARGET SELECTION

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit under 35 U.S.C. § 119(e) to U.S.

Provisional Patent Application No. 61/943,231, entitled "IMBALANCED CROSS- INHIBITORY MECHANISM FOR SPATIAL TARGET SELECTION," filed on February 21, 2014, and to U.S. Provisional Patent Application No. 61/943,227, entitled "DYNAMIC SPATIAL TARGET SELECTION," filed on February 21, 2014, the disclosure of which is expressly incorporated by reference herein in its entirety.

BACKGROUND

Field

[0002] Certain aspects of the present disclosure generally relate to neural system engineering and, more particularly, to systems and methods for an imbalanced cross- inhibitory mechanism for spatial target selection.

Background

[0003] An artificial neural network, which may comprise an interconnected group of artificial neurons (i.e., neuron models), is a computational device or represents a method to be performed by a computational device. Artificial neural networks may have corresponding structure and/or function in biological neural networks. However, artificial neural networks may provide innovative and useful computational techniques for certain applications in which traditional computational techniques are cumbersome, impractical, or inadequate. Because artificial neural networks can infer a function from observations, such networks are particularly useful in applications where the complexity of the task or data makes the design of the function by conventional techniques burdensome. Thus, it is desirable to provide a neuromorphic receiver to select a target based on an imbalanced cross-inhibitory mechanism specified for target cells.

SUMMARY

[0004] According to an aspect of the present disclosure, a method of selecting a target from among multiple targets is presented. The method includes setting an imbalance for connections in a neural network based on a selection function. The method also includes modifying a relative activation between the targets based on the imbalance. The relative activation corresponds to one or more targets.

[0005] Another aspect of the present disclosure is directed to an apparatus for selecting a target from among multiple targets. The apparatus includes means for setting an imbalance for connections in a neural network based on a selection function. The apparatus also includes means for modifying a relative activation between the targets based on the imbalance. The relative activation corresponds to one or more targets.

[0006] In another aspect of the present disclosure, a computer program product for selecting a target from among multiple targets is disclosed. The computer readable medium has non-transitory program code recorded thereon which, when executed by the processor(s), causes the processor(s) to perform operations of setting an imbalance for connections in a neural network based on a selection function. The program code also causes the processor(s) to modify a relative activation between the targets based on the imbalance. The relative activation corresponds to one or more targets.

[0007] Another aspect of the present disclosure is directed to an apparatus for selecting a target from among multiple targets, the apparatus having a memory and at least one processor coupled to the memory. The processor(s) is configured to set an imbalance for connections in a neural network based on a selection function. The processor(s) is also configured to modify a relative activation between the targets based on the imbalance. The relative activation corresponds to one or more targets.

[0008] Additional features and advantages of the disclosure will be described below. It should be appreciated by those skilled in the art that this disclosure may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the teachings of the disclosure as set forth in the appended claims. The novel features, which are believed to be characteristic of the disclosure, both as to its organization and method of operation, together with further objects and advantages, will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The features, nature, and advantages of the present disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like reference characters identify correspondingly throughout.

[0010] FIGURE 1 illustrates an example network of neurons in accordance with certain aspects of the present disclosure.

[0011] FIGURE 2 illustrates an example of a processing unit (neuron) of a computational network (neural system or neural network) in accordance with certain aspects of the present disclosure.

[0012] FIGURE 3 illustrates an example of spike-timing dependent plasticity (STDP) curve in accordance with certain aspects of the present disclosure.

[0013] FIGURE 4 illustrates an example of a positive regime and a negative regime for defining behavior of a neuron model in accordance with certain aspects of the present disclosure.

[0014] FIGURES 5 and 6 illustrate target maps according to aspects of the present disclosure.

[0015] FIGURE 7 illustrates conventional cross-inhibition of neurons.

[0016] FIGURE 8 illustrates a target map according to an aspect of the present disclosure.

[0017] FIGURE 9 illustrates an example implementation of designing a neural network using a general-purpose processor in accordance with certain aspects of the present disclosure. [0018] FIGURE 10 illustrates an example implementation of designing a neural network where a memory may be interfaced with individual distributed processing units in accordance with certain aspects of the present disclosure.

[0019] FIGURE 11 illustrates an example implementation of designing a neural network based on distributed memories and distributed processing units in accordance with certain aspects of the present disclosure.

[0020] FIGURE 12 illustrates an example implementation of a neural network in accordance with certain aspects of the present disclosure.

[0021] FIGURE 13 is a block diagram illustrating selecting a target in a neural network in accordance with an aspect of the present disclosure.

DETAILED DESCRIPTION

[0022] The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0023] Based on the teachings, one skilled in the art should appreciate that the scope of the disclosure is intended to cover any aspect of the disclosure, whether implemented independently of or combined with any other aspect of the disclosure. For example, an apparatus may be implemented or a method may be practiced using any number of the aspects set forth. In addition, the scope of the disclosure is intended to cover such an apparatus or method practiced using other structure, functionality, or structure and functionality in addition to or other than the various aspects of the disclosure set forth. It should be understood that any aspect of the disclosure disclosed may be embodied by one or more elements of a claim. [0024] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0025] Although particular aspects are described herein, many variations and permutations of these aspects fall within the scope of the disclosure. Although some benefits and advantages of the preferred aspects are mentioned, the scope of the disclosure is not intended to be limited to particular benefits, uses or objectives. Rather, aspects of the disclosure are intended to be broadly applicable to different technologies, system configurations, networks and protocols, some of which are illustrated by way of example in the figures and in the following description of the preferred aspects. The detailed description and drawings are merely illustrative of the disclosure rather than limiting, the scope of the disclosure being defined by the appended claims and equivalents thereof.

AN EXAMPLE NEURAL SYSTEM, TRAINING AND OPERATION

[0026] FIGURE 1 illustrates an example artificial neural system 100 with multiple levels of neurons in accordance with certain aspects of the present disclosure. The neural system 100 may have a level of neurons 102 connected to another level of neurons 106 through a network of synaptic connections 104 (i.e., feed-forward connections). For simplicity, only two levels of neurons are illustrated in FIGURE 1, although fewer or more levels of neurons may exist in a neural system. It should be noted that some of the neurons may connect to other neurons of the same layer through lateral connections. Furthermore, some of the neurons may connect back to a neuron of a previous layer through feedback connections.

[0027] As illustrated in FIGURE 1, each neuron in the level 102 may receive an input signal 108 that may be generated by neurons of a previous level (not shown in FIGURE 1). The signal 108 may represent an input current of the level 102 neuron. This current may be accumulated on the neuron membrane to charge a membrane potential. When the membrane potential reaches its threshold value, the neuron may fire and generate an output spike to be transferred to the next level of neurons (e.g., the level 106). In some modeling approaches, the neuron may continuously transfer a signal to the next level of neurons. This signal is typically a function of the membrane potential. Such behavior can be emulated or simulated in hardware and/or software, including analog and digital implementations such as those described below.

[0028] In biological neurons, the output spike generated when a neuron fires is referred to as an action potential. This electrical signal is a relatively rapid, transient, nerve impulse, having an amplitude of roughly 100 mV and a duration of about 1 ms. In a particular embodiment of a neural system having a series of connected neurons (e.g., the transfer of spikes from one level of neurons to another in FIGURE 1), every action potential has basically the same amplitude and duration, and thus, the information in the signal may be represented only by the frequency and number of spikes, or the time of spikes, rather than by the amplitude. The information carried by an action potential may be determined by the spike, the neuron that spiked, and the time of the spike relative to other spike or spikes. The importance of the spike may be determined by a weight applied to a connection between neurons, as explained below.

[0029] The transfer of spikes from one level of neurons to another may be achieved through the network of synaptic connections (or simply "synapses") 104, as illustrated in FIGURE 1. Relative to the synapses 104, neurons of level 102 may be considered presynaptic neurons and neurons of level 106 may be considered postsynaptic neurons. The synapses 104 may receive output signals (i.e., spikes) from the level 102 neurons and scale those signals according to adjustable synaptic weights

where P is a total number of synaptic connections between the neurons of levels 102 and 106 and i is an indicator of the neuron level. In the example of FIGURE 1, i represents neuron level 102 and i+1 represents neuron level 106. Further, the scaled signals may be combined as an input signal of each neuron in the level 106. Every neuron in the level 106 may generate output spikes 110 based on the corresponding combined input signal. The output spikes 110 may be transferred to another level of neurons using another network of synaptic connections (not shown in FIGURE 1).

[0030] Biological synapses can mediate either excitatory or inhibitory

(hyperpolarizing) actions in postsynaptic neurons and can also serve to amplify neuronal signals. Excitatory signals depolarize the membrane potential (i.e., increase the membrane potential with respect to the resting potential). If enough excitatory signals are received within a certain time period to depolarize the membrane potential above a threshold, an action potential occurs in the postsynaptic neuron. In contrast, inhibitory signals generally hyperpolarize (i.e., lower) the membrane potential.

Inhibitory signals, if strong enough, can counteract the sum of excitatory signals and prevent the membrane potential from reaching a threshold. In addition to counteracting synaptic excitation, synaptic inhibition can exert powerful control over spontaneously active neurons. A spontaneously active neuron refers to a neuron that spikes without further input, for example due to its dynamics or a feedback. By suppressing the spontaneous generation of action potentials in these neurons, synaptic inhibition can shape the pattern of firing in a neuron, which is generally referred to as sculpturing. The various synapses 104 may act as any combination of excitatory or inhibitory synapses, depending on the behavior desired.

[0031] The neural system 100 may be emulated by a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, a software module executed by a processor, or any combination thereof. The neural system 100 may be utilized in a large range of applications, such as image and pattern recognition, machine learning, motor control, and alike. Each neuron in the neural system 100 may be implemented as a neuron circuit. The neuron membrane charged to the threshold value initiating the output spike may be implemented, for example, as a capacitor that integrates an electrical current flowing through it.

[0032] In an aspect, the capacitor may be eliminated as the electrical current integrating device of the neuron circuit, and a smaller memristor element may be used in its place. This approach may be applied in neuron circuits, as well as in various other applications where bulky capacitors are utilized as electrical current integrators. In addition, each of the synapses 104 may be implemented based on a memristor element, where synaptic weight changes may relate to changes of the memristor resistance. With nanometer feature-sized memristors, the area of a neuron circuit and synapses may be substantially reduced, which may make implementation of a large-scale neural system hardware implementation more practical.

[0033] Functionality of a neural processor that emulates the neural system 100 may depend on weights of synaptic connections, which may control strengths of connections between neurons. The synaptic weights may be stored in a non- volatile memory in order to preserve functionality of the processor after being powered down. In an aspect, the synaptic weight memory may be implemented on a separate external chip from the main neural processor chip. The synaptic weight memory may be packaged separately from the neural processor chip as a replaceable memory card. This may provide diverse functionalities to the neural processor, where a particular functionality may be based on synaptic weights stored in a memory card currently attached to the neural processor.

[0034] FIGURE 2 illustrates an exemplary diagram 200 of a processing unit (e.g., a neuron or neuron circuit) 202 of a computational network (e.g., a neural system or a neural network) in accordance with certain aspects of the present disclosure. For example, the neuron 202 may correspond to any of the neurons of levels 102 and 106 from FIGURE 1. The neuron 202 may receive multiple input signals 204_I-204_N, which may be signals external to the neural system, or signals generated by other neurons of the same neural system, or both. The input signal may be a current, a conductance, a voltage, a real-valued, and/or a complex-valued. The input signal may comprise a numerical value with a fixed-point or a floating-point representation. These input signals may be delivered to the neuron 202 through synaptic connections that scale the signals according to adjustable synaptic weights 206_I-206N (W_I_WN), where N may be a total number of input connections of the neuron 202.

[0035] The neuron 202 may combine the scaled input signals and use the combined scaled inputs to generate an output signal 208 (i.e., a signal Y). The output signal 208 may be a current, a conductance, a voltage, a real-valued and/or a complex-valued. The output signal may be a numerical value with a fixed-point or a floating-point representation. The output signal 208 may be then transferred as an input signal to other neurons of the same neural system, or as an input signal to the same neuron 202, or as an output of the neural system.

[0036] The processing unit (neuron) 202 may be emulated by an electrical circuit, and its input and output connections may be emulated by electrical connections with synaptic circuits. The processing unit 202 and its input and output connections may also be emulated by a software code. The processing unit 202 may also be emulated by an electric circuit, whereas its input and output connections may be emulated by a software code. In an aspect, the processing unit 202 in the computational network may be an analog electrical circuit. In another aspect, the processing unit 202 may be a digital electrical circuit. In yet another aspect, the processing unit 202 may be a mixed- signal electrical circuit with both analog and digital components. The computational network may include processing units in any of the aforementioned forms. The computational network (neural system or neural network) using such processing units may be utilized in a large range of applications, such as image and pattern recognition, machine learning, motor control, and the like.

[0037] During the course of training a neural network, synaptic weights (e.g., the

weights 1 and/or the weights 206I-206N from

FIGURE 2) may be initialized with random values and increased or decreased according to a learning rule. Those skilled in the art will appreciate that examples of the learning rule include, but are not limited to the spike-timing-dependent plasticity (STDP) learning rule, the Hebb rule, the Oja rule, the Bienenstock-Copper-Munro (BCM) rule, etc. In certain aspects, the weights may settle or converge to one of two values (i.e., a bimodal distribution of weights). This effect can be utilized to reduce the number of bits for each synaptic weight, increase the speed of reading and writing from/to a memory storing the synaptic weights, and to reduce power and/or processor

consumption of the synaptic memory.

Synapse Type

[0038] In hardware and software models of neural networks, the processing of synapse related functions can be based on synaptic type. Synapse types may be non- plastic synapses (no changes of weight and delay), plastic synapses (weight may change), structural delay plastic synapses (weight and delay may change), fully plastic synapses (weight, delay and connectivity may change), and variations thereupon (e.g., delay may change, but no change in weight or connectivity). The advantage of multiple types is that processing can be subdivided. For example, non-plastic synapses may not require plasticity functions to be executed (or waiting for such functions to complete). Similarly, delay and weight plasticity may be subdivided into operations that may operate together or separately, in sequence or in parallel. Different types of synapses may have different lookup tables or formulas and parameters for each of the different plasticity types that apply. Thus, the methods would access the relevant tables, formulas, or parameters for the synapse's type. [0039] There are further implications of the fact that spike -timing dependent structural plasticity may be executed independently of synaptic plasticity. Structural plasticity may be executed even if there is no change to weight magnitude (e.g., if the weight has reached a minimum or maximum value, or it is not changed due to some other reason) s structural plasticity (i.e., an amount of delay change) may be a direct function of pre-post spike time difference. Alternatively, structural plasticity may be set as a function of the weight change amount or based on conditions relating to bounds of the weights or weight changes. For example, a synapse delay may change only when a weight change occurs or if weights reach zero but not if they are at a maximum value. However, it may be advantageous to have independent functions so that these processes can be parallelized reducing the number and overlap of memory accesses.

DETERMINATION OF SYNAPTIC PLASTICITY

[0040] Neuroplasticity (or simply "plasticity") is the capacity of neurons and neural networks in the brain to change their synaptic connections and behavior in response to new information, sensory stimulation, development, damage, or dysfunction. Plasticity is important to learning and memory in biology, as well as for computational neuro science and neural networks. Various forms of plasticity have been studied, such as synaptic plasticity (e.g., according to the Hebbian theory), spike-timing-dependent plasticity (STDP), non-synaptic plasticity, activity-dependent plasticity, structural plasticity and homeostatic plasticity.

[0041] STDP is a learning process that adjusts the strength of synaptic connections between neurons. The connection strengths are adjusted based on the relative timing of a particular neuron's output and received input spikes (i.e., action potentials). Under the STDP process, long-term potentiation (LTP) may occur if an input spike to a certain neuron tends, on average, to occur immediately before that neuron's output spike. Then, that particular input is made somewhat stronger. On the other hand, long-term depression (LTD) may occur if an input spike tends, on average, to occur immediately after an output spike. Then, that particular input is made somewhat weaker, and hence the name "spike-timing-dependent plasticity." Consequently, inputs that might be the cause of the postsynaptic neuron's excitation are made even more likely to contribute in the future, whereas inputs that are not the cause of the postsynaptic spike are made less likely to contribute in the future. The process continues until a subset of the initial set of connections remains, while the influence of all others is reduced to an insignificant level.

[0042] Because a neuron generally produces an output spike when many of its inputs occur within a brief period (i.e., being cumulative sufficient to cause the output), the subset of inputs that typically remains includes those that tended to be correlated in time. In addition, because the inputs that occur before the output spike are

strengthened, the inputs that provide the earliest sufficiently cumulative indication of correlation will eventually become the final input to the neuron.

[0043] The STDP learning rule may effectively adapt a synaptic weight of a synapse connecting a presynaptic neuron to a postsynaptic neuron as a function of time difference between spike time t_pre of the presynaptic neuron and spike time t of the postsynaptic neuron (i.e., t = t - t_pre ). A typical formulation of the STDP is to increase the synaptic weight (i.e., potentiate the synapse) if the time difference is positive (the presynaptic neuron fires before the postsynaptic neuron), and decrease the synaptic weight (i.e., depress the synapse) if the time difference is negative (the postsynaptic neuron fires before the presynaptic neuron).

[0044] In the STDP process, a change of the synaptic weight over time may be typically achieved using an exponential decay, as given by:

where k₊ and k_ Tagn(At) are time constants for positive and negative time difference, respectively, a₊ and a_ are corresponding scaling magnitudes, and μ is an offset that may be applied to the positive time difference and/or the negative time difference.

[0045] FIGURE 3 illustrates an exemplary diagram 300 of a synaptic weight change as a function of relative timing of presynaptic and postsynaptic spikes in accordance with the STDP. If a presynaptic neuron fires before a postsynaptic neuron, then a corresponding synaptic weight may be increased, as illustrated in a portion 302 of the graph 300. This weight increase can be referred to as an LTP of the synapse. It can be observed from the graph portion 302 that the amount of LTP may decrease roughly exponentially as a function of the difference between presynaptic and postsynaptic spike times. The reverse order of firing may reduce the synaptic weight, as illustrated in a portion 304 of the graph 300, causing an LTD of the synapse.

[0046] As illustrated in the graph 300 in FIGURE 3, a negative offset μ may be applied to the LTP (causal) portion 302 of the STDP graph. A point of cross-over 306 of the x-axis (y=0) may be configured to coincide with the maximum time lag for considering correlation for causal inputs from layer i-1. In the case of a frame-based input (i.e., an input that is in the form of a frame of a particular duration comprising spikes or pulses), the offset value μ can be computed to reflect the frame boundary. A first input spike (pulse) in the frame may be considered to decay over time either as modeled by a postsynaptic potential directly or in terms of the effect on neural state. If a second input spike (pulse) in the frame is considered correlated or relevant to a particular time frame, then the relevant times before and after the frame may be separated at that time frame boundary and treated differently in plasticity terms by offsetting one or more parts of the STDP curve such that the value in the relevant times may be different (e.g., negative for greater than one frame and positive for less than one frame). For example, the negative offset μ may be set to offset LTP such that the curve actually goes below zero at a pre-post time greater than the frame time and it is thus part of LTD instead of LTP.

NEURON MODELS AND OPERATION

[0047] There are some general principles for designing a useful spiking neuron model. A good neuron model may have rich potential behavior in terms of two computational regimes: coincidence detection and functional computation. Moreover, a good neuron model should have two elements to allow temporal coding: arrival time of inputs affects output time and coincidence detection can have a narrow time window. Finally, to be computationally attractive, a good neuron model may have a closed- form solution in continuous time and stable behavior including near attractors and saddle points. In other words, a useful neuron model is one that is practical and that can be used to model rich, realistic and biologically-consistent behaviors, as well as be used to both engineer and reverse engineer neural circuits. [0048] A neuron model may depend on events, such as an input arrival, output spike or other event whether internal or external. To achieve a rich behavioral repertoire, a state machine that can exhibit complex behaviors may be desired. If the occurrence of an event itself, separate from the input contribution (if any), can influence the state machine and constrain dynamics subsequent to the event, then the future state of the system is not only a function of a state and input, but rather a function of a state, event, and input.

[0049] In an aspect, a neuron n may be modeled as a spiking leaky-integrate-and- fire neuron with a membrane voltage v_n (t) governed by the following dynamics:

where a and β are parameters, w_{m n} is a synaptic weight for the synapse connecting a presynaptic neuron m to a postsynaptic neuron n, and y_m (t) is the spiking output of the neuron m that may be delayed by dendritic or axonal delay according to At_{m n} until arrival at the neuron n's soma.

[0050] It should be noted that there is a delay from the time when sufficient input to a postsynaptic neuron is established until the time when the postsynaptic neuron actually fires. In a dynamic spiking neuron model, such as Izhikevich's simple model, a time delay may be incurred if there is a difference between a depolarization threshold v_t and a peak spike voltage v _k . For example, in the simple model, neuron soma dynamics can be governed by the pair of differential equations for voltage and recovery, i.e.:

where v is a membrane potential, u is a membrane recovery variable, k is a parameter that describes time scale of the membrane potential , a is a parameter that describes time scale of the recovery variable u, b is a parameter that describes sensitivity of the recovery variable u to the sub-threshold fluctuations of the membrane potential a membrane resting potential, / is a synaptic current, and C is a membrane's

capacitance. In accordance with this model, the neuron is defined to spike

when v > v peak '

Hunzinger Cold Model

[0051] The Hunzinger Cold neuron model is a minimal dual-regime spiking linear dynamical model that can reproduce a rich variety of neural behaviors. The model's one- or two-dimensional linear dynamics can have two regimes, wherein the time constant (and coupling) can depend on the regime. In the sub-threshold regime, the time constant, negative by convention, represents leaky channel dynamics generally acting to return a cell to rest in a biologically-consistent linear fashion. The time constant in the supra-threshold regime, positive by convention, reflects anti-leaky channel dynamics generally driving a cell to spike while incurring latency in spike- generation.

[0052] As illustrated in FIGURE 4, the dynamics of the model 400 may be divided into two (or more) regimes. These regimes may be called the negative regime 402 (also interchangeably referred to as the leaky-integrate-and-fire (LIF) regime, not to be confused with the LIF neuron model) and the positive regime 404 (also interchangeably referred to as the anti-leaky-integrate-and-fire (ALIF) regime, not to be confused with the ALIF neuron model). In the negative regime 402, the state tends toward rest (v_) at the time of a future event. In this negative regime, the model generally exhibits temporal input detection properties and other sub-threshold behavior. In the positive regime 404, the state tends toward a spiking event (v₅ ). In this positive regime, the model exhibits computational properties, such as incurring a latency to spike depending on subsequent input events. Formulation of dynamics in terms of events and separation of the dynamics into these two regimes are fundamental characteristics of the model.

[0053] Linear dual-regime bi-dimensional dynamics (for states v and u ) may be defined by convention as: dv

(5)

where q_p and r are the linear transformation variables for coupling.

[0054] The symbol p is used herein to denote the dynamics regime with the convention to replace the symbol p with the sign "-" or "+" for the negative and positive regimes, respectively, when discussing or expressing a relation for a specific regime.

[0055] The model state is defined by a membrane potential (voltage) v and recovery current u . In basic form, the regime is essentially determined by the model state. There are subtle, but important aspects of the precise and general definition, but for the moment, consider the model to be in the positive regime 404 if the voltage v is above a threshold ( v₊ ) and otherwise in the negative regime 402.

[0056] The regime-dependent time constants include τ _ which is the negative regime time constant, and τ₊ which is the positive regime time constant. The recovery current time constant r_M is typically independent of regime. For convenience, the negative regime time constant τ _ is typically specified as a negative quantity to reflect decay so that the same expression for voltage evolution may be used as for the positive regime in which the exponent and τ₊ will generally be positive, as will be r_M .

[0057] The dynamics of the two state elements may be coupled at events by transformations offsetting the states from their null-clines, where the transformation variables are:

r = δ(ν + ε) (8) where δ , ε , β and ν_ , ν₊ are parameters. The two values for v_p are the base for reference voltages for the two regimes. The parameter v_ is the base voltage for the negative regime, and the membrane potential will generally decay toward v_ in the negative regime. The parameter v₊ is the base voltage for the positive regime, and the membrane potential will generally tend away from v₊ in the positive regime.

[0058] The null-clines for v and u are given by the negative of the transformation variables q_p and r , respectively. The parameter δ is a scale factor controlling the slope of the u null-cline. The parameter ε is typically set equal to - v_ . The parameter β is a resistance value controlling the slope of the v null-clines in both regimes. The τ time-constant parameters control not only the exponential decays, but also the null-cline slopes in each regime separately.

[0059] The model may be defined to spike when the voltage v reaches a value v_s . Subsequently, the state may be reset at a reset event (which may be one and the same as the spike event): v = v_ (9) u = u + Au (10) where v_and Au are parameters. The reset voltage v_ is typically set to v_ .

[0060] By a principle of momentary coupling, a closed form solution is possible not only for state (and with a single exponential term), but also for the time required to reach a particular state. The close form state solutions are:

At

v(t + At) = (v(t)+ q_p > - q_p (11)

At

u(t + At) = (u(t) + r)e ^τ" - r (12)

[0061] Therefore, the model state may be updated only upon events, such as an input (presynaptic spike) or output (postsynaptic spike). Operations may also be performed at any particular time (whether or not there is input or output).

[0062] Moreover, by the momentary coupling principle, the time of a postsynaptic spike may be anticipated so the time to reach a particular state may be determined in advance without iterative techniques or Numerical Methods (e.g., the Euler numerical method). Given a prior voltage state v₀ , the time delay until voltage state v_f is reached is given by:

At = r_p log^^ (13) v₀ + q_P

[0063] If a spike is defined as occurring at the time the voltage state v reaches v_s , then the closed-form solution for the amount of time, or relative delay, until a spike occurs as measured from the time that the voltage is at a given state v is:

∞ otherwise where v₊ is typically set to parameter v₊ , although other variations may be possible.

[0064] The above definitions of the model dynamics depend on whether the model is in the positive or negative regime. As mentioned, the coupling and the regime p may be computed upon events. For purposes of state propagation, the regime and coupling (transformation) variables may be defined based on the state at the time of the last (prior) event. For purposes of subsequently anticipating spike output time, the regime and coupling variable may be defined based on the state at the time of the next (current) event.

[0065] There are several possible implementations of the Cold model, and executing the simulation, emulation or model in time. This includes, for example, event-update, step-event update, and step-update modes. An event update is an update where states are updated based on events or "event update" (at particular moments). A step update is an update when the model is updated at intervals (e.g., 1ms). This does not necessarily require iterative methods or Numerical methods. An event-based implementation is also possible at a limited time resolution in a step-based simulator by only updating the model if an event occurs at or between steps or by "step-event" update.

IMBALANCED TARGET SELECTION

[0066] Systems specified to take action on multiple targets, such as spatial targets, use various criteria for selecting one or more targets. The selection of a target may depend on a problem being solved. For example, one selection criterion uses the spatial relationship between targets and the object's current position. In this example, the selection criterion selects the target closest to the object's current position. Moreover, in the present example, the selection criterion selects a target based on an arbitrary function of spatial location.

[0067] In another configuration, the selection criterion is based on a network implementation and a representation of spatial locations. For example, in a

conventional implementation, locations are represented by a pair of integers (x,y). Targets may be represented by a list of x, y pairs, along with an x, y pair for the object's current position. The selection criteria can be applied by iterating through the list of targets and selecting the target that meets the selection criteria, such as selecting the target closest to the object's current position.

[0068] Spatial locations can be represented with a two-dimensional (2D) grid of spiking cells. The location of each cell in the grid may be mapped to position in physical space. A property of the cell may be indicated by the cell's activity, such as the spiking rate. In one configuration, an active cell indicates that the position is a target of interest. If an object includes a map of targets that is relative to the object's current position, one or more targets may be selected based on cross-inhibition.

Selecting the target based on cross-inhibition may be referred to as winner-take-all. That is, the object selects one or more targets having an activity rate that is greater than the activity rate of other targets. In the present application, target cells may be referred to as targets.

[0069] The weights of the connections may be asymmetric to bias the target selection. For example, a cell, such as a target cell, inhibits cells that are farther from the cell and/or the object. Moreover, in this example, target cells that are closer to the object (e.g., robot) receive less inhibition weights and/or receive excitatory weights. Cells that are equidistant from the object may have random imbalances in their cross- inhibition to mitigate a tie between targets. In one configuration, the excitatory weight and/or inhibitory weight (e.g., target bias) provided via the connections is based on the following equation:

[0070] In equation 15, c is scaling constant. In one configuration, c is equal to thirty. Furthermore, a is a shape constant and may be equal to .1. Moreover, r is a random number, such as zero or one, and may be used to provide a random imbalance. Additionally, D_pre is the distance of the presynaptic cell from the center and D_post is the distance of the postsynaptic cell from the center.

[0071] Aspects of the present disclosure are specified for a compact network that is wired to perform target selection based on spatial relationships of targets. In the above example, the imbalance in inhibitory weights is specified to select the target that is closest to the object. The selection may be referred to as winning. However, any arbitrary selection criteria may be used to bias the target selection.

[0072] As shown in FIGURE 5, a target map 500 may be represented by a 2D grid of place cells 502. The presence of a target at a location is specified by an activity, such as a spiking interval, of a cell. In one configuration, it is assumed that the coordinates of the target(s) in the target map 500 have been transformed to be relative to the object's position.

[0073] Coordinate transformation refers to the conversion of a representation of space relative to a first reference frame to a substantially similar representation relative to a second reference frame. For example, an object, such as a robot, may be given a set of coordinates for a target relative to the northwest corner of a room. In this example, the coordinates for the target are based on a world-centric reference frame (i.e., allocentric coordinate representation). Still, for an object to plan a movement toward that target, it is desirable to convert the allocentric coordinates to a representation relative to the object's current position and direction (i.e., egocentric reference frame). That is, the allocentric coordinates should be converted to egocentric coordinates. The egocentric coordinates of the target would change as the object moved around the room, still, the allocentric coordinates would remain the same as the object moved around the room. It would be desirable to maintain the egocentric coordinates based on a fixed position for the object, such as a center of a map.

[0074] As shown in FIGURE 5, the location of the object 504 is in the center of the target map 500. That is, in contrast to an allocentric map (not shown), the coordinates for the object 504 and the targets 506, 508, 510 in the target map 500 of FIGURE 5 are based on a reference frame from the object's position.

[0075] As previously discussed, the object is specified to select one or more targets based on a selection criteria, such as the target that is nearest to the object. In the present configuration, the network uses cross-inhibition to reduce the spiking of targets that are not nearest to the object. Moreover, the spiking of targets near the robot may be increased or reduced at a rate that is less than the spiking reduction of targets that are further from the object. In one configuration, a soft target selection is specified to select one or more targets. In another configuration, a hard target selection is specified to select only one target. Each target may correspond to one or more active neurons. Alternatively, multiple targets may correspond to one active neuron. Both the soft target selection and the hard target selection select the target(s) that is more active in comparison to other targets.

[0076] FIGURE 6 illustrates an example of target selection according to an aspect of the present disclosure. As shown in FIGURE 6, a first target map 600 of cells 612 includes an object 604 and multiple targets 606, 608, and 610. Specifically, the first target 606 is nearest to the object 604 in comparison to the second target 608 and the third target 610. Thus, because the first target 606 is nearest to the object 604, the network uses cross-inhibition to reduce the spiking of the second target 608 and the third target 610.

[0077] That is, the spiking of the targets farther from the object is reduced in comparison to the target that is nearest to the object. The one or more targets near the object may be the only spiking targets or may spike at a rate that is greater than targets that are farther from the robot. Therefore, because a target nearest to the object is the only spiking target or spikes at a greater rate in comparison to the other targets, the object selects the nearest target. As shown in FIGURE 6, as a result of the cross- inhibition, a second target map 602 only includes one active target 616 near an object 614.

[0078] In a conventional network, cross-inhibition is specified to allow one cell to spike at a rate that is greater than another cell. That is, when it is desired for one of the cells to be more likely to win, inhibitory weights may imbalance the bias for selection. For example, if one cell is closer to the object, then the inhibitory weights may bias the spiking of the other targets.

[0079] FIGURE 7 illustrates an example of cross-inhibition. As shown in FIGURE 7, the first cell 702 inhibits the second cell 704 so the first cell 702 is more likely to win. That is, an inhibitory weight may be output via a first inhibitory connection 706. The first inhibitory connection 706 is connected to the output 710 of the first cell 702. A second inhibitory connection 708 is also connected to the output 712 of the second cell 704. The second inhibitory connection 708 may also output an inhibitory weight to the first cell 702. Still, in this configuration, the inhibitory weight of the first inhibitory connection 706 is greater than the inhibitory weight of second inhibitory connection 708. Therefore, the first cell 702 inhibits the second cell 704 so the first cell 702 is more likely to win. Furthermore, the first cell 702 receives a signal (e.g., spike) via a first input 714 and the second cell 704 receives a signal (e.g., spike) via a second input 716.

[0080] As previously discussed, the aforementioned cross-inhibition may be applied to a two-dimension grid of cells. FIGURE 8 illustrates an example of cross-inhibition for target selection in a target map 800. As previously discussed, in one configuration, a selection function can be specified via relative scaling of the weights. That is, a specific target may have a spike rate that is greater than the spike rate of other targets.

[0081] As an example, as shown in FIGURE 8, the target 808 closest to the object cell 810 (referred to as "object") is selected because cells, such as the target cells 808 and/or non-target cells 812, closer to the object 810 inhibit cells, such as the target cells 802, 804, 806 and/or non-target cells 812, that are farther from the object 810. That is, the spiking of the target cells 802, 804, 806 that are not near the object 810 is inhibited so the object 810 selects the closest target cell 808. In one configuration, multiple targets may be candidate targets, however, based on the cross-inhibition, only one target is an active target.

[0082] As shown in FIGURE 8, the cells 808, 812, 810 may inhibit each other. For example, the target cell 808 closest to the object 810 inhibits the surrounding cells 812. Furthermore, the surrounding cells 812 may also inhibit or excite the target cell 808. Still, the inhibition output from the target cell 808 is greater than the inhibition received at the target cell 808 from the surrounding cells 812. The cells 808, 810, 812 provide inhibitory and/or excitatory outputs via connections 816.

[0083] Furthermore, FIGURE 8 shows the cells adjacent to the target cell 808 having inhibitory connections. Still, aspects of the present disclosure are not limited to inhibitory connections only being specified between cells and the inhibitory connections may be specified between cells of any distance.

[0084] As discussed above, in one configuration, an imbalance is set between connections in a neural network. The imbalance may be an inhibitory weight or an excitatory weight. The inhibitory weight decreases the spiking rate of a neuron and the excitatory weight increases the spiking of a neuron. The inhibitory weight may be provided via feed forward logical inhibitory connections and/or feedback logical inhibitory connections. Alternatively, or in addition to, the excitatory weight may be provided via feed forward excitatory inhibitory connections and/or feedback logical excitatory connections. The connection may be one or more first input layer

connection, neuron inputs, lateral connections, and/or other type of connection. That is, in one configuration, the connection is an input to a neuron. Alternatively, or in addition to, the connection is a lateral connection between neurons.

[0085] Furthermore, the imbalance is set based on a selection function, such as the distance of a target cell from an object. Still, the selection function is not limited to the distance of the target from the object and may be based on other criteria. For example, in another configuration, one or more targets are selected based on the probabilities of the targets. Each target may correspond to multiple active neurons or one active neuron. The probability may refer to spiking probability.

[0086] Moreover, in one configuration, a relative activation between neurons corresponding to candidate target cells is modified. The relative activation corresponds to one or more target cells and is based on the amount of imbalance between targets. The relative activation is specified so that one or more targets (e.g., neurons) have a greater amount of activity in comparison to other targets.

[0087] In one configuration, the targets are spatial targets. As previously discussed, one or more targets are selected based on an amount of imbalance provided via the connections between neurons. That is, the object selects the target with the highest spiking rate. The targets may be one or more active neurons.

[0088] FIGURE 9 illustrates an example implementation 900 of the aforementioned target selection using a general-purpose processor 902 in accordance with certain aspects of the present disclosure. Variables (neural signals), synaptic weights, system parameters associated with a computational network (neural network), delays, and frequency bin information may be stored in a memory block 904, while instructions executed at the general-purpose processor 902 may be loaded from a program memory 906. In an aspect of the present disclosure, the instructions loaded into the general- purpose processor 902 may comprise code for setting an amount of imbalance of connections in a neural network and/or modifying relative activation between targets based on the amount of imbalance.

[0089] FIGURE 10 illustrates an example implementation 1000 of the

aforementioned target selection where a memory 1002 can be interfaced via an interconnection network 1004 with individual (distributed) processing units (neural processors) 1006 of a computational network (neural network) in accordance with certain aspects of the present disclosure. Variables (neural signals), synaptic weights, system parameters associated with the computational network (neural network) delays, frequency bin information, relative activation, and/or connection imbalance, may be stored in the memory 1002, and may be loaded from the memory 1002 via

connection(s) of the interconnection network 1004 into each processing unit (neural processor) 1006. In an aspect of the present disclosure, the processing unit 1006 may be configured to set an amount of imbalance of connections in a neural network and/or modify relative activation between targets based on the amount of imbalance.

[0090] FIGURE 11 illustrates an example implementation 1100 of the

aforementioned target selection. As illustrated in FIGURE 11, one memory bank 1102 may be directly interfaced with one processing unit 1104 of a computational network (neural network). Each memory bank 1102 may store variables (neural signals), synaptic weights, and/or system parameters associated with a corresponding processing unit (neural processor) 1104 delays, frequency bin information, relative activation, and/or connection imbalance. In an aspect of the present disclosure, the processing unit 1104 may be configured to set an amount of imbalance of connections in a neural network and/or modify relative activation between targets based on the amount of imbalance.

[0091] FIGURE 12 illustrates an example implementation of a neural network 1200 in accordance with certain aspects of the present disclosure. As illustrated in FIGURE 12, the neural network 1200 may have multiple local processing units 1202 that may perform various operations of methods described above. Each local processing unit 1202 may comprise a local state memory 1204 and a local parameter memory 1206 that store parameters of the neural network. In addition, the local processing unit 1202 may have a local (neuron) model program (LMP) memory 1208 for storing a local model program, a local learning program (LLP) memory 1210 for storing a local learning program, and a local connection memory 1212. Furthermore, as illustrated in FIGURE 12, each local processing unit 1202 may be interfaced with a configuration processing unit 1214 for providing configurations for local memories of the local processing unit, and with a routing connection processing unit 1216 that provide routing between the local processing units 1202.

[0092] In one configuration, a neuron model is configured for setting an amount of imbalance of connections in a neural network and/or modifying relative activation between neurons based on the amount of imbalance. The neuron model includes a setting means and modifying means. In one aspect, the setting means and modifying means may be the general-purpose processor 902, program memory 906, memory block 904, memory 1002, interconnection network 1004, processing units 1006, processing unit 1104, local processing units 1202, and or the routing connection processing units 1216 configured to perform the functions recited. In another configuration, the aforementioned means may be any module or any apparatus configured to perform the functions recited by the aforementioned means. [0093] According to certain aspects of the present disclosure, each local processing unit 1202 may be configured to determine parameters of the neural network based upon desired one or more functional features of the neural network, and develop the one or more functional features towards the desired functional features as the determined parameters are further adapted, tuned and updated.

[0094] FIGURE 13 illustrates a method 1300 for selecting a target in a neural network. In block 1302, the neuron model sets an amount of imbalance of connections in a neural network. The imbalance may be set based on a selection function.

Furthermore, in block 1304, the neuron model modifies a relative activation between targets based on the amount of imbalance. The relative activation may correspond to one of the targets.

[0095] The various operations of methods described above may be performed by any suitable means capable of performing the corresponding functions. The means may include various hardware and/or software component(s) and/or module(s), including, but not limited to, a circuit, an application specific integrated circuit (ASIC), or processor. Generally, where there are operations illustrated in the figures, those operations may have corresponding counterpart means-plus- function components with similar numbering.

[0096] As used herein, the term "determining" encompasses a wide variety of actions. For example, "determining" may include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Additionally, "determining" may include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory) and the like. Furthermore, "determining" may include resolving, selecting, choosing, establishing and the like.

[0097] As used herein, a phrase referring to "at least one of a list of items refers to any combination of those items, including single members. As an example, "at least one of: a, b, or c" is intended to cover: a, b, c, a-b, a-c, b-c, and a-b-c.

[0098] The various illustrative logical blocks, modules and circuits described in connection with the present disclosure may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array signal (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components or any combination thereof designed to perform the functions described herein. A general- purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

[0099] The steps of a method or algorithm described in connection with the present disclosure may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in any form of storage medium that is known in the art. Some examples of storage media that may be used include random access memory (RAM), read only memory (ROM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, a hard disk, a removable disk, a CD-ROM and so forth. A software module may comprise a single instruction, or many instructions, and may be distributed over several different code segments, among different programs, and across multiple storage media. A storage medium may be coupled to a processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.

[00100] The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.

[00101] The functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in hardware, an example hardware configuration may comprise a processing system in a device. The processing system may be implemented with a bus architecture. The bus may include any number of interconnecting buses and bridges depending on the specific application of the processing system and the overall design constraints. The bus may link together various circuits including a processor, machine-readable media, and a bus interface. The bus interface may be used to connect a network adapter, among other things, to the processing system via the bus. The network adapter may be used to implement signal processing functions. For certain aspects, a user interface (e.g., keypad, display, mouse, joystick, etc.) may also be connected to the bus. The bus may also link various other circuits such as timing sources, peripherals, voltage regulators, power management circuits, and the like, which are well known in the art, and therefore, will not be described any further.

[00102] The processor may be responsible for managing the bus and general processing, including the execution of software stored on the machine-readable media. The processor may be implemented with one or more general-purpose and/or special- purpose processors. Examples include microprocessors, microcontrollers, DSP processors, and other circuitry that can execute software. Software shall be construed broadly to mean instructions, data, or any combination thereof, whether referred to as software, firmware, middleware, microcode, hardware description language, or otherwise. Machine-readable media may include, by way of example, random access memory (RAM), flash memory, read only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable Read-only memory (EEPROM), registers, magnetic disks, optical disks, hard drives, or any other suitable storage medium, or any combination thereof. The machine-readable media may be embodied in a computer-program product. The computer-program product may comprise packaging materials.

[00103] In a hardware implementation, the machine-readable media may be part of the processing system separate from the processor. However, as those skilled in the art will readily appreciate, the machine-readable media, or any portion thereof, may be external to the processing system. By way of example, the machine-readable media may include a transmission line, a carrier wave modulated by data, and/or a computer product separate from the device, all which may be accessed by the processor through the bus interface. Alternatively, or in addition, the machine-readable media, or any portion thereof, may be integrated into the processor, such as the case may be with cache and/or general register files. Although the various components discussed may be described as having a specific location, such as a local component, they may also be configured in various ways, such as certain components being configured as part of a distributed computing system.

[00104] The processing system may be configured as a general-purpose processing system with one or more microprocessors providing the processor functionality and external memory providing at least a portion of the machine-readable media, all linked together with other supporting circuitry through an external bus architecture.

Alternatively, the processing system may comprise one or more neuromorphic processors for implementing the neuron models and models of neural systems described herein. As another alternative, the processing system may be implemented with an application specific integrated circuit (ASIC) with the processor, the bus interface, the user interface, supporting circuitry, and at least a portion of the machine-readable media integrated into a single chip, or with one or more field programmable gate arrays (FPGAs), programmable logic devices (PLDs), controllers, state machines, gated logic, discrete hardware components, or any other suitable circuitry, or any combination of circuits that can perform the various functionality described throughout this disclosure. Those skilled in the art will recognize how best to implement the described functionality for the processing system depending on the particular application and the overall design constraints imposed on the overall system.

[00105] The machine-readable media may comprise a number of software modules. The software modules include instructions that, when executed by the processor, cause the processing system to perform various functions. The software modules may include a transmission module and a receiving module. Each software module may reside in a single storage device or be distributed across multiple storage devices. By way of example, a software module may be loaded into RAM from a hard drive when a triggering event occurs. During execution of the software module, the processor may load some of the instructions into cache to increase access speed. One or more cache lines may then be loaded into a general register file for execution by the processor. When referring to the functionality of a software module below, it will be understood that such functionality is implemented by the processor when executing instructions from that software module.

[00106] If implemented in software, the functions may be stored or transmitted over as one or more instructions or code on a computer-readable medium. Computer- readable media include both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage medium may be any available medium that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. In addition, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared (IR), radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Thus, in some aspects computer-readable media may comprise non-transitory computer-readable media (e.g., tangible media). In addition, for other aspects computer-readable media may comprise transitory computer- readable media (e.g., a signal). Combinations of the above should also be included within the scope of computer-readable media.

[00107] Thus, certain aspects may comprise a computer program product for performing the operations presented herein. For example, such a computer program product may comprise a computer-readable medium having instructions stored (and/or encoded) thereon, the instructions being executable by one or more processors to perform the operations described herein. For certain aspects, the computer program product may include packaging material.

[00108] Further, it should be appreciated that modules and/or other appropriate means for performing the methods and techniques described herein can be downloaded and/or otherwise obtained by a user terminal and/or base station as applicable. For example, such a device can be coupled to a server to facilitate the transfer of means for performing the methods described herein. Alternatively, various methods described herein can be provided via storage means (e.g., RAM, ROM, a physical storage medium such as a compact disc (CD) or floppy disk, etc.), such that a user terminal and/or base station can obtain the various methods upon coupling or providing the storage means to the device. Moreover, any other suitable technique for providing the methods and techniques described herein to a device can be utilized.

[00109] It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

CLAIMS WHAT IS CLAIMED IS:

1. A method of selecting a target from a plurality of targets, comprising:

setting an imbalance for connections in a neural network based at least in part on a selection function; and

modifying a relative activation between the plurality of targets based at least in part on the imbalance, the relative activation corresponding to at least one target.

2. The method of claim 1, in which each target is a spatial target.

3. The method of claim 1, in which each target comprises at least one active neuron.

4. The method of claim 1, further comprising selecting the at least one target based at least in part on the imbalance.

5. The method of claim 4, further comprising selecting two or more targets of the plurality of targets based at least in part on probabilities of each target.

6. The method of claim 1, in which the selection function is based at least in part on a distance between the each target and an object.

7. The method of claim 1, in which the imbalance comprises at least inhibitory weights, excitatory weights, or a combination thereof.

8. The method of claim 1, in which the at least one target has a greater amount of activity in comparison to other targets based at least in part on the relative activation.

9. The method of claim 1, in which the connections comprise at least feed forward logical inhibitory connections, feed forward logical excitation connections, feedback logical inhibitory connections, feedback logical excitation connections, or a

combination thereof.

10. The method of claim 1, in which the connections are at least first input layer connections, neuron inputs, lateral connections, or a combination thereof.

11. An apparatus for selecting a target from a plurality of targets, comprising:

means for setting an imbalance for connections in a neural network based at least in part on a selection function; and

means for modifying a relative activation between the plurality of targets based at least in part on the imbalance, the relative activation corresponding to at least one target.

12. The apparatus of claim 11, in which each target is a spatial target.

13. The apparatus of claim 11, in which each target comprises at least one active neuron.

14. The apparatus of claim 11, further comprising means for selecting the at least one target based at least in part on the imbalance.

15. The apparatus of claim 14, further comprising means for selecting two or more targets of the plurality of targets based at least in part on probabilities of each target.

16. The apparatus of claim 11, in which the selection function is based at least in part on a distance between the each target and an object.

17. An apparatus for selecting a target from a plurality of targets, comprising:

a memory unit; and

at least one processor coupled to the memory unit, the at least one processor being configured:

to set an imbalance for connections in a neural network based at least in part on a selection function; and

to modify a relative activation between the plurality of targets based at least in part on the imbalance, the relative activation corresponding to at least one target.

18. The apparatus of claim 17, in which each target is a spatial target.

19. The apparatus of claim 17, in which each target comprises at least one active neuron.

20. The apparatus of claim 17, in which the at least one processor is further configured to select the at least one target based at least in part on the imbalance.

21. The apparatus of claim 20, in which the at least one processor is further configured to select two or more targets of the plurality of targets based at least in part on probabilities of each target.

22. The apparatus of claim 17, in which the selection function is based at least in part on a distance between the each target and an object.

23. The apparatus of claim 17, in which the imbalance comprises at least inhibitory weights, excitatory weights, or a combination thereof.

24. The apparatus of claim 17, in which the at least one target has a greater amount of activity in comparison to other targets based at least in part on the relative activation.

25. The apparatus of claim 17, in which the connections comprise at least feed forward logical inhibitory connections, feed forward logical excitation connections, feedback logical inhibitory connections, feedback logical excitation connections, or a

combination thereof.

26. The apparatus of claim 17, in which the connections are at least first input layer connections, neuron inputs, lateral connections, or a combination thereof.

27. A computer program product for selecting a target from a plurality of targets, comprising:

a non-transitory computer-readable medium having non-transitory program code recorded thereon, the program code comprising: program code to set an imbalance for connections in a neural network based at least in part on a selection function; and

program code to modify a relative activation between the plurality of targets based at least in part on the imbalance, the relative activation corresponding to at least one target.