WO2015042643A1

WO2015042643A1 - A multi-stage cmos amplifier circuit

Info

Publication number: WO2015042643A1
Application number: PCT/AU2014/000936
Authority: WO
Inventors: Efstratios Skafidas; Hoa Thai DUONG; Robin J EVANS; Viet Hoang LE; Anh Huynh
Original assignee: University of Melbourne
Current assignee: University of Melbourne
Priority date: 2013-09-30
Filing date: 2014-09-25
Publication date: 2015-04-02
Anticipated expiration: 2016-03-30

Abstract

A multi-stage CMOS power amplifier circuit comprises a plurality of amplifier stages (120,430,440,450,460) connected by respective ones of a plurality of transformers (T₂-T₅), wherein each transformer (T₂-T₅) comprises a first winding in a first metal layer of a CMOS chip and a second winding arranged in a second metal layer of the CMOS chip superimposed on the first winding, wherein the first and second windings of each transformer have a width (W) and a radius (R), and impedance matching between the amplifier stages is provided by the width (W) and the radius (R) of the respective transformers (T₂-T₅).

Description

A MULTI-STAGE CMOS AMPLIFIER CIRCUIT

Field The present invention relates to a multi-stage CMOS amplifier circuit and a CMOS power amplifier suitable for a stage of the multi-stage CMOS amplifier circuit.

Background

There has been considerable interest in automotive radar systems as they have the potential to provide a more secure and comfortable driving environment. Radar

technology forms the basis for advanced automotive

features such as collision avoidance, intelligent cruise control, auxiliary speed detection, blind spot detection, lane change warning, and automatic parking assist.

Recently, interest has focussed on the 76-77 GHz frequency band because it is available for automotive applications in most parts of the world, with few national restrictions in operational parameters such as bandwidth, output power.

Currently, these systems are only available in premium cars because of their cost. Accordingly, there is a research into delivering these devices more cheaply, for example, by using relatively cheap CMOS technology. A power amplifier circuit is one of the key components in a radar system. Accordingly, there is a need for an appropriate CMOS based amplifier circuit.

Summary In a first aspect, the invention provides a multi-stage CMOS power amplifier circuit comprising a plurality of amplifier stages connected by respective ones of a plurality of transformers, wherein each transformer comprises a first winding in a first metal layer of a CMOS chip and a second winding arranged in a second metal layer of the CMOS chip superimposed on the first winding, wherein :

the first and second windings of each transformer have a width and a radius ; and

impedance matching between the amplifier stages is provided by the width and the radius of the respective transformers.

In an embodiment, the first winding of at least one of the plurality of transformers has a first winding bias port for providing a voltage to one or more transistors of a connected amplifier stage.

In an embodiment, the first winding comprises a loop between two first winding connectors for connecting to an amplifier stage and the bias port is located opposite the two first winding connectors.

In an embodiment, the second winding of at least one of the plurality of transformers has a second winding bias port for providing a voltage to one or more transistors of a connected amplifier stage.

In an embodiment, the second winding comprises a loop between two connectors for connecting to an amplifier stage and the bias port is located opposite the two connectors.

In an embodiment, the second winding of said at least one of the plurality of transformers has a second winding bias port for providing a voltage to a connected amplifier stage;

the second winding comprises a loop between two second winding connectors for connecting to an amplifier stage; and

the second winding bias port of the second winding is located opposite the two second winding connectors and the first winding bias port.

In an embodiment, the multi-stage CMOS power amplifier circuit comprises five amplifier stages.

In an embodiment, at least one of the width and the radius is different for a first one of the transformers relative to a second one of the transformers.

In an embodiment, a first transformer connected to an input of an input amplifier has a first width and a first radius and a second transformer connected to an output of the input amplifier has a second radius smaller than the first radius.

In an embodiment, a last transformer connected to an output of an output amplifier has a last transformer width greater than said first width and a last transformer radius greater than said first radius.

In an embodiment, said input amplifier stage comprises a pair of transmission lines for input matching of the circuit.

In an embodiment, each amplifier stage comprises:

first and second transistors;

first and second RC circuits each comprising a resistor and capacitor connected in parallel, the first and second RC circuits connected between the respective gates of the first and second transistors and first and second ports of a transformer which provides the input to the respective amplifier stage; and

first and second cross-coupling capacitors, the first cross-coupling capacitor connected between the gate of the first transistor and the drain of the second transistor and the second cross-coupling capacitor connected between the gate of the second cross-coupling capacitor and the drain of the first transistor.

In a second aspect, the invention provides a differential CMOS power amplifier for a multi-stage transformer

connected amplifier circuit, the power amplifier

comprising:

first and second transistors;

first and second RC circuits each comprising a resistor and capacitor connected in parallel, the first and second RC circuits connected between the respective gates of the first and second transistors and first and second input ports of the amplifier circuit; and

In an embodiment, the differential CMOS power amplifier comprises a pair of transmission lines for input matching of the circuit.

Accordingly, embodiments of the invention are capable of providing a 77 GHz power amplifier based on multiple passive transformer-coupled architectures in 65-nm CMOS technology. The proposed architecture provides a DC blocking property, a power supply with RF choke,

differential to differential/single-ended conversion, input/output and interstage matching of the passive transformers such that embodiments of the invention may provide a high gain, low power and compact power amplifier at 77 GHz. Brief Description of the invention

Embodiments of the invention will be described with reference to the accompanying drawings in which:

Figure 1 show an input matching network for the first stage of the 77 GHz power amplifier of an embodiment of the invention;

Figure 2 is a simplified equivalent single-ended input matching network in which neutralization capacitors C_n are neglected;

Figure 3A is a simplified network of Figure 1 and Figure 3B is an equivalent circuit of Figure 3A

Figure 4 show a five-stage 77 GHz differential power amplifier of an embodiment of the invention;

Figure S shows bias circuits for the power amplifier of the embodimen ;

Figure 6 shows a 1-to-l transformer layout of the

embodiment;

Figure 7 is a die micrograph of the proposed 77 GHz power amplifier circuit;

Figure 8 is a graph of measured S-parameters of the five- stage 77 GHz power amplifier;

Figure θ is a graph of the measured reverse isolation the 77 GHz power amplifier; and

Figure 10 is a graph of the gain, output power and power added ef iciency responses . Detailed description

Referring to the drawings , there is shown an embodiment of a multi-stage CMOS power amplifier circuit having a plurality of amplifier stages connected by respective ones of a plurality of transformers. The illustrated embodiment has five amplifier stages but other configurations can be achieved using the same technique. In the embodiments impedance matching is achieved by configuring the radius and/or width of the windings of the transformers. The embodiments employ a differential CMOS power amplifier that has an RC circuit and cross-coupling capacitors. Figure 1 shows the input matching network of the 77 GHz five-stage power amplifier. The input 110 is represented by a voltage source V_s having and associated resistance R_s and capacitance C_s. The input 110 is coupled to an input amplifier stage 120 by first transformer Ti . In the embodiment, each amplifier stage comprises a differential power amplifier formed by first and second transistors Mi and M2.

In an embodiment, the differential power amplifier is neutralized by adding cross coupled capacitors (C_n) to cancel the inherent parasitic capacitance C_gd of the two transistors Mi and M₂ and provide high isolation from the output to the input. In order to improve stability, an RC network (R_x, C_x) provided by a resistor R_x and a capacitor C_x connected in parallel, is connected between each port of the transformer at the gate of each transistor Mi, M₂. In the input stage, transmission lines 121,122 are provided between the ports of the input transformer Ti and the RC networks. The transmission lines 121,122 are used for tuning the input matching, where Z_± is the characteristic impedance and θι is electrical length of the transmission line . Figure 2 depicts an equivalent single-ended input matching network for the architecture in Figure l_f where the network between the gate and drain ports is represented by the y-Matrix 210. Input impedances Z_A and Z_B of the network are calculated in accordance with equations (1) and (2) , respectively. The unilateralization condition is satisfied when is = 0 , the input impedance *S_A can be simplified as shown in (3) . i

-+ ¥<T +

iff (1)

\IR_s+sC

Z,+jZ.tanff,

7 -7 (2)

' Z. + JZ_A tan&,

A s mpl fied network derived from, the network 100 of Figure 1 is shown in Figure 3. In Figure 3Ά k is the coupling coefficient between primary and secondary ports of the transformer, and ¾ represent the conductor losses, and

L, ;¾ ... 2¾ 5¾_Ϊ"_Ϊ ρ**ί¾ ·¾ γ·>

secondary windings of the transformer, respectively.

In the equivalent circui of Figure 3& shown in Figure 3B , the effects of ¾ in the secondary circuit ve been converted into a series reflected impedance Zo in the r ma y circuit of the transformer. T e reflected impedance ¾ and input impedance ¾i_K can be calculated by equations (4) and (5) , respectively.

where M— k^jL^L, is the mutual inductance of the

transformer .

Therefore , the input matching condition can be obtained from equation (6) . By equating the real and imaginary parts of a complex condition (€} , dissensions of the circui can be cfe ivsid To si slifv this Hia ehinor

condition, L_x and L₂ are set to resonate with C_s and

±magf{2'Z_s,} , respectively. Therefore, from equations (5) a d

Figure 4 sh ws the architecture of the transformer-coupled five-stage power amplifier of an embodiment . The five-stag power amplifier circuit 400 comprises the input 110 and input 120 (first) amplifier stages shown in Figure 1, second 430, third 440 , fourth 450 , and output 460 (fifth) amplifier stages. The output stage 460 is coupled by transforsser g to load 470. Xfc is assumed that the

resistance of the load R_L is 50 Ohms.

The power amplifier circuit 400 was designed for a 1.2 V supply and 11 dBm (12 m ) output power for radar

automotive applications. With Vug,_sa ™0■ 22 V, the vol ag swing at the output is VQ_V — ^"¾s_,.sat™Q.98 V, The power amplifier is 2^*P_SK3J!£/ ( DD ~ V_Ds₍sat - 24.5 m&.

With 0.24 ffl¾ um current density at the peak frequency £¾_¾x, in order to obtain highest gain at 77 GUz , the width of the transistors Mg,Mio of the output stage 460 is selected as 24,5 m¾./(0.24 κιΆ/μκι) ¾ 100 u . Transistor widths for the transistors of the first (Mi,Ma) , second (M3,M ) , third (Ms^Mg) , and fourth (M7,Mg) amplifier stages are also chosen by the same method to be 50 ]m, 60 u∑R_f 70 um, and 80 ia respectively .

The transformers Ti~Tg are designed taking" into account the co-considerations of maximum output power and sufficient ower matching. The transformers Τχ~ $ also provide the DC blocking property, power supply with RF choke, single- ended to differential conversion, differential to m chings . The required bias voltages for each stage V_bi_as.. where i 1 . . . 5 is generated f om the current mirror circuit as shown in Figure 5 . In the embodim , bias

supplies Iftaf — 100 pA have been used.

Figure 6 shows the layout 600 of each of the transformers of the embodiment. Each transformer winding 610 , 620 is a single loop extending between the of the input section connectors V_itH._fV_iti_ and output section connectors

respectively . A shown in Figure 6 , each loop 610 , 620 is octagonal-shaped due to limitations on implementing a circular loop in the CMOS process at the required

dimensions. In this respect, the embodiment was designed for fabrication using a 65-nm CMOS process with eight metal layers , In the embodiment , the output section

(secondary winding 610 } is on the top thick aluminium layer, the input section (primary winding 620} is on the second top thick metal layer, and the ground plane 630 is on the bottom metal layer of the 65-nm CMOS technology. It will be appreciated that relative positions of the input and output sections can be reversed. That is, that either the input winding or output winding be superimposed on the other winding to allow for inductive coupling.

Bias signals which can be used either as a bias voltage V_bi_as or power supply V_BD of the input and output sections respectively are taken from the primary winding bias port V_b i and the secondary winding bias ¾_₀, respectively as shown in Figure 6. As shown in Figure 6 , the bias ports are located diametrically opposite the connectors of the winding to which they belong and between the connectors of the other winding. This arrangement makes the circuit size more compact.

As indicated above by configuring the width (W) and radius (R) of each pair of primary and secondary windings such that at least one of the width and the radius is different for a one of the transformers relative to another one of the transformers, the matching condition in equation (7) can be obtained.

Dimensions of the required transformers for the five-stage amplifier circuit 400 were extracted by HFSS v.12 (High Frequency Structural Simulator version 12, available from ANSYS Inc. of Canonsburg, Pennsylvania, USA) . A summary of the details of transformers and circuit components is given in Table 1. The power loss contribution of each transformer is about 1.5 dB.

It will be apparent that in an embodiment, the width of the transformer is kept the same for each of Ti-T₅ such that matching is achieved by varying the radius, e.g. such that a second transformer has a smaller radius than the first transformer. The final transformer Τβ has a larger width, in part, because it carries more power than the other transformers.

Varying the radius (R) of the transformer shifts the matching network into the correct frequency band. The effect of R is mostly related to varying the inductance and conductor losses (rl, r2) of the primary and secondary sections of the transformer in order to change the

matching property of the network. It will be appreciated that for lower frequency bands, a larger R is required.

However, if R is too large, the transformer will occupy a large physical area of the chip. In that case, more turns are required for the transformer. In order to have an appropriate bandwidth, R of each stage is chosen to cover a wide frequency range. Varying the width (W) of the transformer changes the coupling coefficient k between the primary and secondary sections of the transformer and hence the capacitance of the matching network. In addition, wider width W allows a higher maximum power and results in lower conductor losses (rl, r2) .

Table 1 - Detailed Circuit Components of the Proposed Power Amplifier

Experimental Results The power amplifier circuit 400 was fabricated using a 65- nm CMOS process with eight metal layers: a micrograph of the amplifier circuit 400 is shown in Figure 7. The size of the power amplifier including input/output and DC pads

2

is 0.4 x 0.85 mm .

On-wafer S-parameter measurements up to 100 GHz have been performed by a ME7808B Broadband V A produced by Anritsu Corporation of Kanagawa Japan and a probe station produced by Suss MicroTec of Garching, Germany. Figure 8 shows the S-parameter measurement results for the power amplifier 400. The measured results show very good matching at input Sii and output S₂₂ ports with return losses less than -10 dB in the 67-100 GHz frequency range. The transmission gain ( S₂₁ ) of the power amplifier is 18.5 dB at 77 GHz.

Figure 9 shows the measured reverse isolation of the power amplifier 400. The isolation between input and output ( S₁₂ ) is better than -42 dB within the bandwidth from 65 to 100 GHz range. At 77 GHz, the reverse isolation is about -48 dB.

To perform output power measurement, a 60 GHz passive up- mixer was used to up-convert a 17 GHz signal to a 77 GHz input signal before feeding to the amplifier 400. Then, the 77 GHz output signal of the amplifier is down-converted to 17 GHz by a 60 GHz passive down-mixer before connecting to a 40 GHz spectrum analyzer (an MS2668C spectrum analyser produced by Anritsu Corporation of Kanagawa) . Calibration for the conversion loss has been taken into account for this measurement.

Figure 10 shows the output power performance the power amplifier 400 in terms of gain 1010, output power 1020 and power added efficiency (PAE) 1030. The measured results show that an output compression point (OPi_dB) of +9.5 dBm and a saturated output power of +10.5 dBm were measured at 77 GHz.

As can be seen from the results, a constant gain of 18.5 dB with good linearity has been achieved for input power less than -10 dBm and maximum PAE of 7.1 %. The DC power consumption of the power amplifier 400 is 150 mW.

The performance of the power amplifier circuit 400 is compared in Table 2 with the CMOS 77 GHz power results described in the following references:

[1] T. Suzuki, Y. Kawano, M. Sato, T. Hirose and K.

Joshin, "60 and 77 GHz power amplifier in standard 90 nm CMOS," ISSCC Dig. Tech. Papers, pp. 562-563. Feb. 2008.

[2] B. Wicks, E. Skafidas , and R. Evans, "A 77-95 GHz

Wideband CMOS Power Amplifier," Microwave Integrated Circuit Conf., pp. 555-559. Feb. 2008. [3] J. Lee, C. C. Chen, J. H. Tsai, K. Y. Lin and H.

Wang, "A 68-83 GHz power amplifier in 90 nm CMOS," 2009 IEEE MTT-S Int. Microwave Symp. Dig., pp. 437-440, June 2009. [4] Y . A. Li , M. H . Hung, S . J. Huang, and J. Lee ,

"A Fully-Integrated 77 GHz FMCW Radar System in 65 nm CMOS," ISSCC Dig. Tech. Papers, pp. 216-217, Feb. 2010.

[5] T. Y. Chang, C. S. Wang, and C. K. Wang, "A 77 GHz power amplifier using transformer-based power combiner in 90 nm CMOS," Proc IEEE CICC, pp. 1-4, Sept. 2010.

It will be apparent from Table 2 that power amplifier 400 provides the highest gain with competitive output power and relatively compact size. Table 2 - Comparison With Published CMOS mm-Wave Power Amplifier Results

(^aPads are excluded from the chip size in Ref [5] )

In the claims which follow and in the preceding

description of the invention, except where the context requires otherwise due to express language or necessary implication, the word "comprise" or variations such as

"comprises" or "comprising" is used in an inclusive sense, i.e. to specify the presence of the stated features but not to preclude the presence or addition of further features in various embodiments of the invention.

It is to be understood that, the reference to prior art publications does not constitute an admission that the publication form part of the common general knowledge in the art in any country.

Claims

CLAIMS :

1. A multi-stage CMOS power amplifier circuit comprising a plurality of amplifier stages connected by respective ones of a plurality of transformers, wherein each transformer comprises a first winding in a first metal layer of a CMOS chip and a second winding arranged in a second metal layer of the CMOS chip superimposed on the first winding, wherein:

2. A multi-stage CMOS power amplifier circuit as claimed in claim 1, wherein the first winding of at least one of the plurality of transformers has a first winding bias port for providing a voltage to one or more transistors of a connected amplifier stage.

3. A multi-stage CMOS power amplifier circuit as claimed in claim 2, wherein the first winding comprises a loop between two first winding connectors for connecting to an amplifier stage and the bias port is located opposite the two first winding connectors.

4. A multi-stage CMOS power amplifier circuit as claimed in any one of claims 1 to 3, wherein the second winding of at least one of the plurality of transformers has a second winding bias port for providing a voltage to one or more transistors of a connected amplifier stage.

5. A multi-stage CMOS power amplifier circuit as claimed in claim 4 , wherein the second winding comprises a loop between two connectors for connecting to an amplifier stage and the bias port is located opposite the two connectors .

6. A multi-stage CMOS power amplifier circuit as claimed claim 3 , wherein :

the second winding of said at least one of the plurality of transformers has a second winding bias port for providing a voltage to a connected amplifier stage; the second winding comprises a loop between two second winding connectors for connecting to an amplifier stage; and

7. A multi-stage CMOS power amplifier circuit as claimed in any one of claims 1 to 6, comprising five amplifier stages .

8. A multi-stage CMOS power amplifier circuit as claimed in any one of claims 1 to 7 , wherein at least one of the width and the radius is different for a first one of the transformers relative to a second one of the transformers.

9. A multi-stage CMOS power amplifier circuit as claimed in claim 1, wherein a first transformer connected to an input of an input amplifier has a first width and a first radius and a second transformer connected to an output of the input amplifier has a second radius smaller than the first radius.

10. A multi-stage CMOS power amplifier circuit as claimed in claim 9, wherein a last transformer connected to an output of an output amplifier has a last transformer width greater than said first width and a last transformer radius greater than said first radius.

11. A multi-stage CMOS power amplifier circuit as claimed in claim 9 or claim 10, wherein said input amplifier stage comprises a pair of transmission lines for input matching of the circuit.

12. A multi-stage CMOS power amplifier circuit as claimed in any one of claims 1 to 11, wherein each amplifier stage comprises :

first and second transistors;

13. A differential CMOS power amplifier for a multi-stage transformer connected amplifier circuit, the power amplifier comprising:

first and second transistors;

14. A differential CMOS power amplifier as claimed in claim 13, comprising a pair of transmission lines for input matching of the circuit.