WO2015035736A1 - 一种半导体发光器件的制备方法 - Google Patents

一种半导体发光器件的制备方法 Download PDF

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WO2015035736A1
WO2015035736A1 PCT/CN2014/000838 CN2014000838W WO2015035736A1 WO 2015035736 A1 WO2015035736 A1 WO 2015035736A1 CN 2014000838 W CN2014000838 W CN 2014000838W WO 2015035736 A1 WO2015035736 A1 WO 2015035736A1
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epitaxial layer
emitting device
light emitting
semiconductor light
substrate
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PCT/CN2014/000838
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English (en)
French (fr)
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朱浩
范振灿
刘国旭
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易美芯光（北京）科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate

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  • This invention relates to the field of optoelectronic devices. More particularly, the present invention relates to a method of fabricating a semiconductor light emitting device.
  • the sapphire substrate is the main substrate for epitaxial growth of GaN-based LEDs, and its conductivity and heat dissipation are relatively poor. Due to the poor conductivity of sapphire substrates, conventional GaN-based LEDs use a lateral structure that causes current blockage and heat generation. The poor thermal conductivity limits the power of the light emitting device. After the sapphire substrate is removed by laser stripping technology, the LED is made into a vertical structure, which can effectively solve the problem of heat dissipation and light emission. In order to improve the light efficiency and power of GaN-based LEDs, a laser-peeled sapphire substrate technology is proposed.
  • the epitaxial layer is prepared on a sapphire substrate, the epitaxial layer is bonded to the support substrate, and then the sapphire substrate is removed by laser lift-off.
  • the device is constructed in a vertical configuration.
  • the GaN epitaxial layer epitaxially grown on the sapphire substrate is typically etched prior to stripping of the sapphire substrate to create a plurality of discrete dies, facilitating subsequent chip dicing processes and increasing production efficiency.
  • an epitaxial layer is usually etched by an Inductively Coupled Plasma (ICP) etching method.
  • ICP Inductively Coupled Plasma
  • ICP etching in an alternating electromagnetic field, a gas discharge phenomenon enters a plasma state, and the plasma acts perpendicularly on the substrate and reacts with it to form a volatile gaseous substance to achieve the purpose of etching.
  • parameters such as ICP ion source power, RF power, gas flow, and chamber pressure all have an effect on the etch.
  • the existing ICP process parameters often prevent the plasma from acting perpendicularly on the surface of the substrate, that is, the sidewall angle of the etching is much less than 90°, which causes cracks and the like in the subsequent laser stripping process, and the performance of the chip is lowered. And production yield.
  • the present invention provides a method for fabricating a semiconductor light emitting device, which comprises sequentially growing a buffer layer and an N-type GaN layer on a sapphire substrate.
  • An active layer, a P-type GaN layer, forming an epitaxial layer the method further comprising etching the epitaxial layer to expose the sapphire substrate to generate a plurality of discrete dies, wherein the etched epitaxial layer has a sidewall tilt angle of 60° ⁇ 90°, the method further comprises combining the etched epitaxial layer with the support substrate, and removing the sapphire substrate by laser stripping.
  • the epitaxial layer has a sidewall inclination of 75° to 85°.
  • the method of bonding the etched epitaxial layer to the support substrate is eutectic bonding or post-coating curing.
  • a portion of the epitaxial layer remains as a spacer between the dies, and at least one of the spacers around the dies is disconnected.
  • the width of the groove between the spacer strip and the edge of the adjacent die is 1-100 microns.
  • the separator has a width of from 5 to 100 microns.
  • the present invention provides a method for fabricating a semiconductor light-emitting device, which changes the etching process parameters so that the sidewall tilt angle of the epitaxial layer after etching is 60° to 90°, which is close to vertical. This results in fewer bevels, which is more conducive to subsequent manufacturing processes, improving performance and yield.
  • 1a and 1b are partial schematic views after epitaxial layer etching.
  • FIGS. 2a-2g are schematic illustrations of a manufacturing process in accordance with one embodiment of the present invention.
  • 3a-3h are schematic views of a manufacturing process in accordance with another embodiment of the present invention.
  • 4a-4g are schematic views of a manufacturing process in accordance with another embodiment of the present invention.
  • 5a-5h are schematic illustrations of a manufacturing process in accordance with another embodiment of the present invention.
  • the logo in the figure shows:
  • FIG. 1a and FIG. 1b There are two kinds of epitaxial layer structures after etching in the prior art, as shown in FIG. 1a and FIG. 1b.
  • a portion of the epitaxial layer remains as a spacer 2 between each two adjacent dies 1 shown in FIG. 1a, and the spacer 2 is discontinuous, and a spacer 3 is formed between the spacer 2 and the adjacent dies 1.
  • a groove 3 is formed directly between each two adjacent dies 1, without a spacer.
  • a buffer layer, an N-type GaN layer, an active layer, and a P-type GaN layer are sequentially grown on the sapphire substrate 100 to form an epitaxial layer 110.
  • the sapphire substrate 100 is mechanically ground and thinned and polished. As shown in FIG. 2a, a buffer layer, an N-type GaN layer, an active layer, and a P-type GaN layer are sequentially grown on the sapphire substrate 100 to form an epitaxial layer 110.
  • the sapphire substrate 100 is mechanically ground and thinned and polished.
  • the epitaxial layer 110 is etched by ICP etching, the chamber pressure is set to 700 mPa, the flow rates of Cl 2 , BCl 3 and Ar gas are 50 sccm, 10 sccm and 5 sccm, respectively, and the RF power is 200 W, and the ion source power is 500W, the epitaxial layer 110 is etched to expose the sapphire substrate 100 to form a plurality of discrete dies 1 while a portion of the epitaxial layer 110 remains as a spacer 2 between each two adjacent dies 1
  • the spacer 2 between the dies 1 is discontinuous, the width of the spacer 2 is 20 micrometers, and the width of the trench 3 between the edges of the adjacent dies 1 is 10 micrometers.
  • the etched epitaxial layer 110 is bonded to the support substrate 120 by eutectic bonding.
  • the support substrate 120 is any one of Si, ceramic, W, Cu, Mo, GaAs, graphite, and glass.
  • a resin paste 210 is applied on the other side of the support substrate 120, and the resin paste 210 functions to relieve stress during laser lift-off.
  • the resin paste 210 is flattened using a transparent auxiliary substrate 220 such as glass or sapphire, and then the resin paste 210 is cured by ultraviolet light to remove the auxiliary substrate 220.
  • a transparent auxiliary substrate 220 such as glass or sapphire
  • the sapphire substrate 100 is removed by laser lift-off.
  • the resin glue 210 is removed.
  • the residual spacer 2 is removed, and the P and N electrodes are formed by a general process to complete the preparation of the semiconductor light emitting device.
  • the sidewall tilt angle of the epitaxial layer of this embodiment is 75°, and the chip production yield is improved.
  • a buffer layer, an N-type GaN layer, an active layer, and a P-type GaN layer are sequentially grown on the sapphire substrate 100 to form an epitaxial layer 110.
  • the sapphire substrate 100 is mechanically ground and thinned and polished. As shown in FIG. 3a, a buffer layer, an N-type GaN layer, an active layer, and a P-type GaN layer are sequentially grown on the sapphire substrate 100 to form an epitaxial layer 110.
  • the sapphire substrate 100 is mechanically ground and thinned and polished.
  • the epitaxial layer 110 is etched by ICP etching, the chamber pressure is set to 400 mPa, the flow rates of Cl 2 , BCl 3 and Ar gas are 45 sccm, 15 sccm and 5 sccm, respectively, and the RF power is 320 W, and the ion source power is 600W, the epitaxial layer 110 is etched to expose the sapphire substrate 100 to form a plurality of discrete dies 1 while a portion of the epitaxial layer 110 remains as an isolation strip 2 between each two adjacent dies 1
  • the spacer 2 between the dies 1 is discontinuous, the width of the spacer 2 is 40 micrometers, and the width of the trench 3 between the edges of the adjacent dies 1 is 10 micrometers.
  • a high-temperature epoxy resin modified paste is applied on the etched epitaxial layer 110, and is cured after being bonded to the first temporary substrate 310.
  • the sapphire substrate 100 was removed using a laser lift-off method using a 248 nm excimer laser with a power of 550 milliwatts.
  • the modified heterocyclic resin paste is applied to the release surface, and then bonded to the second temporary substrate 320 to be cured. As shown in FIG.
  • the first temporary substrate 310 is etched with hydrofluoric acid plus hydrogen peroxide plus nitric acid (5:2:2), and the high temperature epoxy is etched at 100 ° C with toluene. Resin modified glue.
  • the exposed epitaxial layer is bonded to the support substrate 120, which is a silicon substrate.
  • the support substrate 120 is protected with wax, the second temporary substrate 320 is etched with hydrofluoric acid plus hydrogen peroxide plus nitric acid (5:2:2), and the modified heterocyclic resin glue is etched away with hydrogen peroxide gas, and then The surface of the obtained N-type GaN layer was cleaned.
  • the residual spacer 2 is removed, and the P and N electrodes are formed by a general process to complete the preparation of the semiconductor light emitting device.
  • the sidewall tilt angle of the epitaxial layer of this embodiment is 80°, and the chip production yield is remarkably improved.
  • a buffer layer, an N-type GaN layer, an active layer, and a P-type GaN layer are sequentially grown on the sapphire substrate 100 to form an epitaxial layer 110.
  • the sapphire substrate 100 is mechanically ground and thinned and polished. As shown in FIG. 4a, a buffer layer, an N-type GaN layer, an active layer, and a P-type GaN layer are sequentially grown on the sapphire substrate 100 to form an epitaxial layer 110.
  • the sapphire substrate 100 is mechanically ground and thinned and polished.
  • the epitaxial layer 110 is etched by ICP etching, the chamber pressure is set to 700 mPa, the flow rates of Cl 2 , BCl 3 and Ar gas are 50 sccm, 10 sccm and 5 sccm, respectively, and the RF power is 100 W, and the ion source power is 600W, the epitaxial layer 110 is etched to expose the sapphire substrate 100 to form a plurality of discrete dies 1 while a portion of the epitaxial layer 110 remains as an isolation strip 2 between each two adjacent dies 1
  • the spacer 2 between the dies 1 is discontinuous, the width of the spacer 2 is 20 micrometers, and the width of the trench 3 between the edges of the adjacent dies 1 is 10 micrometers.
  • the support substrate 120 is any one of Si, ceramic, W, Cu, Mo, GaAs, graphite, and glass.
  • a resin paste 210 is applied on the other side of the support substrate 120.
  • the resin glue 210 functions to relieve stress during the laser lift-off process.
  • the resin paste 210 is flattened using a transparent auxiliary substrate 220 such as glass or sapphire, and then the resin paste 210 is cured by ultraviolet light to remove the auxiliary substrate 220.
  • a transparent auxiliary substrate 220 such as glass or sapphire
  • the sapphire substrate 100 is removed by laser lift-off. As shown in Fig. 4g, the resin glue 210 is removed. The residual spacer 2 is removed, and the P and N electrodes are formed by a general process to complete the preparation of the semiconductor light emitting device.
  • the sidewall of the epitaxial layer of this embodiment has an inclination angle of 60°, and the chip production yield is slightly improved.
  • a buffer layer, an N-type GaN layer, an active layer, and a P-type GaN layer are sequentially grown on the sapphire substrate 100 to form an epitaxial layer 110.
  • the sapphire substrate 100 is mechanically ground and thinned and polished. As shown in FIG. 5a, a buffer layer, an N-type GaN layer, an active layer, and a P-type GaN layer are sequentially grown on the sapphire substrate 100 to form an epitaxial layer 110.
  • the sapphire substrate 100 is mechanically ground and thinned and polished.
  • the epitaxial layer 110 is etched to expose the sapphire substrate 100 to form a plurality of discrete dies 1 while A portion of the epitaxial layer 110 remains as a spacer 2 between each two adjacent dies 1, and the spacer 2 between the different dies 1 is discontinuous, and the width of the spacer 2 is 40 micrometers, and the phase
  • the width of the groove 3 between the edges of the adjacent core 1 is 10 ⁇ m, and the inclination of the sidewall of the epitaxial layer after etching is 90°. As shown in FIG.
  • a high-temperature epoxy resin modified paste is applied on the etched epitaxial layer 110, and is cured after being bonded to the first temporary substrate 310.
  • the sapphire substrate 100 was removed using a laser lift-off method using a 248 nm excimer laser with a power of 550 milliwatts.
  • a TiAu protective layer is deposited on the peeling surface and bonded to the second temporary substrate 320. As shown in FIG.
  • the first temporary substrate 310 is etched with hydrofluoric acid plus hydrogen peroxide plus nitric acid (5:2:2), and the high temperature epoxy is etched at 100 ° C with toluene. Resin modified glue.
  • the exposed epitaxial layer is bonded to the support substrate 120, which is a silicon substrate.
  • the support substrate 120 is protected with wax, the second temporary substrate 320 is etched with hydrofluoric acid and hydrogen peroxide plus nitric acid (5:2:2), and the modified heterocyclic resin glue is etched away with hydrogen peroxide gas, and then The surface of the obtained N-type GaN layer was cleaned.
  • the residual spacer 2 is removed, and the P and N electrodes are formed by a general process to complete the preparation of the semiconductor light emitting device.
  • the sidewall of the epitaxial layer of this embodiment has an inclination angle of 90°, and the chip production yield is greatly improved.

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Abstract

一种半导体发光器件的制备方法，通过改变刻蚀的工艺参数使得刻蚀得到的外延层侧壁倾角为60°～90°，接近于垂直，从而避免了生产中的芯片开裂等现象，提高生产良率。

Description

一种半导体发光器件的制备方法 技术领域
本发明涉及光电器件领域。更具体而言，本发明涉及一种半导体发光器件的制备方法。
背景技术
在LED芯片制备工艺中，蓝宝石衬底作为GaN基LED外延生长的主要衬底，其导电性和散热性都比较差。由于蓝宝石衬底导电性差，传统的GaN基LED采用横向结构，导致电流堵塞和发热。而较差的导热性能限制了发光器件的功率。采用激光剥离技术将蓝宝石衬底去除后，将发光二极管做成垂直结构，可以有效解决散热和出光问题。为了提高GaN基LED的光效和功率，提出了激光剥离蓝宝石衬底技术，即在蓝宝石衬底上制备外延层之后，将外延层与支撑基板结合，然后采用激光剥离方法去除蓝宝石衬底，将器件做成垂直结构。在蓝宝石衬底剥离之前通常刻蚀外延生长在蓝宝石衬底上的GaN外延层以产生多个分立的管芯，方便后续的芯片切割工艺，提高生产效率。目前，通常采用感应耦合等离子体(Inductively Coupled Plasma，简称ICP)刻蚀法刻蚀外延层。ICP刻蚀的原理是在交变的电磁场中，气体产生放电现象进入等离子态，等离子垂直作用于基片，并与其反应生成可挥发的气态物质，以达到刻蚀的目的。在ICP工艺中，ICP离子源功率、射频功率、气体流量、腔室压力等参数都会对刻蚀产生影响。但是，现有的ICP工艺参数往往使得等离子体不能垂直作用于基板表面，即刻蚀得到的侧壁倾角远远小于90°，使得在后续的激光剥离工艺中产生裂纹等现象，降低了芯片的性能及生产良率。
发明内容
为了解决在芯片生产过程中芯片由于激光剥离产生裂纹导致生产良率低的问题，本发明提出一种半导体发光器件的制备方法，该方法包括在蓝宝石衬底上依次生长缓冲层、N型GaN层、活性层、P型GaN层，形成外延层，该方法还包括刻蚀所述外延层至暴露蓝宝石衬底以产生多个分立的管芯，其中刻蚀后的外延层侧壁倾角为60°～90°，该方法还包括将刻蚀后的外延层与支撑基板结合，采用激光剥离方法去除蓝宝石衬底。
优选地，所述外延层侧壁倾角为75°～85°。
优选地，所述刻蚀后的外延层与支撑基板结合的方法为共晶键合或涂胶后固化。
优选地，所述管芯之间都保留部分外延层作为隔离带，并且管芯四周的隔离带至少有一处是不相连的。
优选地，所述隔离带与相邻管芯边缘之间槽的宽度为1-100微米。
优选地，所述隔离带的宽度为5-100微米。
本发明的有益效果：
与现有技术相比，本发明提供一种半导体发光器件的制备方法，该方法通过改变刻蚀的工艺参数，使得刻蚀后的外延层侧壁倾角为60°～90°，接近于垂直，从而产生较少的斜面，更有利于后续的制造工艺，提高了性能及良率。
附图说明
图1a、图1b为外延层刻蚀之后的局部示意图。
图2a-2g为本发明一个实施例的制造过程的示意图。
图3a-3h为本发明另一个实施例的制造过程的示意图。
图4a-4g为本发明另一个实施例的制造过程的示意图。
图5a-5h为本发明另一个实施例的制造过程的示意图。
图中标识说明：
管芯1，隔离带2，槽3，蓝宝石衬底100，外延层110，支撑基板120，树脂胶210，辅助基板220，第一临时基板310，第二临时基板320。
具体实施方式
下面结合附图和实施例对本发明进一步说明。
现有技术中刻蚀后的外延层结构有两种，如图1a和图1b所示。图1a所示每两个相邻的管芯1之间都保留部分外延层作为隔离带2，并且隔离带2是不连续的，隔离带2与相邻的管芯1之间形成有槽3；图1b所示，每两个相邻的管芯1之间直接形成有槽3，无隔离带。
实施例1
如图2a所示，在蓝宝石衬底100上依次生长缓冲层、N型GaN层、活性层、P型GaN层，形成外延层110。对蓝宝石衬底100进行机械研磨减薄并抛光。如图2b所示，采用ICP刻蚀法刻蚀外延层110，腔室压力设置为700mPa，Cl2、BCl3和Ar气体流量分别为50sccm、10sccm和5sccm，射频功率为200W，离子源功率为500W，将外延层110刻蚀至暴露蓝宝石衬底100，形成多个分立的管芯1，同时每两个相邻的所述管芯1之间都保留部分外延层110作为隔离带2，不同管芯1之间的隔离带2是不连续的，隔离带2的宽度为20微米，与相邻管芯1边缘之间槽3的宽度为10微米，刻蚀后的外延层侧壁倾角为75°。如图2c所示，将刻蚀后的外延层110通过共晶键合的方法与支撑基板120结合。所述支撑基板120为Si、陶瓷、W、Cu、Mo、GaAs、石墨、玻璃中的任意一种。如图2d所示，在支撑基板120的另一侧涂敷树脂胶210，所述树脂胶210在激光剥离过 程中起到缓解应力的作用。为了使涂敷上去的树脂胶210平整，如图2e所示，使用透明的辅助基板220如玻璃、蓝宝石将树脂胶210压平，然后采用紫外光将树脂胶210固化，去除辅助基板220。如图2f所示，采用激光剥离的方法去除蓝宝石衬底100。如图2g所示，去除所述树脂胶210。去除残留的隔离带2，采用通用工艺形成P、N电极，完成半导体发光器件的制备。
本实施例的外延层侧壁倾角为75°，芯片生产良率有所提高。
实施例2
如图3a所示，在蓝宝石衬底100上依次生长缓冲层、N型GaN层、活性层、P型GaN层，形成外延层110。对蓝宝石衬底100进行机械研磨减薄并抛光。如图3b所示，采用ICP刻蚀法刻蚀外延层110，腔室压力设置为400mPa，Cl2、BCl3和Ar气体流量分别为45sccm、15sccm和5sccm，射频功率为320W，离子源功率为600W，将外延层110刻蚀至暴露蓝宝石衬底100，形成多个分立的管芯1，同时每两个相邻的所述管芯1之间都保留部分外延层110作为隔离带2，不同管芯1之间的隔离带2是不连续的，隔离带2的宽度为40微米，与相邻管芯1边缘之间槽3的宽度为10微米，刻蚀后的外延层侧壁倾角为80°。如图3c所示，在刻蚀后的外延层110上涂敷高温环氧树脂改性胶，与第一临时基板310粘结之后固化。如图3d所示，使用激光剥离的方法去除蓝宝石衬底100，采用248纳米准分子激光，功率550毫瓦。如图3e所示，在剥离面上涂敷改性杂环树脂胶后与第二临时基板320粘结之后固化。如图3f所示，用蜡保护第二临时基板320之后，用氢氟酸加双氧水加硝酸(5∶2∶2)腐蚀第一临时基板310，采用甲苯在100℃下进行腐蚀该高温环氧树脂改性胶。如图3g所示，将暴露出的外延层键合到支撑基板120上，所述支撑基板120为硅基板。如图3h所示，将支撑基板120用蜡进行保护，用氢氟酸加双氧水加硝酸(5∶2∶2)腐蚀第二临时 基板320，并用硫酸双氧水腐蚀掉改性杂环树脂胶，然后对于得到的N型GaN层表面进行清洗。去除残留的隔离带2，采用通用工艺形成P、N电极，完成半导体发光器件的制备。
本实施例的外延层侧壁倾角为80°，芯片生产良率显著提高。
实施例3
如图4a所示，在蓝宝石衬底100上依次生长缓冲层、N型GaN层、活性层、P型GaN层，形成外延层110。对蓝宝石衬底100进行机械研磨减薄并抛光。如图4b所示，采用ICP刻蚀法刻蚀外延层110，腔室压力设置为700mPa，Cl2、BCl3和Ar气体流量分别为50sccm、10sccm和5sccm，射频功率为100W，离子源功率为600W，将外延层110刻蚀至暴露蓝宝石衬底100，形成多个分立的管芯1，同时每两个相邻的所述管芯1之间都保留部分外延层110作为隔离带2，不同管芯1之间的隔离带2是不连续的，隔离带2的宽度为20微米，与相邻管芯1边缘之间槽3的宽度为10微米，刻蚀后的外延层侧壁倾角为60°。如图4c所示，在刻蚀后的外延层110上涂胶后与支撑基板120粘结并固化。所述支撑基板120为Si、陶瓷、W、Cu、Mo、GaAs、石墨、玻璃中的任意一种。如图4d所示，在支撑基板120的另一侧涂敷树脂胶210。所述树脂胶210在激光剥离过程中起到缓解应力的作用。为了使涂敷上去的树脂胶210平整，如图4e所示，使用透明的辅助基板220如玻璃、蓝宝石将树脂胶210压平，然后采用紫外光将树脂胶210固化，去除辅助基板220。如图4f所示，采用激光剥离的方法去除蓝宝石衬底100。如图4g所示，去除所述树脂胶210。去除残留的隔离带2，采用通用工艺形成P、N电极，完成半导体发光器件的制备。
本实施例的外延层侧壁倾角为60°，芯片生产良率略有提高。
实施例4
如图5a所示，在蓝宝石衬底100上依次生长缓冲层、N型GaN层、活性层、P型GaN层，形成外延层110。对蓝宝石衬底100进行机械研磨减薄并抛光。如图5b所示，采用355nm紫外激光，激光功率为1.2W，频率为120KHz，速率为120mm/s，将外延层110刻蚀至暴露蓝宝石衬底100，形成多个分立的管芯1，同时每两个相邻的所述管芯1之间都保留部分外延层110作为隔离带2，不同管芯1之间的隔离带2是不连续的，隔离带2的宽度为40微米，与相邻管芯1边缘之间槽3的宽度为10微米，刻蚀后的外延层侧壁倾角为90°。如图5c所示，在刻蚀后的外延层110上涂敷高温环氧树脂改性胶，与第一临时基板310粘结之后固化。如图5d所示，使用激光剥离的方法去除蓝宝石衬底100，采用248纳米准分子激光，功率550毫瓦。如图5e所示，在剥离面上沉积TiAu保护层之后与第二临时基板320键合。如图5f所示，用蜡保护第二临时基板320之后，用氢氟酸加双氧水加硝酸(5∶2∶2)腐蚀第一临时基板310，采用甲苯在100℃下进行腐蚀该高温环氧树脂改性胶。如图5g所示，将暴露出的外延层键合到支撑基板120上，所述支撑基板120为硅基板。如图5h所示，将支撑基板120用蜡进行保护，用氢氟酸加双氧水加硝酸(5∶2∶2)腐蚀第二临时基板320，并用硫酸双氧水腐蚀掉改性杂环树脂胶，然后对于得到的N型GaN层表面进行清洗。去除残留的隔离带2，采用通用工艺形成P、N电极，完成半导体发光器件的制备。
本实施例的外延层侧壁倾角为90°，芯片生产良率大大提高。
以上所述，仅为本发明中的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉该技术的人在本发明所揭露的技术范围内，可轻易想到的变换或替换都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应该以权利要求书的保护范围为准。

Claims (6)

  1. 一种半导体发光器件的制备方法，包括：
    在蓝宝石衬底上依次生长缓冲层、N型GaN层、活性层、P型GaN层，形成外延层；
    刻蚀所述外延层至暴露蓝宝石衬底以产生多个分立的管芯；将刻蚀后的外延层与支撑基板结合；
    采用激光剥离方法去除蓝宝石衬底；
    其特征在于刻蚀后的外延层侧壁倾角为60°～90°。
  2. 根据权利要求1所述的半导体发光器件的制备方法，其特征在于所述外延层侧壁倾角为75°～85°。
  3. 根据权利要求1所述的半导体发光器件的制备方法，其特征在于所述刻蚀后的外延层与支撑基板结合的方法为共晶键合或涂胶后固化。
  4. 根据权利要求1所述的半导体发光器件的制备方法，其特征在于所述管芯之间都保留部分外延层作为隔离带，并且管芯四周的隔离带至少有一处是不相连的。
  5. 根据权利要求4所述的半导体发光器件的制备方法，其特征在于所述隔离带与相邻管芯边缘之间槽的宽度为1-100微米。
  6. 根据权利要求4所述的半导体发光器件的制备方法，其特征在于所述隔离带的宽度为5-100微米。
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