WO2015027538A1 - Single stage pfc flyback power supply ripple deduction current circuit - Google Patents

Single stage pfc flyback power supply ripple deduction current circuit Download PDF

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Publication number
WO2015027538A1
WO2015027538A1 PCT/CN2013/083523 CN2013083523W WO2015027538A1 WO 2015027538 A1 WO2015027538 A1 WO 2015027538A1 CN 2013083523 W CN2013083523 W CN 2013083523W WO 2015027538 A1 WO2015027538 A1 WO 2015027538A1
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Prior art keywords
transistor
resistor
input
power supply
terminal
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PCT/CN2013/083523
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French (fr)
Chinese (zh)
Inventor
许国伟
黄鹤鸣
肖灵
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深圳市东方之星电源有限公司
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Publication of WO2015027538A1 publication Critical patent/WO2015027538A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/14—Arrangements for reducing ripples from dc input or output
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
    • H02M1/4208—Arrangements for improving power factor of AC input
    • H02M1/4258—Arrangements for improving power factor of AC input using a single converter stage both for correction of AC input power factor and generation of a regulated and galvanically isolated DC output voltage
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the present invention relates to the field of electronic lighting technology, and in particular, to a single-stage PFC flyback power supply de-ripple current line.
  • the current line structure suitable for the LED driver power supply is a single type.
  • the pole PFC flyback structure, the driving mode of the single-stage PFC flyback structure has the advantages of high efficiency, high power factor and the like.
  • This kind of single-stage PFC line because the ripple voltage after PF correction, energy transmission and power frequency rectification is transmitted to the output, it causes a large congenital ripple, and 100Hz/120Hz power frequency ripple is added to the LED illuminant. On, causing the LED illuminator to appear 100Hz/120Hz stroboscopic.
  • the existing solution solves the single-stage PFC flyback driving power supply structure circuit, as shown in FIG. 1, the single-stage PFC flyback of the single-stage PFC flyback driving power supply structure line
  • the power supply adopts constant voltage output, and the latter stage adds a 1-stage DC-DC conversion power supply to realize power frequency ripple output.
  • the disadvantages of this type of circuit are as follows: First, the circuit is complicated, and there are many electronic components, resulting in high cost. Second, it requires more space to store the DC-DC conversion power supply, and additionally generates EMC problems, which will increase the cost again.
  • a single-stage PFC flyback power supply de-ripple current line which mainly includes an input positive pole (Vi+), an input negative pole (Vi ⁇ ), an output positive pole (Vo+), an output negative pole (Vo-), a Zener tube (ZD2), a capacitor (CD1), a second resistor (RD2), a first transistor (QD1), and a second transistor (Q2), the cathode of the Zener diode (ZD2) is connected to the anode of the input terminal (Vi+), the anode is connected to a connection point of one end of the second resistor (RD2) and the end of the capacitor (CD1), and the other end of the second resistor (RD2) is connected to the second transistor (Q2) a base, the other end of the capacitor (CD1) is simultaneously connected to the input negative terminal (Vi -), the output negative terminal (Vo-); the second triode (Q2) collector and a connection point of a collector of the first transistor (QD1) is connected to the positive terminal (
  • a diode is further included; a cathode of the diode (DDI) is connected in series to a cathode of the Zener diode (ZD2), and a cathode thereof is connected to the anode (Vi+) of the input terminal.
  • a first resistor (RD1) is further included; one end of the first resistor (RD1) is coupled to the anode of the diode (DDI) and connected to the positive terminal (Vi+) of the input terminal, and One end is connected in parallel with the anode of the Zener diode (ZD2), and one end of the capacitor (CD1) and one end of the second resistor (RD2) are connected.
  • the single-stage PFC flyback power supply de-ripple current line provided by the present invention has beneficial effects:
  • FIG. 1 is a schematic diagram of a prior art solution for a single-stage PFC flyback drive power supply structure.
  • FIG. 2 is a schematic circuit diagram of a first embodiment of a single-stage PFC flyback power supply for removing ripple according to the present invention.
  • FIG. 3 is a schematic circuit diagram of a second embodiment of a single-stage PFC flyback power supply for removing ripple according to the present invention.
  • FIG. 4 is a schematic circuit diagram of a third embodiment of a single-stage PFC flyback power supply for removing ripple according to the present invention.
  • Figure 5a is a diagram of one of the input waveforms of the present invention.
  • Figure 5b is a diagram of one of the output waveforms of the present invention.
  • Vi+ positive input
  • Vi- negative at the input
  • Vo+ positive at the output
  • Vo- negative at the output
  • ZD2 Zener
  • CD1 capacitor
  • RD2 second resistor
  • QD1 One transistor
  • Q2 second transistor
  • DDI diode
  • RD1 first resistor.
  • the present invention provides a single-stage PFC flyback power supply de-ripple current line, including an input positive terminal (Vi+), an input negative terminal (Vi ⁇ ), and an output positive terminal (Vo+).
  • the input positive terminal (Vi+) is connected to the cathode of the Zener diode (ZD2), the collector of the first transistor (QD1), and the collector of the second transistor (Q2).
  • the anode of the Zener diode (ZD2) is connected to one end of the second resistor (RD2) and one end of the capacitor (CD1), and the other end of the second resistor (RD2) is connected to the base of the second transistor (Q2), the capacitor
  • the other end of (CD1) is negative at the same time as the input Polar (Vi -), output negative (Vo-) connection.
  • the emitter of the second transistor (Q2) is connected to the base of the first transistor (QD1), and the emitter of the first transistor (QD1) is connected to the anode of the output (Vo+).
  • the second resistor (RD2) is applied to the base of the second transistor (Q2), amplified by the second transistor (Q2), and applied to the base of the first transistor (QD1) to make the first transistor (QD1)
  • the operation is in an amplified state, and a smooth voltage/current waveform is output from the positive terminal (Vo+) and the negative terminal (Vo-) (see Figure 5b).
  • a diode (DDI) is further included, which is specifically a positive electrode of the positive terminal (Vi+) and the diode (DDI), a collector of the first transistor (QD1), and a second The collector of the triode (Q2) is connected, the cathode of the diode (DDI) is connected in series with the cathode of the Zener diode (ZD2), the anode of the Zener diode (ZD2) and the end of the second resistor (RD2), and the capacitance (CD1) One end of the second resistor (RD2) is connected to the base of the second transistor (Q2), and the other end of the capacitor (CD1) is simultaneously connected to the negative terminal of the input terminal (Vi -) and the negative terminal of the output terminal (Vo-). connection.
  • the emitter of the second transistor (Q2) is connected to the base of the first transistor (QD1), and the emitter of the first transistor (QD1) is connected to the positive terminal (
  • the embodiment further includes a diode (DDI) and a first resistor (RD1) relative to the first embodiment, specifically the input positive terminal (Vi+) and one end of the first resistor (RD1). , the anode of the diode (DDI), the collector of the first transistor (QD1), the collector of the second transistor (Q2), and the cathode of the diode (DDI) cathode series regulator (ZD2)
  • the other end of the first resistor (RD1) is connected in parallel, and the other end of the first resistor (RD1) is simultaneously connected to the anode of the Zener diode (ZD2), one end of the second resistor (RD2), and one end of the capacitor (CD1).
  • the other end of the resistor (RD2) is connected to the base of the second transistor (Q2), and the other end of the capacitor (CD1) is connected to both the input negative (Vi -) and the output negative (Vo-).
  • the emitter of the second transistor (Q2) is connected to the base of the first transistor (QD1), and the emitter of the first transistor (QD1) is connected to the positive terminal (Vo+) of the output.

Abstract

A single stage PFC flyback power supply ripple deduction current circuit, which relates to the electrical lighting technology field and mainly comprises input/output ends (Vi+, Vi-/Vo+, Vo-), a stabilivolt (ZD2), a capacity (CD1), a second resistor (RD2), a first transistor (QD1) and a second transistor (Q2). A positive electrode (Vi+) of the input end is connected to a cathnode of the stabilivolt (ZD2), a collector of the first transistor (QD1) and a collector of the second transistor (Q2). An anode of the stabilivolt (ZD2) is connected to one end of the second resistor (RD2) and one end of the capacity (CD1). The other end of the second resistor (RD2) is connected to a base of the second transistor (Q2). The other end of the capacity (CD1) is connected to a negative electrode (Vi-) of the input end and a negative electrode (Vo-) of the output end. An emitter of the second transistor (Q2) is connected to a base of the first transistor (QD1). An emitter of the first transistor (QD1) is connected to a positive electrode (Vo+) of the output end. The current circuit implements power frequency ripple deduction of a single stage PFC flyback structure circuit at a low cost; no extra EMC problem will be generated; and the circuit is simple.

Description

一种单级 PFC反激电源去紋波电流线路 技术领域  Single-stage PFC flyback power supply de-ripple current line
本发明涉及电子照明技术领域， 特别涉及一种单级 PFC反激电源去紋波电 流线路。  The present invention relates to the field of electronic lighting technology, and in particular, to a single-stage PFC flyback power supply de-ripple current line.
背景技术 Background technique
随着 LED技术的快速发展与应用日益成熟， LED驱动电源作为 LED能够发光 显示的重要部分， 其技术发展迅猛。 为了实现节能高效要求， 对 LED驱动电 源提出了 PF (功率因素） 大于或等于 0. 9 的要求， 再加上由于体积受到限 制，目前适用于 LED驱动电源的线路结构较为广泛的是一种单极 PFC反激结 构， 这种单级 PFC反激结构的驱动方式具有高效率、 高功率因数等优点。 这 种单级 PFC线路， 由于实现了 PF校正、 能量传输、 工频整流后的紋波电压 传输到了输出，因此造成了先天性紋波较大， 100Hz/ 120Hz工频紋波加在 LED 发光体上， 造成 LED发光体出现 100Hz/120Hz频闪。  With the rapid development and application of LED technology, LED drive power is an important part of LED display, and its technology is developing rapidly. In order to achieve energy-saving and high-efficiency requirements, the requirements for PF (power factor) greater than or equal to 0.9 for the LED driver power supply, plus the limitation of the volume, the current line structure suitable for the LED driver power supply is a single type. The pole PFC flyback structure, the driving mode of the single-stage PFC flyback structure has the advantages of high efficiency, high power factor and the like. This kind of single-stage PFC line, because the ripple voltage after PF correction, energy transmission and power frequency rectification is transmitted to the output, it causes a large congenital ripple, and 100Hz/120Hz power frequency ripple is added to the LED illuminant. On, causing the LED illuminator to appear 100Hz/120Hz stroboscopic.
为了解决紋波大造成的频闪问题，现有方案解决单级 PFC反激驱动电源 结构线路， 如附图 1 所示， 该单级 PFC反激驱动电源结构线路的前级单级 PFC反激电源采用恒压输出， 后级增加 1级 DC-DC转换电源， 实现工频紋波 输出。 但是这种线路的缺点在于： 一是线路复杂， 电子元器件多， 造成成本 较高； 二是需要更大空间存放 DC-DC转换电源， 同时还额外产生 EMC问题， 会再次增加成本。  In order to solve the stroboscopic problem caused by large ripple, the existing solution solves the single-stage PFC flyback driving power supply structure circuit, as shown in FIG. 1, the single-stage PFC flyback of the single-stage PFC flyback driving power supply structure line The power supply adopts constant voltage output, and the latter stage adds a 1-stage DC-DC conversion power supply to realize power frequency ripple output. However, the disadvantages of this type of circuit are as follows: First, the circuit is complicated, and there are many electronic components, resulting in high cost. Second, it requires more space to store the DC-DC conversion power supply, and additionally generates EMC problems, which will increase the cost again.
发明内容 Summary of the invention
为了解决上述现有的技术不足与缺陷， 本发明的目的在于提供一种线路简 单、 低成本的单级 PFC反激电源去紋波电流线路。 本发明的目的是通过采用以下技术方案来实现的： In order to solve the above-mentioned prior art deficiencies and shortcomings, it is an object of the present invention to provide a single-stage PFC flyback power supply de-ripple current line with simple wiring and low cost. The object of the present invention is achieved by adopting the following technical solutions:
一种单级 PFC反激电源去紋波电流线路， 其主要包括输入端正极（Vi+)、 输 入端负极 （Vi -)、 输出端正极 （Vo+)、 输出端负极 （Vo-)、 稳压管 （ZD2)、 电容 (CD1)、 第二电阻 （RD2)、 第一三极管 （QD1)和第二三极管 （Q2), 所述稳压 管（ZD2)的阴极连接所述输入端正极（Vi+)， 其阳极连接所述第二电阻（RD2) 一端与所述电容 （CD1) —端的连接点， 所述第二电阻 （RD2) 另一端连接所述 第二三极管（Q2)的基极，所述电容（CD1)另一端同时与所述输入端负极（Vi -)、 所述输出端负极 （Vo-) 相连接； 所述第二三极管 （Q2) 的集电极与所述第一三 极管 （QD1) 的集电极的连接点与所述输入端正极 （Vi+) 连接， 所述第二三极 管（Q2)的发射极连接所述第一三极管（QD1)的基极，所述第一三极管（QD1) 的发射极连接所述输出端正极 （Vo+)。  A single-stage PFC flyback power supply de-ripple current line, which mainly includes an input positive pole (Vi+), an input negative pole (Vi −), an output positive pole (Vo+), an output negative pole (Vo-), a Zener tube (ZD2), a capacitor (CD1), a second resistor (RD2), a first transistor (QD1), and a second transistor (Q2), the cathode of the Zener diode (ZD2) is connected to the anode of the input terminal (Vi+), the anode is connected to a connection point of one end of the second resistor (RD2) and the end of the capacitor (CD1), and the other end of the second resistor (RD2) is connected to the second transistor (Q2) a base, the other end of the capacitor (CD1) is simultaneously connected to the input negative terminal (Vi -), the output negative terminal (Vo-); the second triode (Q2) collector and a connection point of a collector of the first transistor (QD1) is connected to the positive terminal (Vi+) of the input terminal, and an emitter of the second transistor (Q2) is connected to the first transistor (QD1) The base of the first transistor (QD1) is connected to the positive terminal (Vo+) of the output terminal.
作为本发明可选技术方案， 还包括二极管 （DDI); 所述二极管 （DDI) 的 负极串联接所述稳压管 （ZD2) 的阴极， 其正极与所述输入端正极 （Vi+) 连接。  As an alternative technical solution of the present invention, a diode (DDI) is further included; a cathode of the diode (DDI) is connected in series to a cathode of the Zener diode (ZD2), and a cathode thereof is connected to the anode (Vi+) of the input terminal.
作为本发明可选技术方案， 还包括第一电阻 （RD1); 所述第一电阻 （RD1) 一端与所述二极管 （DDI) 的正极并联接后与所述输入端正极 （Vi+) 连接， 另 一端与所述稳压管 （ZD2) 的阳极并联后连接所述电容 （CD1) 的一端、 以及第 二电阻 （RD2) 的一端。  As an optional technical solution of the present invention, a first resistor (RD1) is further included; one end of the first resistor (RD1) is coupled to the anode of the diode (DDI) and connected to the positive terminal (Vi+) of the input terminal, and One end is connected in parallel with the anode of the Zener diode (ZD2), and one end of the capacitor (CD1) and one end of the second resistor (RD2) are connected.
综上所述， 本发明所提供的单级 PFC反激电源去紋波电流线路， 具有的有 益效果：  In summary, the single-stage PFC flyback power supply de-ripple current line provided by the present invention has beneficial effects:
1、 线路简单， 电子元器件少， 大大降低了成本。  1, the line is simple, less electronic components, greatly reducing the cost.
2、 能去除单级 PFC反激电源的紋波， 实现无工频紋波， 并且不会额外产生 EMC问题。  2. It can remove the ripple of the single-stage PFC flyback power supply, realizes no power frequency ripple, and does not cause additional EMC problems.
3、 线路简单从而形成生产工艺简单， 提高了生产效率， 降低了生产成本。 附图说明 3. The circuit is simple and the production process is simple, the production efficiency is improved, and the production cost is reduced. DRAWINGS
图 1为现有方案解决单级 PFC反激驱动电源结构线路的示意图。  FIG. 1 is a schematic diagram of a prior art solution for a single-stage PFC flyback drive power supply structure.
图 2为本发明单级 PFC反激电源去除紋波第一实施例的线路原理图。  2 is a schematic circuit diagram of a first embodiment of a single-stage PFC flyback power supply for removing ripple according to the present invention.
图 3为本发明单级 PFC反激电源去除紋波第二实施例的线路原理图。  3 is a schematic circuit diagram of a second embodiment of a single-stage PFC flyback power supply for removing ripple according to the present invention.
图 4为本发明单级 PFC反激电源去除紋波第三实施例的线路原理图。  4 is a schematic circuit diagram of a third embodiment of a single-stage PFC flyback power supply for removing ripple according to the present invention.
图 5a为本发明的其中一种输入波形图。  Figure 5a is a diagram of one of the input waveforms of the present invention.
图 5b为本发明的其中一种输出波形图。  Figure 5b is a diagram of one of the output waveforms of the present invention.
附图标记说明： Vi+: 输入端正极， Vi-: 输入端负极， Vo+: 输出端正极， Vo-: 输出端负极， ZD2: 稳压管， CD1: 电容， RD2: 第二电阻， QD1: 第一三 极管， Q2: 第二三极管， DDI: 二极管， RD1: 第一电阻。 DESCRIPTION OF REFERENCE NUMERALS: Vi+: positive input, Vi- : negative at the input, Vo+: positive at the output, Vo-: negative at the output, ZD2: Zener, CD1: capacitor, RD2: second resistor, QD1: One transistor, Q2: second transistor, DDI: diode, RD1: first resistor.
具体实施方式 detailed description
下面通过实施例并结合附图， 对本发明的技术方案作进一步详细的说明。 下述参照附图对本发明的实施方式的说明旨在对本发明的总体发明构思进行解 释， 而不应当理解为对本发明的一种限制。  The technical solution of the present invention will be further described in detail below by way of embodiments and with reference to the accompanying drawings. The description of the embodiments of the present invention is intended to be illustrative of the present invention, and is not intended to
参照附图 2至图 5b所示， 本发明提供一种单级 PFC反激电源去紋波电流线 路， 包括输入端正极 （Vi+)、 输入端负极 （Vi -)、 输出端正极 （Vo+)、 输出端负 极（Vo-)、 稳压管（ZD2)、 电容（CD1)、第二电阻（RD2)、第一三极管（QD1)、 第二三极管 （Q2)、 二极管 （DDI) 和第一电阻 （RD1)。  Referring to FIG. 2 to FIG. 5b, the present invention provides a single-stage PFC flyback power supply de-ripple current line, including an input positive terminal (Vi+), an input negative terminal (Vi −), and an output positive terminal (Vo+). Output negative (Vo-), Zener (ZD2), capacitor (CD1), second resistor (RD2), first transistor (QD1), second transistor (Q2), diode (DDI) and First resistance (RD1).
如图 2 第一实施例所示， 输入端正极 （Vi+) 与稳压管 （ZD2) 的阴极、 第 一三极管 （QD1) 的集电极、 第二三极管 （Q2) 的集电极连接， 稳压管 （ZD2) 的阳极与第二电阻（RD2) 的一端、 电容（CD1) 的一端连接， 第二电阻（RD2) 的另一端连接第二三极管（Q2) 的基极， 电容（CD1) 的另一端同时与输入端负 极 （Vi -)、 输出端负极 （Vo-) 连接。 第二三极管 （Q2) 的发射极连接第一三极 管 （QD1) 的基极， 第一三极管 （QD1) 的发射极与输出端正极 （Vo+) 连接。 As shown in the first embodiment of FIG. 2, the input positive terminal (Vi+) is connected to the cathode of the Zener diode (ZD2), the collector of the first transistor (QD1), and the collector of the second transistor (Q2). The anode of the Zener diode (ZD2) is connected to one end of the second resistor (RD2) and one end of the capacitor (CD1), and the other end of the second resistor (RD2) is connected to the base of the second transistor (Q2), the capacitor The other end of (CD1) is negative at the same time as the input Polar (Vi -), output negative (Vo-) connection. The emitter of the second transistor (Q2) is connected to the base of the first transistor (QD1), and the emitter of the first transistor (QD1) is connected to the anode of the output (Vo+).
结合图 2第一实施例， 当带较大紋波电压 /电流（如图 5a所示） 由输入端正 极 （Vi+) 和输入端负极 （Vi-) 输入， 经稳压管 （ZD2) 加至电容 （CD1) 上， 利 用稳压管 （ZD2) 反向泄漏电流 （稳压管两端电压远低于其标称稳压值）， 在电 容（CD1)处形成一个平滑的直流电压，经第二电阻（RD2)加至第二三极管（Q2) 的基极， 经第二三极管 （Q2) 放大后加至第一三极管 （QD1) 的基极， 使第一 三极管 （QD1) 工作处于放大状态， 从输出端正极 （Vo+) 和输出端负极 （Vo-) 输出平滑的电压 /电流波形 （如图 5b所示）。  Referring to the first embodiment of FIG. 2, when a large ripple voltage/current (shown in FIG. 5a) is input from the input positive (Vi+) and the input negative (Vi-), it is added to the Zener (ZD2) through the Zener diode (ZD2). On the capacitor (CD1), using the Zener diode (ZD2) reverse leakage current (the voltage across the Zener diode is much lower than its nominal regulation value), a smooth DC voltage is formed at the capacitor (CD1). The second resistor (RD2) is applied to the base of the second transistor (Q2), amplified by the second transistor (Q2), and applied to the base of the first transistor (QD1) to make the first transistor (QD1) The operation is in an amplified state, and a smooth voltage/current waveform is output from the positive terminal (Vo+) and the negative terminal (Vo-) (see Figure 5b).
如图 3第二实施例所示， 还包括一颗二极管 （DDI), 具体详细为输入端正 极（Vi+) 与二极管 （DDI) 的正极、 第一三极管 （QD1) 的集电极、 第二三极管 (Q2) 的集电极连接， 二极管 （DDI) 的负极串联接稳压管 （ZD2) 的阴极， 稳 压管 （ZD2) 的阳极与第二电阻（RD2) 的一端、 电容（CD1) 的一端连接， 第二 电阻 （RD2) 的另一端连接第二三极管 （Q2) 的基极， 电容 （CD1) 的另一端同 时与输入端负极 （Vi -)、 输出端负极 （Vo-) 连接。 第二三极管 （Q2) 的发射极 连接第一三极管（QD1)的基极，第一三极管（QD1)的发射极与输出端正极 (Vo+) 连接。  As shown in the second embodiment of FIG. 3, a diode (DDI) is further included, which is specifically a positive electrode of the positive terminal (Vi+) and the diode (DDI), a collector of the first transistor (QD1), and a second The collector of the triode (Q2) is connected, the cathode of the diode (DDI) is connected in series with the cathode of the Zener diode (ZD2), the anode of the Zener diode (ZD2) and the end of the second resistor (RD2), and the capacitance (CD1) One end of the second resistor (RD2) is connected to the base of the second transistor (Q2), and the other end of the capacitor (CD1) is simultaneously connected to the negative terminal of the input terminal (Vi -) and the negative terminal of the output terminal (Vo-). connection. The emitter of the second transistor (Q2) is connected to the base of the first transistor (QD1), and the emitter of the first transistor (QD1) is connected to the positive terminal (Vo+) of the output.
结合图 3第二实施例， 当带较大紋波电压 /电流（如图 5a所示） 由输入端正 极 （Vi+) 和输入端负极 （Vi-) 输入， 经二极管 （DD1)、 稳压管 （ZD2) 串联， 加至电容 （CD1) 上， 利用稳压管 （ZD2) 反向泄漏电流 （稳压管两端电压远低 于其标称稳压值），在电容 ( CD1 )处形成一个平滑的直流电压，经第二电阻（ RD2 ) 加至第二三极管（Q2)的基极，经第二三极管（Q2)放大后加至第一三极管（QD1) 的基极， 使第一三极管 （QD1) 工作处于放大状态， 从输出端正极 （Vo+) 和输 出端负极 （Vo-) 输出平滑的电压 /电流波形 （如图 5b所示）。 In conjunction with the second embodiment of FIG. 3, when a large ripple voltage/current (shown in FIG. 5a) is input from the input positive (Vi+) and the input negative (Vi-), through the diode (DD1), the Zener (ZD2) In series, applied to the capacitor (CD1), using the Zener diode (ZD2) reverse leakage current (the voltage across the Zener diode is much lower than its nominal regulation value), forming a capacitor (CD1) A smooth DC voltage is applied to the base of the second transistor (Q2) via a second resistor (RD2), amplified by a second transistor (Q2), and applied to the base of the first transistor (QD1) , make the first transistor (QD1) work in the amplified state, from the output positive (Vo+) and lose The output negative (Vo-) outputs a smooth voltage/current waveform (as shown in Figure 5b).
如图 4第三实施例所示， 本实施例相对第一实施例还包括二极管（DDI)和 第一电阻 （RD1), 具体详细为输入端正极 （Vi+) 与第一电阻 （RD1) 的一端、 二极管 （DDI) 的正极、 第一三极管 （QD1) 的集电极、 第二三极管 （Q2) 的集 电极连接，二极管（DDI)的负极串联稳压管（ZD2)的阴极后与第一电阻（RD1) 的另一端并联， 第一电阻 （RD1) 的另一端同时与稳压管 （ZD2) 的阳极、 第二 电阻 （RD2) 的一端、 电容 （CD1) 的一端连接， 第二电阻 （RD2) 的另一端连 接第二三极管 （Q2) 的基极， 电容 （CD1) 的另一端同时与输入端负极 （Vi -)、 输出端负极 （Vo-) 连接。 第二三极管 （Q2) 的发射极连接第一三极管 （QD1) 的基极， 第一三极管 （QD1) 的发射极与输出端正极 （Vo+) 连接。  As shown in the third embodiment of FIG. 4, the embodiment further includes a diode (DDI) and a first resistor (RD1) relative to the first embodiment, specifically the input positive terminal (Vi+) and one end of the first resistor (RD1). , the anode of the diode (DDI), the collector of the first transistor (QD1), the collector of the second transistor (Q2), and the cathode of the diode (DDI) cathode series regulator (ZD2) The other end of the first resistor (RD1) is connected in parallel, and the other end of the first resistor (RD1) is simultaneously connected to the anode of the Zener diode (ZD2), one end of the second resistor (RD2), and one end of the capacitor (CD1). The other end of the resistor (RD2) is connected to the base of the second transistor (Q2), and the other end of the capacitor (CD1) is connected to both the input negative (Vi -) and the output negative (Vo-). The emitter of the second transistor (Q2) is connected to the base of the first transistor (QD1), and the emitter of the first transistor (QD1) is connected to the positive terminal (Vo+) of the output.
结合图 4第三实施例， 当带较大紋波电压 /电流（如图 5a所示） 由输入端正 极 （Vi+) 和输入端负极 （Vi-) 输入， 经二极管 （DD1)、 稳压管 （ZD2) 串联后 与第一电阻（RD1) 并联， 加至电容（CD1)上， 利用稳压管（ZD2)反向泄漏电 流 （稳压管两端电压远低于其标称稳压值）， 在电容 （CD1) 处形成一个平滑的 直流电压，经第二电阻（RD2)加至第二三极管（Q2)的基极，经第二三极管（Q2) 放大后加至第一三极管 （QD1) 的基极， 使第一三极管 （QD1) 工作处于放大状 态， 从输出端正极 （Vo+) 和输出端负极 （Vo-) 输出平滑的电压 /电流波形 （如 图 5b所示）。  In conjunction with the third embodiment of FIG. 4, when a large ripple voltage/current (shown in FIG. 5a) is input from the input positive (Vi+) and the input negative (Vi-), through the diode (DD1), the Zener diode (ZD2) Connected in series with the first resistor (RD1), applied to the capacitor (CD1), and reversed the leakage current using the Zener diode (ZD2) (the voltage across the regulator is much lower than its nominal regulation value) , a smooth DC voltage is formed at the capacitor (CD1), applied to the base of the second transistor (Q2) via the second resistor (RD2), amplified by the second transistor (Q2) and added to the first The base of the transistor (QD1) causes the first transistor (QD1) to operate in an amplified state, outputting a smooth voltage/current waveform from the output positive (Vo+) and the output negative (Vo-) (Figure 5b) Shown).
以上所述实施例仅表达了本发明的优选实施方式， 其描述较为具体与详细， 但并不能因此而理解为对本发明专利范围和实施例的限制。 应当指出的是， 对 于本领域的普通技术人员来说， 在不脱离本发明构思的前提下， 还可以做出若 干变形和改进， 这些都属于本发明的保护范围。  The above-mentioned embodiments are merely illustrative of the preferred embodiments of the present invention, and the description thereof is not to be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the spirit and scope of the invention.

Claims

权利要求书  Claim
一种单级 PFC反激电源去紋波电流线路， 其主要包括输入端正极 （Vi+)、 输入端负极（Vi -)、 输出端正极（Vo+)、 输出端负极（Vo-)、 稳压管（ZD2)、 电容 （CD1)、 第二电阻 （RD2)、 第一三极管 （QD1) 和第二三极管 （Q2), 其特征在于： 所述稳压管（ZD2) 的阴极连接所述输入端正极（Vi+)， 其阳极 连接所述第二电阻（RD2)—端与所述电容（CD1)—端的连接点， 所述第二 电阻 （RD2) 另一端连接所述第二三极管 （Q2) 的基极， 所述电容 （CD1) 另一端同时与所述输入端负极 （Vi -)、 所述输出端负极 （Vo-) 相连接； 所述 第二三极管 （Q2) 的集电极与所述第一三极管 （QD1) 的集电极的连接点与 所述输入端正极 （Vi+) 连接， 所述第二三极管 （Q2) 的发射极连接所述第 一三极管 （QD1) 的基极， 所述第一三极管 （QD1) 的发射极连接所述输出 端正极 （Vo+)。  A single-stage PFC flyback power supply de-ripple current line, which mainly includes an input positive pole (Vi+), an input negative pole (Vi −), an output positive pole (Vo+), an output negative pole (Vo-), a Zener tube (ZD2), a capacitor (CD1), a second resistor (RD2), a first transistor (QD1), and a second transistor (Q2), characterized in that: a cathode connection of the Zener diode (ZD2) An input positive terminal (Vi+) having an anode connected to a connection point of the second resistor (RD2) end and the capacitor (CD1) end, and the other end of the second resistor (RD2) connected to the second three pole a base of the tube (Q2), the other end of the capacitor (CD1) is simultaneously connected to the input negative terminal (Vi -), the output negative terminal (Vo-); the second triode (Q2) a connection point of the collector to the collector of the first transistor (QD1) is connected to the positive terminal (Vi+) of the input terminal, and an emitter of the second transistor (Q2) is connected to the first three The base of the pole tube (QD1), the emitter of the first transistor (QD1) is connected to the positive terminal of the output (Vo+).
根据权利要求 1，所述的单级 PFC反激电源去紋波电流线路，其特征在于， 还包括二极管（DDI); 所述二极管（DDI)的负极串联接所述稳压管（ZD2) 的阴极， 其正极与所述输入端正极 （Vi+) 连接。  The single-stage PFC flyback power supply de-ripple current line according to claim 1, further comprising a diode (DDI); wherein a cathode of the diode (DDI) is connected in series to the Zener diode (ZD2) The cathode has its positive electrode connected to the positive terminal (Vi+) of the input terminal.
根据权利要求 2，所述的单级 PFC反激电源去紋波电流线路，其特征在于， 还包括第一电阻 （RD1); 所述第一电阻 （RD1) —端与所述二极管 （DDI) 的正极并联后与所述输入端正极 （Vi+) 连接， 另一端与所述稳压管 （ZD2) 的阳极并联后连接所述电容 （CD1) 的一端、 以及第二电阻 （RD2) 的一端。  The single-stage PFC flyback power supply de-ripple current line according to claim 2, further comprising a first resistor (RD1); said first resistor (RD1)-terminal and said diode (DDI) The positive pole is connected in parallel with the positive terminal (Vi+) of the input terminal, and the other end is connected in parallel with the anode of the Zener diode (ZD2), and is connected to one end of the capacitor (CD1) and one end of the second resistor (RD2).
PCT/CN2013/083523 2013-08-28 2013-09-16 Single stage pfc flyback power supply ripple deduction current circuit WO2015027538A1 (en)

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