WO2014190892A1 - Al-w-o stack structure applicable to resistive random access memory - Google Patents
Al-w-o stack structure applicable to resistive random access memory Download PDFInfo
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- WO2014190892A1 WO2014190892A1 PCT/CN2014/078496 CN2014078496W WO2014190892A1 WO 2014190892 A1 WO2014190892 A1 WO 2014190892A1 CN 2014078496 W CN2014078496 W CN 2014078496W WO 2014190892 A1 WO2014190892 A1 WO 2014190892A1
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- WIPO (PCT)
- Prior art keywords
- oxide layer
- random access
- resistive random
- access memory
- tungsten
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
- H10N70/028—Formation of switching materials, e.g. deposition of layers by conversion of electrode material, e.g. oxidation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
- H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
Definitions
- novel resistive random access memories have many advantages, including good scaling performance, convenience for 3D stacking, simple structure, high memory density, low operation voltage, small operation current, high speed in reading and writing, low power consumption, compatibility with traditional CMOS (complementary metal oxide semiconductors) and so on.
- the novel resistive random access memories (RRAM) are of sandwich structure filled with one-element or multi-element metal oxides between upper electrodes and lower electrodes, wherein the filled one-element or multi-element metal oxide layers are resistive switching layers.
- the novel resistive random access memories have excellent performances. Their performances are closely associated with the material selection and the structure composition of resistive switching layers. Research groups around the world are trying to develop new materials, new combinations and new structures to improve the performances of the resistive random access memories. The operation voltage, the high resistance-low resistance ratio, the number of write-erase cycles and other performances of the resistive random access memories can be improved by selecting different material combinations.
- the Al-W-0 stack structure applicable to the resistive random access memory includes a tungsten bottom electrode, a tungsten oxide layer formed on the tungsten bottom electrode, an aluminum oxide layer formed on the tungsten oxide layer and an aluminum top electrode formed on the aluminum oxide layer.
- the thickness of the aluminum oxide layer is 3-10nm.
- Fig. 2 is a transmission electron micrograph diagram of the Al-W-0 stack structure applicable to the resistive random access memory according to the embodiment of the invention.
- the description that the first feature is "above” or “below” the second feature can include the direct contact between the first feature and the second feature and can also include the contact between the first and second features through another feature between them but not the direct contact. Furthermore, the description that the first feature is arranged “over”, “above” and “on” the second feature comprises the situation that the first feature is arranged just above or aslant above the second feature or only indicates that the horizontal height of the first feature is higher than that of the second feature.
- the invention provides an Al-W-0 stack structure applicable to a resistive random access memory.
- the core idea of the technical scheme of the invention is as follows: two metals, namely aluminum and tungsten are selected for stacking double metal oxide layers, wherein tungsten oxide is thicker, about 50nm thick and being as the lower layer; and aluminum oxide is thinner in thickness, about 5nm thick, manufactured by a contact type oxidation process as the upper layer.
- the invention utilizes the different properties of two metals, namely aluminum and tungsten in bonding with oxygen ions, and obtains a resistive random access memory with more stable performances, lower power consumption and larger high resistance-low resistance ratio.
- the aluminum oxide layer 210 is formed in a contact type oxidation way.
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
An Al-W-O stack structure applicable to a resistive random access memory according to an embodiment of the invention comprises a tungsten top electrode, a tungsten oxide layer formed on the tungsten lower electrode, an aluminum oxide layer formed on the tungsten oxide layer and an aluminum top electrode formed on the aluminum oxide layer. The invention utilizes the different properties of two metals, namely aluminum and tungsten in bonding with oxygen ions, to obtain a resistive random access memory with more stable performances, lower power consumption and larger high resistance-low resistance ratio.
Description
Description
AL-W-O STACK STRUCTURE APPLICABLE TO RESISTIVE RANDOM
ACCESS MEMORY
Field of the Invention
The invention belongs to semiconductor manufacturing technologies, in particular to an Al-W-0 stack structure applicable to a resistive random access memory.
Background of the Invention
Along with continuous development of semiconductor technologies and further popularization of electronic equipment in society, especially the popularization of portable electronics, such as mobile phones, and the development of special electronic equipment, such as medical instruments, the sizes of microelectronics are continuously reduced. Meanwhile, the development of video and music entertainment causes the data size increases constantly, which further causes the applications of memories, especially non- volatile memories become more and more important. In the current society, FLASH memories definitely dominate in the non- volatile memories. However, along with the situation that the sizes of the microelectronics become below deep nanometer, a large number of defects of the traditional FLASH memories arise. On the other hand, novel resistive random access memories (RRAM) have many advantages, including good scaling performance, convenience for 3D stacking, simple structure, high memory density, low operation voltage, small operation current, high speed in reading and writing, low power consumption, compatibility with traditional CMOS (complementary metal oxide semiconductors) and so on. The novel resistive random access memories (RRAM) are of sandwich structure filled with one-element or multi-element metal oxides between upper electrodes and lower electrodes, wherein the filled one-element or multi-element metal oxide layers are resistive switching layers. The mechanism is that according to the different voltages applicable to the structure, the resistances of the resistive switching layers change correspondingly in high resistive state and low resistive state to open or block current flow channels, and the significant difference between the high resistance state and the low resistance state is utilized for storing information.
The novel resistive random access memories have excellent performances. Their
performances are closely associated with the material selection and the structure composition of resistive switching layers. Research groups around the world are trying to develop new materials, new combinations and new structures to improve the performances of the resistive random access memories. The operation voltage, the high resistance-low resistance ratio, the number of write-erase cycles and other performances of the resistive random access memories can be improved by selecting different material combinations.
Summary of the Invention
The invention intends to at least solve one of the aforementioned technical problems to some extent or at least provide a useful business option. Therefore, one object of the invention is to provide an Al-W-0 stack structure applicable to a resistive random access memory, which has the advantages of more stable performances, lower power consumption and larger high resistance-low resistance ratio.
According to an embodiment of the invention the Al-W-0 stack structure applicable to the resistive random access memory includes a tungsten bottom electrode, a tungsten oxide layer formed on the tungsten bottom electrode, an aluminum oxide layer formed on the tungsten oxide layer and an aluminum top electrode formed on the aluminum oxide layer.
In one embodiment of the invention, the tungsten oxide layer is formed in a thermal oxidation method.
In one embodiment of the invention, the thickness of the tungsten oxide layer is 30-70nm.
In one embodiment of the invention, the aluminum oxide layer is formed in a contact type oxidation method.
In one embodiment of the invention, the temperature of contact type oxidation is 400-500° C, and the time of contact type oxidation is 50-200s.
In one embodiment of the invention, the thickness of the aluminum oxide layer is 3-10nm.
The invention utilizes the different properties of two metals, namely the ability of aluminum and tungsten in bonding with oxygen ions, and the obtained resistive random access memory has more stable performances, lower power consumption and larger high resistance-low resistance ratio.
The additional aspects and the advantages of the invention will be given in part in the following description, and part of them will become apparent from the following description or be known by practices of the invention.
Description of the Drawings
The above and/or the additional aspects and the advantages of the invention will become apparent and easy to understand in the following description of embodiments in conjunctions with the drawings, wherein,
Fig. 1 is a structure schematic diagram of an Al-W-0 stack structure applicable to a resistive random access memory according to an embodiment of the invention;
Fig. 2 is a transmission electron micrograph diagram of the Al-W-0 stack structure applicable to the resistive random access memory according to the embodiment of the invention.
Detailed Description of the Embodiments
The embodiments of the invention are described below in detail, and the examples of the embodiments are shown in the drawings, wherein identical or similar reference numerals throughout the specification denote identical or similar elements or the elements with identical or similar functions. The embodiments described with reference to the drawings are exemplary, and they aim at illustrating the invention and should not be interpreted as limiting the invention.
In the description of the invention, it should be understood that the direction or position relations indicated by the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like are the direction or position relations shown in the drawings, and are merely used for facilitating the description of the invention and simplifying the description rather than indicating or implying that the indicated devices or elements must be in specific directions, be constructed and operated in the specific directions, so that the terms can not be interpreted as limiting the invention. In addition, the terms "first" and "second" are only used for the purpose of description and should not be interpreted as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features. Therefore, the
features defining "first" and "second" can clearly or implicitly include one or more of the features. In the description of the invention, "more" means two or more unless otherwise specifically limited.
In the invention, unless otherwise clearly specified and limited, the terms "mounting", "connected", "connection", "fixing" and the like should be understood in a broad sense. For example, the connection can be fixed connection, detachable connection or integrated connection; the connection can be mechanical connection or electrical connection; and the connection can be direct connection, indirect connection through an intermediate medium or internal communication of two elements. For those ordinary skilled in the art, the specific meanings of the terms in the invention can be understood according to specific situations.
In the invention, unless otherwise clearly specified and limited, the description that the first feature is "above" or "below" the second feature can include the direct contact between the first feature and the second feature and can also include the contact between the first and second features through another feature between them but not the direct contact. Furthermore, the description that the first feature is arranged "over", "above" and "on" the second feature comprises the situation that the first feature is arranged just above or aslant above the second feature or only indicates that the horizontal height of the first feature is higher than that of the second feature. The description that the first feature is arranged "under", "below" and "underneath" the second feature comprises the situation that the first feature is arranged just below or aslant below the second feature or only indicates that the horizontal height of the first feature is lower than that of the second feature.
In relation to the issue mentioned in the background of the invention that the operation voltage, the high resistance-low resistance ratio, the number of write-erase cycles and other performances of the resistive random access memories can be improved by selecting different material combinations, the invention provides an Al-W-0 stack structure applicable to a resistive random access memory.
The core idea of the technical scheme of the invention is as follows: two metals, namely aluminum and tungsten are selected for stacking double metal oxide layers, wherein tungsten oxide is thicker, about 50nm thick and being as the lower layer; and aluminum oxide is thinner in thickness, about 5nm thick, manufactured by a contact type oxidation process as the upper layer. The
invention utilizes the different properties of two metals, namely aluminum and tungsten in bonding with oxygen ions, and obtains a resistive random access memory with more stable performances, lower power consumption and larger high resistance-low resistance ratio.
Fig. 1 is a structure schematic diagram of an Al-W-0 stack structure applicable to a resistive random access memory according to an embodiment of the invention, and as shown in the figure, the Al-W-0 stack structure applicable to the resistive random access memory according to the embodiment of the invention comprises a tungsten bottom electrode 100, a tungsten oxide layer 110 formed on the tungsten bottom electrode 100, an aluminum oxide layer 210 formed on the tungsten oxide layer 110 and an aluminum top electrode 200 formed on the aluminum oxide layer 210.
In one embodiment of the invention, the tungsten oxide layer 110 is formed in a thermal oxidation way.
In one embodiment of the invention, the thickness of the tungsten oxide layer 110 is 30-70nm, preferably 50nm. Under the condition of maintaining process and device stability, the roughness of tungsten oxide should be as smaller as possible.
In one embodiment of the invention, the aluminum oxide layer 210 is formed in a contact type oxidation way.
In one embodiment of the invention, the temperature of contact type oxidation is 400-500° C, and the time is 50-200s.
In one embodiment of the invention, the thickness of the second oxide layer 210, i.e. the aluminum oxide layer 210 is 3-10nm, preferably 5nm. If the thickness of the second oxide layer 210 is too thin, the double-layer resistive switching performance will not exist, and if the thickness is too thick, the resistance value will be too large, and the resistive switching operation can not be performed.
In order to enable those skilled in the art to understand the invention better, the formation method of the Al-W-0 stack structure of the invention is now presented as follows: metal tungsten is selected as the lower layer, whose thickness is larger. Firstly, the tungsten oxide layer which is about 50nm thick is obtained on the metal tungsten lower electrode in a thermal oxidation way; then, a layer of metal aluminum is manufactured as an upper electrode on the tungsten oxide layer in an evaporation deposition way; and finally, an ultra-thin aluminum oxide layer which is about 5nm thick is obtained by adopting a contact type oxidation technique, wherein a fast
thermal annealing process is used in the contact type oxidation method, with the different attractive forces of aluminum and tungsten against oxygen atoms, the metal aluminum layer can capture oxygen atoms from the oxygen-rich tungsten oxide layer so as to form the ultra-thin stacked aluminum oxide layer.
Fig. 2 is a transmission electron micrograph diagram of the Al-W-0 stack structure applicable to the resistive random access memory according to an embodiment of the invention, showing the thickness of each layer of the ultra-thin stacked and mixed oxide layers of Al-W-O.
In the description of the Specification, the description with reference to terms "one embodiment", "some embodiments", "example", "specific example", "some examples" or the like means that the specific features, the structure, the materials or the features described in conjunction with the embodiment or the example are/is encompassed in at least one embodiment or example of the invention. In the Specification, the schematic representation of the terms does not necessarily refer to the identical embodiment or example. Furthermore, the described specific features, structure, materials or characteristics can be combined in one or more embodiments or examples in an appropriate way.
Although the embodiments of the invention have been illustrated and described above, it can be understood that the embodiments are exemplary and can not be construed as limiting the invention; and those ordinary skilled in the art can make changes, modifications, substitutions and variations to the embodiments within the scope of the invention without departing from the principle and purpose of the invention.
Claims
1. An Al-W-0 stack structure applicable to a resistive random access memory, comprising:
a tungsten bottom electrode;
a tungsten oxide layer formed on the tungsten lower electrode;
an aluminum oxide layer formed on the tungsten oxide layer; and
an aluminum top electrode formed on the aluminum oxide layer.
2. The Al-W-0 stack structure applicable to the resistive random access memory according to claim 1, characterized in that the tungsten oxide layer is formed in a thermal oxidation way.
3. The Al-W-0 stack structure applicable to the resistive random access memory according to claim 1, characterized in that a thickness of the tungsten oxide layer is 30-70nm.
4. The Al-W-0 stack structure applicable to the resistive random access memory according to claim 1, characterized in that the aluminum oxide layer is formed in a contact type oxidation way.
5. The Al-W-0 stack structure applicable to the resistive random access memory according to claim 1, characterized in that a temperature of the contact type oxidation is 400-500°C, and a time of the contact type oxidation is 50-200s.
6. The Al-W-0 stack structure applicable to the resistive random access memory according to claim 1, characterized in that a thickness of the aluminum oxide layer is 3-10nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/758,463 US20160072062A1 (en) | 2013-05-28 | 2014-05-27 | Al-w-o stack structure applicable to resistive random access memory |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013102046217A CN103268917A (en) | 2013-05-28 | 2013-05-28 | Al-W-O piling structure applied to resistive random access memory |
| CN201310204621.7 | 2013-05-28 |
Publications (1)
| Publication Number | Publication Date |
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| WO2014190892A1 true WO2014190892A1 (en) | 2014-12-04 |
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| PCT/CN2014/078496 Ceased WO2014190892A1 (en) | 2013-05-28 | 2014-05-27 | Al-w-o stack structure applicable to resistive random access memory |
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| Country | Link |
|---|---|
| US (1) | US20160072062A1 (en) |
| CN (1) | CN103268917A (en) |
| WO (1) | WO2014190892A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103268917A (en) * | 2013-05-28 | 2013-08-28 | 清华大学 | Al-W-O piling structure applied to resistive random access memory |
| CN103474572A (en) * | 2013-09-28 | 2013-12-25 | 复旦大学 | Flexible-substrate-based resistive random access memory with CRS action and preparation method thereof |
| CN107122828B (en) * | 2017-05-09 | 2020-05-05 | 清华大学 | Circuit structure and driving method thereof, neural network |
| CN108963072A (en) * | 2017-05-27 | 2018-12-07 | 旺宏电子股份有限公司 | Semiconductor structure and forming method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194512A (en) * | 2010-02-09 | 2011-09-21 | 索尼公司 | Memory component, memory device, and method of operating memory device |
| CN102487123A (en) * | 2010-12-06 | 2012-06-06 | 中国科学院微电子研究所 | Nanoscale non-volatile resistive random access memory unit and preparation method thereof |
| US20120295398A1 (en) * | 2011-05-16 | 2012-11-22 | Varian Semiconductor Equipment Associates, Inc. | Ion implant modification of resistive random access memory devices |
| CN103268917A (en) * | 2013-05-28 | 2013-08-28 | 清华大学 | Al-W-O piling structure applied to resistive random access memory |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102347440A (en) * | 2010-08-02 | 2012-02-08 | 复旦大学 | Resistive memory and preparation method thereof |
| CN103682090B (en) * | 2012-09-17 | 2016-12-21 | 复旦大学 | The manufacture method of resistor-type memory and resistor-type memory |
-
2013
- 2013-05-28 CN CN2013102046217A patent/CN103268917A/en active Pending
-
2014
- 2014-05-27 WO PCT/CN2014/078496 patent/WO2014190892A1/en not_active Ceased
- 2014-05-27 US US14/758,463 patent/US20160072062A1/en not_active Abandoned
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102194512A (en) * | 2010-02-09 | 2011-09-21 | 索尼公司 | Memory component, memory device, and method of operating memory device |
| CN102487123A (en) * | 2010-12-06 | 2012-06-06 | 中国科学院微电子研究所 | Nanoscale non-volatile resistive random access memory unit and preparation method thereof |
| US20120295398A1 (en) * | 2011-05-16 | 2012-11-22 | Varian Semiconductor Equipment Associates, Inc. | Ion implant modification of resistive random access memory devices |
| CN103268917A (en) * | 2013-05-28 | 2013-08-28 | 清华大学 | Al-W-O piling structure applied to resistive random access memory |
Also Published As
| Publication number | Publication date |
|---|---|
| US20160072062A1 (en) | 2016-03-10 |
| CN103268917A (en) | 2013-08-28 |
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