WO2014175963A1 - Photolithographic, thickness non-uniformity, compensation features for optical photolithographic semiconductor structure formation - Google Patents

Photolithographic, thickness non-uniformity, compensation features for optical photolithographic semiconductor structure formation Download PDF

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Publication number
WO2014175963A1
WO2014175963A1 PCT/US2014/020186 US2014020186W WO2014175963A1 WO 2014175963 A1 WO2014175963 A1 WO 2014175963A1 US 2014020186 W US2014020186 W US 2014020186W WO 2014175963 A1 WO2014175963 A1 WO 2014175963A1
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Prior art keywords
semiconductor region
region
active
active semiconductor
control electrode
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French (fr)
Inventor
Paul J. Duval
Paul M. RYAN
Christopher J. Macdonald
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Raytheon Co
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Raytheon Co
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/61—Formation of materials, e.g. in the shape of layers or pillars of insulating materials using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/0698—Local interconnections

Definitions

  • This disclosure relates generally to optical photolithographic semiconductor structure formation and more particularly to photolithographic, thickness non-u formity, compensation features for optical photolithographic senaconductor structure formation.
  • a gate electrode controls a flow of carriers passing through the active semiconductor region between a source electrode and a drain electrode. More particularly, the active semiconductor region has a pair of source and drain electrodes in ohmic contact with the active semiconductor region and a gate electrode in Schottky contact with the source and drain region.
  • the gate electrode is a control electrode for controlling a flow of carriers through the active semiconductor region between the source and drain electrodes.
  • One technique used to isolate the active devices is to etch away boundary portions of the semiconductor active region down to an insulating layer to thereby leave isolated semiconductor mesas with each active device being formed in a corresponding one of the mesas.
  • Another technique uses ion implantation around the boundary portions of the semiconductor active regions to render ihe boundary regions inactive (i.e,, into a non- semiconductor, insulating region) to isolate the active devices.
  • the region in the active semiconductor region under the gate electrode and through which the carriers flow is sometimes referred to as the gate channel
  • the region of the active semiconductor region i between the source and drain electrodes is sometimes referred to as the source-drain (SD) channel.
  • the length of the gate electrode is the dimension of the gate electrode measured along a direction passing through the source and drain electrodes and is referred to as the gate length.
  • One process used to form, such FET is to first form source and drain contacts in ohmic contact with the surface of the active semiconductor region as shown in (FIG, 1 A) and then cover the entire semiconductor surface including the source (S) and draia (D) contacts, with a dielectric layer, as shown in FIG. 2A.
  • a photoresist layer is deposited over the entire dielectric layer (both hie portion of the dielectric layer on the active semiconductor region and the portion of the dielectric layer adjacent to the semiconductor active region, as shown in FIGS. IB- ID and 28.
  • the elevation of the tops of the scarce and drain contacts above the surface of the substrate creates topography height variations in the photoresist layer (i.e., the above-described "pools") at the two ends of semiconductor active regions lying between the two ohmic contact metals used for the source and drain contacts.
  • This topography height variation causes the above-described pooling. ft is noted that this pooling of photoresist layer near the source and drain contacts is also over portions of the active semiconductor region including the region between the source and drain contacts where there the gate channel is to be formed.
  • a binary mask not shown, is placed over the photoresist layer.
  • the masked photoresist layer is exposed to ultraviolet light, and then developed to form a window In the photoresist layer over portions of the dielectric layer disposed over the gate formation region on the active semiconductor region, FIG, 2C.
  • the windowed photoresist layer is exposed to an etchant to remove the exposed dielectric layer and thereby expose the region of the active semiconductor region where the gate electrode is to be contact therewith, FIG. 2D.
  • the gate electrode is to be formed in Schottky contact with the exposed region of the active semiconductor region.
  • portions of the above- described pooling of the photoresist are created on the outer portions of the source and drain contacts and on the region where the gate electrode is to make Schottky contact with the underlying portion of the active semiconductor region (i.e., the source drain (SD) channel). That is, the pooling of photoresist layer near the source and drain contacts is also over portions of the active semiconductor region including the region between the source and drain contacts where there the gate channel is to be formed,
  • This pooling causes the photoresist to be thicker than the desired thickness o the active semiconductor region and. after the photoresist is developed, results in a failure of that portio of the gate electrode to make contact with the underlying portion of the active semiconductor region, but rather terminates on the silicon nitride dielectric layer as shown in FIGS. 2 and 2E, The failure to make contact with the underlying portion of the acti ve semiconductor region results in a. "pinched characteristic 5 ; die gate fails to make Schottky contact with the active semiconductor region.
  • T is has been addressed in the e-beam process by adding a patch feature to allow additional exposure in this region; however when less expensive optical lithography is used to pattern the photoresist layer, a patch feature requires either an additional mask and exposure step using a sub resolution patch feature, or a patch made by increasing the size of the gate in the region where the resist is thicker so that additional exposure energy can be transferred to this region.
  • an increase in the exposure dose of the ultraviolet light would be required to clear the pooling region in photoresist layer near the edge of the SD channel and thereby prevent "pinched gates".
  • CD critical dimension
  • a semiconductor structure having: a substrate having an inactive region and an adjacent active semiconductor region; an active device formed in the active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region, between a pair of electrical contacts on the surface of the substrate; and a photolithographic., thickness non-uniformity, compensation feature, on the inactive • region.
  • the inventors have recognized that making the pooling occur in regions off the active semiconductor region ⁇ i.e., on the inactive region) removes the requirement of using the increase in the exposure dose of the ultraviolet light on the active semiconductor region where the gate is to be formed.
  • the noil-uniformity, compensation feature shifts the pooling from regions on the active semiconductor region to regions off the active semiconductor region. More particularly, the photoresist layer is deposited with a proper thickness on the non-pad regions of the substrate so that t is proper thickness will be on the portions of the active semiconductor region where the gate electrode will be -formed,
  • the non-uniformity, compensation feature fecludes pads, the pads being at substantially the same elevation as the tops of the electrical contacts, and elevating the photoresist in regions off of the active region (i.e., the elevated regions causing the pooling). This elevated photoresist men. continues over the active
  • the pads are on the inactive region.
  • the feature comprises two pair of pads on opposite sides of the active semiconductor region.
  • the pads in each pair of the pads are disposed along parallel lines displaced from a line passing through the control electrode.
  • the compensation feature comprises a region in the control electrode on the inactive region that is wider than a region of the control electrode on the active semiconductor region and narrower than the contact pad for the control electrode. The width of the region i the control electrode is selected to increase the relative intensity of uliraviolet light transmitted such that the thicker resist in the region of the gate electrode is sufficiently exposed,
  • a method for forming a semiconductor structure, such structure having: a substrate having an active semiconductor region and an adjacent inactive region; an active devi ce formed in the active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through fee active semiconductor region between a pair of electrical contacts.
  • the method includes: forming a. photoresist layer over the pair of contacts prior to formation of the gate elecrode; and providing a photolithographic, thickness non-umformity, compensation feature prior to the forming of the photoresist layer, the feature being disposed on the surface substrate on the inactive region for preventing pooling of the photoresist layer on the active semiconducting region.
  • the feature forming includes forming pads on the inactive region.
  • a semiconductor structure comprising: a substrate; as active device formed in the active semiconductor region of the substrate, fee active device having a control electrode for controlling a flow of carriers through, the active semiconductor regi on between a pair of electrode, the control electrode extending from the active semiconductor region to a contact pad on the inactive region and wherein a portion of the control electrode between, the acti ve semiconductor region and the contact pad is wider than a portion of the control electrode on the active semiconductor region.
  • a semiconductor structure comprising: a substrate; an active device formed in an active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active serni conductor region between a pair of additional electrodes on the active semiconductor
  • control electrode extending f om the active serai conductor region to a region on the substrate off of the active semiconductor region; a pair of pads off of the active semiconductor region and adjacent to the pair of additional electrodes; and wherein the portion of the control electrode off of the active semiconductor region is disposed between the pair of pads.
  • FIG. 1 A is a plan view sketch of a semiconductor FET structure according to the PRIOR ART prior to forming a gate electrode for the FET;
  • FIGS. IB- ID are a cross sectional sketch of the semiconductor FET structure of FIG. 1 A according to the PRIOR ART, such cross section being taken along line 1 B-IB, 1C-1C and I D- I D, respectively in FIG. 1A;
  • FIG. 2 is a plan view sketch of the semiconductor ' FET structure of FIG. 1 A according to the PRIOR ART forming a gate el ctrode for the FET;
  • FIGS, 2A-2E are cross sectional sketches of the semiconductor FET structure of FIG. 2 according to the PRIOR ART at various stages in the fabrication, thereof; the cross section of FIG. 2E being taken along line 2E-2E in FIG. 2;
  • FIG. 3 is a plan view sketch of a semiconductor FET structure according to the disclosure prior to forming a gate electrode for the FET;
  • FIG. 4 is a cross sectional sketch of the semiconductor FET structure of FIG. 3 according to the disclosure after forming photoresist layer over the structure of FIG, 3 for use in subsequently forming a gate electrode for the FET; 6
  • FIG. 5 is a plan view sketch of the senhcondno or FET structure of FIG. 3 according to the disclosure
  • FIGS, 5A-5E are cross sectional sketches of the semiconductor FET structure of FIG. 5 according to the disclosure at various stages in the fabrication thereof; the cross section of FIG. 5E being taken along iirne 5E-5E is FIG. 5;
  • FIGS. 6A-6E are cross sectional sketches of the semiconductor FET structure of FIG. 5 according to the disclosure at various stages in the fabrication thereof the cross section of FIG. 6E being taken along line 6 ⁇ -6 ⁇ in. FIG. 5;
  • FIG. 7 is a plan view of a mask used in the fabrication of the gate electrode for the semiconductor FET structure of FIG. 3 according to the disclosure.
  • FIG. 8 is a plan view sketch of the semiconductor FET structure of FIG. 3 according to an alternative embodiment of the disclosure.
  • FIG. 3 a semiconductor structure 10 Is shown having a.
  • the substrate has an active semiconductor region 16 and an adjacent inactive region 17, As will be described, an active device wit! be formed In an active serr conductor region 16 of the substrate 12, hen? a field effect transistor (FET) having a control electrode, here gate electrode (GATE), to be described, for controlling a flow of carriers through the active semiconductor regio 16 between a pair of electrical contacts,, here source contact S and drain contact D, as shown in FIG. 3, in ohmic contact with the active semiconductor region. 16.
  • FET field effect transistor
  • GATE gate electrode
  • the 3 includes a plurality of photoHthographic, thickness non-uniformity, compensation, features 18, disposed on the surface substrate 12, off of the active semiconductor region 16 (i.e., the inactive region 17),
  • the features 18 are pads formed is this example as extended portions of the source S and drain D contact material; however the extended portions are disposed on non-active portions of the substrate 12 and not on the active semiconductor region 16-
  • the features 18 are on the surface of the substrate 12 sad off of the active semiconductor region 16.
  • the features 1 S comprise two pair of the pads 1 S on opposite sides of the active semiconductor region 1 , as shown.
  • a photoliihographic, thickness non-urriformity, compensation feature 18 is formed prior to the forming of the photoresist layer for preventing forming pooling of the photoresist layer on the active semiconducting region 16.
  • a photoresist layer 22 is deposited over the surface of the formed structure. More particularly, the photoresist layer 22 is deposited with a proper thickness on the non-pad regions of the substrate so that this proper thickness will be on the portions of the active semiconductor region 1 (FIG. 3) where the gate electrode (GATE) will be formed (i.e., on the non-electrical contact regions).
  • the pads 18 being at substantially the same elevation as the tops of the electrical contacts (i.e., the source S and d ain D contacts) and extended beyond the active region 16 cause the photoresist layer 22 to pool in the region off the active region 16 while the photoresist layer 22 over the active region and hi the region between the source and drain contacts is deposited at the optimum thickness for forming the gate electrode. Further, as will be described, shifting of the position of the pooling regions 24 to regions off the semiconductor active regions 16 (i.e., on the inactive region 17) enables the use of gate electrode (GATE) formation
  • a. dielectric layer 40 is deposited, over the surface of the structure, as shown. It is noted that the dielectric layer 40 is disposed over the region 24 in the active semiconductor region 16 (FIG. 3) where the gate electrode (GATE) is to be formed, over the source S and drain (.0) contacts and. also over the pads 18 (FIG. 6 A). It is noted that the pooling 26 of the photoresist layer 22 thickens the photoresist layer 22 over the inactive region 17(off the active semiconductor region 16) whereas the photoresist layer 22 is thinner over the active semiconductor region. 22 (FIG.
  • a window 50 is fonned through the photoresist layer 22 using conventional optical photolithographic-etching processing to expose the underlying portion of the silicon nitride layer that is over the regions where the gate electrode (GATE) is to be formed.
  • a mask 52 not shown in FIGS.. 5C or 6C and shown in FIG. 7, has a rrower opening with length LI when positioned in the region over the active semiconductor region 16 where the gate channel is to be formed than the length L2 over the off active semiconductor region (i.e,, on the inactive region 17) and which leads the gate electrode (GATE) in the gate channel to a contact pad 60, FIG, 8. it is noted that the length 12 is narrower than the length L3 of the gate contact pad 60, FIG. 8.
  • the portions of the dielectric layer 40 are etched to expose underlying portions of the active semiconductor region 16, as shown in FIG. SD and underlying portions, as shown in FIG. 6D.
  • die gate electrode (GATE) Is fonned on the exposed potations of the active semico ductor region 17, as shows in FIG. 5E and underlying portions of the inactive region 17 as shown h FIG. 6E which leads the gate electrode (GATE) in the gate channel to a contact pad 60, FIG. 8.
  • the pads 18 in each pair of the pads 18 are disposed along parallel lines displaced from a line passing through the gate electrode (GATE) portion on the active semiconductor region 16.
  • the gate electrode extends from the active semiconductor regio 16 to a region on the substrate off of the active semiconductor region 16 between each one the two pair of pads 18.
  • a semiconductor structure includes a substrate having an. Inactive region and an adjacent active semiconductor region; an active device formed hi the active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers th ough the active semiconductor region between a pair of electrical contacts; and a photolithographic, thickness non-umformity, compensation feature, disposed on the surface substrate on the 20186 inactive region.
  • One or more of the following elements may comprise independently or in combination with another element including wherein the feature comprises pads on the surface of the substrate and on the inactive region; wherein the feature comprises two pair of pads on opposite sides of th e active semiconductor region; wherein the pads in each pair of the pads are disposed along parallel lines displaced fr m a line passing through the control electrode; wherein the compensation feature comprises a region in the control electrode on the inacti ve region wider than, a region of the control electrode on. the active semiconductor region and narrower than the contact pad for the control electrode; and wherein the pads are exten sions of the pair of electrical conductors.
  • a method for forming a semiconductor structure includes, such structure having: a substrate; an active device formed is an active semiconductor region of the substrate, the active device having a controi electrode for controlling a flow of carriers through fhe active semiconductor region between, a pair of electrical contacts, the method comprising: forming a photoresist layer over the pair of contacts prior to formation of the gate electrode; and providing a photolithographic, thickness ncm-xixriformity, compensation feature prior to the forming of the photoresist layer, the feature being disposed on the surface substrate off of the active semiconductor region for preventing pooling of the photoresist layer on the active sernieondueting region.
  • the feature forming may include forming pads on. the surface of the substrate and off of the active semiconductor region.
  • a semiconductor structure includes a substrate; an active device formed in an. active semiconductor region of fhe substrate, the active device having a control electrode for controlling a flow of carriers through fhe active semiconductor region, the control electrode extending from, fhe active semiconductor region, to a contact pad on the substrate off of the active
  • control electrode between the active semiconductor region and the contact pad is wider than a portio of the control electrode on the active semiconductor region
  • a semiconductor structure includes a substrate; an active device formed in an active semiconductor region T/US2014/020186 of the substrate, the active device having a control electrode for controlling a flow of carriers through t e active semiconductor region between a pair of additi onal electrodes on the active semiconductor region, the control electrode extending from the active semiconductor region to a regi on on the substrate off of the active semiconductor region; a pair of pads off of the active semiconductor region and adjacent to the pair of additional electrodes; and wherein the portion of the control electrode off of the active semiconductor region is disposed between the pair of pads.
  • a region of the control electrode off of the acti ve semiconductor region can be wider than a. region of the control electrode on the active semiconductor region.
  • a semiconductor structure may also include a substrate; an active device formed in an active semiconductor region, the active device having a control electrode for controlling a flow of carriers through the active
  • the control electrode may extend f m the active semiconductor region to a region on the substrate off of the acti e semicond uctor region; and wherein the control electrode off of the active semiconductor region is disposed between one of the two pair of pads.
  • a semiconductor structure includes a substrate; an active device formed in an active semiconductor region of the substrate, the active device having a con rol electrode for controlling a flow of carriers through the active semiconductor region, the control electrode extending f om, a region on the active semiconductor region to a region on the substrate off of the active semiconductor region, the control electxode terminating in a contact pad on the substrate off of the acti ve semiconductor region; and wherein a region in the control electrode off of the active semiconductor region wider than a. region of the control electrode on active semiconductor region and narrower than the contact pad for the control electrode.
  • One or more of the following elements may comprise independently or in combination with another element including a pair of additional electrodes on the active semiconductor region and wherein the control electrode controls the flow of carriers between the pair of additional electrode, and two pair of pads the subs trate off of the active semiconductor region and. adjacent to the pair of additional electrodes; wherein the pair of additional electrodes extend along parallel lines; wherein each pair of the two pair of pad s is disposed rectifg a corresponding one of the parallel lines; wherein the control electrode extends from the active semiconductor region to a region on the substrate off of the active
  • control electrode off of the active semicond uctor region is disposed between the pair of pads; wherein the control electrode is disposed along a line parallel to the aforementioned parallel lines and extends, at each opposing end of the control electrode, from the active semiconductor region to regions on the substrate off of the active sem conductor region; and wherein each opposing end of the control electrode is disposed between a corresponding one of the pair of pads.
  • pads 18' may be separate f om the source and drain contacts;, as shown in FIG. 9. Accordingly, other embodiments are within the scope of the following claims.

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  • Junction Field-Effect Transistors (AREA)

Abstract

A semiconductor structure having a substrate; an active device formed in an active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region between a pair of electrical contacts; and a photolithographic, thickness non-uniformity, compensation feature, disposed on the surface substrate off of the active semiconductor region. In one embodiment the feature comprises pads on the surface of the substrate and off of the active semiconductor region.

Description

PHOTOLITHOGRAPHIC, THICKNESS NOM"IJMF0MMIT¾ COMPENSATION FEATIJSES FOR OPTICAL PHOTOLITHOGRAPHIC SEMICONDUCTOR STRUCTURE
FORMATION
TECHNICAL FIELD
[0001] This disclosure relates generally to optical photolithographic semiconductor structure formation and more particularly to photolithographic, thickness non-u formity, compensation features for optical photolithographic senaconductor structure formation. BACKGROUND AND SUMMARY
[0002] As is known in the art, photolithography is used extensively in the fabrication of a wide variety of semiconductor structures. One type of semiconductor structure has active devices, such as field effect transistors (FETs), formed in active semiconductor regions (sometimes referred to as the active regions) of a substrate. More particularly, a plurality of active semiconductor devices is formed in a semiconductor region, typically a semiconductor epitaxial layer, formed over the substrate, A gate electrode controls a flow of carriers passing through the active semiconductor region between a source electrode and a drain electrode. More particularly, the active semiconductor region has a pair of source and drain electrodes in ohmic contact with the active semiconductor region and a gate electrode in Schottky contact with the source and drain region. The gate electrode is a control electrode for controlling a flow of carriers through the active semiconductor region between the source and drain electrodes.
[0003] One technique used to isolate the active devices is to etch away boundary portions of the semiconductor active region down to an insulating layer to thereby leave isolated semiconductor mesas with each active device being formed in a corresponding one of the mesas. Another technique uses ion implantation around the boundary portions of the semiconductor active regions to render ihe boundary regions inactive (i.e,, into a non- semiconductor, insulating region) to isolate the active devices. The region in the active semiconductor region under the gate electrode and through which the carriers flow is sometimes referred to as the gate channel The region of the active semiconductor region i between the source and drain electrodes is sometimes referred to as the source-drain (SD) channel. The length of the gate electrode is the dimension of the gate electrode measured along a direction passing through the source and drain electrodes and is referred to as the gate length.
[0004] One process used to form, such FET is to first form source and drain contacts in ohmic contact with the surface of the active semiconductor region as shown in (FIG, 1 A) and then cover the entire semiconductor surface including the source (S) and draia (D) contacts, with a dielectric layer, as shown in FIG. 2A. Next, a photoresist layer is deposited over the entire dielectric layer (both hie portion of the dielectric layer on the active semiconductor region and the portion of the dielectric layer adjacent to the semiconductor active region, as shown in FIGS. IB- ID and 28. More particularly, the elevation of the tops of the scarce and drain contacts above the surface of the substrate creates topography height variations in the photoresist layer (i.e., the above-described "pools") at the two ends of semiconductor active regions lying between the two ohmic contact metals used for the source and drain contacts. This topography height variation causes the above-described pooling. ft is noted that this pooling of photoresist layer near the source and drain contacts is also over portions of the active semiconductor region including the region between the source and drain contacts where there the gate channel is to be formed.
[0005] Alter the photoresist layer deposition, a binary mask, not shown, is placed over the photoresist layer. Next, the masked photoresist layer is exposed to ultraviolet light, and then developed to form a window In the photoresist layer over portions of the dielectric layer disposed over the gate formation region on the active semiconductor region, FIG, 2C. Next, the windowed photoresist layer is exposed to an etchant to remove the exposed dielectric layer and thereby expose the region of the active semiconductor region where the gate electrode is to be contact therewith, FIG. 2D. Next, the gate electrode is to be formed in Schottky contact with the exposed region of the active semiconductor region. Unfortunately, because of the change in the surface topology over which the photoresist layer is deposited, for example over the source and drain contacts, portions of the above- described pooling of the photoresist are created on the outer portions of the source and drain contacts and on the region where the gate electrode is to make Schottky contact with the underlying portion of the active semiconductor region (i.e., the source drain (SD) channel). That is, the pooling of photoresist layer near the source and drain contacts is also over portions of the active semiconductor region including the region between the source and drain contacts where there the gate channel is to be formed,
[0006] This pooling causes the photoresist to be thicker than the desired thickness o the active semiconductor region and. after the photoresist is developed, results in a failure of that portio of the gate electrode to make contact with the underlying portion of the active semiconductor region, but rather terminates on the silicon nitride dielectric layer as shown in FIGS. 2 and 2E, The failure to make contact with the underlying portion of the acti ve semiconductor region results in a. "pinched characteristic5; die gate fails to make Schottky contact with the active semiconductor region.
[0007] T is has been addressed in the e-beam process by adding a patch feature to allow additional exposure in this region; however when less expensive optical lithography is used to pattern the photoresist layer, a patch feature requires either an additional mask and exposure step using a sub resolution patch feature, or a patch made by increasing the size of the gate in the region where the resist is thicker so that additional exposure energy can be transferred to this region. When using optical lithography without one of these patch, features, an increase in the exposure dose of the ultraviolet light would be required to clear the pooling region in photoresist layer near the edge of the SD channel and thereby prevent "pinched gates". This would however result in an increase in gate channel length in the region of the active semiconductor region where there is this increased exposure and thus would limit the minimum critical dimension (CD) (he., the gate channel length) that can. be achieved with a binary mask and this increase of the gate channel length In the active region of the device can cause poor electrical performance.
[0008] In accordance with the present disclosure, a semiconductor structure is provided having: a substrate having an inactive region and an adjacent active semiconductor region; an active device formed in the active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region, between a pair of electrical contacts on the surface of the substrate; and a photolithographic., thickness non-uniformity, compensation feature, on the inactive • region.
[0009] The inventors have recognized that making the pooling occur in regions off the active semiconductor region {i.e., on the inactive region) removes the requirement of using the increase in the exposure dose of the ultraviolet light on the active semiconductor region where the gate is to be formed. The noil-uniformity, compensation feature shifts the pooling from regions on the active semiconductor region to regions off the active semiconductor region. More particularly, the photoresist layer is deposited with a proper thickness on the non-pad regions of the substrate so that t is proper thickness will be on the portions of the active semiconductor region where the gate electrode will be -formed,
[0010] In one embodiment, the non-uniformity, compensation feature fecludes pads, the pads being at substantially the same elevation as the tops of the electrical contacts, and elevating the photoresist in regions off of the active region (i.e., the elevated regions causing the pooling). This elevated photoresist men. continues over the active
semiconductor region at substantially the same elevation as the tops of the electrical contacts while being at the proper elevation over the active semiconductor region where the gate electrode is to be formed (i.e., the non-electrical contact regions). Further such shifting of the position of the pooling to regions off the semiconductor active regions enables the use of gate formation compensation such as enlarging the gate opening in fee gate mask to allow more energy to he delivered to the region of thicker resist with, any increase in gate length resulting from, this larger section occurring in a region which does not impact device performance (i.e., off of the active semiconductor region).
[0011] in one embodiment, the pads are on the inactive region..
[0012] in one embodiment, the feature comprises two pair of pads on opposite sides of the active semiconductor region.
[0013] ha one embodiment, the pads in each pair of the pads are disposed along parallel lines displaced from a line passing through the control electrode. [0014] ¾ one embodiment, the compensation feature comprises a region in the control electrode on the inactive region that is wider than a region of the control electrode on the active semiconductor region and narrower than the contact pad for the control electrode. The width of the region i the control electrode is selected to increase the relative intensity of uliraviolet light transmitted such that the thicker resist in the region of the gate electrode is sufficiently exposed,
[0015] In one embodiment, a method is provided for forming a semiconductor structure, such structure having: a substrate having an active semiconductor region and an adjacent inactive region; an active devi ce formed in the active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through fee active semiconductor region between a pair of electrical contacts. The method includes: forming a. photoresist layer over the pair of contacts prior to formation of the gate elecrode; and providing a photolithographic, thickness non-umformity, compensation feature prior to the forming of the photoresist layer, the feature being disposed on the surface substrate on the inactive region for preventing pooling of the photoresist layer on the active semiconducting region.
[0016] In one embodiment, the feature forming includes forming pads on the inactive region.
[0017] In one embodiment, a semiconductor structure is provided comprising: a substrate; as active device formed in the active semiconductor region of the substrate, fee active device having a control electrode for controlling a flow of carriers through, the active semiconductor regi on between a pair of electrode, the control electrode extending from the active semiconductor region to a contact pad on the inactive region and wherein a portion of the control electrode between, the acti ve semiconductor region and the contact pad is wider than a portion of the control electrode on the active semiconductor region.
[0018] in one embodiment, a semiconductor structure is provided, comprising: a substrate; an active device formed in an active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active serni conductor region between a pair of additional electrodes on the active semiconductor
s region, the control electrode extending f om the active serai conductor region to a region on the substrate off of the active semiconductor region; a pair of pads off of the active semiconductor region and adjacent to the pair of additional electrodes; and wherein the portion of the control electrode off of the active semiconductor region is disposed between the pair of pads.
[0019] The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, ami advantages of the disclosure will be apparent from the description and drawings, and from the claims.
DESCRIPTION OF DRAWINGS
[0020] FIG. 1 A is a plan view sketch of a semiconductor FET structure according to the PRIOR ART prior to forming a gate electrode for the FET; [0021] FIGS. IB- ID are a cross sectional sketch of the semiconductor FET structure of FIG. 1 A according to the PRIOR ART, such cross section being taken along line 1 B-IB, 1C-1C and I D- I D, respectively in FIG. 1A;
[0022] FIG. 2 is a plan view sketch of the semiconductor 'FET structure of FIG. 1 A according to the PRIOR ART forming a gate el ctrode for the FET;
[0023] FIGS, 2A-2E are cross sectional sketches of the semiconductor FET structure of FIG. 2 according to the PRIOR ART at various stages in the fabrication, thereof; the cross section of FIG. 2E being taken along line 2E-2E in FIG. 2;
[0024] FIG. 3 is a plan view sketch of a semiconductor FET structure according to the disclosure prior to forming a gate electrode for the FET;
[0025] FIG. 4 is a cross sectional sketch of the semiconductor FET structure of FIG. 3 according to the disclosure after forming photoresist layer over the structure of FIG, 3 for use in subsequently forming a gate electrode for the FET; 6
[0026] FIG. 5 is a plan view sketch of the senhcondno or FET structure of FIG. 3 according to the disclosure;
[0027] FIGS, 5A-5E are cross sectional sketches of the semiconductor FET structure of FIG. 5 according to the disclosure at various stages in the fabrication thereof; the cross section of FIG. 5E being taken along iirne 5E-5E is FIG. 5;
[0028] FIGS. 6A-6E are cross sectional sketches of the semiconductor FET structure of FIG. 5 according to the disclosure at various stages in the fabrication thereof the cross section of FIG. 6E being taken along line 6Έ-6Ε in. FIG. 5;
[0029] FIG. 7 is a plan view of a mask used in the fabrication of the gate electrode for the semiconductor FET structure of FIG. 3 according to the disclosure;
[0030] FIG. 8 is a plan view sketch of the semiconductor FET structure of FIG. 3 according to an alternative embodiment of the disclosure.
[0031 ] Like reference symbols in the various drawings Indicate like elements.
DETAILED DESCRIPTION
[0032] Referring now to FIG. 3, a semiconductor structure 10 Is shown having a.
semiconductor substrate 12. The substrate has an active semiconductor region 16 and an adjacent inactive region 17, As will be described, an active device wit! be formed In an active serr conductor region 16 of the substrate 12, hen? a field effect transistor (FET) having a control electrode, here gate electrode (GATE), to be described, for controlling a flow of carriers through the active semiconductor regio 16 between a pair of electrical contacts,, here source contact S and drain contact D, as shown in FIG. 3, in ohmic contact with the active semiconductor region. 16. The structure shown in FIG. 3 includes a plurality of photoHthographic, thickness non-uniformity, compensation, features 18, disposed on the surface substrate 12, off of the active semiconductor region 16 (i.e., the inactive region 17), Here the features 18 are pads formed is this example as extended portions of the source S and drain D contact material; however the extended portions are disposed on non-active portions of the substrate 12 and not on the active semiconductor region 16- Thus, the features 18 are on the surface of the substrate 12 sad off of the active semiconductor region 16. Here, the features 1 S comprise two pair of the pads 1 S on opposite sides of the active semiconductor region 1 , as shown. As will be described, a photoliihographic, thickness non-urriformity, compensation feature 18 is formed prior to the forming of the photoresist layer for preventing forming pooling of the photoresist layer on the active semiconducting region 16.
[0033] Mote particularly, after forming the source S and drain D contacts and the features 18, and referring also to FIG. 4, a photoresist layer 22 is deposited over the surface of the formed structure. More particularly, the photoresist layer 22 is deposited with a proper thickness on the non-pad regions of the substrate so that this proper thickness will be on the portions of the active semiconductor region 1 (FIG. 3) where the gate electrode (GATE) will be formed (i.e., on the non-electrical contact regions). The pads 18 being at substantially the same elevation as the tops of the electrical contacts (i.e., the source S and d ain D contacts) and extended beyond the active region 16 cause the photoresist layer 22 to pool in the region off the active region 16 while the photoresist layer 22 over the active region and hi the region between the source and drain contacts is deposited at the optimum thickness for forming the gate electrode. Further, as will be described, shifting of the position of the pooling regions 24 to regions off the semiconductor active regions 16 (i.e., on the inactive region 17) enables the use of gate electrode (GATE) formation
compensation with any increase in gate length occurring in a region (i.e., off of the acti ve semiconductor region 16) which does not impact device performance.
[0034] More particularly, and referring now to FIGS. 5A and 6A, after forming the source and drain contacts in. ohmic contact with the active semiconductor region 16, a. dielectric layer 40 is deposited, over the surface of the structure, as shown. It is noted that the dielectric layer 40 is disposed over the region 24 in the active semiconductor region 16 (FIG. 3) where the gate electrode (GATE) is to be formed, over the source S and drain (.0) contacts and. also over the pads 18 (FIG. 6 A). It is noted that the pooling 26 of the photoresist layer 22 thickens the photoresist layer 22 over the inactive region 17(off the active semiconductor region 16) whereas the photoresist layer 22 is thinner over the active semiconductor region. 22 (FIG. 4). [0035] Refemng now to FIGS. 5C and 6C, a window 50 is fonned through the photoresist layer 22 using conventional optical photolithographic-etching processing to expose the underlying portion of the silicon nitride layer that is over the regions where the gate electrode (GATE) is to be formed. It is noted that a mask 52, not shown in FIGS.. 5C or 6C and shown in FIG. 7, has a rrower opening with length LI when positioned in the region over the active semiconductor region 16 where the gate channel is to be formed than the length L2 over the off active semiconductor region (i.e,, on the inactive region 17) and which leads the gate electrode (GATE) in the gate channel to a contact pad 60, FIG, 8. it is noted that the length 12 is narrower than the length L3 of the gate contact pad 60, FIG. 8.
[0036] Refemng now to FIG. SD and 6D, the portions of the dielectric layer 40 are etched to expose underlying portions of the active semiconductor region 16, as shown in FIG. SD and underlying portions, as shown in FIG. 6D.
[0037] Next, after rem ving the photoresist layer 22, die gate electrode (GATE) Is fonned on the exposed potations of the active semico ductor region 17, as shows in FIG. 5E and underlying portions of the inactive region 17 as shown h FIG. 6E which leads the gate electrode (GATE) in the gate channel to a contact pad 60, FIG. 8.
[0038] Several observations shown are noted. First, referring to FIG. 8, the pads 18 in each pair of the pads 18 are disposed along parallel lines displaced from a line passing through the gate electrode (GATE) portion on the active semiconductor region 16. Next, the gate electrode extends from the active semiconductor regio 16 to a region on the substrate off of the active semiconductor region 16 between each one the two pair of pads 18.
[0039] it should now be appreciated a semiconductor structure according to the disclosure includes a substrate having an. Inactive region and an adjacent active semiconductor region; an active device formed hi the active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers th ough the active semiconductor region between a pair of electrical contacts; and a photolithographic, thickness non-umformity, compensation feature, disposed on the surface substrate on the 20186 inactive region. One or more of the following elements may comprise independently or in combination with another element including wherein the feature comprises pads on the surface of the substrate and on the inactive region; wherein the feature comprises two pair of pads on opposite sides of th e active semiconductor region; wherein the pads in each pair of the pads are disposed along parallel lines displaced fr m a line passing through the control electrode; wherein the compensation feature comprises a region in the control electrode on the inacti ve region wider than, a region of the control electrode on. the active semiconductor region and narrower than the contact pad for the control electrode; and wherein the pads are exten sions of the pair of electrical conductors.
[0040] it should now be appreciated a method for forming a semiconductor structure according to the disclosure includes, such structure having: a substrate; an active device formed is an active semiconductor region of the substrate, the active device having a controi electrode for controlling a flow of carriers through fhe active semiconductor region between, a pair of electrical contacts, the method comprising: forming a photoresist layer over the pair of contacts prior to formation of the gate electrode; and providing a photolithographic, thickness ncm-xixriformity, compensation feature prior to the forming of the photoresist layer, the feature being disposed on the surface substrate off of the active semiconductor region for preventing pooling of the photoresist layer on the active sernieondueting region. Furthermore, the feature forming may include forming pads on. the surface of the substrate and off of the active semiconductor region.
[0041] It should now also be appreciated a semiconductor structure according to the disclosure includes a substrate; an active device formed in an. active semiconductor region of fhe substrate, the active device having a control electrode for controlling a flow of carriers through fhe active semiconductor region, the control electrode extending from, fhe active semiconductor region, to a contact pad on the substrate off of the active
semiconductor region and wherein a portion, of the control electrode between the active semiconductor region and the contact pad is wider than a portio of the control electrode on the active semiconductor region,
[0042] It should now also he appreciated a semiconductor structure according to the disclosure includes a substrate; an active device formed in an active semiconductor region T/US2014/020186 of the substrate, the active device having a control electrode for controlling a flow of carriers through t e active semiconductor region between a pair of additi onal electrodes on the active semiconductor region, the control electrode extending from the active semiconductor region to a regi on on the substrate off of the active semiconductor region; a pair of pads off of the active semiconductor region and adjacent to the pair of additional electrodes; and wherein the portion of the control electrode off of the active semiconductor region is disposed between the pair of pads. Furthermore a region of the control electrode off of the acti ve semiconductor region can be wider than a. region of the control electrode on the active semiconductor region. A semiconductor structure may also include a substrate; an active device formed in an active semiconductor region, the active device having a control electrode for controlling a flow of carriers through the active
semiconductor region between, a pair of electrical contacts on the active semiconductor region, wherein the pair of electrical contacts extend along parallel lines: and two pair of pads off of the active semiconductor region, each pair of the two pair of pads being disposed along a corresponding one of the parallel lines. The control electrode may extend f m the active semiconductor region to a region on the substrate off of the acti e semicond uctor region; and wherein the control electrode off of the active semiconductor region is disposed between one of the two pair of pads.
[0043] It should now also be appreciated a semiconductor structure according to the disclosure includes a substrate; an active device formed in an active semiconductor region of the substrate, the active device having a con rol electrode for controlling a flow of carriers through the active semiconductor region, the control electrode extending f om, a region on the active semiconductor region to a region on the substrate off of the active semiconductor region, the control electxode terminating in a contact pad on the substrate off of the acti ve semiconductor region; and wherein a region in the control electrode off of the active semiconductor region wider than a. region of the control electrode on active semiconductor region and narrower than the contact pad for the control electrode. One or more of the following elements may comprise independently or in combination with another element including a pair of additional electrodes on the active semiconductor region and wherein the control electrode controls the flow of carriers between the pair of additional electrode, and two pair of pads the subs trate off of the active semiconductor region and. adjacent to the pair of additional electrodes; wherein the pair of additional electrodes extend along parallel lines; wherein each pair of the two pair of pad s is disposed alorsg a corresponding one of the parallel lines; wherein the control electrode extends from the active semiconductor region to a region on the substrate off of the active
semiconductor region; and wherein the control electrode off of the active semicond uctor region is disposed between the pair of pads; wherein the control electrode is disposed along a line parallel to the aforementioned parallel lines and extends, at each opposing end of the control electrode, from the active semiconductor region to regions on the substrate off of the active sem conductor region; and wherein each opposing end of the control electrode is disposed between a corresponding one of the pair of pads.
[0044] A number of embodiments of the disclosure have been described. Nevertheless, It will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, the pads 18' may be separate f om the source and drain contacts;, as shown in FIG. 9. Accordingly, other embodiments are within the scope of the following claims.

Claims

WHAT IS CLAIMED IS:
1. A semiconductor structure, comprising:
a substrate having an inactive region and an adjacent active semiconductor region; an active device formed in the active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region between a pair of electrical contacts; and
a photolithographic, thickness non-uniformity, compensation feature, disposed on the surface substrate on the inactive region.
2. The semiconductor structure recited in claim 1 wherein the feature comprises pads on fee surface of the substrate and on the inactive region,
3. The semiconductor structure recited in claim 1 wherein the feature comprises two pair of pads on opposite sides of the active semiconductor region.
4. The semiconductor structure recited in claim 3 wherein the pads in each pair of the pads are disposed along parallel lines displaced from a line passing through, the control electrode,
5. The semiconductor structure recited in claim 1 wherein the compensation feature comprises a region in the control electrode on the inactive region wider than a region of the control electrode on the active semiconductor region and narrower than the contact pad for the control electrode.
6. A method for forming a semiconductor structure, such structure having: a substrate; an active device formed in an active semiconductor region of the substrate, the active device having a control, electrode for controlling a flow of carriers through the active
semiconductor region between a pair of electrical contacts, fee method compr sing;
forming a photoresist layer over the pair of contacts prior to formation of the gate electrode; and
providing a photolithographic, thickness son-unifbrniity, compensation feature prior to the forming of the photoresist layer, the feature being disposed on the surface substrate off of the active semiconductor region for preventing pooling of the photoresist layer on the active semiconducting region.
?. "Ore method recited in claim 6 wherein the feature forming includes forming pads on the surface of the substrate and off of the active semiconductor region.
8. A semiconductor structure, comprising:
a substrate;
an active device formed in a active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region, the control electrode extending from the active
semiconductor region to a contact pad on the substrate off of the active semiconductor region and wherein a portion of the control electrode between the active semiconductor region and the contact pad is wider than a portion of the control electrode on the active semiconductor region.
9. A semiconductor structure, comprising:
a substrate;
an active device formed in an active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region between a pair of additional electrodes on the active semiconductor region, the control electrode extending from the active semiconductor region to a region on the substrate off of the active semiconductor region;
a pair of pads off of the active semiconductor region and adjacent to the pair of additional electrodes; and
wherein the portion of the control electrode off of the active semiconductor region is disposed between the pair of pads,
1.0. The semiconductor structure recited, in claim 9 wherein a region of the control electrode off of the active semiconductor region is wider than a region of the control electrode on the active semiconductor region.
1 L A. semiconductor structure, comprising: a substrate;
an active device formed in an active semiconductor region, the active device having a control electrode for controlling a flow of carriers through the active
semiconductor region between a. pair of electrical contacts on the active semiconductor region, wherein the pair of electrical contacts extend along parallel lines; and
two pair of pads off of the active semicond uctor region, each pair of the two pair of pads being disposed along a corresponding one of the parallel lines,
12. The semiconductor structure recited in claim 11, wherein fee control electrode extends fr m the active semiconductor region to a region on the substrate off of the active semiconductor region; and wherein the control electrode off of the active semiconductor region, is disposed between one of the two pair of pads.
13. A semiconductor structure, comprising:
a substrate;
an active device formed in an active semicond uctor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region, the control electrode extending from a region on the active semiconductor region to a region on the substrate off of the active semiconductor region, the control electrode terminating in a contact pad on the substrate off of the active
semiconductor region; and
wherein a region in the control electrode off of the active semiconductor region wider than a region of the control electrode on active semiconductor region and narrower than the contact pad for the control electrode.
14. The semiconductor structure recited in claim 1.3 including:
a pair of additional electrodes on the active semiconductor region and wherein the control electrode controls the flow of carriers between, the pair of additional electrode., and two pair of pads the substrate off of the active semiconductor region and adjacent to the pair of additional electrodes;
wherein the pair of additional electrodes extend along parallel lines;
wherein each pair of the two pair of pads is disposed along a corresponding one of the parallel lines. is. T e semiconductor structure recited in claim 14, herein the control electrode extends from the active semiconductor region to a region on the suhstrate off of the active semiconductor region; and wherein the control electrode off of the active semiconductor region is d isposed between the pair of ds.
16. The semiconductor structure recited in claim 14 wherein the control electrode is disposed along a line parallel to the aforementioned parallel lines and extends, at each opposing end of the control electrode, from the active semiconductor region to r gions on the substrate off of the active semiconductor region; ami wherein each opposing end of the control electrode is disposed, between a corresponding one of the pair of pads,
17. The semiconductor structure recited in claim 2 wherein the pads are extensions of the pair of electrical conductors.
18. The semiconductor structure recited in claim 3 wherein the pads are extensions of the electrical conductors.
PCT/US2014/020186 2013-04-26 2014-03-04 Photolithographic, thickness non-uniformity, compensation features for optical photolithographic semiconductor structure formation Ceased WO2014175963A1 (en)

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