WO2014166547A1 - Electronic device and method for producing an electronic device - Google Patents

Electronic device and method for producing an electronic device Download PDF

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Publication number
WO2014166547A1
WO2014166547A1 PCT/EP2013/057698 EP2013057698W WO2014166547A1 WO 2014166547 A1 WO2014166547 A1 WO 2014166547A1 EP 2013057698 W EP2013057698 W EP 2013057698W WO 2014166547 A1 WO2014166547 A1 WO 2014166547A1
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WO
WIPO (PCT)
Prior art keywords
bond
electronic device
pad
semiconductor chip
bond pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/EP2013/057698
Other languages
French (fr)
Inventor
Vinod Panicker VISVANATHAN
Sathappan SHANMUGAM CHETTIAR
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ams Osram International GmbH
Original Assignee
Osram Opto Semiconductors GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osram Opto Semiconductors GmbH filed Critical Osram Opto Semiconductors GmbH
Priority to PCT/EP2013/057698 priority Critical patent/WO2014166547A1/en
Publication of WO2014166547A1 publication Critical patent/WO2014166547A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/85—Packages
    • H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07336—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07521—Aligning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5434—Dispositions of bond wires the connected ends being on auxiliary connecting means on bond pads, e.g. on other bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/581—Auxiliary members, e.g. flow barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/752—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention relates to an electronic device accord ⁇ ing to claim 1 and to a method for producing an electronic device according to claim 11.
  • the ball stitch on ball bonding sequence comprises a first step of forming a stud ball bump on a bond pad. In a second step the contact pad is reversely bonded to the bond pad by ball bond ⁇ ing onto the contact pad and stitch bonding onto the ball bump arranged on the bond pad. It is necessary to prevent an electric short between a bond wire and a surface of a semiconductor chip.
  • An electronic device comprises a semiconductor chip with a surface.
  • a bond pad is arranged on said surface.
  • a layer of electrically insulating material is arranged on said surface in a section of said surface. The section is arranged between said bond pad and an edge of said surface.
  • a bond wire is ar ⁇ ranged between said bond pad and a contact pad.
  • Advanta ⁇ geously, the layer of electrically insulating material of this electronic device prevents an electric short between the bond wire and the surface of the semiconductor chip. This al ⁇ lows for arranging the bond wire in a low loop above the sur ⁇ face of the semiconductor chip. Advantageously, this allows for providing the bond wire with a short length, allowing for arranging more interconnections per unit area.
  • signal wires and ground wires may be brought very closely to ⁇ gether in order to minimize inductances.
  • a short bond wire may also prevent the bond wire from swaying or sagging. Ad ⁇ vantageously, this also prevents neighbouring bond wires from shorting .
  • the electronic device comprises a board.
  • the chip is arranged on said board.
  • the contact pad is also ar ⁇ ranged on said board.
  • the bond wire provides an electrical connection between the semiconductor chip and the board of the electronic device.
  • the contact pad is arranged on a second semiconductor chip.
  • the bond wire serves to connect the two semiconductor chips di- rectly to each other, allowing for a high bandwidth connection.
  • the direct connection between the semi ⁇ conductor chips may eliminate layers of chip level wiring, substrate level wiring and board level wiring and allow for a routing with higher flexibility.
  • said layer of electrically insulating material comprises a resist. Advanta ⁇ geously, this allows for an easy and cost-efficient arrange ⁇ ment of the layer of electrically insulating material on the surface of the semiconductor chip.
  • said layer of in ⁇ sulating material comprises a thickness of less than 1 pm.
  • a layer with such a thickness provides a suf ⁇ ficient electrical insulation.
  • a thickness of said layer of insulating material is smaller or equal to a thickness of said bond pad.
  • this allows for the bond wire to run from the bond pad to the contact pad in a low-profile loop.
  • a thickness of said layer of insulating material differs from a thickness of said bond pad by less than 20 %.
  • this ensures that the layer of insulating material prevents an electric short between the bond wire and the surface of the semicon ⁇ ductor chip.
  • the bond wire ex ⁇ tends less than 100 pm above said bond pad.
  • the bond wire com ⁇ prises gold.
  • bond wires comprising gold pro- vide good mechanical and electrical properties.
  • the semiconductor chip is an optoelectronic semiconductor chip.
  • the electronic device is an optoelectronic device.
  • the optoelectronic semiconductor chip may for example be a light emitting diode chip, a semiconductor laser chip or a chip comprising a photovoltaic solar cell.
  • a method for producing an electronic device comprises steps of providing a semiconductor chip comprising a surface, wherein a bond pad is arranged on said surface, of arranging a layer of electrically insulating material on said surface in a section of said surface, wherein the section is arranged between said bond pad and an edge of said surface, and of ar ⁇ ranging a bond wire between said bond pad and a contact pad.
  • this method allows for producing an elec ⁇ tronic device with a low height profile.
  • the bond wire of the electronic device is advantageously secured against shorting to the surface of the semiconductor chip by the layer of electrically insulating material arranged on the surface of the semiconductor chip. This may decrease a yield loss due to wire shorts.
  • the method allows for using very short bond wires which enables providing more interconnections per unit area and allows for using small semiconductor chips with small bond pads.
  • the bond wire is arranged us- ing a ball stitch on ball bonding sequence.
  • this allow for arranging the bond wire with a wire loop with a low height profiles.
  • the bond wire is bonded from the contact pad to the bond pad.
  • this allows for connecting the bond wire to the bond pad at a low angle, allowing for a low overall height profile.
  • Figure 1 shows a schematic sectional representation of a part of an electronic device
  • Figure 2 shows a schematic flow diagram of a method for pro ⁇ ducing an electronic device.
  • Figure 1 shows a schematic sectional drawing of a part of an electronic device 100.
  • the electronic device 100 my be an op ⁇ toelectronic device or another kind of electronic device.
  • the electronic device 100 may for example be a light-emitting di ⁇ ode (LED) device, a laser device or a photovoltaic device.
  • LED light-emitting di ⁇ ode
  • the electronic device 100 comprises a semiconductor chip 200.
  • the semiconductor chip 200 may be an optoelectronic semiconductor chip or another kind of semiconductor chip.
  • the semiconductor chip 200 may for example be a light-emitting diode chip, a semiconductor laser chip or a chip comprising a photovoltaic cell.
  • the semiconductor chip 200 may also be re ⁇ ferred to as a die.
  • the semiconductor chip 200 comprises an upper surface 210 and a lower surface 220 on the opposite side of the upper surface 210.
  • the upper surface 210 may be provided for a passage of electromagnetic radiation, for example a passage of visible light .
  • a bond pad 230 is arranged on the upper surface 210 of the semiconductor chip 200.
  • the bond pad 230 is provided for electrically connecting the semiconductor chip 200. Further electric contacts of the semiconductor chip 200 may be ar- ranged on the upper surface 210 or the lower surface 220 of the semiconductor chip 200.
  • the electronic device 100 further comprises a board 300.
  • the board 300 serves as a carrier for the semiconductor chip 200.
  • the semiconductor chip 200 is arranged on an upper side 310 of the board 300.
  • the lower surface 220 of the semiconductor chip 200 faces the upper side 310 of the board 300.
  • the lower surface 220 of the semiconductor chip 200 may for example be soldered or glued onto the upper side 310 of the board 300.
  • the board 300 of the electronic device 100 also serves to provide an electrical connection to the semiconductor chip 200.
  • a contact pad 330 is arranged on the upper side 310 of the board 300 nearby the semiconductor chip 200.
  • a bond wire 110 runs from the contact pad 330 on the upper side 310 of the board 300 to the bond pad 230 on the upper surface 210 of the semiconductor chip 200 and electrically connects the con ⁇ tact pad 330 to the bond pad 230.
  • the bond wire 110 comprises an electrically conducting material.
  • the bond wire 110 may for example comprise gold.
  • the bond wire 110 may for example comprise a diameter of 30 pm or 38 pm.
  • the bond wire 110 forms a loop with a low height profile. Between the bond pad 230 and the contact pad 330, the bond wire 110 reaches a bond wire height 140 above the upper surface 210 of the semicon ⁇ ductor chip 200.
  • the bond wire height 130 is preferably below 100 pm, in particular below 90 pm.
  • the bond wire 110 may be arranged between the bond pad 230 and the contact pad 330 using a ball stitch on ball bonding (BSOB) sequence.
  • BSOB ball stitch on ball bonding
  • the bond wire 110 is connected to the bond pad 230 on the upper surface 210 of the semicon ⁇ ductor chip 200 by a stitch bond 120 and to the contact pad 330 on the upper side 310 of the board 300 by a ball bond 130.
  • An acute angle between the bond wire 110 and the bond pad 230 at the location of the stitch bond 120 may support a low-profile loop of the bond wire 110.
  • the ball bond 130 may be created before the stitch bond 120.
  • the bond wire 110 may be bonded from the contact pad 330 to the bond pad 230.
  • the bond wire 110 runs in close proximity to the upper surface
  • the bond wire 110 should remain electrically insulated from the upper surface 210 of the semiconductor chip 200.
  • an insulating layer 240 is arranged in a section
  • the section 211 is located between the bond pad 230 and an outer edge 215 of the upper surface 210.
  • the bond wire 110 extends over the section 211 of the upper surface 210 and thus over the insulating layer 240 arranged in that section 211.
  • the insulating layer 240 comprises an electrically insulating material.
  • the insulating layer 240 may for example comprise a resist .
  • the lateral dimensions of the insulating layer 240 are large enough to prevent the bond wire 110 from touching the upper surface 210 of the semiconductor chip 200 even if the bond wire 110 sways or sags.
  • the lateral dimensions of the insu ⁇ lating layer 240 may for example be as large as the lateral dimensions of the bond pad 230 or larger than the lateral di ⁇ mensions of the bond pad 230.
  • the bond bad 230 comprises a bond pad thickness 235.
  • the insulat- ing layer 240 comprises an insulating layer thickness 245 in the direction perpendicular to the upper surface 210.
  • the bond pad thickness 235 may be below 1 pm.
  • the bond pad thick ⁇ ness 235 may for example be 900 nm.
  • the thickness 235 of the bond pad 230 is preferably about the same as the thickness 235 of the bond pad 230 or less than the thickness 235 of the bond pad 230.
  • the thickness 245 of the insulating layer 240 and the thickness 235 of the bond pad 230 preferably differ by less than 20 %.
  • the thickness 245 of the insulating layer 240 is preferably less than 1 pm.
  • the contact pad 330 is not arranged on the board 300 but is a bond pad of a further semiconductor chip.
  • the bond wire 110 consequently serves to electrically connect the bond pad 230 of the semiconductor chip 200 to the bond pad of the further semiconductor chip.
  • the board 300 may be omitted in this embodiment.
  • Figure 2 shows a schematic flow diagram of a method 400 for producing the electronic device 100.
  • the semiconductor chip 200 is provided.
  • the semiconductor chip 200 comprises the upper surface 210 with the bond pad 230 arranged on the upper surface 210.
  • the insulating layer 240 is arranged on the upper surface 210.
  • the insulating layer 240 is arranged in the section 211 which is located between the bond pad 230 and the edge 215 of the upper surface 210.
  • the insulating layer 240 comprises an electrically insulating material, for example a resist.
  • the insulating layer 240 may for example be arranged on the upper surface 210 in a last production step during a front-end assembly before polishing the semiconduc ⁇ tor chip 200.
  • the bond wire 110 is arranged between the bond pad 230 and the contact pad 330.
  • the bond wire 110 may for example be arranged using a ball stitch on ball bond ⁇ ing sequence.
  • the bond wire 110 may be bonded from the con ⁇ tact pad 330 to the bond pad 230.

Landscapes

  • Wire Bonding (AREA)

Abstract

An electronic device comprises a semiconductor chip (200) with a surface. A bond pad (230) is arranged on said surface. A layer of electrically insulating material (240) is arranged on said surface in a section of said surface. The section is arranged between said bond pad (230) and an edge of said surface. A bond wire (110) is arranged between said bond pad (230) and a contact pad (330).

Description

Description
Electronic device and method for producing an electronic de- vice
The present invention relates to an electronic device accord¬ ing to claim 1 and to a method for producing an electronic device according to claim 11.
It is known in the state of the art to arrange semiconductor chips of electronic devices on boards. It is further known to electrically connect bond pads arranged on such semiconductor chips to contact pads arranged on such boards by bond wires. One known method of arranging a bond wire is the ball stitch on ball bonding sequence. This method allows for producing low-profile bond connections with bond wire loops that extend only to a limited height above a chip surface. The ball stitch on ball bonding sequence comprises a first step of forming a stud ball bump on a bond pad. In a second step the contact pad is reversely bonded to the bond pad by ball bond¬ ing onto the contact pad and stitch bonding onto the ball bump arranged on the bond pad. It is necessary to prevent an electric short between a bond wire and a surface of a semiconductor chip. It is known in the state of the art to provide bond wires with electrically insulating coatings in order to prevent such short circuits. Such coating increases the cost of the bonding wire. It is also known to design electronic devices with defined minimal clearances between bond wires and chip surfaces or bond wires and neighbouring bond wires respectively to prevent wire shorts. This puts a limit on increasing the number of inter¬ connections per unit area and the possibility of reducing the size of electronic devices.
It is an object of the present invention to provide an elec¬ tronic device. This objective is achieved by an electronic device with the features of claim 1. It is a further object of the present invention to provide a method for producing an electronic device. This objective is achieved by a method comprising the features of claim 11. Preferred embodiments are disclosed in the dependant claims.
An electronic device comprises a semiconductor chip with a surface. A bond pad is arranged on said surface. A layer of electrically insulating material is arranged on said surface in a section of said surface. The section is arranged between said bond pad and an edge of said surface. A bond wire is ar¬ ranged between said bond pad and a contact pad. Advanta¬ geously, the layer of electrically insulating material of this electronic device prevents an electric short between the bond wire and the surface of the semiconductor chip. This al¬ lows for arranging the bond wire in a low loop above the sur¬ face of the semiconductor chip. Advantageously, this allows for providing the bond wire with a short length, allowing for arranging more interconnections per unit area. Consequently, signal wires and ground wires may be brought very closely to¬ gether in order to minimize inductances. A short bond wire may also prevent the bond wire from swaying or sagging. Ad¬ vantageously, this also prevents neighbouring bond wires from shorting .
In an embodiment the electronic device comprises a board. The chip is arranged on said board. The contact pad is also ar¬ ranged on said board. Advantageously, the bond wire provides an electrical connection between the semiconductor chip and the board of the electronic device.
In an embodiment of the electronic device, the contact pad is arranged on a second semiconductor chip. Advantageously, the bond wire serves to connect the two semiconductor chips di- rectly to each other, allowing for a high bandwidth connection. Advantageously, the direct connection between the semi¬ conductor chips may eliminate layers of chip level wiring, substrate level wiring and board level wiring and allow for a routing with higher flexibility.
In an embodiment of the electronic device, said layer of electrically insulating material comprises a resist. Advanta¬ geously, this allows for an easy and cost-efficient arrange¬ ment of the layer of electrically insulating material on the surface of the semiconductor chip. In an embodiment of the electronic device, said layer of in¬ sulating material comprises a thickness of less than 1 pm. Advantageously, a layer with such a thickness provides a suf¬ ficient electrical insulation. In an embodiment of the electronic device, a thickness of said layer of insulating material is smaller or equal to a thickness of said bond pad. Advantageously, this allows for the bond wire to run from the bond pad to the contact pad in a low-profile loop.
In an embodiment of the electronic device, a thickness of said layer of insulating material differs from a thickness of said bond pad by less than 20 %. Advantageously, this ensures that the layer of insulating material prevents an electric short between the bond wire and the surface of the semicon¬ ductor chip.
In an embodiment of the electronic device, the bond wire ex¬ tends less than 100 pm above said bond pad. Advantageously, this results in a low height profile of the electronic de¬ vice .
In an embodiment of the electronic device, the bond wire com¬ prises gold. Advantageously, bond wires comprising gold pro- vide good mechanical and electrical properties.
In an embodiment of the electronic device, the semiconductor chip is an optoelectronic semiconductor chip. In this embodi- ment the electronic device is an optoelectronic device. The optoelectronic semiconductor chip may for example be a light emitting diode chip, a semiconductor laser chip or a chip comprising a photovoltaic solar cell.
A method for producing an electronic device comprises steps of providing a semiconductor chip comprising a surface, wherein a bond pad is arranged on said surface, of arranging a layer of electrically insulating material on said surface in a section of said surface, wherein the section is arranged between said bond pad and an edge of said surface, and of ar¬ ranging a bond wire between said bond pad and a contact pad. Advantageously, this method allows for producing an elec¬ tronic device with a low height profile. The bond wire of the electronic device is advantageously secured against shorting to the surface of the semiconductor chip by the layer of electrically insulating material arranged on the surface of the semiconductor chip. This may decrease a yield loss due to wire shorts. The method allows for using very short bond wires which enables providing more interconnections per unit area and allows for using small semiconductor chips with small bond pads.
In an embodiment of the method, the bond wire is arranged us- ing a ball stitch on ball bonding sequence. Advantageously, this allow for arranging the bond wire with a wire loop with a low height profiles.
In an embodiment of the method, the bond wire is bonded from the contact pad to the bond pad. Advantageously, this allows for connecting the bond wire to the bond pad at a low angle, allowing for a low overall height profile.
The accompanying drawings are included in order to provide a further understanding of the present invention and are incorporated into and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they will be better understood by reference to the following detailed description. The ele- ments of the drawings are not to scale with regard to each other .
Figure 1 shows a schematic sectional representation of a part of an electronic device; and
Figure 2 shows a schematic flow diagram of a method for pro¬ ducing an electronic device.
Figure 1 shows a schematic sectional drawing of a part of an electronic device 100. The electronic device 100 my be an op¬ toelectronic device or another kind of electronic device. The electronic device 100 may for example be a light-emitting di¬ ode (LED) device, a laser device or a photovoltaic device.
The electronic device 100 comprises a semiconductor chip 200. The semiconductor chip 200 may be an optoelectronic semiconductor chip or another kind of semiconductor chip. The semiconductor chip 200 may for example be a light-emitting diode chip, a semiconductor laser chip or a chip comprising a photovoltaic cell. The semiconductor chip 200 may also be re¬ ferred to as a die.
The semiconductor chip 200 comprises an upper surface 210 and a lower surface 220 on the opposite side of the upper surface 210. The upper surface 210 may be provided for a passage of electromagnetic radiation, for example a passage of visible light . A bond pad 230 is arranged on the upper surface 210 of the semiconductor chip 200. The bond pad 230 is provided for electrically connecting the semiconductor chip 200. Further electric contacts of the semiconductor chip 200 may be ar- ranged on the upper surface 210 or the lower surface 220 of the semiconductor chip 200.
The electronic device 100 further comprises a board 300. The board 300 serves as a carrier for the semiconductor chip 200. The semiconductor chip 200 is arranged on an upper side 310 of the board 300. The lower surface 220 of the semiconductor chip 200 faces the upper side 310 of the board 300. The lower surface 220 of the semiconductor chip 200 may for example be soldered or glued onto the upper side 310 of the board 300.
The board 300 of the electronic device 100 also serves to provide an electrical connection to the semiconductor chip 200. A contact pad 330 is arranged on the upper side 310 of the board 300 nearby the semiconductor chip 200. A bond wire 110 runs from the contact pad 330 on the upper side 310 of the board 300 to the bond pad 230 on the upper surface 210 of the semiconductor chip 200 and electrically connects the con¬ tact pad 330 to the bond pad 230. The bond wire 110 comprises an electrically conducting material. The bond wire 110 may for example comprise gold. The bond wire 110 may for example comprise a diameter of 30 pm or 38 pm.
Between the bond pad 230 of the semiconductor chip 200 and the contact pad 330 of the board 300, the bond wire 110 forms a loop with a low height profile. Between the bond pad 230 and the contact pad 330, the bond wire 110 reaches a bond wire height 140 above the upper surface 210 of the semicon¬ ductor chip 200. The bond wire height 130 is preferably below 100 pm, in particular below 90 pm.
The bond wire 110 may be arranged between the bond pad 230 and the contact pad 330 using a ball stitch on ball bonding (BSOB) sequence. In this case, the bond wire 110 is connected to the bond pad 230 on the upper surface 210 of the semicon¬ ductor chip 200 by a stitch bond 120 and to the contact pad 330 on the upper side 310 of the board 300 by a ball bond 130. An acute angle between the bond wire 110 and the bond pad 230 at the location of the stitch bond 120 may support a low-profile loop of the bond wire 110. The ball bond 130 may be created before the stitch bond 120. The bond wire 110 may be bonded from the contact pad 330 to the bond pad 230.
Due to the low height profile of the loop of the bond wire 110 between the bond pad 230 and the contact pad 330, the bond wire 110 runs in close proximity to the upper surface
210 of the semiconductor chip 200. In order to prevent a short between the bond wire 110 and the semiconductor chip
200, the bond wire 110 should remain electrically insulated from the upper surface 210 of the semiconductor chip 200. To this end, an insulating layer 240 is arranged in a section
211 on the upper surface 210 of the semiconductor chip 200. The section 211 is located between the bond pad 230 and an outer edge 215 of the upper surface 210. The bond wire 110 extends over the section 211 of the upper surface 210 and thus over the insulating layer 240 arranged in that section 211.
The insulating layer 240 comprises an electrically insulating material. The insulating layer 240 may for example comprise a resist . The lateral dimensions of the insulating layer 240 are large enough to prevent the bond wire 110 from touching the upper surface 210 of the semiconductor chip 200 even if the bond wire 110 sways or sags. The lateral dimensions of the insu¬ lating layer 240 may for example be as large as the lateral dimensions of the bond pad 230 or larger than the lateral di¬ mensions of the bond pad 230.
In a direction perpendicular to the upper surface 210, the bond bad 230 comprises a bond pad thickness 235. The insulat- ing layer 240 comprises an insulating layer thickness 245 in the direction perpendicular to the upper surface 210. The bond pad thickness 235 may be below 1 pm. The bond pad thick¬ ness 235 may for example be 900 nm. The thickness 235 of the bond pad 230 is preferably about the same as the thickness 235 of the bond pad 230 or less than the thickness 235 of the bond pad 230. The thickness 245 of the insulating layer 240 and the thickness 235 of the bond pad 230 preferably differ by less than 20 %. The thickness 245 of the insulating layer 240 is preferably less than 1 pm.
In an alternative embodiment of the electronic device, the contact pad 330 is not arranged on the board 300 but is a bond pad of a further semiconductor chip. In this embodiment, the bond wire 110 consequently serves to electrically connect the bond pad 230 of the semiconductor chip 200 to the bond pad of the further semiconductor chip. The board 300 may be omitted in this embodiment.
Figure 2 shows a schematic flow diagram of a method 400 for producing the electronic device 100.
In a first step 410, the semiconductor chip 200 is provided. The semiconductor chip 200 comprises the upper surface 210 with the bond pad 230 arranged on the upper surface 210.
In a second step 420, the insulating layer 240 is arranged on the upper surface 210. The insulating layer 240 is arranged in the section 211 which is located between the bond pad 230 and the edge 215 of the upper surface 210. The insulating layer 240 comprises an electrically insulating material, for example a resist. The insulating layer 240 may for example be arranged on the upper surface 210 in a last production step during a front-end assembly before polishing the semiconduc¬ tor chip 200.
In a third step 430, the bond wire 110 is arranged between the bond pad 230 and the contact pad 330. The bond wire 110 may for example be arranged using a ball stitch on ball bond¬ ing sequence. The bond wire 110 may be bonded from the con¬ tact pad 330 to the bond pad 230. While the invention has been described in detail with refer¬ ence to specific embodiments thereof, it will be apparent to one of ordinary skill in the art that various changes and modifications can be made therein without departing from the spirit and scope thereof. Accordingly, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
1 Q
Reference numbers
100 electronic device
110 bond wire
120 stitch bond
130 ball bond
140 bond wire height
200 semiconductor chip
210 upper surface
211 section
215 edge
220 lower surface
230 bond pad
235 bond pad thickness
240 insulating layer
245 insulating layer thickness
300 board
310 upper side
330 contact pad
400 production method
410 first step
420 second step
430 third step

Claims

An electronic device (100)
comprising a semiconductor chip (200) with a surface (210) ,
wherein a bond pad (230) is arranged on said surface (210) ,
wherein a layer (240) of electrically insulating material is arranged on said surface (210) in a section (211) of said surface (210),
wherein the section (211) is arranged between said bond pad (230) and an edge (215) of said surface (210);
wherein a bond wire (110) is arranged between said bond pad (230) and a contact pad (330) .
The electronic device (100) as claimed in claim 1, wherein the electronic device (100) comprises a board (300) ,
wherein the chip (200) is arranged on said board (300), wherein the contact pad (330) is arranged on said board (300) .
The electronic device (100) as claimed in claim 1, wherein the contact pad (330) is arranged on a second semiconductor chip.
The electronic device (100) as claimed in any one of the preceding claims,
wherein said layer (240) of electrically insulating mate¬ rial comprises a resist.
The electronic device (100) as claimed in any one of the preceding claims,
wherein said layer (240) of insulating material comprises a thickness (245) of less than 1 pm.
6. The electronic device (100) as claimed in any one of the preceding claims, wherein a thickness (245) of said layer (240) of insulat¬ ing material is smaller or equal to a thickness (235) of said bond pad (230) . 7. The electronic device (100) as claimed in any one of the preceding claims,
wherein a thickness (245) of said layer (240) of insulat¬ ing material differs from a thickness (235) of said bond (230) pad by less than 20 %.
8. The electronic device (100) as claimed in any one of the preceding claims,
wherein the bond wire (110) extends less than 100 pm above said bond pad (230) .
9. The electronic device (100) as claimed in any one of the preceding claims,
wherein the bond wire (110) comprises gold. 10. The electronic device (100) as claimed in any one of the preceding claims,
wherein the semiconductor chip (200) is an optoelectronic semiconductor chip. 11. A method for producing an electronic device (100)
comprising the following steps:
- providing a semiconductor chip (200) comprising a surface (210), wherein a bond pad (230) is arranged on said surface (210) ;
- arranging a layer (240) of electrically insulating ma¬ terial on said surface (210) in a section (211) of said surface (210), wherein the section (211) is arranged be¬ tween said bond pad (230) and an edge (215) of said sur¬ face (210);
- arranging a bond wire (110) between said bond pad (230) and a contact pad (330) .
12. The method as claimed in claim 11,
wherein the bond wire (110) is arranged using a ball stitch on ball bonding sequence. 13. The method as claimed in any one of claims 11 and 12, wherein the bond wire (110) is bonded from the contact pad (330) to the bond pad (230) .
PCT/EP2013/057698 2013-04-12 2013-04-12 Electronic device and method for producing an electronic device Ceased WO2014166547A1 (en)

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Application Number Priority Date Filing Date Title
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