WO2014163168A1

WO2014163168A1 - Application-specific virtual machine generation system, device, method, and program

Info

Publication number: WO2014163168A1
Application number: PCT/JP2014/059903
Authority: WO
Inventors: 幸一中本; 幸秀辻
Original assignee: 日本電気株式会社; 兵庫県
Priority date: 2013-03-30
Filing date: 2014-03-28
Publication date: 2014-10-09
Also published as: JPWO2014163168A1; JP6350831B2

Abstract

Means (1-4) are provided on a host computer, and generated interpreter and application-specific instruction-embedded code are installed on a target computer. 1) A specialized instruction definition means for defining an application-specific instruction, 2) a compiler generation means for generating a compiler capable of generating a specialized instruction-embedded code obtained by combining the application-specific instruction and a general-purpose virtual machine instruction, 3) an interpreter generation means for generating the interpreter capable of analyzing and executing the specialized instruction-embedded code, and 4) a specialized instruction-embedded code generation means for generating the application-specific instruction-embedded code by compiling a source code written in a general-purpose programming language by the compiler generated by the complier generation means.

Description

Application-specific virtual machine generation system, apparatus, method, and program

The present invention relates to a virtual machine generation technique specialized for an application for reducing power consumption when updating a computer program.

In recent years, sensor networks that network sensor nodes having a sensing function by wireless communication have attracted attention. Since a large number of sensor nodes are distributed in the sensor network, it is possible to reduce the number of sensor node batteries to be replaced or to eliminate the need for replacement (the number of replacements is 0), and to increase the usable time of the entire system. Necessary for practical use of sensor networks. On the other hand, versatility is required for the CPU (Central Processing Unit) of the sensor node, the amount of accessible memory increases, and the program size installed in the sensor node increases. When the program size mounted on the sensor node increases, there is a problem that the power consumption at the time of updating the program increases.
In addition to the sensor node, when the CPU of the target computer is required to be versatile and the accessible memory amount is large, the size of the instruction code of the target computer tends to increase. Usually, the instruction code of such a target computer is generated by a host computer. Therefore, the target computer has a problem in that power consumption increases because the program size received when updating the program is large.
As shown in FIG. 8, such a system includes, for example, a host computer 1 that generates an instruction code program and a target computer 2 that executes the instruction code program.
In a general sensor network, as shown in FIG. 8, the compiler 20 compiles a processing program (a source program written in a programming language such as C language) of the target computer 2 on the host computer 1. Then, the compiler 20 generates a program of the instruction code (second CPU 22 instruction program 23) of the second CPU 22 of the target computer 2. The second CPU 22 instruction program 23 generated by the compiler 20 is transferred from the host computer 1 to the target computer 2 and stored in the memory of the target computer 2. Then, the second CPU 22 reads the second CPU 22 instruction program 23 from the memory of the target computer 2 and executes it. If the second CPU 22 instruction program 23 is changed, the above process is repeated.
Here, when a program is executed by a computer, its execution method is roughly divided into two methods, a compiler method and an interpreter method. In the following, the compiler and interpreter will be described.
The compiler is a process for converting a program written in a programming language into a machine language instruction code that can be understood by the CPU. The CPU executes the program based on the machine language instruction code. In the compiling method, at the stage where the CPU executes the program, syntax analysis and translation into machine language are finished, so that an optimal execution processing speed by the CPU can be obtained. However, the compiler method has a problem that it is difficult to change the instruction code to be executed.
For the compiler, the interpreter is a process for translating a program written in a programming language into an intermediate instruction code different from the machine language. The interpreter interprets and executes the program based on the intermediate instruction code. Therefore, in the interpreter system, it is easier to add instruction codes than in the compile system.
Also, by changing the interpreter, the function of the instruction code can be easily changed. However, in the case of the interpreter method, it is difficult to increase the speed because the interpreter executes the intermediate instruction code as a program. Recently, the processing speed of the CPU itself has become very high, and unless it is a special application that requires high-speed processing, the interpreter method can satisfy the required processing.
Note that the interpreter in this specification and the drawings is used synonymously with a virtual machine. That is, the interpreter is software that converts a source program of a specific programming language into an intermediate instruction code and interprets and executes the intermediate instruction code program.
In addition, in the case of a target computer that operates by battery drive such as a sensor node as described below, a technique for executing at high speed by reducing the program size while maintaining versatility is known.
For example, in a multimedia application, the program size can be reduced by adding multimedia extension instructions and saturation instructions used in multimedia to the CPU instructions.
Also, an application specific instruction processor (ASIP: Application Specific Instruction Processor) in which an application specific instruction code is implemented in hardware on a CPU is known (see, for example, Non-Patent Document 1).
Also known is a technique for generating a program such as Java (registered trademark) in a virtual machine instruction format (byte code) independent of the CPU of the target computer, and executing the program on the CPU of the target computer by a virtual machine instruction interpreter. (For example, see Non-Patent Document 2).
In this technique, since the byte code is executed on the stack, it is not necessary to specify an operand, so the instruction code size is reduced. As a result, the program size is reduced.
In addition, a technique for proposing a virtual machine in order to reduce the download size of a program on an OS (Operating System) dedicated to the sensor node is known (see, for example, Non-Patent Document 3).
In the technique disclosed in Non-Patent Document 3, the virtual machine instruction code is fixed in order to reduce the download size of the program.
Also, a technique is known in which a byte instruction code of a virtual machine code is replaced with a macro instruction code, and when the virtual machine interprets the macro instruction code, the implementation address of the macro instruction code is checked and the instruction is executed. (See Patent Document 1).
In recent years, a non-volatile logic circuit using a non-volatile element that can change specifications in a manufactured logic circuit is known (see, for example, Patent Documents 2 to 7). Programmable semiconductor integrated circuits such as FPGA (Field Programmable Gate Array) can change the logic operation and wiring connection by storing the operation of the logic circuit and arithmetic circuit and the connection between the logic circuit and arithmetic circuit in the memory. And However, since the memory element is formed in the same layer as the transistor on the semiconductor substrate, there is a problem of occupying a very large area. For this reason, the programmable integrated circuit has a problem that the chip area increases and the manufacturing cost increases. Further, in the FPGA, since the area of the wiring switch for changing the connection between the logic circuit and the arithmetic circuit is increased, there is a problem that the ratio of the logic circuit and the arithmetic circuit in the chip area is reduced.
In the non-volatile logic circuit using the non-volatile element, it is possible to replace both the memory element or the memory circuit for storing the configuration information and the pass transistor for connecting the wirings with a wiring structure. .

Japanese translation of PCT publication No. 2003-510681 JP 2009-124175 A JP 2009-117866 A Patent No. 4992859 Japanese Patent No. 4985583 Patent No. 4992858 Japanese Patent No. 4356542

In view of the above situation, an object of the present invention is to reduce the power consumption required at the time of program update and execution of a target computer by reducing the size of a program transferred to and executed by a target computer such as a sensor node. To do.
It is another object of the present invention to reduce power consumption required for program update and execution by partially executing a program on a target computer.

In order to achieve the above object, the application-specific virtual machine generation system of the present invention is provided with the following means 1) to 4) on the host computer and the interpreter generated by the following 3) interpreter generation means on the target computer. In addition, the application specific instruction embedded code generated by the specialized instruction embedded code generating means 4) below is mounted.
1) Specialized instruction defining means for defining a virtual machine instruction (application specific instruction) specialized for each application.
2) Compiler generation means for generating a compiler capable of generating a special instruction embedded code combining a defined application special instruction and a general-purpose virtual machine instruction.
3) Interpreter generating means for generating an interpreter capable of interpreting and executing the specialized instruction embedded code.
4) Specialized instruction embedded code generation means for generating application-specific instruction embedded code by compiling source code written in a general-purpose programming language with a compiler generated by the compiler generation means.
In the system configured as described above, the size of a program to be transferred / executed to the target computer can be reduced, and the power required for updating and executing the program on the target computer can be reduced.
Here, a virtual machine instruction specialized for each application (application-specific instruction) means a virtual machine instruction code compactized in accordance with the characteristics of the application source code described in a high-level program language.
The characteristics of the application source code include, for example, frequent repeat processing (loop processing), frequent conditional branch processing, frequent store instructions, predictable number of data to be stored, constants to store, It has characteristics indicating that the number of data digits can be predicted, a series of processing frequently occurs, and the like.
The specialized instruction defining means analyzes the characteristics of the application source code and creates a replacement table that replaces these characteristics with specialized character strings, numeric strings, symbols, and codes that do not appear in the source code. Specifically, on the host computer screen, special instruction code that replaces repeated processing (loop processing), special instruction code that replaces conditional branch processing, and special instruction code that replaces a series of processes such as store / forward Define.
The general-purpose virtual machine instructions are the same instructions that the host computer compiles the target processing program and generates a program of the instruction code of the CPU of the target computer.
The compiler generating means of 2) generates a compiler capable of generating a special instruction embedded code combining the application specific instruction defined in 1) and a general-purpose virtual machine instruction. This compiler differs from conventional compilers in that it can generate specialized instruction embedded code that combines application-specific instructions and general-purpose virtual machine instructions.
The interpreter generating means of 3) generates an interpreter that can interpret and execute the specialized instruction embedded code. The interpreter generated on the host computer is transferred to the target computer and mounted on the target computer.
The specialized instruction embedded code generation means of 4) above compiles the source code of a program described in a general-purpose program language (that is, a high-level program language) with a compiler generated by the compiler generation means, Generate application specific instruction embedded code.
That is, the compiler generated by the compiler generation unit analyzes the source code of the target process. The compiler compiles while discriminating an application-specific instruction code included in the source code and a general-purpose virtual machine-specific instruction code. Therefore, the compiler can generate the special instruction embedded code combining the application special instruction code and the virtual machine instruction code.
In the application-specific virtual machine generation system of the present invention, the specialized instruction embedded code generation means compiles the source code of the pre-update program and the source code of the post-update program with the compiler, respectively, Analyzing the specialized instruction embedded code and the application specialized instruction embedded code of the updated program to generate an application specialized instruction embedded differential code, and the interpreter includes an application specialized instruction embedded differential code, More preferably, the application-specific instruction embedded code before update is merged and interpreted.
By generating the difference code and transferring it to the target computer, the program size transferred / executed to the target computer can be further reduced, and the power consumption associated with the transfer can be further reduced.
In the application-specific virtual machine generation system of the present invention, the interpreter is configured by a nonvolatile logic circuit using a nonvolatile element, and a part of the circuit board of the target computer is configured by a nonvolatile logic circuit. preferable.
According to the above configuration, a part of the program of the target computer is transferred to the nonvolatile theory.

Can be reduced. In addition, when the present invention is applied to a sensor node in which power ON / OFF operations are frequently performed, since it is non-volatile, it is not necessary to transfer the configuration data of the interpreter that occurs every time it recovers, reducing power consumption. And a delay at the time of starting can be avoided.
Further, in the nonvolatile logic circuit, an extension instruction can be added and hard coding (hardware) for the additional instruction can be performed, and the interpreter in the present invention can be realized.
In the application-specific virtual machine generation system of the present invention, the application-specific instruction specifically means that an instruction code composed of a plurality of words is shortened and replaced with an instruction code having a shorter length. Is.
Another application-specific instruction is to integrate a plurality of instruction codes and replace them with an instruction code having a shorter length.
In addition, another application specific instruction shortens the processing data to the number of bits corresponding to the assumed value, or changes the address of the processing data to a position identifier shortened to the number of bits corresponding to the assumed address. Is. For example, shortening to the number of bits corresponding to the assumed address means changing to a 4-bit position identifier if the assumed address is 0 to 15, and changing to an 8-bit position identifier if it is 0 to 255. That is.
Another application-specific instruction shortens the instruction code bit by limiting the number of instruction codes. For example, if the number of instruction codes is 32, the instruction code bits can be expressed by 5 bits, and further the instruction code is limited to 4 instruction codes, that is, if the number of instruction codes is 4, the instruction code The code bit can be expressed by 2 bits.
Next, the application-specific virtual machine generation device of the present invention includes the following a) to d).
a) Specialized instruction definition means for defining a virtual machine instruction (application specific instruction) specialized for each application.
b) Compiler generation means for generating a compiler capable of generating a special instruction embedded code combining a defined application special instruction and a general-purpose virtual machine instruction.
c) Interpreter generating means for generating an interpreter capable of interpreting and executing the specialized instruction embedded code.
d) Specialized instruction embedded code generation means for generating application-specific instruction embedded code by compiling source code written in a general-purpose programming language with a compiler generated by the compiler generation means.
According to the application-specific virtual machine generation apparatus of the present invention, the size of a program to be transferred / executed to a target computer can be reduced, and power consumption required when updating and executing a program on the target computer can be reduced.
Note that the descriptions of a) to d) are the same as those of 1) to 4) described above, and a description thereof will be omitted.
Next, the application-specific virtual machine generation method of the present invention includes the following A) to D).
A) A specialized instruction defining step for defining a virtual machine instruction (application specialized instruction) specialized for each application.
B) A compiler generation step for generating a compiler capable of generating a special instruction embedded code combining a defined application special instruction and a general-purpose virtual machine instruction.
C) An interpreter generation step for generating an interpreter capable of interpreting and executing the specialized instruction embedded code.
D) A specialized instruction embedded code generation step of generating an application specific instruction embedded code by compiling source code written in a general-purpose programming language with a compiler generated by the compiler generation means.
According to the application-specific virtual machine generation method of the present invention, the size of a program to be transferred / executed to a target computer can be reduced, so that it is possible to reduce power consumption required when updating and executing a program on the target computer.
The description of A) to D) is the same as 1) to 4) described above, and the description is omitted.
In the application-specific virtual machine generation method of the present invention, the interpreter generated by the interpreter generation step and the application-specific instruction embedded code generated by the specialized instruction embedded code generation step are transferred to the target computer. More preferably, a transfer step is further provided.
Since the application specific instruction embedded code generated by the special instruction embedded code generation step optimizes the program size, it is possible to reduce power consumption due to data transfer when the target computer updates the program.
In the application-specific virtual machine generation method of the present invention, the interpreter generated in the interpreter generation step is configured by a nonvolatile logic circuit using a nonvolatile element, and a part of the circuit board of the target computer is configured as a nonvolatile logic. It is more preferable to further comprise a circuit configuration step configured by a circuit and a transfer step of transferring the application-specific instruction embedded code generated by the specific instruction embedded code generation step to the target computer.
Thereby, a part of the program on the target computer is executed by hardware, and the power consumption required at the time of program update and execution can be reduced.
Further, in the specialized instruction embedded code generation step in the application specific virtual machine generation method of the present invention, the source code of the pre-update program and the source code of the post-update program are respectively compiled by the compiler, and the application special of the program before update is compiled. By analyzing the embedded instruction embedded code and the application-specific instruction embedded code of the updated program, an application-specific instruction embedded differential code is generated, and the interpreter executes the application-specific instruction embedded differential code and the pre-update More preferably, the application-specific instruction embedded code is merged and interpreted.
By generating the difference code and transferring it to the target computer, the program size transferred / executed to the target computer can be further reduced, and the power consumption associated with the transfer can be further reduced.
The application-specific virtual machine generation program of the present invention causes a computer to function as the following i) to iv).
i) Specialized instruction definition means for defining virtual machine instructions (application specific instructions) specialized for each application.
ii) Compiler generation means for generating a compiler capable of generating special instruction embedded code combining the defined application specific instruction and a general-purpose virtual machine instruction.
iii) interpreter generating means for generating an interpreter capable of interpreting and executing the specialized instruction embedded code.
iv) specialized instruction embedded code generation means for generating application specific instruction embedded code by compiling source code written in a general-purpose programming language with the compiler generated by the compiler generation means.
According to the application-specific virtual machine generation program of the present invention, the size of a program to be transferred / executed to the target computer can be reduced, and the power consumption required when updating and executing the program of the target computer can be reduced.
The description of i) to iv) is the same as 1) to 4) described above, and the description is omitted.

According to the present invention, by making the instruction code of a program specialized for an application, the program size can be reduced, and as a result, the program size transmitted at the time of program update is reduced.
Further, according to the present invention, there is an effect that the power consumption during the program execution can be reduced by executing a part of the program in the target computer by hardware.

FIG. 1 is a block diagram showing an application-specific virtual machine generation system.
FIG. 2A is a conceptual diagram showing a constant store instruction by a conventional CPU.
FIG. 2B is a conceptual diagram showing an application specific instruction.
FIG. 3A is a schematic diagram illustrating store and forward operations between sensor nodes.
FIG. 3B is a conceptual diagram showing a store instruction and a forward instruction by a conventional CPU.
FIG. 3C is a conceptual diagram showing an application specific instruction.
FIG. 4 is an explanatory diagram of a specialized instruction for a function call instruction.
FIG. 5 is a block diagram showing another type of application-specific virtual machine generation system.
FIG. 6 is a flowchart showing a processing flow of the host computer.
FIG. 7 is a flowchart showing a processing flow of the target computer.
FIG. 8 is a block diagram showing a conventional system.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The scope of the present invention is not limited to the following examples and illustrated examples, and many changes and modifications can be made.
The application-specific virtual machine generation system of the present invention will be described with reference to FIG. The application-specific virtual machine generation system of the present invention is a system that includes a host computer 1 and a target computer 2 that can be connected by data transfer means including a communication network such as wireless communication. A connectable system includes both a constantly connected system and a temporarily connected system.
First, as shown in FIG. 1, the specialized instruction defining unit 12 defines a specialized instruction for each application (hereinafter referred to as “AP specialized instruction”). The compiler generation unit 14 generates a compiler 16 (hereinafter referred to as “AP-specific compiler 16”) that generates a program of an AP-specific instruction and a normal virtual machine instruction. The interpreter generation means 15 generates an interpreter 17 that interprets and executes a program of an AP special instruction and a normal virtual machine instruction (hereinafter referred to as “AP special instruction interpreter 17”). The compiler generation unit 14 and the interpreter generation unit 15 are called a virtual machine generator 13 specialized for an application.
The non-volatile circuit converting means 18 converts the AP-specific instruction interpreter 17 into an AP-specific interpreter 25 using a non-volatile logic circuit.
The specialized instruction embedded code generation means 19 has an AP specialized compiler 16. The AP special compiler 16 operates on the host computer 1 and compiles the processing program 3 written in a programming language such as C language into a program 24 based on AP special instructions. The program 24 based on the AP special instruction is transferred to the target computer 2. In the target computer 2, an AP specialized instruction interpreter 25 based on a nonvolatile circuit interprets and executes the program 24 based on the AP specialized instruction. At this time, by specializing the execution instruction code of the program for the application, the program size can be reduced, so that the power related to program transmission can be reduced. In addition, since the program 24 by the AP special instruction is executed by the AP special instruction interpreter 25 by the nonvolatile circuit, the power consumption is reduced.

With reference to FIG. 2A and FIG. 2B, a method for changing the variable value of the program in the constant store instruction will be described.
In the sensor node, it is expected that the variable value of the program in the sensor node is often changed in order to adjust the parameter of data collection.
When changing a variable value of a program, a constant store instruction is prepared in a general CPU as shown in FIG. 2A. However, since the CPU is generally used, two 32 bits (one word) are required.
Referring to FIG. 2B, in the application-specific virtual machine generation system, if the variable value of a program can be changed by specifying a constant value with a value represented by 16 bits and a storage location with an 8-bit identifier, This can be realized by one 32-bit (one word). Therefore, in the application-specific virtual machine generation system, a constant store instruction code composed of a plurality of two words is shortened and replaced with a one-word constant store instruction code.

With reference to FIG. 3A, FIG. 3B, and FIG. 3C, the operation | movement which the sensor node in a sensor network transfers a sensor command is demonstrated.
Referring to FIG. 3A, the sensor node B stores the sensor command received from the adjacent sensor node A and transmits the data to the next adjacent sensor node C. The sensor node C performs the same process as that of the sensor node B when there is a further adjacent sensor node.
In order to program this operation with a general-purpose instruction code, a store instruction code and a forward instruction code are required separately as shown in FIG. 3B. In practice, an instruction of several tens of steps is required.
On the other hand, in the application-specific virtual machine generation system, the operation can be realized with one store-forward instruction as shown in FIG. 3C. In this case, it is assumed that the store address of the command data of the sensor node can be specified by an 8-bit identifier, and the address of the adjacent node is held by the wireless driver. Since it can be realized by one store-forward instruction, the size of the program 24 by the AP-specific instruction is reduced, so that the power required for data transmission can be reduced.

Next, with reference to FIG. 4, application specific instructions relating to programs in which function call instructions frequently appear will be described. For example, a program that frequently uses a function called changeCalVal () is assumed. The function called changeCalVal () has two actual arguments, one of which is a variable, and the other is a threshold constant. It is also assumed that the value that the variable can take when operating the program is an integer of 100 or less.
In such a case, the application-specific instruction defines an application-specific instruction code for changeCalVal (x, v). Specifically, if there is a description of changeCalVal (x, v) (x and v are arguments), it is recognized as a continuous instruction of three lines of codeof (changeCalVal), codeof (x), and codeof (v). . Then, the code corresponding to the execution function changeCalVal is arranged in the upper 16 bits in the 32-bit code as shown in FIG. 4, and the values corresponding to the two actual arguments (x, v) of the execution function are set in the lower 16 bits. Deploy. Here, codeof (A) represents the encoded A.
The following definition indicates that changeCalVal (x, v) on the left side of :: = is associated with the application-specific instruction code on the right side of :: =.
changeCalVal (x, v) :: =
codeof (changeCalVal)
codeof (x)
codeof (v)
As a result, it is possible to compress an instruction code that required at least 96 bits including the pointer information (address information) of the function, the 32-bit information of the actual argument x, and the 32-bit information of the actual argument v to 32 bits. Become. If there is changeCalVal (x, v) in the program source code, the application (AP) specialized compiler 16 converts it into a specialized instruction code compressed to 32 bits.

Next, an application-specific instruction relating to a program having a frequently executed statement pattern will be described. For example, suppose a program in which conditional branch instructions frequently appear as frequently executed statement patterns.
In such a case, as shown below, the conditional parameter of the conditional branch is recognized as an instruction continuous with the call function after the branch, and these are converted into a compressed special instruction code.
The following definition indicates that the executable statement pattern of the if statement on the left side of :: = corresponds to the application-specific instruction code on the right side of :: =.
if (x> 0) {
method1 ();
} Else {
method2 ();
}
:: = codeof (callMethod)
codeof (0)
codeof (method1)
codeof (method2)

FIG. 5 is a block diagram illustrating functions of the application-specific virtual machine generation system according to the fifth embodiment. Referring to FIG. 5, unlike the system described above, in order to reduce the amount of the program transferred to the sensor node serving as the target computer 2, the source code of the pre-update program 3a and the source code of the post-update program 3b are respectively AP-specific. Compile with the compiler 16. The AP-specific compiler 16 analyzes the application-specific instruction embedded code of the pre-update program 3a and the application-specific instruction embedded code of the post-update program 3b, and the difference program 26 is an application-specific instruction embedded differential code. Is generated.
In the sensor node which is the target computer 2, the AP special instruction interpreter 25 using a nonvolatile circuit interprets and executes a program obtained by merging the pre-update program 27 and the difference program 26 using the AP special instruction.

6 is a flowchart of processing executed by the host computer 1, and FIG. 7 is a flowchart of processing executed by the target computer 2.
A processing flow of the host computer 1 will be described with reference to FIG.
First, the host computer 1 defines a virtual machine instruction (AP special instruction) specialized for each application (step S11).
Next, an AP specialized compiler capable of generating specialized instruction embedded code combining an application (AP) specialized instruction and a general-purpose virtual machine instruction is generated (step S12).
Next, an AP special instruction interpreter capable of interpreting and executing the special instruction embedded code is generated (step S13).
Then, the source code of the program is compiled by the AP specialized compiler generated in step S12, and an application (AP) specialized instruction embedded code is generated (step S14).
The processing flow of the target computer 2 will be described with reference to FIG.
First, the target computer 1 downloads an AP-specific instruction interpreter from the host computer 1 (transfers it from the host computer to the target computer) (step S21).
Next, the AP-specific instruction embedded code is downloaded from the host computer 1 (step S22).
Then, the AP special instruction interpreter interprets and executes the AP special instruction embedded code (step S23).
In FIG. 7, as in the first embodiment, the AP-specific instruction interpreter is configured by a nonvolatile logic circuit using a nonvolatile element, and a part of the circuit board of the target computer is configured by a nonvolatile logic circuit. In this case, steps S22 and S23 are performed without performing step S21.

The present invention is useful for a battery-driven sensor node and actuator node. Further, the present invention can be applied to a computer system that can be used for several decades with only a battery. For example, it can be used in a wide range of fields that require data collection, such as buildings, tunnels, farms, and roads.

DESCRIPTION OF SYMBOLS 1 Host computer 2 Target computer 3 Program 3a Program before update 3b Program after update 12 Specialized instruction definition means 13 Virtual machine generator 14 Compiler generation means 15 Interpreter generation means 16 AP specialization compiler 17 AP specialization interpreter 18 Nonvolatile circuitization means 19 Specialized instruction embedded code generation means 20 Compiler This application claims priority based on Japanese Patent Application No. 2013-075504 filed on March 30, 2013, the entire disclosure of which is here Into.

Claims

On the host computer
1) specialized instruction defining means for defining virtual machine instructions (application specialized instructions) specialized for each application;
2) Compiler generation means for generating a compiler capable of generating special instruction embedded code combining the defined application specific instruction and a general-purpose virtual machine instruction;
3) interpreter generating means for generating an interpreter capable of interpreting and executing the specialized instruction embedded code;
4) Specialized instruction embedded code generation means for generating application-specific instruction embedded code by compiling source code written in a general-purpose programming language with the compiler generated by the compiler generation means;
With
5) On the target computer,
The interpreter generated by the interpreter generating means;
The application-specific instruction embedded code generated by the specialized instruction embedded code generation means is mounted,
An application-specific virtual machine generation system characterized by that.
The specialized instruction embedded code generation means compiles the source code of the pre-update program and the source code of the post-update program with the compiler, respectively, and the application special instruction embedded code of the pre-update program and the application special of the post-update program Analyzing embedded instruction embedded code and generating application specific instruction embedded differential code,
The interpreter merges and interprets the application-specific instruction embedded differential code and the application-specific instruction embedded code before update.
The application-specific virtual machine generation system according to claim 1.
The interpreter is composed of a nonvolatile logic circuit using a nonvolatile element,
A part of the circuit board of the target computer is composed of the nonvolatile logic circuit,
The application-specific virtual machine generation system according to claim 1 or 2.
The application specific instruction is:
4. The application-specific virtual machine according to claim 1, wherein an instruction code composed of a plurality of words is shortened and replaced with an instruction code having a shorter length. Generation system.
The application specific instruction is:
The application-specific virtual machine generation system according to any one of claims 1 to 3, wherein a plurality of instruction codes are integrated and replaced with an instruction code having a shorter length.
The application specific instruction is:
Reduce processing data to the number of bits corresponding to the expected value,
Or
4. The application-specific virtual machine generation system according to claim 1, wherein an address of the processing data is changed to a position identifier shortened to a bit number corresponding to an assumed address.
The application specific instruction is:
4. The application-specific virtual machine generation system according to claim 1, wherein the instruction code bits are shortened by limiting the number of instruction codes.
1) specialized instruction defining means for defining virtual machine instructions (application specialized instructions) specialized for each application;
2) Compiler generation means for generating a compiler capable of generating special instruction embedded code combining the defined application specific instruction and a general-purpose virtual machine instruction;
3) interpreter generating means for generating an interpreter capable of interpreting and executing the specialized instruction embedded code;
4) Specialized instruction embedded code generation means for generating application-specific instruction embedded code by compiling source code written in a general-purpose programming language with the compiler generated by the compiler generation means;
An application-specific virtual machine generation device characterized by comprising:
1) a specialized instruction definition step for defining a virtual machine instruction (application specialized instruction) specialized for each application;
2) a compiler generating step for generating a compiler capable of generating a specialized instruction embedded code combining the defined application specialized instruction and a general-purpose virtual machine instruction;
3) an interpreter generation step for generating an interpreter capable of interpreting and executing the specialized instruction embedded code;
4) A specialized instruction embedded code generation step of generating an application specific instruction embedded code by compiling a source code written in a general-purpose programming language with the compiler generated by the compiler generation unit;
An application-specific virtual machine generation method characterized by comprising:
A transfer step of transferring the interpreter generated by the interpreter generation step and the application-specific instruction embedded code generated by the specialized instruction embedded code generation step to a target computer;
The application-specific virtual machine generation method according to claim 9, further comprising:
A circuit configuration step in which the interpreter generated by the interpreter generation step is configured by a nonvolatile logic circuit using a nonvolatile element, and a part of a circuit board of a target computer is configured by the nonvolatile logic circuit;
On the target computer,
A transfer step of transferring the application-specific instruction embedded code generated by the specialized instruction embedded code generation step;
The application-specific virtual machine generation method according to claim 9, further comprising:
In the special instruction embedded code generation step, the source code of the pre-update program and the source code of the post-update program are respectively compiled by the compiler, and the application special instruction embedded code of the pre-update program and the application special of the post-update program are compiled. Analyzing embedded instruction embedded code and generating application specific instruction embedded differential code,
The interpreter merges and interprets the application-specific instruction embedded differential code and the application-specific instruction embedded code before update.
12. The application-specific virtual machine generation method according to claim 9, wherein the application-specific virtual machine is generated.
Computer
1) Specialized instruction definition means for defining virtual machine instructions (application specific instructions) specialized for each application,
2) Compiler generation means for generating a compiler capable of generating a special instruction embedded code combining the defined application specific instruction and a general-purpose virtual machine instruction;
3) interpreter generating means for generating an interpreter capable of interpreting and executing the specialized instruction embedded code;
4) Specialized instruction embedded code generation means for generating application specific instruction embedded code by compiling source code written in a general-purpose programming language with the compiler generated by the compiler generation means,
Application-specific virtual machine generation program to function as.