WO2014140082A1 - High efficiency solar cells on silicon substrates - Google Patents

High efficiency solar cells on silicon substrates Download PDF

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Publication number
WO2014140082A1
WO2014140082A1 PCT/EP2014/054803 EP2014054803W WO2014140082A1 WO 2014140082 A1 WO2014140082 A1 WO 2014140082A1 EP 2014054803 W EP2014054803 W EP 2014054803W WO 2014140082 A1 WO2014140082 A1 WO 2014140082A1
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layer
buffer layer
active layer
substrate
portions
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PCT/EP2014/054803
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French (fr)
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Hans VON KÄNEL
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Pilegrowth Tech S.R.L.
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Priority to US61/779,511 priority
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Publication of WO2014140082A1 publication Critical patent/WO2014140082A1/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L31/00Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L31/00Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H01L31/035281Shape of the body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L31/00Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus peculiar to the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0687Multiple junction or tandem solar cells
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/54Material technologies
    • Y02E10/544Solar cells from Group III-V materials

Abstract

Structures and methods for the formation of efficient solar cells from lattice and thermally mismatched semiconductor materials on Si substrates which minimize the effect of cracks and other defects on cell performance.

Description

HIGH EFFICIENCY SOLAR CELLS ON SILICON SUBSTRATES

DESCRIPTION

Cross reference to related applications

This application claims the priority of the US Provisional Application No. 61/77951 1 tiled 13 March 2013. It is related to the International patent application WO 201 1/135432, filed April 26, 201 1 by Hans von Kane I. and Leonida M iglio, entitled DISLOCATION AND STRESS MANAGEMENT BY MASK-LESS PROCESSES USING SUBSTRATE PATTERNING AND M ETHODS FOR DEVICE FABRICATION", the entire disclosure of which is hereby incorporated by reference.

Field of the Invention

The invention relates to structures suitable for high-efficiency single and multiple junction solar cells on Si substrates and methods for their fabrication.

Background of the invention

Current triple-junction solar cells can reach efficiencies around 40 % and consist of Gao.5Ino.5P, Gao.98lno.02As, and Ge cells lattice-matched to a Ge substrate, which acts as the bottom cell.

Even higher efficiencies have been demonstrated for lattice mismatched

(metamorphic) ceils on GaAs substrates, wherein the bottom Ge cell is replaced by an InGaAs cell (see for example J.F. Geisz et al., Applied Physics Letters 93, 1 23505 (2008).

Replacing expensiv e, fragile and heavy Ge substrates with large, mechanically stable and inexpensive Si wafers has been considered highly desirable for decades.

Yet most materials from which such ceils are made are characterized by lattice spacings differing significantly from those of Si.

Growing an epitaxial layer on a lattice mismatched substrate results in mechanical stress, which, when exceeding a certain limit, is relieved by plastic relaxation.

In high misfit systems, plastic relaxation is usually preceded by elastic relaxation, whereby the surface does not remain flat. For lower misfit, an epitaxial film may remain flat, while stress is relieved exclusively by misfit dislocations. Misfit dislocations are accompanied by threading arms extending to the surface of the growing film.

These threading dislocations can be very detrimental to the functioning of a device if they traverse its active region. The density of threading dislocations should therefore be kept as low as possible.

There are several ways to lower threading dislocation densities (TDD).

One approach is based on compositional grading of relaxed buffer layers, as described for the example of Sii_xGex/Si(001) in the US patent No. US 5,221 ,413 to Brasen et al .

When graded up to a final Ge content of 100%, such buffer layers can be considered as a virtual Ge substrate nearly lattice matched to GaAs.

Compositional grading has also been used in the metamorphic ceils grown on GaAs substrates mentioned above (see for example J.F. Geisz et al.. Applied Physics Letters 93, 123505 (2008).

The grading approach is suitable from the point of view of dislocation reduction, for example with TDDs for Ge/Si(001) in the best case dropping to values in the low 106 cm range.

On the other hand, this example has the drawback of a large buffer layer thickness of about 10 tun. With the thermal expansion coefficients of Ge and GaAs (or other III-V compounds ) exceeding that of Si by about a factor of two, layer cracking during cooling from the growth temperature becomes a serious problem (see for example V. K. Yang et al., Journal of Applied Phy sics 93, 3859 (2003 ).

Another approach involves a reduction of the epitaxial growth area, i.e., by making the epitaxial structures small.

This can be achieved for example by providing the substrate with a dielectric mask, exposing the clean semiconductor surface only within mask openings previously defined by lithography and etching.

The idea behind is that, for sufficient layer thickness, threading arms arising from the interface will exit through the sides of the epitaxial structure, rather than reaching the upper surface.

The concept was applied to various semiconductor combinations, such as Si, Ge, III-V materials, 11- VI materials, all of w hich are characterized by 60-degree dislocations gliding in { 1 1 1 } planes (see for example the UK. patent application No. GB22 1 55 14 to Goodfellow et al).

Similarly, the concept was appl ied to GaAs mesas grown into oxide openings on Si(001) by molecular beam epitaxy (MBE) or chemical vapour deposition (CVD) (see for example the US patent No. US 5, 158,907 to Fitzgerald.

The technique, also termed "epitaxial necking", was shown to be effective not only in reducing TDDs in GaAs mesas grown on Si by MBE, but also in eliminating cracks (see for example Fitzgerald et al .. Journal of Electronic Materials 20, 839 ( 1991 ).

The idea of causing defects to terminate at non-crystal line side walls has, in addition to "epitaxial necking", become known also under the name of "Aspect ratio trapping (ART)". Even sessile dislocations oriented along the growth direction may reach the side walls w hen the oxide openings are filled by faceted material in addition to the 60-degrce dislocations gliding in { 1 1 1 } gl ide planes (see for example the International patent application No. WO2008030574 to Bai et al.).

A further extension of the technology of TDD reduction involved combining the described patterning by means of dielectric masks with selective epitaxy, followed by epitaxial lateral overgrowth (ELO). For the example of Ge on Si(OOl) it was argued that by continuing the process until coalescence one may hope to obtain essentially defect-free continuous films (see for example Langdo et al .. Applied Physics Letters 76, 3700 (2000).

Unfortunately, however, the process has been found to be accompanied by the accumulation of high TDDs in the region of coalescence (see for example Fiorenza et al., ECS Transactions 33, 963 (2010).

The technology described above, i.e., substrate patterning allowing for "epitaxial necking" or ART, has been appl ied to the fabrication of electronic and optoelectronic devices made from lattice mismatched materials (see for example the US patent appl ication No. US2009039361 to Li ct al. ).

The possibil ity to replace Ge-wafers by Si -wafers as substrates for multi-junction solar cells has been identified as another important application of ART.

This application implies the epitaxial growth of relatively thick layer stacks, unless cells are grown on both sides of the substrate.

In this latter approach, taking the exam le of a triple-junction cel l, the sub-cell with an intermediate band gap of about 1 . 1 eV is made from the Si substrate, while the sub-cell with the largest band gap is typically made from InGaP, by an ART process applied for example to the top surface, as wel l as the sub-cel l with the smallest band gap by another ART process on the bottom surface of the substrate (see for example the US patent application No. US2009065047 to Fiorenza et al.).

The approach of fabricating sub-cells on both sides of a Si-wafer minimizes the problem of thermal layer cracking because of relatively thin epi layers. The narrow trenches of 300 500 urn typically used in ART may in addition allow for some elastic relaxation, as w ell as the somewhat compliant nature of the Si02 mask.

In view of frequent thermal cycling during solar cell operation, it may, however, still be disadvantageous to have a structure composed of laterally varying thermal properties. Moreover, the concept requires the use of wetting layers, which, in addition to the dislocation trapping regions, absorb some of the solar radiation, thus lowering the cell efficiency. The problems with thermal mismatch appear to become even more significant when multi-junction solar cel ls are grown on the same side of a Si substrate by using ART and ELO processes.

The conventional triple-junction cel l requires the bottom sub-cell made from Ge preferably to be about 20 iim thick for current matching reasons. With layer cracking due to thermal mismatch setting in above about 5 iim, it is unlikely that such a configuration will ever work.

As a possible alternative, a triple-junction in which al l sub-cel ls are made entirely from l l l-V materials has been suggested ( see for example the International patent application No. WO2010033813 to Fiorcnza et al.).

In this type of cell the Ge no longer acts as an active material but needs to form a coalesced layer by an ART + ELO process, before growing the active l l l-V layer stack. The coalesced Ge layer and the active l l l-V layers, containing graded layers to accommodate the lattice constants betw een mismatched l l l-V layers, are, altogether at least 5 iim thick, such that Wafer bow ing and/or layer cracking are expected to become serious obstacles during further device processing and solar cell operation.

Another approach for solving mismatch problems involves deep substrate patterning and epitaxial growth after removal of the dielectric mask (see for example the International patent application No. WO201 1 135432 to von Kanei and iglio).

Here, tall epitaxial islands are grown onto elevated substrate structures, such as pillars or ridges as opposed to openings in a dielectric mask.

In this case, dislocations escape through the free surfaces of the epitaxial islands instead of exciting through the interface between the epitaxial material and the dielectric, as in ART.

Moreover, in this approach layer cracking does not occur since continuous layers are prevented from forming through the use of low surface diffusion lengths combined with mutual flux shielding by neighbouring epitaxial islands.

Wafer bowing on the other hand can still occur by material depositing at the side walls of etched subst rate feat ures or on the bottom of t renches.

There is thus a need for methods permitting the fabrication of semiconductor dev ices w hich do not suffer from wafer bowing, excessive dislocation formation and layer cracking.

Especially, there is a need for methods permitting the fabrication of multiple-junction solar cells on large area Si substrates with efficiencies matching or approaching the efficiency of cells fabricated on Ge or gallium arsenide wafers. Brief description of the invention

The present invention thus provides a solar cel l structure, according to the following claim 1 and related dependent claims.

In a further aspect, the present invention relates to a method of forming a solar cell structure, according to the following claim 1 1 and related dependent claims.

Brief description of the drawings

Fig. I A- 1 , 1A-2, I B, 1C, ID, 1 E schematically show a first embodiment of the solar cel l structure and method, according to the invention;

Fig. 2 schematically shows a further embodiment of the solar ceil structure and method, according to the invention;

Fig. 3 schematically shows a further embodiment of the solar cell structure and method, according to the invention;

Fig. 4A-4B schematically show a further embodiment of the solar cell structure and method, according to the invention;

Fig. 5A-5B schematical ly show a further embodiment of the solar cell structure and method, according to the invention.

Detailed description of the preferred embodiments

As described above, the invention relates to solar ceil structures and to methods suitable for fabrication of said solar ceil structures from lattice mismatched semiconductor layers on Si substrates.

Its aim is to solve the problems arising from, replacing Ge substrates used for high- efficiency single and multiple junction cells with light, large area Si substrates. These problems are mainly wafer bowing, layer cracking and excessive dislocation formation.

First embodiment

A first embodiment of the invention will now be described in relation to Fig. lA-1 ,

1 A-2.

It relates to a solar cell structure 100 and a fabrication process thereof, wherein the problem of wafer bowing and layer cracking by differences of thermal expansion coefficients is minimized.

The solar cell structure 100 comprises a substrate 1 10 and an active layer stack.

For the sake of clarity, the active layer stack is her defined as the portion of the solar cell structure, in which the absorption and transformation of solar radiation into electrical current is operated. The substrate 110 is made of Si.

The fabrication method of the solar cell structure 100 thus comprises the step of prov iding the Si substrate 1 10, e.g. by processing a Si wafer.

The substrate 110 of the solar ceil structure 100 is shown in cross-section in Fig. lA-1 and in plan-view in Fig. 1 A-2.

The substrate 1 10 comprises a bottom region 1 1 OA and one or more elevated regions 1 14 that protrude from the bottom region 1 10A.

The substrate 110 comprises one or more trenches 124, 128, 129 that bound the elev ated regions 1 14.

Preferably, the substrate 1 10 is patterned and comprises a plurality of elevated regions

1 14, which are separated by the trenches 124, 128, 129.

The elevated regions 114 comprise one or more upper surfaces 118 whereas the trenches 124, 128, 129 comprise one or more side walls 126 and one or more bottom walls

125.

The elevated regions 1 14 and the trenches 124, 128, 129 may be obtained by selectively etching the substrate 100.

The length L of the elevated regions 1 14 may range from about 1 m to 10 iim, or preferably from about 10 iim to 100 iim.

The elev ated regions 1 14 of this size are preferably chosen in accordance ith typical crack distances on the order of 100 iim in the solar cell structure 100.

In an aspect of the embodiment suitable for solar cell designs where thermal crack formation is of lesser concern, larger lengths L may be permissible, for example from 100 iim to 1 mm, or from 1 mm to about 1 cm, or even several cm, for example 4 cm.

The length L may even span the diameter of the wafer in which the substrate 100 is realized.

For example, this may occur for smaller differences of thermal expansion coefficients or thinner layers and for solar cells w ith metal grids designed to minimize the effect of cracks on solar cell performance.

The width W of the elevated regions 1 14 may range from about 1 iim to 10 iim, or from 10 iim to 100 iim.

In an aspect of the embodiment suitable for solar ceil designs for which thermal crack formation is of lesser concern, the width W may range from 100 iim to about 1 mm or from about 1 mm to 1 cm, or even several cm, for example 4 cm.

The width W may ev en span the diameter of the wafer in which the substrate 100 is realized.

For example, this may occur for smaller differences of thermal expansion coefficients or thinner layers and for solar ceils with metal grids designed to minimize the effect of cracks on solar cell performance.

The rectangular shape of the elevated regions 114 is shown for purposes of illustration only. Other shapes of the elevated regions 114 are possible as well as patterns of different symmetry.

The elevated regions 1 14 may for example be quadratic, where the length L of the squares may range from about 1 iim to about 10 iim, or preferably from about 10 iim to about 100 iim. Even larger sizes from about 100 μπι to I mm, or from about 1 mm to 1 cm, or even several cm, for example 4 cm, may be permissible for solar cell designs for which thermal crack format ion is of lesser concern. The length L may even span the diameter of the wafer.

The side walls 126 of the trenches 124, 128, 129 may not be vertical, i.e. arranged substantially perpendicular with respect to the bottom region 11 OA of the substrate 100. The trenches 124, 128, 129 may for example be under-etched. Moreover, they may not all have the same width.

In Fig. 1 A -2 an example is shown with trenches of three different widths di, d2, and As a result of the different trench widths, the elevated substrate regions 1 14 may be arranged in blocks 127.

The depth h of the trenches 124, 128, 129 may preferably range from about 1 iim to about 10 iim, or from about 10 iim to about 100 iim.

Their widths di, d2,

Figure imgf000008_0001
may range from about 1 iim to about 5 inn, or from about 5 iim to about 20 iim. It is advisable to provide wider trenches to larger depths.

Thei aspect ratio h/d (trench depth to trench width) may for example range from about 1 to 5, or preferably from about 2 to 5. Even larger aspect ratios may help in reducing material deposition on the side wails 126 and bottom wails 125 in the subsequent epitaxy steps (see for example Figs. IB, 1C).

The substrate 1 10 may be a Si-wafer with a resistivity between about 1 mOcm and 10 mOcm, or preferably between about 10 mOcm and 100 mOcm, or between about 100 mOcm and 1 Ocm, or about 1 Ocm to about 100 Ocm, or even from about 100 Ocm to about 10 kOcm. The doping can be either of p-type or n-type, depending on the kind of solar cell structure grown on top.

The substrate 110 may be a Si(001) wafer, misoriented towards a [110] direction in order to facilitate the formation of double layer surface steps which have been found to be useful for eliminating anti-phase domains during growth of the active layer stack comprising l l l-V compound semiconductor layers.

Selective etching of the substrate 100 may involve the adoption of masking and etching techniques of known type.

Referring now to Fig. I B, the solar cell structure 100 comprises at least a buffer layer 130 that is superimposed on the substrate 1 1 0.

For the sake of clarity, the relative position of the layers of the solar cel l structure 100 is here referred to a growth direction G of the solar cell structure 1 00, which is directed distal ly w ith respect to the bottom portion 1 1 OA of the substrate 100 (figure IB), as normal ly employed in planar semiconductor processing technologies.

The fabrication method of the solar cel l structure 100 thus comprises the step of providing the buffer layer 130 on the substrate 1 10.

The buffer layer 1 30 is an epitaxial semiconductor layer that is grown on the substrate

1 1 0.

The buffer layer 1 30 may or may not be thermally and lattice mismatched with the substrate 1 10.

The buffer layer 1 30 may or may not form a part of the active layer stack of the solar cel l structure 100, i.e. it may not contribute significantly to the absorption and transformation of solar radiation.

In both cases, the buffer layer 1 30 may assure the presence of double layer steps suitable for the growth of epitaxial compound semiconductor layers free of anti-phase domains.

The buffer layer 130 may act as a layer for lattice parameter matching to facil itate subsequent growth of f urther layers of the active layer stack, which comprises at least one active layer 1 50 made from l i i-V compound semiconductor materials. Lattice parameter matching may for example be achieved by grading the buffer layer 130.

In other cases, the buffer layer 1 30 may also act both as a lattice parameter matching layer and as part of the active layer stack of the solar cell structure 100.

Preferably, the buffer layer 130 is an epitaxial layer of semiconductor material.

The buffer layer 1 30 may for example be a Ge layer or a compound semiconductor layer, such as a graded SiGe layer, a graded GaAsP layer, a graded InGaP layer, or any other layer providing lattice parameter matching for example to a GaAs layer.

If it is made of Ge, the buffer layer 130 is thermally and lattice mismatched with the substrate 1 1 0. If it is made of given semiconductor compounds (e.g. GaP), the buffer layer 130 may be thermally and/or lattice matched with the substrate 1 1 0.

If it does not form part of the active layer stack, the buffer layer 130 may be thick just a few monolayers (where a monolayer is single packed layer of atoms or molecules), or thick from a few monolayers to about 1 0 nm, or from about 1 0 nm to 1 00 nm, or from about 100 nm to 1 iim, or even from about 1 iim to about 10 urn.

If it forms part of the active layer stack, the buffer layer 1 30 may be thick from about 1 00 nm to 1 iim, or from about 1 iim to 1 0 iim, or even from about 1 0 iim to at least 20 iim. For example, a Ge buffer layer with a thickness of about 2 iim to 3 iim may be sufficient for use as the bottom ceil in a dual or triple junction solar ceil.

The buffer layer 1 30 is grown on the substrate 1 1 0, so that one or more first portions 133 of it are superimposed on the elevated regions 1 14 of the substrate 1 10.

The first portions 133 of the buffer layer 130 comprise one or more first upper facets 1 39, which may be substantially horizontal, i.e. arranged substantial ly paral lel with respect to the bottom region 1 1 OA of the substrate 1 10, and one or more first side facets 138, which may be substantially vertical, i.e. arranged substantial ly perpendicular with respect to the bottom region 1 10A of the substrate 1 10

The first portions 1 33 of the buffer layer 1 30 may comprise one or more first inclined facets 132.

The solar ceil structure 100 comprises one or more first gap regions 130A that bound the first portions 1 33 of the buffer layer 1 30.

When the substrate 1 10 is patterned and comprises a plurality of elevated regions 1 14, the first gap regions 1 3 OA separate adjacent first portions 1 33 of the buffer layer 1 30, which are grown on adjacent elevated regions 1 1 4. In this case, each first gap region 1 30 A is defined by the first side facets 138 and by the first inclined facets 1 32 of adjacent first portions 1 33 of the buffer layer 1 30.

Each first gap region 1 30 A is positioned above a corresponding trench 1 24, 128, 1 29 of the substrate 1 10 to form a common groove.

Depending on the method of growth, the buffer layer 1 30 may grow in a more or less con formal manner, so that first side material 1 36 of the buffer layer 1 30 may be present on the side walls 1 26 of the trenches 1 24, 128, 1 29. There may also be first bottom material 1 34 of the buffer layer 1 30 on the bottom wal ls 1 25 of the trenches 124, 128, 1 29.

The deposition of material 1 34, 1 36 of the buffer layer 1 30 on the walls 1 34, 1 36 of the trenches 124, 128, 1 29 may cause the obstruction of said trenches and of the corresponding first gap regions 1 0 A.

The buffer layer 1 30 may be doped, for example to a level between 1016 and 1017 cm"3,

17 3 18 3 18 3 19 3 or preferably between 1 0 cm and a few 10 cm , or even between 1 0 cm and 1 0 cm .

As mentioned above, the solar cell structure 100 comprises at least one active layer 1 50 that is superimposed on the buffer layer 130.

The fabrication method of the solar cel l structure 100 thus comprises the step of providing the at least one active layer 1 50 on the buffer layer 130.

For the sake of clarity, it is evidenced that the solar cel l structure 100 may comprise a single active layer 1 50 in some embodiments (e.g. in the embodiment shown in figures 1 B- 1E) and a plurality of active layers in other embodiments (e.g. in embodiments similar to the one shown in figure 4A).

The at least one active layer 1 0 is an epitaxial semiconductor layer that comprises I I I- V compounds of semiconductor materials.

The at least one active layer 1 50 is grown on the buffer layer 130 and forms a part of the active layer stack of the solar cell structure 1 00, i.e. it contributes significantly to the absorption and transformation of solar radiation.

The at least one active layer 1 50 is grown on the buffer layer 1 30, so that one or more second portions 1 53 of it are superimposed on the first portions 1 33 of the buffer layer 130.

The second portions 1 53 of the at least one active layer 1 50, which are grown on the first upper facets 139 of the first portions 133 of the buffer layer 130, comprise one or more second upper facets 1 59, which may be substantial ly horizontal, i.e. arranged substantially paral lel with respect to the bottom region 1 1 OA of the substrate 1 10, and one or more second side facets 158, w hich may be substantially vertical, i.e. arranged substantially perpendicular with respect to the bottom region 1 10A of the substrate 1 1 0

The second portions 1 53 of the at least one active layer 1 50 may comprise one or more second inclined facets 152.

The solar ceil structure 100 (in particular the active layer stack) comprises one or more second gap regions 150A that bound the second portions 1 53 of the at least one active layer 150.

When the substrate 1 10 is patterned and comprises a plurality of elevated regions 1 14, the second gap regions 150A separate adjacent second portions 153 of the at least one active layer 1 50, w hich are grown on adjacent first portions 133 of the buffer layer 1 30 that are in turn grow n on adjacent elevated regions 1 14. In this case, each second gap region 1 50 A is defined by the second side facets 158 and by the second inclined facets 152 of adjacent second portions 153 of the at least one active layer 150.

Each second gap region 1 50 A is positioned above a corresponding first gap region 130A that is in turn positioned above a corresponding trench 124 of the substrate 1 10 to form a common groove.

The at least one active layer 150 may comprise second side material 156 on the side walls 1 26 of the trenches 124, 128, 1 29 or covering the first side material 136 of the buffer layer 130, which is deposited thereon.

The second side material 156 of the at least one active layer 150 may cover also the first side facets 138 and first inclined facets 1 32 of adjacent first portions 133 of the buffer layer 1 30.

The at least one active layer 150 may also comprise second bottom material 154 on the bottom walls 125 of the trenches 124, 128, 1 29 or covering the first bottom material 134 of the buffer layer 1 30, which is deposited thereon.

The deposition of material 1 54, 1 56 of the at least one active layer 1 50 on the walls 134, 1 36 of the trenches 124, 128, 129 and/or on facets 1 32, 138 of adjacent first portions 1 33 of the buffer layer 130 may cause the obstruction of said trenches, of the corresponding first gap regions 1 30 A and of the corresponding second gap regions 130 A.

As a result of the deposition of material of the buffer layer 1 30 and of the at least one active layer 1 50 on the walls 1 34, 136 of the trenches 124, 128, 1 29, the trench widths d i , d2, d3 may be chosen to be wide enough to prevent the obstruction of said trenches, of the corresponding first gap regions 130 A and of the corresponding second gap regions 150A.

The presence of material 136, 1 56 on the side walls 1 26 of the trenches may be disadvantageous for solar cel l operation because of increased leakage currents through regions of heavily dislocated material.

The presence of material 134, 1 54 on the bottom walls 125 of the trenches may be undesirable because of increased wafer bowing.

Finally, the inclined facets 132 of the first portions 133 of the buffer layer 130 m ay- compl icate the growth of the at least one active layer 1 50 because they may exhibit different surface diffusion lengths with respect to the corresponding upper facets 139.

Referring now to Fig. 1C, the fabrication method of the solar cell structure 1 00 may comprise the step of performing a chemical mechanical polishing (CMP) step of the buffer layer 1 30 before growing the layer 1 50 thereon.

In this way, the first incl ined facets 1 32 of the first portions 133 of the buffer layer 1 30 are preferably removed. When a CMP step is employed, the thickness of the buffer layer 130 is preferably chosen to be somewhat thicker than a buffer layer 130 which is not subject to CMP.

For example, for a Ge buffer layer 130, the thickness is preferably in the range of 3 iim to 5 iim.

When the indirect gap of Ge is to contribute to its photocurrent generation, a thickness of about 5 lira to 1 0 iim, or even about 1 0 iim to 30 iim may be more suitable.

Apart from facet removal, performing a CMP on the buffer layer 130 has the additional benefit of restoring the surface misorientation of this latter.

Indeed, the upper facets 139 of the fi st portions 133 of the buffer layer 1 30 hav e been found to slowly rotate towards the exact (001 ) orientation as growth proceeds, especial ly when elevated regions 1 14 of the substrate 1 10 hav e dimensions comparable to surface diffusion lengths.

Further, double layer steps, which may be advantageous for the subsequent growth of the at least one active layer 1 50 (particularly for a single-domain l l !-V active layer stack), are more likely to form as a result of the CMP.

As shown in figure 1C, the material 1 34, 136 of the buffer layer 1 30, which is deposited on the walls 125, 126 of the trenches 124, 128, 129, can also be removed by the chemical etching action of the CMP step, which, in addition, may serve as an epi-ready treatment for the first portions 133 of the buffer layer 130.

The chemical etching action on the buffer layer 130 may lead to some ov er-etching of side facets 138 of the first portions 1 33, whereby the upper surface 1 18 of the elevated regions 1 14 may be partial ly exposed and one or more substrate steps 1 1 9 may form.

Subsequent growth of the at least one activ e layer 1 50 may again result in partial ly con form a I coverage of the substrate steps 1 19 and of the walls 125, 126 and/or of the side facets 138 of the first portions 1 33 by material 1 54, 1 56 of the at least one active layer 1 50, as shown in Fig. 1C.

According to another aspect of the embodiment, the growth of the at least one activ e layer 1 50 is performed directly on the buffer layer 130, without an intermediate CMP step.

This simpl ified fabrication procedure may be adopted especially when the length L and width W of the elevated regions 1 14 are relatively large, for example 50 200 iim.

Such a simpl ified fabrication procedure may be even more favourable for still larger lengths L and widths W, for example 200 urn to 1 mm, or 1 mm to 1 cm, or for several cm up to the size of the entire wafer.

Moreover, for such a simpl ified fabrication procedure to be appl icable, the extension of the first inclined facets 132 of the first portions 1 33 should preferably be small, for example just a few μηι. Small sized facets 132 may easily be achieved by depositing the buffer layer 130 under conditions in which surface diffusion lengths are small, i.e. for example at low substrate temperatures or high deposition rates.

Referring now to Fig. ID, the fabrication method of the solar cell structure 1 00 preferably comprises also the step of performing an etching of the buffer layer 1 30 and of the at least one active layer 1 50.

Etching of the buffer layer 130 and of the at least one active layer 150 results in the complete removal of material 136, 1 56 of the layers 1 30, 1 50 from the side walls 126 of the trenches 124, 128, 129.

Preferably, etching of the buffer layer 1 30 and of the at least one active layer 1 50 is performed so that material 1 34, 1 54 of the layers 130, 1 50, which is deposited on the bottom wall 125 of trenches 124, 128, 129, is also removed.

Preferably, etching of the buffer layer 130 and of the at least one active layer 1 50 is performed so that material 156 of the at least one active layer 150, which is deposited on the first side facets 138 of the first portions 133 of the buffer layer 130, is removed.

Etching of the buffer layer 1 30 and of the at least one active layer 1 50 may be performed by any method known in the art, such as reactive ion etching, plasma etching or wet chemical etching.

Preferably, however, any ion damage occurring during reactive ion etching is subsequently removed, either in a low-energy plasma etching step or by a wet chemical etching step.

Referring now to Fig. IE, the complete formation of the solar cell structure 1 00 is shown.

The buffer layer 130 serves as a lattice parameter matching layer to the at least one active layer 1 50.

The buffer layer 1 30 may form the bottom cell of the solar ceil structure 1 00, for example in a standard triple-junction cell configuration.

In this case, the buffer layer 1 30 may consists of a Ge layer and it should preferably be between 10 and 20 um thick after the CMP and epi-ready treatments in order to ensure current matching of the bottom Ge cel l.

For applications permitting a certain loss of ceil efficiency, caused by the absence of indirect gap contributions to the photocurrent, the buffer layer 1 30 may also be chosen to be less than 10 um thick, for example 2 iim to 3 iim. For the standard triple-junction cell configuration, the at least one active layer 150 may form the top and middle ceil of the solar cell structure 100.

To form the middle ceil of the triple-junction solar ceil 100, the at least one active layer 1 50 consists of a Gain As alloy layer with a very small In content of about 2%, in order to be lattice matched to the Ge bottom cell (the buffer layer 130).

To form the top cell of the solar cel l structure 100, the at least one active layer 1 50 may then be a GalnP alloy with an In content of about 50%.

As shown in figures 1 B- 1 E, the cell structure 1 00 comprises one or more extended grooves 142 formed by the first gap regions 1 30 A in the buffer layer 130, by the second gap regions 1 50 in the at least one active layer 1 50 and by the trenches 124, 128, 129 of the substrate 1 10.

In practice, each extended groove 142 is a common groove formed by a trench 124, 128, 129 and the corresponding first gap region 13 OA and second gap region 150A that are in communication one to another.

Each extended groove 142 is thus substantially defined by the wal ls 125, 126 of the corresponding trench 124, 128, 129, by the first side facets 138 of the corresponding adjacent first portions 133 of the buffer layer 130 and by the second side facets 158 of the corresponding adjacent second portions 1 53 of the at least one active layer 1 50.

Each extended groove 142 spans from the upper facets 1 59 of corresponding adjacent second portions 1 53 of the at least one active layer 1 50 down to the bottom wall 125 of the corresponding trench 124, 128, 1 29, which separates the adjacent elevated regions 1 14, on which said second portions 153 are placed.

The trenches 1 24, 128, 1 29 of the solar cel l structure 1 00 are advantageously designed to assure absence of crack formation in the thick solar cell stack, as well as minimizing wafer bowing.

The fabrication method of the solar ceil structure 100 preferably comprises the step of performing a passivation of the buffer layer 1 30, of the at least one active layer 1 50 and of the trenches 124, 128, 1 29.

The first side facets 138 of the first portions 133 of the buffer layer 130, the second side facets 158 of the second portions 1 53 of the at least one active layer 1 50 and the walls 1 25, 1 26 of the trenches 1 24, 128, 1 29 are preferably covered by a passivation layer 1 60.

In other words, as shown in figures 1 E, the wal ls of each extended groove 142 arc preferably covered by the passivation layer 160.

Passivation may for example comprise a sulphur treatment as known in the art (see for example Zhou Lu et al., A ISOMT 20 1 1 ), and/or the deposition of a passivation layer 160 in a low temperature deposition process.

During the passivation step, the upper facets 159 of the second portions 153 of the at least one active layer 150 are instead not covered by the passivation layer 1 60, e.g. by means of suitable masking techniques.

The fabrication method of the solar cell structure 100 comprises the step of filling the extended grooves 1 42.

The extended grooves 142 are filled by filling material 1 62, which is preferably deposited in a low temperature deposition process.

The fil ling material 1 62 may be for example an oxide or an oxynitride, or a polymeric material.

Obviously, when passivation is employed, the groov es 142 are covered by a passivation layer 1 60 prior to their filling with the fil l ing material 1 62.

As shown in figure IE, the solar ceil structure 100 comprises one or more first metal contacts 166 to the top surface of the active layer stack (the surface of the at least one active layer 1 50 ).

Preferably, the first metal contacts 1 66 are positioned at least partial ly on the top of the extended grooves 142. Preferably, the first metal contacts 1 66 are at least partial ly placed on top of the filling material that fills said grooves..

The fabrication method of the solar ceil structure 100 thus comprises the step of forming the first metal contacts 166 to the active layer stack, preferably on top of the extended grooves 1 42 (and of the material fil ling said grooves).

In a preferred aspect of the embodiment, the passivation layer 160, which covers the walls of the extended grooves 1 42 and the trench fil ling material 1 62, which fills said grooves, do not extend to the very top of the extended grooves 142.

This may increase the contact area between the first metal contacts 166 and the surface of the at least one active layer 150.

Preferably, the forming of the first metal contacts 1 66 comprises the applying of stripes of metal over the filled grooves 142 in order to reduce the loss of active cell area formed by the at least one active layer 1 50.

For the sake of minimizing ceil loss by shadowing, the dimensions L and W of elevated regions 1 1 4, or, equivalently, the distances betw een trenches 1 24, 128, 1 29, are preferably chosen in the range of a few tens of iim, for example 50 iim or 100 urn.

Elevated substrate regions 1 14 sized many tens of iim may be somew hat disadvantageous in terms of threading dislocation densities, large values of which may reduce cel l efficiencies. This problem may. however, be solved by modifying the structure of the buffer layer 130, as may be seen by referring to the embodiment of Fig. 2.

As shown in figure IE, the ceil structure 100 comprises one or more second metal contacts 164 that are preferably formed on a bottom surface HOB of the substrate 1 10.

The fabrication method of the solar cell structure 100 may thus comprise the step of forming the second metal contacts 164.

Preferably, a single metal lic contact 164 is formed across the whole bottom surface HOB of the substrate 1 10.

Second embodiment

Referring now to Fig. 2, it is partially shown a solar cel l structure 200 that solves the problem of excessive threading dislocation densities.

Similarly to the solar ceil structure 100 described above, the solar ceil structure 200 comprises a substrate 2 1 0 having elevated regions 2 14 and trenches 220, 224.

The elevated regions 214 protrude from a bottom region 21 OA of the substrate 210 and are bounded by the trenches 220, 224.

The elevated regions 2 14 comprise upper surfaces 218 whereas the trenches 220, 224 comprise side walls 226 and bottom wal ls 225.

The solar cell structure comprises a buffer layer 2 0 that is grown on the substrate 2 1 0, so that first portions 233 of the buffer layer 230 are positioned on the elevated regions 2 14.

First side material 236, 238 of the buffer layer 230 may be present on side walls 226 of trenches 220, 224.

There may also be first bottom material 232, 234 of said buffer layer on the bottom walls 225 of trenches 220, 224.

The first portions 233 of the buffer layer 230, which are grown on the upper surface 218 of elevated substrate regions 2 14, comprise first upper horizontal facets 250, inclined facets 252 and side facets 235.

The first portions 233 of the buffer layer 230 are bounded by first gap regions 240,

242.

In the solar cell structure 200 of figure 2, the substrate 210 comprises wider trenches 224 having width d i and narrower trenches 220 having width d2, where the widths di, d2 of the trenches 220, 224 are different with d i > d2.

Preferably, the width d2 of the trenches 220 is selected such that the first gap regions 240 between the side facets 235 of the first portions 233 of the buffer layer 230, which are located above the narrower trenches 220, are obstructed during the epita ial growth of the buffer layer 230.

In other words, the buffer layer 230 above the elevated regions 2 14, which are separated by a distance d2, no longer consists of patches of material (the first portions 233) separated by finite gap regions 240, as for the solar cel l structure 1 00.

In the substrate 210, wider tranches 224 are separated by a distance Li whereas narrower trenches 220 are separated by a distance L2.

The distance 1.1 between the wider trenches 224 may preferably be in the range from 10 to 100 iim or for example from 100 iim to 1 mm, or even from 1 mm to 1 cm.

The range should be kept sufficiently smal l, however, to avoid the buffer layer 230 or the active layer stack of the solar cell structure 200 to crack.

For example, if the buffer layer 230 is made of Ge, the distance Li is preferably chosen to be smaller than 1 mm, for example 50 to 200 μηι.

Similar dimensions may ap ly to the dimension W of the elevated regions 2 14 in the direction perpendicular to the page of the drawing of Fig. 2 (see also the dimension W, in figure 1 A-2 ).

The distance L2 between the narrower trenches 220 is on the other hand preferably chosen smal l enough to al low the formation of first portions 233 of the buffer layer 230, hich have a "roof-top" shape, i.e. extended incl ined facets 252 and upper facets 250 with extension approximately equal to zero.

In practice, the distance L2 may for example be as larger as 1 to 2 iim, or preferably about 2 to 5 iim, or even 5 to 20 iim.

Basically, its exact choice depends on the method used for the deposition of buffer layer 230.

Typically, high substrate temperatures lead to large surface diffusion lengths, favouring the formation of incl ined facets 252.

The formation of the first portions 233 of the of the buffer layer 230 (and of the upper and inclined facets thereof) is schematically shown by the thin l ines 250 A, 252 A in figure 2. It is apparent how the extension of the upper facets 25 OA is reduced approximately equal to zero during the grow th of the buffer layer 230, so that the first portions 233 have a "roof-top" shape w hen the growth of the buffer layer 230 is completed.

The etching depth h i of the wider trenches 224 may be chosen to be about equal or larger than the etching depth h2 of the narrower trenches 220. It is, however, advisable to use aspect ratios of height hi to width d i and h2 to d2 of at least one, or preferably about 2 to 5.

A larger aspect ratio of 5 to 10 or even 10 to 20 may help in reducing the amount of material 236, 238 of the buffer layer 230 that is deposited on the side walls of both the w ider and narrower trenches 220, 224.

Large aspect ratios also help in l imiting the amount of material 232, 234 on the bottom of trenches 220, 224.

The "roof-top" shape of the first portions 233 of the buffer layer 230 may greatly help in reducing both the number of 60-degree dislocations 270 lying in { 1 1 1 } planes and dislocations 272 al igned along the growth direction of the buffer layer.

For 60-degree dislocations, "roof-top" faceting is not strictly required since the gl ide planes of said dislocations exit through the side walls 234 as long as the obstructed first gap regions 240 do not close too soon, and as long as the distance L2 is kept sufficiently small .

Vertical dislocations 272 on the other hand can be expel led from the buffer layer 230 only by their interaction w ith the incl ined facets 252, by which they are deflected towards the side walls 234.

The remaining structural features of the solar cell structure 200, which have not been mentioned for the sake of simpl icity, arc substantially similar or identical to the corresponding ones of the solar cell structure 100 described above.

The other process steps for fabricating the solar cel l structure 200, which have not been mentioned for the sake of simplicity, are substantial ly similar or identical to the corresponding ones outl ined for the solar cell structure 100 described above.

Referring now to Fig. 3, it is partial ly show n a solar cell structure 300 having flat, continuous buffer layer patches 333 A of size L i above the narrower trenches 320.

After its growth, the buffer layer 330 is subject to a CMP, whereby the incl ined facets 352 A of the first portions 333 of the buffer layer 330 are removed.

Providing a CMP on the buffer layer 330 restores the surface misorientation back to that of the Si substrate 3 10.

After the CMP, the flattened buffer layer 330 is subject to an epi-ready treatment, by means of which the material of the buffer layer 330, w hich covers the side walls 326 and the bottom walls 322 of the wider trenches 324, is completely or partially removed.

Such a chemical etching may cause some over-etching of the side facets 335 of first portions 333 of the buffer layer 330, which are separated by the (non-obstructed ) first gap regions 342 above the wider trenches 324.

One or more corners 336 of elevated substrate regions 3 14 may thus be exposed.

The solar cell structure 300 has similar appearance as the simpler structure of Fig. ID without the at least one active layer 1 50.

It has, however, the advantage of a greatly reduced threading dislocation density, even when the distance L ] between wider substrate trenches 324 is chosen to be large, for example 50 to 200 iim or even larger.

The remaining structural features of the solar cell structure 300, which have not been mentioned for the sake of simplicity, may be similar or identical to the corresponding ones of the solar cell structures 100, 200 described above.

in particular, structural elements 3 1 0, 3 14, 318, 320, 324, 325, 326, 334, 335, 338, 340, 342, 350A, 352A, 370, 372 of the cel l structure 300 correspond to structural elements 2 10, 214, 218, 220, 224, 225, 226, 234, 235, 238, 240, 242, 250A, 252A, 270, 272 of the solar cell structure 200.

The other process steps for fabricating the solar cell structure 300, which have not been mentioned for the sake of simplicity, may be similar or identical to the corresponding ones outlined for the solar ceil structures 100, 200 described above.

Third embodiment

Referring now to Fig. 4A, the solar ceil structure 400 comprises a substrate 410 having elevated regions 4 14 and trenches 424.

The solar cell structure 400 comprises an active layer stack 430 and a buffer layer 420.

The buffer layer 420 is a Ge (or SiGe) layer that is relatively thin, for example preferably as thin as 1 4 iim, or 1 00 nm to 1 iim, or 10 nm to 100 nm, or even 1 nm to 10 nm.

This solution has the advantage of minimizing the Ge consumption during the growth of the buffer layer 420 on the substrate 4 10.

The buffer layer 430 may also be formed according to the solution il lustrate in figures 2-3. In this case, very small elevated regions 414, for example 1 to 2 iim or even smaller, are advantageously formed in the substrate 41 0, where the buffer layer 420 is configured to consist of continuous patches of material.

Despite being thin, the first portions (not shown) of the buffer layer 420 may hence remain ful ly faceted according to a "roof-top" shape, such that dislocations are expelled, according to the solutions shown in figures 2-3.

For thicknesses below about 1 2 iim, the buffer layer 420 does not form part of the active layer stack and exclusively serves as lattice parameter matching layer to an the at least one active layer of the active layer stack 430.

In the solar cell structure 400, the active layer stack 430 comprises a plurality of superim osed active layers 43 1 , 432, 433, 434, 435 that are made entirely from i i l-V semiconductors.

The fabrication process of the cell structure 400 thus includes forming the superimposed active layers 43 1 , 432, 433. 434, 435 (according to the normal direction of growth G).

A first active layer 43 1 , which has the highest band gap, is preferably directly placed on top of the buffer layer 420.

The first active layer 43 1 may for example be a GalnP layer with an In content close to 50%, such that the layer is lattice matched to the Ge (or SiGe ) buffer layer 420 and has a band gap of about 1.84 eV.

A second active layer 432 is superimposed on the first active layer 43 1 . The second active layer 432 may for example be a graded (Al)GalnP layer whose final lattice parameter is chosen to be equal to that of a thi d active layer 433, which is superimposed on it.

The third active layer 433 may for example be an InGaAs layer with an In content of about 4%, giving rise to a band gap of about 1 .41 eV.

A fourth active layer 434 is superimposed on the third active layer 433.

The layer 434 may for example be a graded layer Galn layer, graded to a final lattice parameter corresponding to that of a fifth active layer 435, which is superimposed on the fourth active layer 434.

The fifth active layer 435 may for example be an InGaAs layer with an In content of about 37%, giving rise to a band gap of about 1 eV.

The indicated band gaps of the group of layers 430 have been shown to be close to the ones offering maximum efficiency of a triple-junction cell, albeit for a cel l stack grown on a GaAs substrate (see for example J.F. Geisz et al .. Applied Physics Letters 93, 1 23505 (2008), the entire disclosure of which is hereby incorporated by reference).

The cell structure 400 of Fig. 4 A permits the active layer stack 430 to be grown on Si substrates while solving the thermal mismatch problems encountered for continuous epitaxial films.

As for the other embodiments described above, the solar cell structure 400 comprises one or more grooves 442 that are formed by the first gap regions 420A obtained in the buffer layer 420, by the second gap regions obtained in the layers 43 1 -435 of the active layer stack 430 and by the trenches 424.

The fabrication process of the cell structure 400 of Fig. 4 A preferably includes passivating the walls of the grooves 442.

The fabrication process of the ceil structure 400 of Fig. 4A includes the filling of the grooves 442 with a filling material 450 and the forming of first metal contacts 462 to the active layer stack 430, as for the embodiments described above.

Preferably, the solar ceil structure 400 comprises one or more first metal contacts 462 covering a relatively wide portion of the upper surface 430B of the active layer stack 430.

The remaining structural features of the solar cell structure 400, which have not been mentioned for the sake of simplicity, are similar or identical to the corresponding ones of the solar cell structures 100, 200, 300, described above.

The other process steps for fabricating the solar cell structure 400, which have not been mentioned for the sake of simplicity, are similar or identical to the corresponding ones outlined for the solar ceil structures 100, 200, 300, described above.

Referring now to Fig. 4B, further preferred steps of the fabrication process of the cell structure 400 are shown.

The fabrication process comprises the further step of flipping the wafer on which the active layer stack 430 has been obtained.

Then, the fabrication process comprises the further step of gluing the activ e layer stack 430 to a heat sink component 470, so that the first metal contacts 462 are placed between the heat sink 470 and the active layer stack 430 (in particular between the heat sink 470 and the fifth layer 435 of the active layer stack 430).

The fabrication process then preferably comprises the step of removing the substrate

410.

Adv antageously, after the removal of the substrate 410, a surface 420B of the buffer layer 420, which is opposite to the contact surface to the first activ e layer 43 1 , remains free.

Further, the first gap regions 42 OA in the buffer layer 430 remain filled with the filling material 450 that fills the grooves 442.

The fabrication process then preferably comprises the step of forming second metal contacts 466 directly on the buffer layer 420 at the surface 420B of this latter.

Preferably, the second metal contacts 466 are superimposed on the filling material 450 that fills the grooves 442 at the first gap regions 420 A of the buffer layer 420.

The fabrication process then preferably comprises the step of forming a further passiv ation layer 480 on the free surface 420B of buffer layer 420 (according to a reference direction Gl).

The passivation layer 480 covers the surface 420B of the buffer layer 420 and is advantageously provided with windows at the second metal contacts 466.

The solar cell structure 400 of figure 4B is thus configured as a triple -junction solar cel l.

Further variants of the solar ceil structure 400 are possible. For example, the solar cell structure 400 may comprise multiple superimposed buffer layers 420 and/or a different number of active layers (even a single active layer) in the active layer stack.

Fourth embodiment

Referring now to Fig. 5, a further embodiment of a cel l structure 500, according to the invention, is shown.

The cell structure 500 comprises a Si substrate 510 that is patterned into elevated regions 5 14, separated by trenches 524, as shown schematical ly in the cross-section of Fig.

5A.

The side wal ls 526 of the trenches 524 need not be vertical (i.e. not substantially perpendicular with respect to the bottom portion 510B of the substrate 5 10). For example, they may be under-etched or exhibit V-groove shape.

The solar cell structure 500 comprises a buffer layer 530 and at least one active layer

550.

The solar cel l structure 500 comprises also a dielectric layer 528 that is superimposed on the side wal ls 526 and bottom w ails 525 of the trenches 524.

The fabrication process of the solar cell structure 500 thus comprises the step of depositing the dielectric layer 528 on the al ls 526, 525 of the trenches 524.

The dielectric layer 528 is deposited prior to the forming of the buffer layer 530 and of the at least one active layer 550.

The dielectric layer 528 may for example be a thermal or deposited oxide, which is deposited on the substrate 510 and then removed by an etching step from the top surface 518 of the elevated regions 5 14 to make this latter epi-ready.

Referring now to Fig. 5B, in the solar cel l structure 500 no material of the buffer layer 530 and of the at least one active layer 550 is deposited inside the trenches 524 because of the presence of dielectric layer 528 covering the wal ls 525. 526 of said trenches.

This may be achieved by using a selective growth technique for the buffer layer 5 0 and the at least one active layer 550, for example by employing CVD and MOCVD, respectively. The buffer layer 530 may comprise first inclined facets 532 that are formed during the selective CVD growth.

The at least one active layer 550 may comprise second inclined facets 552 that are formed during the MOCVD growth.

The facets 532, 552 may help in deflecting threading dislocations away from the active areas of the device.

The remaining structural features of the solar cell structure 500, which have not been mentioned for the sake of simplicity, arc similar or identical to the corresponding ones of the solar cell structures 1 00, 200, 300, 400, described above.

The other process steps for fabricating the solar cell structure 500, which have not been mentioned for the sake of simplicity, are similar or identical to the corresponding ones outl ined for the solar cell structures 1 00, 200, 300, 400, described above.

Advantages

An advantage of the present invention is the abil ity to use large, l ight and mechanically stable Si wafers as a replacement for heav ier and fragile Ge or GaAs substrates for high efficiency solar cel ls.

It is another advantage of the present invention that the thermal mismatch betw een a Si substrate and Ge and l i l-V semiconductor either does not lead to cell cracking during cooling from the growth temperature to room temperature at al l or minimizes the effect of cracks on cell performance.

it is a further advantage of the present invention that intense thermal cycl ing during solar cell operation, for example from - 100 C to +200°C does not lead to cell cracking or minimizes the effect of cracks on cell performance.

It is another advantage of the present invention that it allows Ge consumption to be minimized.

It is yet another advantage of the present invention that the efficiency reduction of solar cel ls made from lattice mismatched materials can be minimized by controll ing the dislocation density.

Claims

A solar cell structure ( 1 00, 200, 300, 400, 500) comprising an active layer stack ( 1 50, 430) and a Si substrate ( 1 10. 2 10, 3 10, 410, 5 10 ),
wherein said substrate comprises one or more elevated regions (1 14, 2 14, 3 14, 414, 5 14) bounded by one or more trenches ( 124, 128, 1 29. 220, 224, 320, 324, 424, 524); wherein said solar cell structure comprises:
- at least one epitaxial semiconductor buffer layer ( 1 30, 230, 330, 420, 530) on said substrate, said buffer layer having one or more first portions ( 1 33, 233, 333 ) superimposed on said elevated regions, said first portions being bounded by one or more first gap regions (130A, 240, 242, 340, 342, 420 A );
- at least one epita ial ! I I-V compound semiconductor active layer ( 1 50, 43 1 , 432, 433, 434, 435, 550) on said buffer layer, said at least one active layer being thermal ly and lattice mismatched with said substrate and being part of said active layer stack, said at least one active layer having one or more second portions ( 1 53, 253, 353 ) superimposed on the first portions of said buffer layer, said second portions being bounded by one or more second gap regions (150A, 430 A );
- one or more grooves ( 142, 442, 542 ) formed by said first gap regions, said second gap regions and said trenches, said grooves being filled by a filling material (162, 450);
- one or more first metal contacts (166, 462 ) to said active layer stack, said first metal contacts being at least partial ly placed on top of the fil ling material that fills said grooves.
The solar cel l structure of claim 1 wherein the size of said elevated regions is smaller than the distance between cracks in said active layer.
The solar cell structure of claim 1 w herein the size of said elevated regions is larger than the distance between cracks in said active layer.
The solar cel l structure of claim 1 , wherein said buffer layer comprises first upper facets ( 1 39) that are dislocation-free.
The solar cel l structure of claim 1 w herein said buffer layer is a lattice parameter matching layer to said at least one active layer.
The solar cel l structure of claim 1 w herein said trenches have walls ( 1 25, 1 26, 225, 226, 325, 326, 525, 526) free from material (134, 1 36, 1 54, 1 56, 232, 236) of said buffer layer and said at least one active layer.
The solar cel l structure of claim 1 , wherein said buffer layer is a Ge layer.
8. The solar cell structure of claim 1 , wherein said buffer layer is a compound semiconductor layer.
9. The solar cel l structure of claim 7, wherein said buffer layer has a maximum thickness of about 3 iim.
1 0. The solar cell structure of claim 7, wherein said buffer layer is at least 10 iim thick.
1 1. A method of forming a solar cell structure, said solar cell structure (100, 200, 300, 400, 500) comprising an active layer stack ( 1 50, 430 ) and a Si substrate (1 10, 2 10, 3 10, 4 10, 5 10),
wherein the method comprises:
providing said substrate (1 10, 2 1 0, 3 10, 4 1 0, 5 10 ) comprising one or more elevated regions (1 14, 2 14, 3 14, 4 14, 5 14 ) bounded by one or more trenches (124, 128, 129, 220, 224, 320, 324, 424, 524);
providing at least one epitaxial semiconductor buffer layer ( 1 30, 230, 330, 420, 530) grown on said substrate, said buffer layer having one or more first portions ( 133, 233, 333 ) grown on said elevated regions, said first portions being bounded by one or more first gap regions (130A, 240, 242, 340, 342, 420A);
providing at least one epitaxial l l l-V compound semiconductor active layer ( 1 50, 431 , 432, 433, 434, 435, 550) grown on said buffer layer, said at least one active layer being thermally and lattice mismatched with said substrate and being part of said active layer stack, said at least one active layer hav ing one or more second portions ( 1 53, 253, 353 ) grown on the first portions of said buffer layer, said second portions being bounded by one or more second gap regions (150A, 43 OA); providing one or more grooves ( 142, 442, 542 ) formed by said first gap regions, said second gap regions and said trenches, said grooves being filled by a filling material ( 162, 450 );
prov iding one or more first metal contacts (166, 466) to said active layer stack, said first metal contacts being at least partial ly deposited on top of the filling material that fil ls said grooves.
1 2. The method of claim 1 1 , wherein the size of said elevated regions is smaller than the distance between cracks in said at least one l l l-V compound semiconductor layer.
13. The method of claim 1 1 , wherein, the size of said elevated regions is larger than the distance between cracks in said at least one l l l-V compound semiconductor layer.
14. The method of claim 1 1 , wherein said buffer layer comprises first upper facets (139) that are dislocation-free.
1 5. The method of claim 1 1 , wherein said buffer layer is a lattice parameter matching layer to said at least one active layer.
16. The method of claim 1 1 , wherein it comprises at least one of the following steps:
growing said buffer layer and said at least one active layer by a selective growth technique, so that no material of said buffer layer and said at least one active layer is deposited on wails (125, 126) of said trenches.
17. The method of claim 1 1 , wherein said buffer layer is subjected to chemical mechanical polishing before epitaxial ly growing said at least one active layer.
18. The method of claim 1 1 , wherein said buffer layer is a Ge layer.
1 9. The method of claim 1 1 , wherein said buffer layer is a compound semiconductor layer.
20. The method of claim 18, wherein said Ge layer has a maximum thickness of about
3 iim .
21. The method of claim 18, wherein said Ge layer is at least 10 iim thick.
22. The method of claim 1 1 , wherein it comprises the step of growing an active layer stack (430) comprising a plurality of superimposed active layers (431 , 432, 433, 434. 435) on said buffer layer by a selective growth technique, so that no material of said active layers is deposited on wails said trenches.
23. The method of claim 1 1 , wherein it comprises the fol lowing steps:
gluing the active layer stack (430) of said cell structure (400) to a heat sink component (470) so that said first metal contacts (462) are positioned between said active layer stack and said heat sink;
removing said substrate (410), so that said buffer layer has a free surface (420B), opposite to the contact surface with said active layer stack;
forming second metal contacts (466) on said free surface of the buffer layer, said second metal contacts being superimposed on said filling material (450).
PCT/EP2014/054803 2013-03-13 2014-03-12 High efficiency solar cells on silicon substrates WO2014140082A1 (en)

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