WO2014110546A1 - Frequency multiplier - Google Patents

Frequency multiplier Download PDF

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Publication number
WO2014110546A1
WO2014110546A1 PCT/US2014/011400 US2014011400W WO2014110546A1 WO 2014110546 A1 WO2014110546 A1 WO 2014110546A1 US 2014011400 W US2014011400 W US 2014011400W WO 2014110546 A1 WO2014110546 A1 WO 2014110546A1
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WO
WIPO (PCT)
Prior art keywords
transistor
coupled
transformer
supply rail
frequency
Prior art date
Application number
PCT/US2014/011400
Other languages
French (fr)
Inventor
Swaminathan Sankaran
Vijaya B. RENTALA
Brian P. Ginsburg
Srinath M. Ramaswamy
Eunyoung Seok
Baher Haroun
Bradley A. Kramer
Franck Seigneret
Original Assignee
Texas Instruments Incorporated
Texas Instruments Japan Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Incorporated, Texas Instruments Japan Limited filed Critical Texas Instruments Incorporated
Priority to JP2015552877A priority Critical patent/JP6375307B2/en
Priority to CN201480004238.XA priority patent/CN104904115B/en
Priority to EP14737568.7A priority patent/EP2973997B1/en
Publication of WO2014110546A1 publication Critical patent/WO2014110546A1/en

Links

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M5/00—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases
    • H02M5/02—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc
    • H02M5/04—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters
    • H02M5/10—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters using transformers
    • H02M5/16—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters using transformers for conversion of frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B19/00—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source
    • H03B19/06—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes
    • H03B19/14—Generation of oscillations by non-regenerative frequency multiplication or division of a signal from a separate source by means of discharge device or semiconductor device with more than two electrodes by means of a semiconductor device
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M5/00—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases
    • H02M5/02—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc
    • H02M5/04—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters
    • H02M5/22—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M5/275—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M5/297—Conversion of ac power input into ac power output, e.g. for change of voltage, for change of frequency, for change of number of phases without intermediate conversion into dc by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal for conversion of frequency

Definitions

  • This relates generally to a frequency multiplier and, more particularly, to a frequency multiplier having lower direct current (DC) power consumption at radio frequency (RF) and millimeter-wave frequencies (e.g., wavelengths between about 0.1mm and 10mm).
  • DC direct current
  • RF radio frequency
  • millimeter-wave frequencies e.g., wavelengths between about 0.1mm and 10mm.
  • FIG. 1 shows an example prior frequency multiplier. As shown, this multiplier 100 operates to generate a differential output signal 2f * L o+ and 23 ⁇ 4 ⁇ >+ that has twice the frequency of the input differential signal f L o+ and 3 ⁇ 4 ⁇ In this example, the differential output signal 2f L o+ and 2fi £ )+ can function as a local oscillator signal for a modulator.
  • the input differential signal fi£>+ and fu in the example of FIG. 1, is provided to the gates of transistors Ql and Q2.
  • Transistors Ql and Q2 are arranged to form a differential pair of transistors that are coupled between a common node and a supply rail (e.g., ground).
  • Inductor L (which is coupled to a supply rail VDD at its center tap) is coupled to the common node of the differential pair Q1/Q2, along with the gate of transistor Q3 (which, as shown, is an NMOS transistor).
  • the source of transistor Q3 is also coupled to the inductor L.
  • the apparatus comprises a first supply rail; a second supply rail; a differential pair of transistors that are configured to receive a first differential signal having a first frequency; a transformer having a primary side and a secondary side, wherein the primary side of the transformer is coupled to the differential pair of transistors, and wherein the secondary side of the transformer is configured to output a second differential signal having a second frequency, wherein the second frequency is greater than the first frequency; a first transistor that is coupled to the first supply rail, the primary side of the transformer, and the differential pair of transistors, and wherein the first transistor is of a first conduction type; and a second transistor that is coupled to the second supply rail, the primary side of the transformer, and the differential pair of transistors, and wherein the second transistor is of a second conduction type.
  • the first transistor may have a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the first transistor is coupled to the primary side of the transformer, the second passive electrode of the first transistor is coupled to the first supply rail, and the control electrode of the first transistor is coupled to the differential pair of transistors.
  • the second transistor may have a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the first transistor is coupled to the primary side of the transformer, wherein the second passive electrode of the first transistor is coupled to the second supply rail, and wherein the control electrode of the first transistor is coupled to the differential pair of transistors.
  • the first supply rail may be ground.
  • the first transistor may be an N-type transistor, and the second transistor may be a P-type transistor.
  • the first transistor may be an NMOS transistor and the second transistor may be a PMOS transistor.
  • the apparatus comprises a first supply rail; a second supply rail; a first MOS transistor that is coupled between a common node and the first supply rail, wherein the first MOS transistor is configured to receive a first portion of a first differential signal at its gate, and wherein the first differential signal has a second frequency; a second MOS transistor that is coupled between the common node and the second supply rail, wherein the second MOS transistor is configured to receive a second portion of the first differential signal at its gate; a transformer having: a primary side with a first terminal, a second terminal, and a center tap, wherein the first terminal of the primary side of the transformer is coupled to the common node, and wherein the center tap of the primary side of the transformer is configured to receive a common mode voltage; and a secondary side with a first terminal, a second terminal, and a center tap, wherein the first terminal of the secondary side of the transformer is configured to output a first portion of a second differential signal, and wherein the center tap of the secondary side
  • the first, second, and third MOS transistors may be NMOS transistors, and the fourth transistor may be a PMOS transistor.
  • the second frequency may be twice the first frequency.
  • FIG. 1 is a diagram of an example of a conventional frequency multiplier with positive feedback
  • FIG. 2 is a diagram of an example of a frequency multiplier with positive feedback implemented in accordance with principles of the invention.
  • FIG. 2 illustrates an example frequency multiplier 200. Similar to multiplier 100, multiplier 200 can, for example, generate a differential output signal 23 ⁇ 4 ⁇ >+ and 23 ⁇ 4 ⁇ >+ that has twice the frequency of the input differential signal f L o+ and f L o-. There are, however, some differences in topology. Namely, inductor L has been replaced by transformer TR, and transistor Q4 (which can, for example, be a PMOS transistor) has been added. In this configuration, transistors Q3 and Q4 are arranged to be of opposite conduction types; for example, transistors Q3 and Q4 are shown to be NMOS and PMOS transistors, respectively.
  • transistors Q3 and Q4 are also coupled between supply rails (e.g., supply rail VDD and ground). Because these transistors Q3 and Q4 are commonly coupled to a terminal of the primary side of the transformer TR and because the gates of transistors Q3 and Q4 are coupled to the common node of differential pair Q1/Q2, these transistors Q3 and Q4 operate as "stacked" transconductance devices. By having this stacked arrangement (e.g., source of transistor Q4 being coupled to the drain of transistor Q3), current reuse between these transconductance devices (e.g., transistors Q3 and Q4) is permitted, which can, for example, double the transconductance density.
  • supply rails e.g., supply rail VDD and ground.
  • the transformer TR has replaced the inductor L in this example with the primary side being coupled to the common node of differential pair Q1/Q2 and the drain and source of transistors Q3 and Q4, respectively, and with the secondary side providing differential output signal 2f L o+ and 2f L o+. Because the transformer TR can offer at least two center taps (e.g., one on the primary side and one of the secondary side), a common mode voltage VCM can be applied to these center taps. This common mode voltage VCM can be selected to allow for improved (e.g., optimized) biasing for transistors Q3 and Q4.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

A frequency multiplier has a differential pair of transistors (Q1, Q2) configured to receive a first differential signal (f*Lo+, fur) having a first frequency, and a transformer (TR). The transformer primary side is coupled to the differential transistor pair, and the transformer secondary is configured to output a second differential signal (2fLo+, 2fLo-) having a second frequency greater than the first frequency. A transistor of first conductivity type (Q3) is coupled to a first supply rail (ground), the transformer primary side, and the differential pair of transistors. A transistor of second conductivity type (Q4) is coupled to a second supply rail (VDD), the transformer primary side, and the differential pair of transistors, where the second transistor is of a second conduction type.

Description

FREQUENCY MULTIPLIER
[0001] This relates generally to a frequency multiplier and, more particularly, to a frequency multiplier having lower direct current (DC) power consumption at radio frequency (RF) and millimeter-wave frequencies (e.g., wavelengths between about 0.1mm and 10mm).
BACKGROUND
[0002] Frequency multipliers have been used in a variety of applications, including RF applications. FIG. 1 shows an example prior frequency multiplier. As shown, this multiplier 100 operates to generate a differential output signal 2f* Lo+ and 2¾χ>+ that has twice the frequency of the input differential signal fLo+ and ¾χτ· In this example, the differential output signal 2fLo+ and 2fi£)+ can function as a local oscillator signal for a modulator. The input differential signal fi£>+ and fu , in the example of FIG. 1, is provided to the gates of transistors Ql and Q2. Transistors Ql and Q2 (which, as shown are NMOS transistors) are arranged to form a differential pair of transistors that are coupled between a common node and a supply rail (e.g., ground). Inductor L (which is coupled to a supply rail VDD at its center tap) is coupled to the common node of the differential pair Q1/Q2, along with the gate of transistor Q3 (which, as shown, is an NMOS transistor). The source of transistor Q3 is also coupled to the inductor L.
[0003] There are, however, some problems with this arrangement. First, the DC power consumption at RF and millimeter-wave frequencies can be high because of a finite transconductance density. Second there is a lack of biasing flexibility at the output of multiplier 100 due to the existence of a single common mode inductor tap (which, in the example of FIG. 1, is coupled to supply rail VDD). Therefore, a frequency multiplier with improved characteristics is needed.
SUMMARY
[0004] An apparatus is provided. In example embodiments, the apparatus comprises a first supply rail; a second supply rail; a differential pair of transistors that are configured to receive a first differential signal having a first frequency; a transformer having a primary side and a secondary side, wherein the primary side of the transformer is coupled to the differential pair of transistors, and wherein the secondary side of the transformer is configured to output a second differential signal having a second frequency, wherein the second frequency is greater than the first frequency; a first transistor that is coupled to the first supply rail, the primary side of the transformer, and the differential pair of transistors, and wherein the first transistor is of a first conduction type; and a second transistor that is coupled to the second supply rail, the primary side of the transformer, and the differential pair of transistors, and wherein the second transistor is of a second conduction type.
[0005] In particular implementations, the first transistor may have a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the first transistor is coupled to the primary side of the transformer, the second passive electrode of the first transistor is coupled to the first supply rail, and the control electrode of the first transistor is coupled to the differential pair of transistors. The second transistor may have a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the first transistor is coupled to the primary side of the transformer, wherein the second passive electrode of the first transistor is coupled to the second supply rail, and wherein the control electrode of the first transistor is coupled to the differential pair of transistors.
[0006] In particular implementations, the first supply rail may be ground. The first transistor may be an N-type transistor, and the second transistor may be a P-type transistor. The first transistor may be an NMOS transistor and the second transistor may be a PMOS transistor.
[0007] In other embodiments, the apparatus comprises a first supply rail; a second supply rail; a first MOS transistor that is coupled between a common node and the first supply rail, wherein the first MOS transistor is configured to receive a first portion of a first differential signal at its gate, and wherein the first differential signal has a second frequency; a second MOS transistor that is coupled between the common node and the second supply rail, wherein the second MOS transistor is configured to receive a second portion of the first differential signal at its gate; a transformer having: a primary side with a first terminal, a second terminal, and a center tap, wherein the first terminal of the primary side of the transformer is coupled to the common node, and wherein the center tap of the primary side of the transformer is configured to receive a common mode voltage; and a secondary side with a first terminal, a second terminal, and a center tap, wherein the first terminal of the secondary side of the transformer is configured to output a first portion of a second differential signal, and wherein the center tap of the secondary side of the transformer is configured to receive a common mode voltage, and wherein the second terminal of the secondary side of the transformer is configured to output a second portion of the second differential signal, wherein the second differential signal has a second frequency, and wherein the second frequency is greater than the first frequency; a third MOS transistor that is coupled between the second terminal of the primary side of the transformer and the second supply rail and that is coupled to the common node at its gate, wherein the third MOS transistor is of a first conduction type; a fourth MOS transistor that is coupled between the second terminal of the primary side of the transformer and the first supply rail and that is coupled to the common node at its gate, and wherein the fourth MOS transistor is of a second conduction type.
[0008] In particular implementations, The first, second, and third MOS transistors may be NMOS transistors, and the fourth transistor may be a PMOS transistor. The second frequency may be twice the first frequency.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] FIG. 1 is a diagram of an example of a conventional frequency multiplier with positive feedback; and
[0010] FIG. 2 is a diagram of an example of a frequency multiplier with positive feedback implemented in accordance with principles of the invention.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
[0011] FIG. 2 illustrates an example frequency multiplier 200. Similar to multiplier 100, multiplier 200 can, for example, generate a differential output signal 2¾χ>+ and 2¾χ>+ that has twice the frequency of the input differential signal fLo+ and fLo-. There are, however, some differences in topology. Namely, inductor L has been replaced by transformer TR, and transistor Q4 (which can, for example, be a PMOS transistor) has been added. In this configuration, transistors Q3 and Q4 are arranged to be of opposite conduction types; for example, transistors Q3 and Q4 are shown to be NMOS and PMOS transistors, respectively. These transistors Q3 and Q4 are also coupled between supply rails (e.g., supply rail VDD and ground). Because these transistors Q3 and Q4 are commonly coupled to a terminal of the primary side of the transformer TR and because the gates of transistors Q3 and Q4 are coupled to the common node of differential pair Q1/Q2, these transistors Q3 and Q4 operate as "stacked" transconductance devices. By having this stacked arrangement (e.g., source of transistor Q4 being coupled to the drain of transistor Q3), current reuse between these transconductance devices (e.g., transistors Q3 and Q4) is permitted, which can, for example, double the transconductance density.
[0012] Better bias can also be achieved. As shown, the transformer TR has replaced the inductor L in this example with the primary side being coupled to the common node of differential pair Q1/Q2 and the drain and source of transistors Q3 and Q4, respectively, and with the secondary side providing differential output signal 2fLo+ and 2fLo+. Because the transformer TR can offer at least two center taps (e.g., one on the primary side and one of the secondary side), a common mode voltage VCM can be applied to these center taps. This common mode voltage VCM can be selected to allow for improved (e.g., optimized) biasing for transistors Q3 and Q4.
[0013] Those skilled in the art will appreciate that modifications may be made to the described example embodiments, and also that many other embodiments are possible, within the scope of the claimed invention.

Claims

CLAIMS What is claimed is:
1. An apparatus comprising:
a first supply rail;
a second supply rail;
a differential pair of transistors that are configured to receive a first differential signal having a first frequency;
a transformer having a primary side and a secondary side, wherein the primary side of the transformer is coupled to the differential pair of transistors, and wherein the secondary side of the transformer is configured to output a second differential signal having a second frequency, wherein the second frequency is greater than the first frequency;
a first transistor that is coupled to the first supply rail, the primary side of the transformer, and the differential pair of transistors, and wherein the first transistor is of a first conduction type; and
a second transistor that is coupled to the second supply rail, the primary side of the transformer, and the differential pair of transistors, and wherein the second transistor is of a second conduction type.
2. The apparatus of Claim 1, wherein the first transistor has a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the first transistor is coupled to the primary side of the transformer, wherein the second passive electrode of the first transistor is coupled to the first supply rail, and wherein the control electrode of the first transistor is coupled to the differential pair of transistors.
3. The apparatus of Claim 2, wherein the second transistor has a first passive electrode, a second passive electrode, and a control electrode, wherein the first passive electrode of the first transistor is coupled to the primary side of the transformer, wherein second passive electrode of the first transistor is coupled to the second supply rail, and wherein the control electrode of the first transistor is coupled to the differential pair of transistors.
4. The apparatus of Claim 3, wherein the first supply rail is ground.
5. The apparatus of Claim 4, wherein the first transistor is a N-type transistor, and wherein the second transistor is a P-type transistor.
6. The apparatus of Claim 5, wherein the first transistor is a NMOS transistor and wherein the second transistor is a PMOS transistor.
7. An apparatus comprising:
a first supply rail;
a second supply rail;
a first MOS transistor that is coupled between a common node and the first supply rail, wherein the first MOS transistor is configured to receive a first portion of a first differential signal at its gate, and wherein the first differential signal has a second frequency;
a second MOS transistor that is coupled between the common node and the second supply rail, wherein the second MOS transistor is configured to receive a second portion of the first differential signal at its gate;
a transformer having:
a primary side with a first terminal, a second terminal, and a center tap, wherein the first terminal of the primary side of the transformer is coupled to the common node, and wherein the center tap of the primary side of the transformer is configured to receive a common mode voltage; and
a secondary side with a first terminal, a second terminal, and a center tap, wherein the first terminal of the secondary side of the transformer is configured to output a first portion of a second differential signal, and wherein the center tap of the secondary side of the transformer is configured to receive a common mode voltage, and wherein the second terminal of the secondary side of the transformer is configured to output a second portion of the second differential signal, wherein the second differential signal has a second frequency, and wherein the second frequency is greater than the first frequency; a third MOS transistor that is coupled between the second terminal of the primary side of the transformer and the second supply rail and that is coupled to the common node at its gate, wherein the third MOS transistor is of a first conduction type;
a fourth MOS transistor that is coupled between the second terminal of the primary side of the transformer and the first supply rail and that is coupled to the common node at its gate, and wherein the fourth MOS transistor is of a second conduction type.
8. The apparatus of Claim 7, wherein the first, second, and third MOS transistors are NMOS transistors, and wherein the fourth transistor is a PMOS transistor.
9. The apparatus of Claim 8, wherein the second supply rail is ground.
10. The apparatus of Claim 8, wherein the second frequency is twice the first frequency.
PCT/US2014/011400 2013-01-14 2014-01-14 Frequency multiplier WO2014110546A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2015552877A JP6375307B2 (en) 2013-01-14 2014-01-14 Frequency multiplier
CN201480004238.XA CN104904115B (en) 2013-01-14 2014-01-14 Frequency multiplier
EP14737568.7A EP2973997B1 (en) 2013-01-14 2014-01-14 Frequency multiplier

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/741,010 US8760899B1 (en) 2013-01-14 2013-01-14 Frequency multiplier
US13/741,010 2013-01-14

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WO2014110546A1 true WO2014110546A1 (en) 2014-07-17

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JP (1) JP6375307B2 (en)
CN (1) CN104904115B (en)
WO (1) WO2014110546A1 (en)

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US10749473B2 (en) * 2017-12-20 2020-08-18 Globalfoundries Inc. Methods, apparatus, and system for a frequency doubler for a millimeter wave device
CN108551331A (en) * 2018-03-23 2018-09-18 杭州电子科技大学 One kind being based on transformer coupled matched millimeter wave low-loss frequency multiplier
US11482924B2 (en) * 2018-07-26 2022-10-25 Analog Devices International Unlimited Company Power isolator exhibiting low electromagnetic interference

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CN104904115A (en) 2015-09-09
JP2016507185A (en) 2016-03-07
US20140198550A1 (en) 2014-07-17
EP2973997A4 (en) 2017-01-18
JP6375307B2 (en) 2018-08-15
EP2973997A1 (en) 2016-01-20
CN104904115B (en) 2018-05-01
US8760899B1 (en) 2014-06-24
EP2973997B1 (en) 2018-08-29

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