GALVANICALLY ISOLATED SEPIC CONVERTER
The present invention relates ' to a galvanically isolated SEPIC converter.
As is known, small- and medium-size electric power generating, systems are becoming increasingly widespread. Systems of this sort, such as photovoltaic systems, are particularly suitable for installation near or on the roofs of industrial and commercial sites, public and private buildings, or even individual homes, and may be used to directly power interior user devices, or support critical electric mains nodes to feed any surplus electric power into the grid.
A common problem encountered in photovoltaic, and also in other types of, systems lies in the various generating units (e.g. individual photovoltaic panels or wind turbines) being- connected in series or series- parallel, and connected to the user devices by a single high-power inverter. A single inverter downstream from the entire system, however., is not normally capable of maximizing the output of individual generating units ■when these, as is invariably the case, do not have exactly" the. same characteristics, i.e. in terms of generating capacity (passing clouds, shade, gusts of
wind, etc.), manufacturing tolerances, or maintenance or ageing conditions.
One recent proposal is to employ microinverters, normally ranging between 200-300 , and each connected to an individual power generating unit. Microinverters, by improving the efficiency of individual power generating units, increase the output of the system as a whole in real operating conditions. Moreover, they may be connected to one another by a conventional electric system, thus also eliminating any problems posed by installing high-voltage direct-current electric mains in critical areas, such as house roofs. Appropriately controlled, microinverters may also perform safety (e.g. automatic cut-off) or mains regulating (e.g. frequency and power control) functions. Microinverters are therefore often preferred, by producing power at a lower unit cost, and , by being easy and cheap to install and safer. In addition, they are also easier to maintain, due to the ease with which each microinverter, and therefore each power generating unit connected to it, can be equipped with a control and monitoring system.
Microinverters often employ converters with galvanic isolation, and a network for recovering the energy accumulated in the dispersion inductors of the isolation transformer. Converters of this ' type have proved especially advantageous in terms of efficiency,
and for this reason are widely used.
Known converters, however, have drawbacks in terms of operating ' conditions, size and cost.: For example, input current ' ripple, though less than in' Buck or Flyback converters, is nevertheless significant, and a reduction in them would be desirable. Size and cost are largely due to the inductors needed, and in this case, too, a reduction would be desirable.
DISCLOSURE OF INVENTION
It is therefore an object of the present invention to provide a SEPIC converter that allows to eliminate or a least reduce the above drawbacks.
According .to the present invention, there is provided a SEPIC converter as defined in Claim 1.
BRIEF DESCRIPTION OF THE DRAWINGS
A number of non-limiting embodiments of the present invention will be described by way of example with reference to the attached drawings, in which:.
Figure 1 is a simplified block diagram of an electric power generating system incorporating a SEPIC converter - in accordance with an embodiment of the present invention;
Figure 2 shows an electric diagram of the SEPIC converter of Figure 1 in a first operating configuration;
Figure 3 shows a graph of . quantities relating to
the SEPIC converter of Figure 2 ;
' Figure 4 shows an electric diagram of the SEPIC converter of Figure 1. in a second ■ operating configuration;
Figure 5 shows an electric diagram of a SEPIC converter in accordance with a different embodiment of the present invention;
Figure 6 shows an electric diagram of a SEPIC converter in accordance with a further embodiment of the present invention.
BEST MODE FOR CARRYING OUT THE INVENTION
Number 1 in Figure 1 indicates as a whole an electric power generating- system comprising a plurality of generating units 2, each with a respective microinverter 3 for connection to a grid 4 and/or. to user devices. 5. Each microinverter 3 comprises a -SEPIC converter 7 in accordance with an embodiment of the present invention, a controlled-bridge stage 8, and a control unit 10.
In the example described, system .1 is a domestic photovoltaic system installed on a house . roof (not shown) , and generating units 2 are individual photovoltaic panels. It is understood, however, that the invention also applies to other types of systems, such as small- or medium-size wind turbines, or to other applications. In some embodiments, each microinverter 3
may be- connected to a different number, e.g. two, ,-three or more, of generating units 2, depending oh the type of system. in which the microinverter is employed. Moreover, SEPIC converter 7 may also be used for specialized applications, not necessarily for converting and feeding electric power into a .grid. A few non- limiting examples of such applications include: powering lighting or security systems in off -grid areas, possibly in conjunction with local power storage systems; vehicularapplications, on land vehicles, marine vessels, or aircraft; and . as a substitute for conventional uninterruptible power supply systems based on internal combustion engines, when other energy sources are available.
SEPIC converter 7 of each microinverter 3 has input terminals 7a, 7b connected to respective generating unit 2 for receiving a direct input voltage VjN; and output terminals 7c, 7d connected to controlled bridge 8 for supplying a first output voltage V0UT1. Controlled-bridge stage 8, controlled by control unit 10, converts the first output voltage V0UTI to an alternating second output voltage V0UT2, which is supplied to grid 4 and user devices 5.
SEPIC converter 7., shown in more detail in Figure 2, is a galvanically isolated SEPIC converter, and has a input network 12 and an output network 13. Input
network 12 comprises a primary winding 15, an auxiliary winding 16, a work capacitor 17 , a main switch 18, and a energy recovery network 19. Output■ etwork 13 comprises a secondary winding 20, an output diode 21, and an output capacitor 22.
Primary winding 15, auxiliary winding 16, and secondary winding 20 are coupled electromagnetically by a common magnetic circuit. In one embodiment, primary winding 15, auxiliary winding 16, and secondary winding 20 are wound about the same ferromagnetic core 24 and therefore coupled to form a transformer 2 . In one embodiment, primary winding 15, auxiliary winding 16, and secondary winding 20 have the same number of turns. Primary winding 15 and auxiliary winding 16 are also electrically coupled, whereas secondary winding 20 is galvanically isolated.
More specifically, primary winding 15 is connected between input terminal 7a and a first node 25, and auxiliary winding 16 is connected between a second node 26 and input terminal 7b. Figure 2 also shows a first parasitic inductor .15a in series with primary winding 15, and a second parasitic inductor 16a in series with auxiliary winding 16. Work capacitor 17 is connected between first node 25 and second node- 26.
Main switch 18, for example, is a MOS transistor having conduction terminals connected respectively to
first node 25 and input terminal 7b, whereas the control terminal 18a receives, via a first enable circuit 50, a first control signal SCi supplied by control unit 10.
In the embodiment shown, in particular, main switch 18 has the source terminal connected to first node 25, and the drain terminal connected to input terminal 7b.
. Figure 2 also shows a mai diode 28, which has anode connected to input terminal 7b and cathode connected to first node 25, and is therefore in parallel to main switch 18. Main diode 28 may be a parasitic diode of main switch 18 or a separate, e.g. discrete, component connected to main switch 18.
First enable circuit 50 comprises a comparator 51 and an enable logic gate 52. Comparator 51 has input terminals connected to the conduction terminals of main switch 18, and is configured to supply a first enable signal ENi( which has an enable value (e.g. high logic value) when the voltage between the conduction terminals of main switch 18 indicates main diode 28 is conducting, and conversely a disable value (e.g. low logic value), i.e. when main diode 28 is cut-off.
Enable logic gate 52 receives first control signal Sci and first enable signal ENi, and is configured to selectively permit transmission of first control signal SCi to control terminal 18a of main switch 18 when first enable signal ENi has the enable value (i.e. when main
diode 28 is conducting). Enable logic gate' 52 is also configured to selectively prevent "switching of main switch -18 when first enable signal ENi has the disable value (i.e. when main diode 28 is. cut-off) . In the embodiment of Figure 2, enable logic gate 52 is an AND gate. In one embodiment, first enable signal - ENX is forcedly set to the enable value by a safety circuit (not shown) ,. if the comparator 51 does not switch within a programmed time interval (for example, the safety circuit may comprise a timer circuit having an output logically in OR with the output of the comparator 51 or the output of the enable logic gate 52) .
Energy recovery network 19 comprises a recovery capacitor 29 and a recovery switch 30 series-connected between second node 26 and . inpμt terminal 7b. More specifically, recovery capacitor 29 is connected between second node 26 and one of the conduction terminals of recovery switch 30. The other conduction terminal of recovery switch 30 is connected to input terminal 7b, and the control terminal 30a receives, via a second enable circuit 53, a second control signal SC2 supplied by control unit 10.
In the embodiment described, recovery switch 30 is an NMOS transistor having drain terminal connected to recovery capacitor 29 and source terminal connected to input terminal 7b.
Figure 2 also shows a recovery diode 31, which has anode and cathode respectively connected to recovery capacitor 29 and to input terminal 7b, and is therefore in parallel to recovery switch 30. Recovery ' diode 31 may be a parasitic diode of recovery switch 30 or a separate, e.g. discrete, component connected to recovery switch 30.
Second enable circuit 53 comprises a comparator 54 and an enable logic, gate 55. Comparator 54 has input terminals connected to the conduction terminals of recovery switch 30, and is configured to supply a second enable signal EN2, which has an enable value (e.g. high logic value) when the voltage between the conduction terminals of recovery switch 30 indicates recovery diode 31 is conducting, and conversely a disable value (e.g. low logic value), i.e. when recovery diode 31 is cutoff.
Enable logic gate 55 receives second control signal Sc2 and second enable signal EN2, and is configured to selectively permit transmission of second control signal SC2 to control terminal 30a of recovery switch 30 when second enable signal EN2 has the enable value (i.e. when recovery diode 31 is conducting) . Enable logic gate 55 is also configured to selectively prevent switching of recovery switch 31 when second enable signal"iEN2 has the disable value (i.e. when recovery diode 31 is cut-off).
In .the embodiment of Figure 2, enable logic gate 55 is also an AND gate.
In output network 13, output capacitor 22 is connected between output terminals 7c, 7d, and secondary winding 20 and output diode 21 are connected in series with each other and in parallel to output capacitor 22. More specifically, secondary winding 20 has terminals connected to output terminal 7d and to the anode of output diode 21, the cathode of which is connected to output terminal 7c.
SEPIC converter 7 operates as follows.
Control unit 10 determines the activation sequence and durations of ON times of main switch 18 and recovery switch 30 through first control signal SCi and second control signal SC2 respectively.
Initially, main switch 18 is closed (on)' and conducts, and recovery switch 30 is cut-off. This configuration is maintained by control unit 10 for . a charge time T0N- In this condition, the direct input voltage VDCiN charges primary winding 15 and its parasitic inductor 15a directly, while auxiliary winding 16, its parasitic inductor 16a, and the parasitic inductor of. secondary winding 20 are also charged by magnetic coupling through common ferromagnetic core 24. A magnetizing current, indicated IM, for magnetizing ferromagnetic core 24 is also absorbed.
Initially, the parasitic inductors are charged rapidly to the value of magnetizing current ,IM/. as shown in the graph of Figure 3 (leakage current IL) . Then, the increase in magnetizing current IM is determined . by the magnetizing inductance of transformer 23.
At this stage, work capacitor 17 is also closed in a loop with auxiliary winding 16, and aids directly in charging auxiliary winding 16 and parasitic inductor 16a, and indirectly, via the coupling to ferromagnetic core 24, in charging primary winding 15, parasitic inductor 15a and the parasitic inductor of secondary winding 20. Across its terminals, work capacitor 17 has a mean work voltage Vc* equal to direct input voltage VDCIN- SO, the same voltage is applied to both primary winding 15 and auxiliary winding 16.
The duration of charge time 0N■ may be controlled by control unit 10, and may be determined either in open-loop manner, e.g. by a clock (not shown), or by comparing an electric quantity of SEPIC converter 7 with a respective threshold. In one embodiment, control unit 10 acquires the input current to SEPIC converter 7 (Figure 1) and compares it with a programmable current threshold. Alternatively, control unit 10 may acquire an output current of SEPIC converter 7 and compare it with a respective current threshold, or acquire first output voltage V0U I and compare it with a respective voltage
When main switch. 18 . opens (and before recovery switch 30 closes) , a transient phase begins in which the currents in first and second1 parasitic inductor 15a and 16a flow to recovery capacitor 29 and charge the parasitic capacitors (shown by dash lines in Figure 2) parallel to main diode 28 and recovery diode 31. Recovery diode 31 starts conducting and ensures substantially zero voltage conditions between the conduction terminals of recovery switch 30.
At this stage, the steady state voltages at work capacitor 17 and recovery capacitor 29 are respectively: CR > V0UT1 (N/M)
where N and M stand for the number of turns in primary winding 15 and secondary winding 20 respectively (in one embodiment, both have the same number of turns) .
When recovery diode 31 starts conducting, second enable circuit 53 sets second enable signal EN2 to the enable value, thus allowing control unit 10 to close recovery switch 30 (Figure 4) . Switching therefore takes place in substantially ZVS (zero voltage switching) conditions.
The configurations of main switch 18 (open) and recovery switch 30 (closed) are maintained for a discharge time T0FF determined by control unit 10. At
this stage, magnetizing current IM is discharged to output capacitor 22 and to a load (not shown) via output diode 21. Through energy recovery network 19,' the energy accumulated in the dispersion inductors may be recovered and used, without it being dissipated by Joule effect (Figure 3) .
At the start of discharge time T0FF, output diode 21 is reverse biased, and only starts conducting after the currents of first parasitic inductor 15a and second parasitic inductor 16a are reversed. This is achieved by recovery capacitor 29 charging gradually at the expense of the current in second parasitic inductor 16a, which decreases to the point of changing sign. And, when the voltage in auxiliary winding 16, reflected in secondary winding 20, equals first output voltage V0U I/ output diode 21 starts conducting.
The current in first parasitic inductor 15a is also reversed when the voltage in recovery capacitor 29 reaches such a value that, reflected in primary winding 15 and added to the voltage in work capacitor 17 (equal to -VIN) , it exceeds input voltage VIN.
The negative current through auxiliary winding 16 turns on main diode 28 of main switch 18, so main switch .18 closes in substantially zero voltage (ZVS) conditions at' the" end of discharge, time T0FF-
The negative current through auxiliary winding 16
may be obtained by selecting the capacitances of the capacitors > or by selecting the duration of discharge time T0FFi given certain capacitance values ,
At the end' of discharge time T0 F, recovery switch 30 is opened. The currents in first parasitic inductor 15a and second parasitic inductor 16a first charge the parasitic capacitor parallel to main diode 28, which starts conducting and ensures substantially zero voltage between the conduction terminals of main switch 18. The conducting state of main diode 28 is detected by the first enable circuit, which assigns the enable value to first enable signal ENX, thus allowing first control signal SCi to be sent to control terminal 18a of main witch 18 to close main switch 18 in ZVS conditions.
Work capacitor 17 is configured to maintain the voltage value (on average, equal to direct input-, voltage VDCIN) in all possible load conditions.
The turn ratio' of primary winding 15, auxiliary winding 16, and secondary winding 20 is selected to fix the duty cycle for a given load value.
"Figure 5 shows a SEPIC converter 107 in "accordance with a different embodiment of the invention. In this case, SEPIC converter 107 comprises primary winding 15, auxiliary winding 16, work capacitor · 17 , .main switch 18, secondary winding 20, output diode 21 and output capacitor 22, as described with reference to Figures 2
and 4, but also comprises a energy recovery, network 119. comprising a recovery capacitor 129 and a recovery switch 130 connected in series between second node 26 and input terminal 7a. More specifically, recovery capacitor 129 is connected between second node 26 and one of the conduction terminals of recovery switch 130. The other conduction terminal of recovery switch 130 is connected to input terminal 7a, and the control terminal receives second control signal SC2 from control unit 10. In the embodiment described, recovery switch 130 is a PMOS transistor with its source terminal . connected to input terminal 7a, and its drain terminal connected to recovery capacitor 129. Figure 5 also shows a recovery diode 131 of recovery switch 130, having its cathode connected to recovery capacitor 129, and its anode connected to second node 26.
SEPIC converter 107 also comprises an enable circuit 50 associated with main switch 18; and an enable circuit 153 comprising a comparator 154 and an enable logic gate 155. Comparator 154 has input terminals connected to the conduction terminals of recovery switch 130, and is configured to supply an enable signal, which has an enable value (e.g. high logic value) when the voltage between the conduction terminals of recovery switch 130 indicates recovery diode 131 is conducting, and conversely a disable value (e.g. low logic value)..
Enable logic gate 155 receives a control signal from "control, .unit 10 ; and' the enable signal from comparator 154, and is configured" to selectively permit transmission of the control signal to the control terminal 130a of recovery switch 130 when the enable signal from comparator 154 has the enable value.
In a further embodiment shown in Figure 6, a SEPIC converter 207 comprises both energy recovery network 19 in Figures 2 and 4, and energy recovery network 119 in Figure 5. SEPIC. converter 207 also comprises enable circuit 50; and further enable circuits (not shown) associated with energy recovery network 19 and energy recovery network 119 and formed respectively in the same way as enable circuit 50 in Figure 2 and enable circuit 153 in Figure 5.
The invention has various advantages, mainly due. to main switch 18 and recovery switch 30 being switched - in particular, opened - in zero voltage switching conditions, provided simply that the energy stored in the parasitic inductors at the start of the respective transitions is enough to charge the parasitic capacitors sufficiently to cause the main diode and the recovery diode to conduct. Switching in ZVS conditions ensures a high degree of efficiency and so allows the SEPIC converter to operate at higher frequencies. The higher work frequencies in turn make it possible to employ
smaller and even cheaper transformers (i.e. with smaller cores and a lower number of turns) . And ZVS conditions are achieved with no need for additional components, and by simply exploiting the effects of the parasitic inductors always present in the transformer windings, and by accurately timing switching of the main switch and recovery switch.
Other advantages are derived by ferromagnetic core 24 coupling primary winding 15 and auxil-iary winding 16 in input network 12, and secondary winding 20 in output network 13. As a result of this coupling, the effects of the inductors in input network 12 are summed (doubled, if primary winding 15 and auxiliary winding 16 have the same number of turns) with respect to inductors formed on . separate cores. Size and cost are therefore both reduced. Moreover, the above coupling also reduces input current ripple, and the advantages afforded by galvanically isolating input network 12 and output network 13 are preserved.
Using at least one energy recovery network on the one hand prevents the energy stored in the parasitic inductors from being dissipated, and, on the other, creates the. conditions enabling substantially zero voltage switching. The SEPIC converter described therefore prevents high overvoltages in the switches, and so has a high degree of efficiency.
Clearly, changes may be made to the SEPIC converter described without, however, departing' from the scope of the present invention, as defined in the accompanying Claims .