WO2014036594A1 - Digital isolator with improved cmti - Google Patents

Digital isolator with improved cmti Download PDF

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Publication number
WO2014036594A1
WO2014036594A1 PCT/AU2013/000989 AU2013000989W WO2014036594A1 WO 2014036594 A1 WO2014036594 A1 WO 2014036594A1 AU 2013000989 W AU2013000989 W AU 2013000989W WO 2014036594 A1 WO2014036594 A1 WO 2014036594A1
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WIPO (PCT)
Prior art keywords
die
isolator
mutually spaced
integrated circuit
circuit portions
Prior art date
Application number
PCT/AU2013/000989
Other languages
French (fr)
Inventor
Yashodhan Vijay Moghe
Russell Glen HAYTER
Annette TENG
Sarah Jane SHARP
Original Assignee
The Silanna Group Pty Ltd
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Publication date
Application filed by The Silanna Group Pty Ltd filed Critical The Silanna Group Pty Ltd
Publication of WO2014036594A1 publication Critical patent/WO2014036594A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Definitions

  • the present invention relates to a digital isolator and a method for producing a digital isolator.
  • a digital isolator is a device that allows the exchange of digital signals across a galvanic isolation barrier between electric circuits, allowing those circuits to communicate, yet their respective grounds may be at very different potentials.
  • the transmission of signals across an electrical isolation barrier is important for many applications, including: (i) mains-connected medical equipment— for patient safety;
  • communications links via cables e.g., USB, Firewire, Ethernet
  • cables e.g., USB, Firewire, Ethernet
  • USB 2.0 (480 Mbps), USB 3.0 (5 Gbps), Firewire (800 Mbps), and gigabit Ethernet).
  • CMTI common-mode transient immunity
  • a digital isolator including:
  • each of the mutually spaced electrodes is disposed below a corresponding one of the integrated circuit portions and does not extend beyond the lateral boundary of the corresponding one of the integrated circuit portions.
  • At least one of the mutually spaced electrodes is electrically floating. In other embodiments, the mutually spaced electrodes are electrically floating.
  • At least one of the mutually spaced electrodes is electrically connected to a corresponding signal pin of the isolator. In some embodiments, the mutually spaced electrodes are connected to respective signal pins of the isolator. In some embodiments, at least one of the mutually spaced electrodes is supported by a corresponding conductive component that is not a signal pin of the isolator.
  • the mutually spaced electrodes are parts of a pre-formed metal frame.
  • the single electrically insulating die is mounted to the mutually spaced electrodes by an electrically conductive adhesive that does not extend across the isolation barrier between the integrated circuit portions.
  • the single electrically insulating die is mounted to the mutually spaced electrodes by an electrically insulating adhesive that extends across the isolation barrier between the integrated circuit portions.
  • a method of producing a digital isolator including:
  • a digital isolator die having integrated circuit portions mutually spaced on a single electrically insulating substrate, an isolation barrier being disposed between the integrated circuit portions to provide galvanic isolation therebetween, and at least one coupling structure to provide signal coupling
  • the step of mounting includes coating an adhesive onto the backside of a wafer including a plurality of instances of the digital isolator die before die singulation, and using the adhesive to attach a singulated digital isolator die to the mutually spaced electrodes, whereby the adhesive extends over the , gap between the mutually spaced electrodes.
  • the step of mounting includes coating an adhesive onto the backside of a wafer including a plurality of instances of the digital isolator die before die singulation, and using the adhesive to attach the singulated digital isolator, die to the mutually spaced electrodes, whereby the adhesive coats only selected regions of the wafer backside prior to die singulation so that it does not extend between the mutually spaced electrodes.
  • the step of mounting includes attaching a double-sided
  • Figures 2A and 2B are schematic plan and cross-sectional end views, respectively, of an example of a packaged single-chip isolator based on the configuration of Figure 1 ;
  • Figures 3A and 3B are schematic plan and cross-sectional end views, respectively, of another example of a packaged single-chip isolator based on the configuration of Figure 1;
  • Figure 4 is a schematic plan view block diagram illustrating the general configuration of a single-chip isolator having four mutually isolated circuit domains
  • Figures 5A and 5B are plan and cross-sectional end views, respectively, of an example of a single-chip isolator based on the configuration of Figure 4;
  • Figure 6 is a flow diagram of an example of a method of producing a single- chip isolator.
  • Figures 7A to 7E are schematic cross-sectional side views illustrating different
  • the single-die isolators described in the single-chip isolator patent applications have been each attached to a single conductive plate or 'die paddle' of a lead frame using an adhesive paste as part of the device packaging process.
  • the die paddle primarily provides mechanical support for the die during the subsequent packaging steps.
  • the lateral dimensions of the die paddle are substantially larger than those of the die itself, and the adhesive paste flows out from under the die onto the exposed surface regions of the paddle surrounding the die as the die is pressed down onto the paddle. Subsequently, wire bonding is used to form electrical connections from pins of the lead frame to respective contact pads of the die.
  • the integrated circuit portions constitute respective circuit domains.
  • the galvanically isolated circuit domains are communicatively coupled by one or more signal coupling elements. These coupling elements can communicatively couple the circuit domains using any of a variety of signal coupling technologies, including, for example, optical coupling, inductive coupling, capacitive coupling, giant magnetoresistance (GMR) coupling, acoustic coupling, mechanical coupling, or any combinations thereof.
  • GMR giant magnetoresistance
  • the types of communication across the isolation barrier 125 can include one or, more of the following: (i) uni- or bi-directional AC or DC power (the DC power being generated via rectification of an AC signal), (ii) uni- or bi-directional analogue communication, and (iii) uni- or bi-directional digital communication.
  • the shielding effect can be enhanced by connecting the shield electrode of a circuit domain to a ground or other local potential of that domain, thereby 'shielding' that circuit domain from transients and electromagnetic noise in the other circuit domains of the die.
  • the single-chip isolators disclosed herein exhibit advantages over prior art isolation devices, including much higher speed digital communications, increased CMTI, and lower cost. Whereas conventional multiple-chip galvanic isolation devices provide data speeds of up to about 150 Mbps per channel, in some embodiments the single-chip isolators disclosed herein provide data speeds in excess of 1 Gbps. Further, where a single- chip isolator is mounted on a single electrode or paddle, the CMTI of such an isolator is limited by the fact that the conductive paddle extends below all of the circuit domains. The single-chip isolators with multiple shielding electrodes disclosed herein inhibit the
  • the coupling element 120 allows the communication of signals across an isolation barrier 125 disposed between the first and second circuit domains 1 15- 1 , 1 15-2.
  • the coupling element 120 maintains galvanic isolation between the circuit domains 1 15-1 , 1 15-2 while at the same time allowing signals to be communicated therebetween.
  • the coupling element 120 can be based any suitable coupling technology, including, for example, optical coupling, inductive coupling (e.g., transformers), capacitive coupling, GMR coupling, acoustic coupling, mechanical coupling, and any combinations thereof.
  • the isolator die 1 10 can be implemented using a silicon-on-insulator (SOI) wafer or substrate, a silicon-on- sapphire (SOS) wafer or substrate, or any other wafer or substrate that includes an electrically insulating layer capable of providing galvanic isolation between semiconductor regions disposed thereon.
  • SOI silicon-on-insulator
  • SOS silicon-on- sapphire
  • the substrate that is used to form the multi-domain chip .1 10 may be a monolithic substrate or a layered substrate formed by, for example, epitaxial growth or bonding methods.
  • An example of a layered substrate is an SOI substrate, which
  • the-art isolators provide data speeds of up to about 150 Mbps per channel
  • the digital isolators on SOS substrates with capacitive coupling elements have been measured as providing data speeds greater than 1 Gbps.
  • Each of the circuit domains 1 15 of the chip 110 is mounted atop its own shield electrode 130.
  • the first circuit domain 1 15-1 is mounted atop a first shield electrode 130-1
  • the second circuit domain 1 15-2 is mounted atop a second shield electrode 130-2.
  • the shield electrodes 130-1, 130-2 are electrically conductive but are physically separate and electrically isolated from one another.
  • the first shield electrode 130-1 may be electrically floating or may be connected to and mechanically anchored by a ground pin or signal pin of the first circuit domain 1 15-1
  • the second shield electrode 130-2 may be electrically floating or may be connected to and mechanically anchored by a ground pin or signal pin of the second circuit domain 1 15-2.
  • the shield electrodes 130-1 , 130-2 are electrically isolated from one another, the ability for common- mode transients in the ground plane of either circuit domain 115 to adversely affect the circuitry of the other circuit domain is inhibited.
  • the thickness of the lead frame 215 (i.e., the thickness of the I/O pins 220 and the shield electrodes 130-1 , 130-2) matches that of typical I/O pins of a discrete integrated circuit (IC) device.
  • the thickness of the lead frame 215 is in a range from about 5 mils to about 15 mils (8 and 10 mils being common industry standards for SOIC packaging).
  • FIG. 1 A and Figure 2B show that the first circuit domain 1 15-1 portion of the die 110 is mounted atop the first shield electrode 130-1 and that the second circuit domain 1 15-2 portion of the die 1 10 is mounted atop the second shield electrode 130-2.
  • the first and second shields 130-1, 130-2 are generally shaped and sized to at least approximately correspond to the physical footprint of the circuit domains 1 15-1, 1 15-2, respectively.
  • the lateral spacing between the shield electrodes 130-1 , 130-2 is selected to satisfy both the required C TI between the two circuit domains 1 15-1 , 1 15-2 and the dielectric strength therebetween.
  • the gaps between the shield electrodes and the gaps are selected to satisfy both the required C TI between the two circuit domains 1 15-1 , 1 15-2 and the dielectric strength therebetween.
  • the shield electrodes 130-1, 130-2 are not connected to any of the I/O pins 220 (i.e., are left electrically floating at an undefined potential), but are mechanically anchored by respective support members formed by other portions of the lead frame separate from the I/O pins 220.
  • the lead frame 215 includes a first pair of support members 320 connected to the first shield electrode 130-1, and a second pair of support members 330 connected to the second shield electrode 130-2, with each of the support members 320, 330 extending between a corresponding pair of the I/O pins 220, as shown.
  • the support members 320, 330 are provided to anchor the shield electrodes 130-1 , 130-2 in position with respect to the die 110 during its encapsulation in the device package 210.
  • a combination of support members and I/O pins as shown in Figure 2 A and Figure 3 A is also possible, for example having one support connected to an I/O pin 220.
  • Other modifications and configurations for supporting the shield electrodes will be apparent to those skilled in the art in light of this disclosure.
  • FIG. 4 shows the isolator 400 having one instance of the coupling element 120 connected between all four of the circuit domains 115, and thereby communication is possible between any two of the circuit domains 115.
  • the coupling element 120 can be implemented to facilitate communications between any two or more of the mutually isolated circuit domains 1 15.
  • separate instances of an coupling element 120 may be provided between any two or more of the circuit domains 1 15, and in any combination.
  • a first instance of the coupling element 120 may be provided between the circuit domain 1 15-1 and the circuit domain 1 15-2
  • a second instance of the coupling element 120 may be provided between the circuit domain 1 15-3 and the circuit domain 1 15-4.
  • the circuit domain 1 15-1 can communicate only with the circuit domain 1 15-2 and vice versa.
  • the circuit domain 115-3 can communicate only with the circuit domain 115-4 and vice versa.
  • the multi -domain chip 410 of Figure 4 can be implemented using an SOS substrate, an SOI substrate, or any other substrate that contains an insulating layer capable of galvanic isolation.
  • Electrodes 130-1 , 130-2, 130-3, 130-4 are electrically conductive elements that are physically separate and electrically isolated from one another. Each of the four shield electrodes 130 may be electrically connected to and mechanically anchored by a corresponding ground or signal pin of the lead frame. Because the shield electrodes 130-1 , 130-2, 130-3, 130-4 are electrically isolated from one another and disposed under only their respective ⁇ domains, common-mode transients on one or more of the ground planes of respective ones of the circuit domains 115-1, 115-2, 115-3, 115-4 are inhibited from coupling into the sensitive circuits of the other circuit domain(s) of the chip to corrupt the signals therein.
  • common-mode transients appear across the coupling element 120, but this may or may not pose a signal integrity problem, depending on the type of isolation element used in the isolator.
  • a common-mode voltage transient generally does not get converted into an output signal.
  • the coupling element 120 is generally differentially balanced to block such transients, as will be readily appreciated by those skilled in the art.
  • the Figures herein are not to scale and the gap or spacing between any two of the shield electrodes 130-1, 130-2, 130-3, 130-4 can be very small in practice and depends on the required CMTI (typically greater than 1 kV ⁇ s) of the device and the dielectric strength of the plastic encapsulate of the device package 210. In one example, the spacing between the shield electrodes 130-1, 130-2, 130-3, 130-4 is about 50 ⁇ .
  • the gap between adjacent shield electrodes poses challenges for packaging the isolator dies. For example, conventional adhesive paste dispensing equipment and methods are often not suitable, as the adhesive paste will flow into the gap between adjacent shield electrodes and may fall through the gap onto the packaging equipment, resulting in unwanted contamination and fouling.
  • Figure 6 is a flow diagram of a method 600 of producing a two-region single- die isolator 200 in accordance with an embodiment of the present invention. It will be appreciated by persons of skill in the art that the method 600 could easily be adapted to making the four region isolator 400 or indeed any such isolator having a practical number
  • the die 1 10 can be attached to the shield electrodes 130- 1 , 130-2 at step 615 by any of a number of methods, or combinations thereof, including : a. Attaching one or more sections of a stiffening (e.g., sticky polyimide) tape 702 under the shield electrodes 130 and bridging the gaps therebetween, and then mounting the die 1 10 onto the tape/shield electrode assembly using a non- conductive adhesive 704.
  • a stiffening e.g., sticky polyimide
  • This method is the closest analogue to the standard production technique where a die is mounted to a single die paddle.
  • the adhesive 704 and the stiffening tape 702 are selected to have dielectric strengths that provide the required galvanic isolation.
  • An example device processing using this technique is shown in cross-sectional end view in Figure 7A; b.
  • the adhesive may be continuous or patterned to keep the adhesive 712 away from the gaps between respective pairs of shield electrodes 130. If the adhesive 712 is continuous, it must be non-conductive in order to maintain galvanic isolation. If the adhesive 712 is patterned, the patterning may include forming adhesive-free saw-streets between dies, such that there is ease of alignment and debris reduction during die singulation. Die singulation may be done with diamond saws or laser scribes or other methods known to. those skilled in the art. An example of the use of a continuous adhesive layer is shown in Figure 7C, while an example of using patterned adhesive is shown in Figure 7D.
  • a wire bonding process using conventional wire-bonding techniques is performed to electrically connect the I/O pads (not shown) of the die 1 10 to the I/O pins 220 of the lead frame.
  • a wire bonding process using conventional wire-bonding techniques is performed to electrically connect the I/O pads (not shown) of the die 1 10 to the I/O pins 220 of the lead frame.
  • Electrodes can be provided by printing or otherwise forming one or more layers of metal or other conductive material(s) on the backside of the isolator die. Irrespective of whether or not the shield electrodes are formed by a lead frame or other form of metal frame, a metal frame is nonetheless used to provide electrical connectivity and/or mechanical support to the die or chip.

Abstract

A digital isolator, including: integrated circuit portions mutually spaced on a single electrically insulating die; an isolation barrier disposed between the integrated circuit portions to provide galvanic isolation therebetween; at least one coupling structure configured to provide signal coupling between the galvanically isolated integrated circuit portions; and mutually spaced electrodes on which the die is mounted, the electrodes being arranged below respective ones of the integrated circuit portions to improve common-mode transient immunity of the isolator.

Description

DIGITAL ISOLATOR WITH IMPROVED CMTI TECHNICAL FIELD
[0001] The present invention relates to a digital isolator and a method for producing a digital isolator. BACKGROUND
[0002] A digital isolator is a device that allows the exchange of digital signals across a galvanic isolation barrier between electric circuits, allowing those circuits to communicate, yet their respective grounds may be at very different potentials. The transmission of signals across an electrical isolation barrier is important for many applications, including: (i) mains-connected medical equipment— for patient safety;
(ii) communications links via cables (e.g., USB, Firewire, Ethernet) between mains-connected equipment— to avoid ground loops;
(iii) isolation of telecommunication equipment from phone lines— for lightning
effective to isolate the new high-speed signaling standards that have emerged (e.g. , USB 2.0 (480 Mbps), USB 3.0 (5 Gbps), Firewire (800 Mbps), and gigabit Ethernet).
[0004] Additionally, a key performance measure of an isolator is its ability to prevent transients in the ground plane of one side of the isolator from corrupting the signals received on another side of the isolator, a measure referred to in the art as common-mode transient immunity, or CMTI. It is generally desirable from the perspective of performance for an isolator to have as high a value of CMTI as possible.
[0005] It is desired to provide a digital isolator and a method of producing a digital isolator that alleviate one or more difficulties of the prior art, or that at least provide a useful alternative.
SUMMARY
[0006] In accordance with some embodiments of the present invention, there is provided a digital isolator, including:
[0008] In some embodiments, each of the mutually spaced electrodes is disposed below a corresponding one of the integrated circuit portions and does not extend beyond the lateral boundary of the corresponding one of the integrated circuit portions.
[0009] In some embodiments, at least one of the mutually spaced electrodes is electrically floating. In other embodiments, the mutually spaced electrodes are electrically floating.
[0010] In some embodiments, at least one of the mutually spaced electrodes is electrically connected to a corresponding signal pin of the isolator. In some embodiments, the mutually spaced electrodes are connected to respective signal pins of the isolator. In some embodiments, at least one of the mutually spaced electrodes is supported by a corresponding conductive component that is not a signal pin of the isolator.
[0011] In some embodiments, the mutually spaced electrodes are parts of a pre-formed metal frame.
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communication of signals between the integrated circuit portions while maintaining the galvanic isolation therebetween.
[0014] In some embodiments, the single electrically insulating die is mounted to the mutually spaced electrodes by an electrically conductive adhesive that does not extend across the isolation barrier between the integrated circuit portions.
[0015J In some embodiments, the single electrically insulating die is mounted to the mutually spaced electrodes by an electrically insulating adhesive that extends across the isolation barrier between the integrated circuit portions.
[0016] In accordance with some embodiments of the present invention, there is provided a method of producing a digital isolator, the method including:
receiving a digital isolator die having integrated circuit portions mutually spaced on a single electrically insulating substrate, an isolation barrier being disposed between the integrated circuit portions to provide galvanic isolation therebetween, and at least one coupling structure to provide signal coupling
digital isolator die to the mutually spaced electrodes, whereby the adhesive does not flow between the mutually spaced electrodes.
[0020] In some embodiments, the step of mounting includes coating an adhesive onto the backside of a wafer including a plurality of instances of the digital isolator die before die singulation, and using the adhesive to attach a singulated digital isolator die to the mutually spaced electrodes, whereby the adhesive extends over the , gap between the mutually spaced electrodes.
(0021] In some embodiments, the step of mounting includes coating an adhesive onto the backside of a wafer including a plurality of instances of the digital isolator die before die singulation, and using the adhesive to attach the singulated digital isolator, die to the mutually spaced electrodes, whereby the adhesive coats only selected regions of the wafer backside prior to die singulation so that it does not extend between the mutually spaced electrodes.
[0022] In some embodiments, the step of mounting includes attaching a double-sided
[0025] Figures 2A and 2B are schematic plan and cross-sectional end views, respectively, of an example of a packaged single-chip isolator based on the configuration of Figure 1 ;
[0026] Figures 3A and 3B are schematic plan and cross-sectional end views, respectively, of another example of a packaged single-chip isolator based on the configuration of Figure 1;
[0027] Figure 4 is a schematic plan view block diagram illustrating the general configuration of a single-chip isolator having four mutually isolated circuit domains;
[0028] Figures 5A and 5B are plan and cross-sectional end views, respectively, of an example of a single-chip isolator based on the configuration of Figure 4;
[0029] Figure 6 is a flow diagram of an example of a method of producing a single- chip isolator; and
[0030] Figures 7A to 7E are schematic cross-sectional side views illustrating different
communications and/or energy transfer) to be communicated between those otherwise mutually isolated integrated circuit portions. Forming isolators on a single die rather than on a multi-die assembly results in lower manufacturing costs, increased signaling speed, and reduced operational power consumption. [0033] As with conventional single-die semiconductor devices, the single-die isolators described in the single-chip isolator patent applications have been each attached to a single conductive plate or 'die paddle' of a lead frame using an adhesive paste as part of the device packaging process. As with conventional devices, the die paddle primarily provides mechanical support for the die during the subsequent packaging steps. The lateral dimensions of the die paddle are substantially larger than those of the die itself, and the adhesive paste flows out from under the die onto the exposed surface regions of the paddle surrounding the die as the die is pressed down onto the paddle. Subsequently, wire bonding is used to form electrical connections from pins of the lead frame to respective contact pads of the die. [00341 Although the conventionally packaged single-die isolators perform well, the
its own ground potential or ground plane that can differ substantially and independently of the ground potentials/planes of the other integrated circuit portions on the same die. Accordingly, the integrated circuit portions constitute respective circuit domains.
[0036] The galvanically isolated circuit domains are communicatively coupled by one or more signal coupling elements. These coupling elements can communicatively couple the circuit domains using any of a variety of signal coupling technologies, including, for example, optical coupling, inductive coupling, capacitive coupling, giant magnetoresistance (GMR) coupling, acoustic coupling, mechanical coupling, or any combinations thereof. [0037] In general, and as described in the single-chip isolator patent applications, the types of communication across the isolation barrier 125 can include one or, more of the following: (i) uni- or bi-directional AC or DC power (the DC power being generated via rectification of an AC signal), (ii) uni- or bi-directional analogue communication, and (iii) uni- or bi-directional digital communication.
of the isolator. This deleterious effect is avoided or at least reduced by limiting the lateral (i.e., in plan view) extent of each electrode to be within the lateral boundary of the corresponding circuit domain, or to at least not overlap with the lateral boundaries of the other circuit domain(s) on the die. Secondly, the shielding effect can be enhanced by connecting the shield electrode of a circuit domain to a ground or other local potential of that domain, thereby 'shielding' that circuit domain from transients and electromagnetic noise in the other circuit domains of the die.
/[0040] The single-chip isolators disclosed herein exhibit advantages over prior art isolation devices, including much higher speed digital communications, increased CMTI, and lower cost. Whereas conventional multiple-chip galvanic isolation devices provide data speeds of up to about 150 Mbps per channel, in some embodiments the single-chip isolators disclosed herein provide data speeds in excess of 1 Gbps. Further, where a single- chip isolator is mounted on a single electrode or paddle, the CMTI of such an isolator is limited by the fact that the conductive paddle extends below all of the circuit domains. The single-chip isolators with multiple shielding electrodes disclosed herein inhibit the
[0043] The coupling element 120 allows the communication of signals across an isolation barrier 125 disposed between the first and second circuit domains 1 15- 1 , 1 15-2. The coupling element 120 maintains galvanic isolation between the circuit domains 1 15-1 , 1 15-2 while at the same time allowing signals to be communicated therebetween. As described above, the coupling element 120 can be based any suitable coupling technology, including, for example, optical coupling, inductive coupling (e.g., transformers), capacitive coupling, GMR coupling, acoustic coupling, mechanical coupling, and any combinations thereof.
[0044] As described in the single-chip isolator patent applications, the isolator die 1 10 can be implemented using a silicon-on-insulator (SOI) wafer or substrate, a silicon-on- sapphire (SOS) wafer or substrate, or any other wafer or substrate that includes an electrically insulating layer capable of providing galvanic isolation between semiconductor regions disposed thereon. The substrate that is used to form the multi-domain chip .1 10 may be a monolithic substrate or a layered substrate formed by, for example, epitaxial growth or bonding methods. An example of a layered substrate is an SOI substrate, which
the-art isolators provide data speeds of up to about 150 Mbps per channel, the digital isolators on SOS substrates with capacitive coupling elements have been measured as providing data speeds greater than 1 Gbps.
[0047] Each of the circuit domains 1 15 of the chip 110 is mounted atop its own shield electrode 130. For example, the first circuit domain 1 15-1 is mounted atop a first shield electrode 130-1, and the second circuit domain 1 15-2 is mounted atop a second shield electrode 130-2. The shield electrodes 130-1, 130-2 are electrically conductive but are physically separate and electrically isolated from one another. The first shield electrode 130-1 may be electrically floating or may be connected to and mechanically anchored by a ground pin or signal pin of the first circuit domain 1 15-1, while the second shield electrode 130-2 may be electrically floating or may be connected to and mechanically anchored by a ground pin or signal pin of the second circuit domain 1 15-2. At least because the shield electrodes 130-1 , 130-2 are electrically isolated from one another, the ability for common- mode transients in the ground plane of either circuit domain 115 to adversely affect the circuitry of the other circuit domain is inhibited.
signal and power pins to which the I/O pads (not shown) of the die 1 10 are connected, for example by wire bonding. The thickness of the lead frame 215 (i.e., the thickness of the I/O pins 220 and the shield electrodes 130-1 , 130-2) matches that of typical I/O pins of a discrete integrated circuit (IC) device. Typically, the thickness of the lead frame 215 is in a range from about 5 mils to about 15 mils (8 and 10 mils being common industry standards for SOIC packaging).
[0050J Figure 2 A and Figure 2B show that the first circuit domain 1 15-1 portion of the die 110 is mounted atop the first shield electrode 130-1 and that the second circuit domain 1 15-2 portion of the die 1 10 is mounted atop the second shield electrode 130-2. Typically, and as shown for this embodiment, the first and second shields 130-1, 130-2 are generally shaped and sized to at least approximately correspond to the physical footprint of the circuit domains 1 15-1, 1 15-2, respectively. The lateral spacing between the shield electrodes 130-1 , 130-2 is selected to satisfy both the required C TI between the two circuit domains 1 15-1 , 1 15-2 and the dielectric strength therebetween. In this regard, it should be understood that although the gaps between the shield electrodes and the gaps
[0052] In an alternative embodiment, as shown in Figure 3A and Figure 3B, the shield electrodes 130-1, 130-2 are not connected to any of the I/O pins 220 (i.e., are left electrically floating at an undefined potential), but are mechanically anchored by respective support members formed by other portions of the lead frame separate from the I/O pins 220.
[0053J In this example, the lead frame 215 includes a first pair of support members 320 connected to the first shield electrode 130-1, and a second pair of support members 330 connected to the second shield electrode 130-2, with each of the support members 320, 330 extending between a corresponding pair of the I/O pins 220, as shown. The support members 320, 330 are provided to anchor the shield electrodes 130-1 , 130-2 in position with respect to the die 110 during its encapsulation in the device package 210. A combination of support members and I/O pins as shown in Figure 2 A and Figure 3 A is also possible, for example having one support connected to an I/O pin 220. Other modifications and configurations for supporting the shield electrodes will be apparent to those skilled in the art in light of this disclosure.
[0055] Figure 4 shows the isolator 400 having one instance of the coupling element 120 connected between all four of the circuit domains 115, and thereby communication is possible between any two of the circuit domains 115. However, in general the coupling element 120 can be implemented to facilitate communications between any two or more of the mutually isolated circuit domains 1 15. For example, separate instances of an coupling element 120 may be provided between any two or more of the circuit domains 1 15, and in any combination. For example, a first instance of the coupling element 120 may be provided between the circuit domain 1 15-1 and the circuit domain 1 15-2, and a second instance of the coupling element 120 may be provided between the circuit domain 1 15-3 and the circuit domain 1 15-4. In this example, the circuit domain 1 15-1 can communicate only with the circuit domain 1 15-2 and vice versa. Similarly, the circuit domain 115-3 can communicate only with the circuit domain 115-4 and vice versa.
[0056] Like the chip 110 of Figure 1, the multi -domain chip 410 of Figure 4 can be implemented using an SOS substrate, an SOI substrate, or any other substrate that contains an insulating layer capable of galvanic isolation. The substrate that is used to form the
electrodes 130-1 , 130-2, 130-3, 130-4 are electrically conductive elements that are physically separate and electrically isolated from one another. Each of the four shield electrodes 130 may be electrically connected to and mechanically anchored by a corresponding ground or signal pin of the lead frame. Because the shield electrodes 130-1 , 130-2, 130-3, 130-4 are electrically isolated from one another and disposed under only their respective οΐΓομίί domains, common-mode transients on one or more of the ground planes of respective ones of the circuit domains 115-1, 115-2, 115-3, 115-4 are inhibited from coupling into the sensitive circuits of the other circuit domain(s) of the chip to corrupt the signals therein. Of course, common-mode transients appear across the coupling element 120, but this may or may not pose a signal integrity problem, depending on the type of isolation element used in the isolator. For example, in the case of inductive coupling, a common-mode voltage transient generally does not get converted into an output signal. For signal coupling elements that are sensitive to common-mode transients, for example capacitive coupling, the coupling element 120 is generally differentially balanced to block such transients, as will be readily appreciated by those skilled in the art.
the circuit domains 1 15-1 , 1 15-2, 115-3, 1 15-4, respectively. As noted above, the Figures herein are not to scale and the gap or spacing between any two of the shield electrodes 130-1, 130-2, 130-3, 130-4 can be very small in practice and depends on the required CMTI (typically greater than 1 kV^s) of the device and the dielectric strength of the plastic encapsulate of the device package 210. In one example, the spacing between the shield electrodes 130-1, 130-2, 130-3, 130-4 is about 50 μηι. The gap between adjacent shield electrodes poses challenges for packaging the isolator dies. For example, conventional adhesive paste dispensing equipment and methods are often not suitable, as the adhesive paste will flow into the gap between adjacent shield electrodes and may fall through the gap onto the packaging equipment, resulting in unwanted contamination and fouling.
[0060] Figure 6 is a flow diagram of a method 600 of producing a two-region single- die isolator 200 in accordance with an embodiment of the present invention. It will be appreciated by persons of skill in the art that the method 600 could easily be adapted to making the four region isolator 400 or indeed any such isolator having a practical number
[0063J The die 1 10 can be attached to the shield electrodes 130- 1 , 130-2 at step 615 by any of a number of methods, or combinations thereof, including : a. Attaching one or more sections of a stiffening (e.g., sticky polyimide) tape 702 under the shield electrodes 130 and bridging the gaps therebetween, and then mounting the die 1 10 onto the tape/shield electrode assembly using a non- conductive adhesive 704. This method is the closest analogue to the standard production technique where a die is mounted to a single die paddle. The adhesive 704 and the stiffening tape 702 are selected to have dielectric strengths that provide the required galvanic isolation. An example device processing using this technique is shown in cross-sectional end view in Figure 7A; b. Applying a measured amount of adhesive 706 on the portion of each of the shield electrodes 130 that corresponds to the location whereon the die 1 10 is to be mounted, and then mounting the die 1 10 so that the adhesive 706 does not flow into the gap 708 between the shield electrodes 130. This method requires
110. The adhesive may be continuous or patterned to keep the adhesive 712 away from the gaps between respective pairs of shield electrodes 130. If the adhesive 712 is continuous, it must be non-conductive in order to maintain galvanic isolation. If the adhesive 712 is patterned, the patterning may include forming adhesive-free saw-streets between dies, such that there is ease of alignment and debris reduction during die singulation. Die singulation may be done with diamond saws or laser scribes or other methods known to. those skilled in the art. An example of the use of a continuous adhesive layer is shown in Figure 7C, while an example of using patterned adhesive is shown in Figure 7D.
[0064J The application and patterning of adhesive may be performed using screen printing/stencilling or other processes well known to those skilled in the art.
[0065] At a step 620, a wire bonding process using conventional wire-bonding techniques is performed to electrically connect the I/O pads (not shown) of the die 1 10 to the I/O pins 220 of the lead frame. In addition, if one or more of the shield electrodes 130
electrodes can be provided by printing or otherwise forming one or more layers of metal or other conductive material(s) on the backside of the isolator die. Irrespective of whether or not the shield electrodes are formed by a lead frame or other form of metal frame, a metal frame is nonetheless used to provide electrical connectivity and/or mechanical support to the die or chip.
[0068] Many modifications will be apparent to those skilled in the art without departing from the scope of the present invention.

Claims

CLAIMS:
1. A digital isolator, including:
integrated circuit portions mutually spaced on a single electrically insulating die;
an isolation barrier disposed between the integrated circuit portions to provide galvanic isolation therebetween;
at least one coupling structure configured to provide signal coupling between the galvanically isolated integrated circuit portions; and
mutually spaced electrodes on which the die is mounted, the electrodes being arranged below respective ones of the integrated circuit portions to , improve common-mode transient immunity "of the isolator.
r
2. The digital isolator of claim 1 , wherein each of the mutually spaced electrodes is disposed below a corresponding one of the integrated circuit portions and does not
7. The digital isolator of any one of claims 1 to 3, wherein the mutually spaced electrodes are connected to respective signal pins of the isolator.
8. The digital isolator of any one of claims 1 to 7, wherein at least one of the mutually spaced electrodes is supported by a corresponding conductive component that is not a signal pin of the isolator.
9. The digital isolator of any one of claims 1 to 8, wherein the mutually spaced electrodes are parts of a pre-formed metal frame.
10. The digital isolator of any one of claims 1 to 9, wherein the at least one coupling structure provides capacitive coupling between the galvanically isolated integrated circuit portions, the integrated circuit portions being formed by a plurality of layers on the single die, the layers including metal and dielectric layers and at least one semiconductor layer; and
12. A method of producing a digital isolator, the method including:
receiving a digital isolator die having integrated circuit portions mutually spaced on a single electrically insulating substrate, an isolation barrier being disposed between the integrated circuit portions to provide galvanic isolation therebetween, and at least one coupling structure to provide signal coupling between the galvanically isolated integrated circuit portions; and mounting the digital isolator die on mutually spaced electrodes such that the electrodes are arranged below respective ones of the integrated circuit portions to improve common-mode transient immunity of the digital isolator.
13. The method of claim 12, wherein the step of mounting includes attaching the mutually spaced electrodes to a stiffening tape, and attaching the digital isolator die to the mutually spaced electrodes using an adhesive.
14. The method of claim 13, wherein the adhesive is an electrically insulating adhesive
17. The method of claim 12, wherein the step of mounting includes coating an adhesive onto the backside of a wafer including a plurality of instances of the digital isolator die before die singulation, and using the adhesive to attach the singulated digital isolator die to the mutually spaced electrodes, whereby the adhesive coats only selected regions of the wafer backside prior to die singulation so that it does not extend between the mutually spaced electrodes.
18. The method of claim 12, wherein the step of mounting includes attaching a double- sided adhesive die attach film (DAF) to the backside of a processed wafer or substrate, dividing the wafer or substrate to provide singulated isolator dies having the DAF film attached thereto, heating the mutually spaced electrodes, and pressing the DAF film attached to the isolator die against the mutually spaced electrodes to attach the isolator die to the mutually spaced electrodes.
19. A digital isolator produced by the method of any one of claims 12 to 18.
PCT/AU2013/000989 2012-09-07 2013-09-02 Digital isolator with improved cmti WO2014036594A1 (en)

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US9660848B2 (en) 2014-09-15 2017-05-23 Analog Devices Global Methods and structures to generate on/off keyed carrier signals for signal isolators
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