WO2014007107A1

WO2014007107A1 - Solid-state imaging device, driving method, and electronic device

Info

Publication number: WO2014007107A1
Application number: PCT/JP2013/067362
Authority: WO
Inventors: 中村　良助; 史彦古閑; 晴久永野川
Original assignee: ソニー株式会社
Priority date: 2012-07-03
Filing date: 2013-06-25
Publication date: 2014-01-09
Also published as: CN104412575A; JPWO2014007107A1

Abstract

The present technology relates to a solid-state imaging device, driving method, and electronic device that allow the practical application of a pixel having an overflow structure. A low-driving-capability transistor generates a transfer pulse to be input to a gate electrode of a transfer transistor for a pixel having an overflow structure. A high-driving-capability transistor is connected in parallel with the low-driving-capability transistor, and generates a transfer pulse. After driving the low-driving-capability transistor, a driving circuit stops the low-driving-capability transistor, and drives the high-driving-capability transistor. The present technology may, for example, be applied to a CMOS image sensor.

Description

Solid-state imaging device, driving method, and electronic apparatus

The present technology relates to a solid-state imaging device, a driving method, and an electronic device, and more particularly, to a solid-state imaging device, a driving method, and an electronic device that enable practical use of a pixel having an overflow structure.

As a solid-state imaging device, a CMOS solid-state imaging device (hereinafter referred to as a CMOS image sensor) that can be manufactured by a process similar to a CMOS (Complementary Metal-Oxide Semiconductor) integrated circuit is known.

The CMOS image sensor is characterized in that an active structure having an amplification function for each pixel can be easily created by a miniaturization technique associated with the CMOS process. The CMOS image sensor also has peripheral circuits such as a drive circuit that drives the pixel array unit and a signal processing circuit that processes signals output from each pixel of the pixel array unit on the same chip (substrate) as the pixel array unit. It can be accumulated in Due to such features, CMOS image sensors have attracted attention, and many researches and developments have been made on CMOS image sensors.

As a result, in recent years, a photoelectric conversion unit that photoelectrically converts light of each wavelength of blue and red in the vertical direction of the same pixel is provided, and a solid-state imaging device having an organic photoelectric conversion film has been proposed for the green photoelectric conversion unit. (For example, refer to Patent Document 1).

In this solid-state imaging device, the green photoelectric conversion unit has a contact unit that transmits the signal charge photoelectrically converted by the organic photoelectric conversion film to the high-concentration N-type diffusion layer formed on the silicon (Si) substrate. Depending on the amount of light, the signal charge overflows over the potential barrier of the P-type impurity region and is accumulated in the N-type accumulation unit. The signal charge accumulated in the accumulation unit is transferred to the floating diffusion (FD) by the transfer transistor.

Such a structure in which the signal charge is overflowed and supplied to the storage unit is called an overflow structure. Here, it has been described that the carrier of the signal charge is an electron, but the case of a hole is the same as that of an electron except that the polarity is switched.

Even in a CMOS image sensor having an overflow structure, a signal having a predetermined potential is applied to a gate electrode of a transfer transistor of each color pixel by a transistor of a vertical drive circuit, as in a general CMOS image sensor not having an overflow structure. Applied.

JP 2011-138927 A

By the way, in the CMOS image sensor provided with the pixel having the overflow structure, it is necessary to devise for practical use.

The present technology has been made in view of such a situation, and makes it possible to put a pixel having an overflow structure into practical use.

A solid-state imaging device according to a first aspect of the present technology includes: a low drive capability transistor that generates a signal to be input to a gate electrode of a transfer transistor of a pixel having an overflow structure; the low drive capability transistor connected in parallel; A solid-state imaging device comprising: a high drive capability transistor that generates a signal to be input to an electrode; and a drive unit that drives the high drive capability transistor after driving the low drive capability transistor and then stopping the low drive capability transistor It is.

The driving method according to the first aspect of the present technology corresponds to the solid-state imaging device according to the first aspect of the present technology.

In the first aspect of the present technology, after the low drive capability transistor that generates a signal to be input to the gate electrode of the transfer transistor of the pixel having the overflow structure is driven, the low drive capability transistor is stopped and the low drive capability is reduced. A high driving capability transistor connected in parallel with the capability transistor and generating a signal to be input to the gate electrode is driven.

An electronic apparatus according to a second aspect of the present technology is connected in parallel to a pixel having an overflow structure, a low drive capability transistor that generates a signal to be input to a gate electrode of a transfer transistor of the pixel, and the low drive capability transistor. A high drive capability transistor that generates a signal to be input to the gate electrode; a drive unit that drives the low drive capability transistor after driving the low drive capability transistor; and drives the high drive capability transistor; And an output unit that outputs image data corresponding to an electrical signal generated by a pixel.

In a second aspect of the present technology, the pixel having an overflow structure, a low drive capability transistor that generates a signal to be input to a gate electrode of a transfer transistor of the pixel, and the low drive capability transistor are connected in parallel, A high drive capability transistor that generates a signal to be input to the gate electrode, and after the low drive capability transistor is driven, the low drive capability transistor is stopped, the high drive capability transistor is driven, and the pixel The image data corresponding to the electrical signal generated by is output.

A solid-state imaging device according to a third aspect of the present technology includes a first transistor that generates a first potential signal to be input to a gate electrode of a transfer transistor of a pixel having an overflow structure, and the first transistor in parallel. A second transistor connected to generate a signal having a second potential higher than the first potential inputted to the gate electrode; and driving the first transistor, and then stopping the first transistor. , A solid-state imaging device including a driving unit that drives the second transistor.

In the third aspect of the present technology, after the first transistor that generates the signal of the first potential to be input to the gate electrode of the transfer transistor of the pixel having the overflow structure is driven, the first transistor is stopped. Then, the second transistor connected in parallel with the first transistor and generating a signal having a second potential higher than the first potential inputted to the gate electrode is driven.

An electronic device according to a fourth aspect of the present technology includes a pixel having an overflow structure, a first transistor that generates a first potential signal input to a gate electrode of a transfer transistor of the pixel, and the first transistor A second transistor that is connected in parallel to generate a signal having a second potential higher than the first potential that is input to the gate electrode; and after driving the first transistor, the first transistor And an output unit that outputs image data corresponding to an electrical signal generated by the pixel.

In a fourth aspect of the present technology, a pixel having an overflow structure, a first transistor that generates a signal of a first potential that is input to a gate electrode of a transfer transistor of the pixel, and the first transistor are parallel to the first transistor. And a second transistor for generating a signal having a second potential higher than the first potential input to the gate electrode, and after the first transistor is driven, the first transistor The transistor is stopped, the second transistor is driven, and image data corresponding to the electrical signal generated by the pixel is output.

According to the present technology, a pixel having an overflow structure can be put into practical use.

It is a block diagram which shows the structural example of one Embodiment of the electronic device to which this technique is applied. It is a figure which shows the structural example of the image sensor of FIG. It is a figure which shows the circuit structural example of the pixel of FIG. It is sectional drawing which shows the outline of a pixel. It is a timing chart which shows an example of a transfer pulse. It is a figure which shows the potential energy of a vertical transfer path. FIG. 3 is a circuit diagram illustrating a first configuration example of a transfer pulse generation circuit. It is a timing chart which shows the 1st example of a transfer pulse. It is a circuit diagram which shows the 2nd structural example of a transfer pulse generation circuit. It is a timing chart which shows the 2nd example of a transfer pulse.

<One embodiment>
[Configuration example of one embodiment of electronic device]
FIG. 1 is a block diagram illustrating a configuration example of an embodiment of an electronic device to which the present technology is applied.

The electronic device 10 includes an optical block 11, an image sensor 12, a camera signal processing unit 13, an image data processing unit 14, a display unit 15, an external interface (I / F) unit 16, a memory unit 17, a media drive 18, an OSD (On Screen Display) unit 19 and control unit 20 are provided. In addition, a user interface (I / F) unit 21 is connected to the control unit 20.

Furthermore, the image data processing unit 14, the external interface unit 16, the memory unit 17, the media drive 18, the OSD unit 19, the control unit 20, and the like are connected to each other via a bus 22. The electronic device 10 captures an image of a subject and displays an image obtained as a result on the display unit 15 or records image data on the media drive 18.

Specifically, the optical block 11 of the electronic device 10 includes a focus lens, a diaphragm mechanism, and the like. The optical block 11 forms an optical image of the subject on the light receiving surface of the image sensor 12.

The image sensor 12 is configured by a CMOS image sensor, a MOS (Metal-Oxide Semiconductor) type solid-state imaging device, or the like. The image sensor 12 receives light from the optical block 11 and photoelectrically converts an optical image obtained by the light reception to generate an electrical signal. The image sensor 12 supplies the generated electrical signal to the camera signal processing unit 13.

The camera signal processing unit 13 performs various camera signal processing such as knee correction, gamma correction, and color correction on the electrical signal supplied from the image sensor 12. The camera signal processing unit 13 functions as an output unit, and outputs image data obtained as a result of camera signal processing to the image data processing unit 14.

The image data processing unit 14 performs an encoding process on the image data supplied from the camera signal processing unit 13. The image data processing unit 14 supplies the encoded data generated by performing the encoding process to the external interface unit 16 and the media drive 18. Further, the image data processing unit 14 performs a decoding process on the encoded data supplied from the external interface unit 16 or the media drive 18.

The image data processing unit 14 supplies the image data generated by performing the decoding process to the display unit 15. In addition, the image data processing unit 14 superimposes the display data acquired from the OSD unit 19 on the processing for supplying the image data supplied from the camera signal processing unit 13 to the display unit 15 and the display unit 15. To supply.

The display unit 15 displays an image corresponding to the image data supplied from the image data processing unit 14 or image data on which display data is superimposed.

The external interface unit 16 includes, for example, a USB (Universal Serial Bus) input / output terminal and the like, and is connected to a printer when printing an image. In addition, a drive is connected to the external interface unit 16 as necessary, and a removable medium such as a magnetic disk or an optical disk is appropriately mounted, and a computer program read from them is stored in the memory unit 17 as necessary. Installed. Further, the external interface unit 16 has a network interface connected to a predetermined network such as a LAN (Local Area Network) or the Internet.

The memory unit 17 stores a program executed by the control unit 20, various data necessary for the control unit 20 to perform processing, and the like. The program stored in the memory unit 17 is read and executed by the control unit 20 at a predetermined timing such as when the electronic device 10 is activated.

A recording medium is mounted on the media drive 18, and the media drive 18 drives the recording medium and records image data supplied from the image data processing unit 14. As the recording medium driven by the media drive 18, for example, any readable / writable removable medium such as a magnetic disk, a magneto-optical disk, an optical disk, or a semiconductor memory is used.

Further, the recording medium may be any kind of removable media, and may be a tape device, a disk, or a memory card. Of course, a non-contact IC (Integrated Circuit) card may be used. Further, the media drive 18 and the recording medium may be integrated and configured by a non-portable storage medium such as a built-in hard disk drive or an SSD (Solid State Drive).

The OSD unit 19 generates display data such as a menu screen or an icon made up of symbols, characters, or figures and outputs it to the image data processing unit 14.

The control unit 20 is configured using a CPU (Central Processing Unit) or the like. The control unit 20 controls each unit so that the electronic device 10 performs an operation according to a user operation by executing a program.

Specifically, the control unit 20 reads the encoded data from the media drive 18 in accordance with an instruction from the user interface unit 21, for example, and other devices connected via the network from the external interface unit 16 Can be supplied. Further, the control unit 20 may acquire encoded data and image data supplied from another device via a network via the external interface unit 16 and supply the acquired data to the image data processing unit 14. it can.

The user interface unit 21 receives an operation from the user and supplies an instruction corresponding to the operation to the control unit 20.

[Image sensor configuration example]
FIG. 2 is a diagram illustrating a configuration example of the image sensor 12 of FIG.

The image sensor 12 of FIG. 2 includes a pixel array unit 32, a vertical drive circuit 33, a column processing unit 34, a horizontal drive circuit 35, a horizontal drive circuit 35 in which pixels 31 including photoelectric conversion elements are two-dimensionally arranged in a matrix. The signal line 36, the output circuit 37, and the timing control circuit 38 are included. These are all integrated on a semiconductor substrate 39 made of the same silicon.

In the pixel array section 32, pixels 31 are two-dimensionally arranged by m rows and n columns (m and n are integers of 1 or more). A row control line (not shown) is wired for each row to the m rows and n columns of pixels 31, and a vertical signal line 31A is wired for each column. In FIG. 2, only the pixels 31 corresponding to 10 rows and 12 columns are shown in order to simplify the drawing.

The pixel 31 receives light from the subject and photoelectrically converts an optical image obtained by the light reception to generate an electrical signal. The pixel 31 supplies the generated electric signal to the column processing unit 34 in accordance with the selection pulse supplied from the vertical drive circuit 33 via the row control line.

The vertical drive circuit 33 is configured by a shift register or the like. The vertical drive circuit 33 sequentially selects each pixel 31 of the pixel array unit 32 in units of rows based on the clock signal and control signal supplied from the timing control circuit 38, and for each pixel 31 in the selected row. A selection pulse is supplied via the row control line. As a result, electric signals are supplied to the column processing unit 34 in units of rows.

The column processing unit 34 is provided with a column signal processing circuit 34A corresponding to each column of the pixels 31 of the pixel array unit 32. The column signal processing circuit 34A acquires an electric signal output from the pixels 31 for one row for each column based on the clock signal and the control signal supplied from the timing control circuit 38.

The column signal processing circuit 34A is a CDS (Correlated Sampling (correlated double sampling)), signal amplification, A / D (Analog / Digital) conversion, etc. for removing fixed pattern noise specific to the pixel 31 from the electric signal. Signal processing. The column signal processing circuit 34 A supplies the electric signal after the signal processing to the output circuit 37 through the horizontal signal line 36 in accordance with the selection pulse from the horizontal driving circuit 35.

The horizontal drive circuit 35 is configured by a shift register or the like. The horizontal drive circuit 35 sequentially selects each column signal processing circuit 34A based on the clock signal and control signal supplied from the timing control circuit 38, and supplies a selection pulse to the selected column signal processing circuit 34A. As a result, the electric signal after signal processing is supplied to the output circuit 37 via the horizontal signal line 36 in units of pixels 31.

The output circuit 37 performs various kinds of signal processing on the electrical signals sequentially supplied from the column signal processing circuits 34A via the horizontal signal line 36, and supplies them to the camera signal processing unit 13 in FIG. Specifically, for example, the output circuit 37 buffers the electric signal as it is, and supplies the buffered electric signal to the camera signal processing unit 13. Alternatively, the output circuit 37 buffers the electrical signal by performing signal processing such as black level adjustment, correction of variation for each column, and signal amplification, and supplies the buffered electrical signal to the camera signal processing unit 13. To do.

The timing control circuit 38 is based on the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the master clock MCK, and controls the clock signal and control that are the reference for the operation of the vertical drive circuit 33, the column processing unit 34, the horizontal drive circuit 35, and the like. Generate signal etc. The timing control circuit 38 supplies the generated clock signal, control signal, and the like to the vertical drive circuit 33, the column processing unit 34, the horizontal drive circuit 35, and the like.

[Pixel circuit configuration example]
FIG. 3 is a diagram illustrating a circuit configuration example of the pixel 31 in FIG. 2.

3, the pixel 31 includes a photoelectric conversion element 51, a transfer transistor 52, an FD (floating diffusion) 53, a reset transistor 54, an amplification transistor 55, and a selection transistor 56.

Here, an example is shown in which N-channel MOS transistors are used as the transfer transistor 52, reset transistor 54, amplification transistor 55, and selection transistor 56, but P-channel MOS transistors can also be used.

In addition, the pixel 31 is connected to a power source having a predetermined potential VDD (for example, 2.5 V). Further, the pixel 31 is provided with a reset wiring 71, a transfer wiring 72, and a selection wiring 73 as row control lines.

The photoelectric conversion element 51 has an anode connected to a first power supply potential, for example, ground. The photoelectric conversion element 51 photoelectrically converts light from the subject into signal charges (photoelectrons) having a charge amount corresponding to the amount of the light, and accumulates the signal charges.

The transfer transistor 52 has a drain connected to the FD 53, a source connected to the cathode of the photoelectric conversion element 51, and a gate connected to the transfer wiring 72. The transfer transistor 52 is turned on (conductive) when the transfer pulse TRF is supplied to the gate from the vertical drive circuit 33 of FIG. Is transferred to the FD 53.

The reset transistor 54 has a drain connected to the power supply wiring 70 to which the power supply is connected, a source connected to the FD 53, and a gate connected to the reset wiring 71. The reset transistor 54 is turned on when a reset pulse RST is supplied to the gate from the vertical drive circuit 33 via the reset wiring 71, and resets the FD 53 by discarding the signal charge of the FD 53 to the power supply wiring 70.

The amplifying transistor 55 has a drain connected to the power supply wiring 70, a source connected to the drain of the selection transistor 56, and a gate connected to the FD 53. The amplification transistor 55 supplies a signal corresponding to the potential of the FD 53 to the selection transistor 56. That is, the amplification transistor 55 supplies an electric signal corresponding to the signal charge accumulated in the photoelectric conversion element 51 to the selection transistor 56.

The selection transistor 56 has a drain connected to the source of the amplification transistor 55, a source connected to the vertical signal line 31A, and a gate connected to the selection wiring 73. The selection transistor 56 is turned on when the selection pulse SEL is supplied to the gate from the vertical drive circuit 33 via the selection wiring 73, and the electrical signal output from the amplification transistor 55 is transmitted via the vertical signal line 31A. To the column signal processing circuit 34A.

As described above, the vertical drive circuit 33 controls the signal charge transfer operation from the photoelectric conversion element 51 to the FD 53 by the transfer pulse TRF. The vertical drive circuit 33 controls the reset operation of the FD 53 by the reset pulse RST. Further, the vertical drive circuit 33 controls a selection operation for selecting the pixel 31 as a pixel that outputs an electric signal by the selection pulse SEL.

[Cross section of pixel]
FIG. 4 is a cross-sectional view illustrating the outline of the pixel 31.

In FIG. 4, light enters the image sensor 12 from the back surface side (upper side in the drawing) opposite to the side on which the transfer transistor 52 is formed on the front surface side (lower side in the drawing) of the semiconductor substrate 39. It is assumed that the back-illuminated CMOS image sensor.

Further, in FIG. 4, only the transfer transistor 52 among the transfer transistor 52, the reset transistor 54, the amplification transistor 55, and the selection transistor 56 is illustrated in order to simplify the drawing.

As shown in FIG. 4, the pixel 31 is provided with a photoelectric conversion element 51, a transfer transistor 52, and the like for each of red, green, and blue. On the back side of the semiconductor substrate 39, an on-chip lens 81, a planarizing film 82, an upper electrode 83, an organic photoelectric conversion film 84, an insulating film 85, and an insulating film 86 are provided in this order from the outside.

The on-chip lens 81 condenses light from the subject on the photoelectric conversion element 51. Light emitted from the on-chip lens 81 is incident on the organic photoelectric conversion film 84 through the planarization film 82 and the upper electrode 83.

On the planarizing film 82, a vertical transfer path 96 described later and a light shielding film 82A that shields the extension 92a are formed. As the light shielding film 82A, for example, Al, Ti, W, or the like can be used. In FIG. 4, the light shielding film 82A is formed on the upper electrode 83 via an insulating film, but in this case, the potential of the light shielding film 82A is not fixed. Therefore, the light shielding film 82A may be formed so as to be in contact with the upper electrode 83. In this case, the potential of the light shielding film 82A is held at the same potential as that of the upper electrode 83.

The upper electrode 83 is made of a transparent conductive film such as an indium tin (ITO) film or an indium zinc oxide film, and a fixed negative voltage VL is applied to the upper electrode 83.

The organic photoelectric conversion film 84 is a green photoelectric conversion element 51G, and has a characteristic of absorbing light having a green wavelength. The organic photoelectric conversion film 84 is made of an organic photoelectric conversion material containing, for example, a rhodamine dye, a melocyanine dye, or quinacridone. The organic photoelectric conversion film 84 receives green light of the incident light and performs photoelectric conversion. Thereby, a pair of electrons and holes is formed in the organic photoelectric conversion film 84.

In the insulating film 85, a lower electrode 85A is formed. The lower electrode 85A is made of a transparent conductive film such as an indium tin (ITO) film or an indium zinc oxide film, and a voltage VH higher than the voltage VL is applied to the lower electrode 85A.

Thereby, the electrons in the pair of electrons and holes formed by the organic photoelectric conversion film 84 are attracted to the lower electrode 85A to which the voltage VH higher than the voltage VL is applied. The voltage VH is determined by the potential of an overflow barrier described later. On the other hand, the hole is drawn to the upper electrode 83 to which the negative voltage VL is applied, and is discharged through a wiring (not shown).

The insulating film 86 is an antireflection film and is made of, for example, hafnium oxide. In this case, since holes are excited on the back side of the semiconductor substrate 39, dark current generated at the back side interface of the semiconductor substrate 39 by application of the voltage VH to the lower electrode 85A can be suppressed.

In the insulating film 86, a contact plug 86A connected to the connecting portion 101 provided on the back side of the semiconductor substrate 39 is formed so as to penetrate therethrough. The contact plug 86 A transfers the signal charge of electrons drawn to the lower electrode 85 A to the connection portion 101.

In the semiconductor substrate 39, a well region 91 made of a p-type semiconductor region is formed. In the well region 91, a blue photoelectric conversion element 51B and a red photoelectric conversion element 51R are formed so as to be stacked in the light incident direction.

The photoelectric conversion element 51B includes an n-type semiconductor region 92 made of n-type impurities formed on the back surface side of the semiconductor substrate 39 and an extension portion 92a formed so as to extend partially so as to reach the front surface side of the semiconductor substrate 39. Consists of.

The n-type semiconductor region 92 is irradiated with light from the subject through the on-chip lens 81, the planarization film 82, the upper electrode 83, the organic photoelectric conversion film 84, the insulating film 85, and the insulating film 86. At this time, since the green light is absorbed by the organic photoelectric conversion film 84, the light irradiated to the n-type semiconductor region 92 is light other than green.

The n-type semiconductor region 92 absorbs blue light having a short wavelength among the irradiated light, performs photoelectric conversion, and accumulates signal charges obtained as a result. The extension part 92 a outputs the signal charge to the surface side of the semiconductor substrate 39. A high-concentration p-type semiconductor region 93 serving as a hole accumulation layer is formed on the surface side of the extension 92a.

The photoelectric conversion element 51R is composed of an n-type semiconductor region 94 formed on the surface side of the semiconductor substrate 39. On the surface side of the n-type semiconductor region 94, a high-concentration p-type semiconductor region 95 serving as a hole accumulation layer is formed.

In the n-type semiconductor region 94, light from the subject passes through the on-chip lens 81, the planarization film 82, the upper electrode 83, the organic photoelectric conversion film 84, the insulating film 85, the insulating film 86, and the n-type semiconductor region 92. Is irradiated. In addition, since green light is absorbed by the organic photoelectric conversion film 84 and blue light is also absorbed by the n-type semiconductor region 92, the light irradiated to the n-type semiconductor region 94 is red light. The n-type semiconductor region 94 absorbs the irradiated red light, performs photoelectric conversion, accumulates signal charges obtained as a result, and outputs the accumulated signal charges to the surface side of the semiconductor substrate 39.

In the photoelectric conversion element 51B (51R), by forming the p-type semiconductor region 93 (95) at the interface of the semiconductor substrate 39, dark current generated at the interface of the semiconductor substrate 39 can be suppressed.

In the well region 91, a vertical transfer path 96 for outputting the signal charge transferred from the contact plug 86A to the surface side of the semiconductor substrate 39 is formed. The vertical transfer path 96 has an overflow structure, and is configured by connecting the connection portion 101, the potential barrier layer 102, and the charge storage layer 103 in order from the back surface side of the semiconductor substrate 39.

The connecting portion 101 is made of an n-type impurity region having a high impurity concentration. The connection portion 101 is supplied with signal charges transferred from the contact plug 86A. The potential barrier layer 102 is made of a low-concentration p-type impurity region, and constitutes an overflow barrier between the connection portion 101 and the charge storage layer 103.

In the connecting portion 101, the signal charge exceeding the saturation charge amount of the connecting portion 101 overflows the potential barrier layer 102 and overflows to the charge storage layer 103. That is, in the connection part 101, the signal charge overflows in the vertical direction. The charge storage layer 103 is composed of an n-type impurity region having a concentration lower than that of the connection portion 101, and stores overflowed signal charges. The charge storage layer 103 outputs the stored signal charge to the surface side of the semiconductor substrate 39.

Note that a high-concentration p-type semiconductor region 104 serving as a hole storage layer is formed on the surface side of the charge storage layer 103. Thereby, dark current generated at the interface of the semiconductor substrate 39 can be suppressed.

In the well region 91, a blue FD 53B is formed adjacent to the extension 92a on the surface side of the semiconductor substrate 39, and a red FD 53R is formed adjacent to the photoelectric conversion element 51R. An FD 53G for green is formed adjacent to the path 96. FD53B, FD53R, and FD53G are configured by n-type high concentration impurity regions.

Further, on the surface side of the semiconductor substrate 39, a multilayer wiring layer 87 having wirings 87C stacked in a plurality of layers (three layers in this embodiment) is formed via an interlayer insulating film 87A.

In the multilayer wiring layer 87, a blue transfer transistor 52B is provided corresponding to the photoelectric conversion element 51B, and a red transfer transistor 52R is provided corresponding to the photoelectric conversion element 51R. A green transfer transistor 52G is provided corresponding to the photoelectric conversion element 51G.

The gate electrode 111B of the transfer transistor 52B is formed on the semiconductor substrate 39 near the extension 92a via the interlayer insulating film 87A, and the gate electrode 111R of the transfer transistor 52R is interlayered on the semiconductor substrate 39 near the photoelectric conversion element 51R. It is formed via an insulating film 87A. The gate electrode 111G is formed on the semiconductor substrate 39 in the vicinity of the vertical transfer path 96 via an interlayer insulating film 87A. The gate electrode 111B, the gate electrode 111R, and the gate electrode 111G are made of, for example, polysilicon.

When the transfer pulse TRF is applied to the gate electrode 111B, the transfer transistor 52B supplies the signal charge corresponding to the blue light accumulated in the n-type semiconductor region 92 and output via the extension 92a to the FD 53B. . When the transfer pulse TRF is applied to the gate electrode 111R, the transfer transistor 52R supplies the FD 53R with a signal charge corresponding to the red light that is accumulated in the n-type semiconductor region 94 and output.

Further, when the transfer pulse TRF is applied to the gate electrode 111G, the transfer transistor 52G supplies the FD 53G with a signal charge corresponding to the green light that is stored in the charge storage layer 103 and output.

As described above, since the pixel 31 has the vertical transfer path 96, the charge storage layer 103 can be formed close to the gate electrode 111G, and transfer from the charge storage layer 103 to the FD 53G is advantageous.

In the present embodiment, the organic photoelectric conversion film 84 is provided as the photoelectric conversion element 51G. However, an organic photoelectric conversion film may be provided as a blue or red photoelectric conversion element. For example, when an organic photoelectric conversion film is provided as a blue photoelectric conversion element, the organic photoelectric conversion film has a characteristic of absorbing light having a blue wavelength. And the photoelectric conversion element comprised similarly to the photoelectric conversion element 51B of FIG. 4 functions as a green photoelectric conversion element, and the photoelectric conversion element comprised similarly to the photoelectric conversion element 51R is as a red photoelectric conversion element. Function.

Further, when an organic photoelectric conversion film is provided as a red photoelectric conversion element, the organic photoelectric conversion film has a characteristic of absorbing light having a red wavelength. And the photoelectric conversion element comprised similarly to the photoelectric conversion element 51B of FIG. 4 functions as a blue photoelectric conversion element, and the photoelectric conversion element comprised similarly to the photoelectric conversion element 51R is as a green photoelectric conversion element. Function.

As the organic photoelectric conversion film that photoelectrically converts blue light, an organic photoelectric conversion material containing a coumaric acid dye, tris-8-hydroxyquinori Al (Alq3), a melocyanine dye, or the like can be used. Moreover, as an organic photoelectric conversion film that photoelectrically converts red light, an organic photoelectric conversion material containing a phthalocyanine dye can be used.

However, in the case where the photoelectric conversion element 51B and the photoelectric conversion element 51R are provided in the semiconductor substrate 39 as in the present embodiment, the difference in the wavelength of the light split between the photoelectric conversion element 51B and the photoelectric conversion element 51R is large. Therefore, the spectral characteristics are good.

[Explanation of shaking of well region generated by transfer pulse TRF]
FIG. 5 is a timing chart showing an example of the transfer pulse TRF.

In FIG. 5, the horizontal axis represents time (t), and the vertical axis represents potential. In addition, from the earliest time, time t0, time t1, time t2, time t3, time t4, and time t5 are set.

In the example of FIG. 5, the potential of the selection wiring 73 changes from the low potential Vlow (for example, the ground potential GND) to the high potential Vhigh at time t0, and returns from the high potential Vhigh to the low potential Vlow at time t5. That is, the selection pulse SEL is supplied to the gate of the selection transistor 56 from time t0 to time t5.

Further, at time t0, the potential of the reset wiring 71 changes from the low potential Vlow to the high potential Vhigh, and returns from the high potential Vhigh to the low potential Vlow at time t1. That is, the reset pulse RST is supplied to the gate of the reset transistor 54 from time t0 to time t1.

As described above, from time t0 to time t1, the selection pulse SEL is supplied to the gate of the selection transistor 56, and the reset pulse RST is supplied to the gate of the reset transistor 54. Accordingly, during this period, the FD 53 is reset by the reset transistor 54, and no electrical signal is supplied to the column signal processing circuit 34A.

The potential of the transfer wiring 72 changes from the low potential Vlow to the high potential Vhigh at time t2, and returns from the high potential Vhigh to the low potential Vlow at time t3. That is, the transfer pulse TRF is supplied to the gate (

gate electrodes

111B, 111R, 111G) of the transfer transistor 52 from time t2 to time t3. At this time, the reset pulse RST is not supplied to the gate of the reset transistor 54.

Therefore, from time t2 to time t3, the signal charge transferred to the FD 53 by the transfer transistor 52 is not discarded, and the electric signal corresponding to the signal charge is sent from the amplification transistor 55 and the selection transistor 56 to the column signal processing circuit 34A. To be supplied.

Thereafter, at time t4, the potentials of the reset wiring 71 and the transfer wiring 72 change from the low potential Vlow to the high potential Vhigh, and return from the high potential Vhigh to the low potential Vlow at time t5. That is, from time t4 to time t5, the reset pulse RST is supplied to the gate of the reset transistor 54, and the transfer pulse TRF is supplied to the gate of the transfer transistor 52.

Accordingly, during this time, the signal charge accumulated in the photoelectric conversion element 51 is transferred to the FD 53 by the transfer transistor 52, and the signal charge is discarded by the reset transistor 54. Therefore, the selection pulse SEL is supplied to the gate of the selection transistor 56 from time t4 to time t5, but no electrical signal is supplied to the column signal processing circuit 34A.

As described above, in the example of FIG. 5, the electric signal corresponding to the light from the subject is supplied to the column signal processing circuit 34A from the time t2 to the time t3.

FIG. 6 is a diagram showing the potential energy of the vertical transfer path 96 when the transfer pulse TRF is the transfer pulse TRF of FIG.

As shown in FIG. 6A, when the transfer pulse TRF is not supplied to the gate of the transfer transistor 52, the potential barrier layer 102 of the vertical transfer path 96 constitutes an overflow barrier whose potential energy is a predetermined value.

However, when the transfer pulse TRF as shown in FIG. 5 is supplied to the gate of the transfer transistor 52, the rising and falling edges of the transfer pulse TRF are steep. Therefore, the well region 91 fluctuates when the transfer pulse TRF rises and falls. Thereby, when the transfer pulse TRF rises, the well region 91 swings to the plus bias side, and the potential energy of the potential barrier layer 102 becomes smaller than a predetermined value.

Therefore, of the signal charges transferred from the contact plug 86A via the connection portion 101, the charges that are not originally overflowed overflow into the charge storage layer 103 as noise charges. As a result, image quality degradation such as an increase in dark current and color shift occurs in the captured image.

Therefore, the vertical drive circuit 33 of the electronic device 10 generates a transfer pulse TRF whose rise is not steep.

[First Configuration Example of Transfer Pulse Generation Circuit]
FIG. 7 is a circuit diagram showing a first configuration example of a transfer pulse generation circuit that generates the transfer pulse TRF in the vertical drive circuit 33.

In the transfer pulse generation circuit 130 of FIG. 7, a low drive capability transistor 132 connected to the power supply line 131 and the control line 133A, and a high drive capability transistor 134 connected to the power supply line 131 and the control line 133B are parallel to the capacitor 135. It is comprised by connecting to.

Specifically, the power supply wiring 131 is connected to a power supply having a high potential Vhigh. The low drive capability transistor 132 is a transistor with a low drive capability compared to the high drive capability transistor 134, and less charge is output in the ON state than the high drive capability transistor 134. The low drive capability transistor 132 has a drain connected to the power supply wiring 131, a gate connected to the control wiring 133 A, and a source connected to the capacitor 135. The low drivability transistor 132 is turned on when a predetermined pulse is input to the gate from the control wiring 133A, and supplies a charge from the power source of the high potential Vhigh to the capacitor 135.

A drive circuit 133 that controls the driving of the low drive capability transistor 132 and the high drive capability transistor 134 is connected to the control wiring 133A. The control wiring 133A supplies a predetermined pulse output from the drive circuit 133 to the low drive capability transistor 132. A drive circuit 133 is connected to the control wiring 133B in the same manner as the control wiring 133A. The control wiring 133B supplies a predetermined pulse output from the drive circuit 133 to the high drive capability transistor 134.

The high drivability transistor 134 is a transistor having a high drivability compared to the low drivability transistor 132, and more charge is output in the on state than the low drivability transistor 132. The high drivability transistor 134 has a drain connected to the power supply wiring 131, a gate connected to the control wiring 133 B, and a source connected to the capacitor 135. The high drivability transistor 134 is turned on when a predetermined pulse is input to the gate from the control wiring 133 B, and supplies a charge from the power source to the capacitor 135.

The capacitor 135 generates a transfer pulse TRF by accumulating charges supplied from the low drive capability transistor 132 and the high drive capability transistor 134. That is, the low drive capability transistor 132 and the high drive capability transistor 134 generate a transfer pulse TRF via the capacitor 135. The generated transfer pulse TRF is supplied to the transfer wiring 72.

[First example of transfer pulse]
FIG. 8 is a timing chart showing the transfer pulse TRF generated by the transfer pulse generation circuit 130 of FIG.

In FIG. 8, the horizontal axis represents time (t), and the vertical axis represents potential. In addition, from the earliest time, time t0, time t1, time t11, time t12, time t13, time t14, time t4, and time t5 are set. The time t0, time t1, time t4, and time t5 in FIG. 8 are the same as those in FIG.

In the example of FIG. 8, the selection pulse SEL and the reset pulse RST are generated as in the example of FIG. At time t11, the potential of the control wiring 133A changes from the low potential Vlow to the high potential Vhigh, and returns from the high potential Vhigh to the low potential Vlow at time t12.

That is, from time t11 to time t12, the drive circuit 133 drives the low drive capability transistor 132 by supplying a pulse to the gate of the low drive capability transistor 132 via the control wiring 133A. At time t12, the drive circuit 133 stops supplying pulses to the low drive capability transistor 132, and stops the low drive capability transistor 132.

As a result, from time t11 to time t12, charges are slowly accumulated in the capacitor 135, and the potential of the transfer wiring 72 gradually rises from the low potential Vlow to the predetermined potential V.

Thereafter, at time t12, the potential of the control wiring 133B changes from the low potential Vlow to the high potential Vhigh, and at time t13, the potential returns from the high potential Vhigh to the low potential Vlow. That is, from time t12 to time t13, the drive circuit 133 drives the high drive capability transistor 134 by supplying a pulse to the gate of the high drive capability transistor 134 via the control wiring 133B. At time t 13, the drive circuit 133 stops supplying pulses to the low drive capability transistor 134 and stops the low drive capability transistor 134.

As a result, from time t12 to time t13, electric charge is quickly accumulated in the capacitor 135, and the potential of the transfer wiring 72 rapidly rises from the potential V to the high potential Vhigh. At time t13, no charge is accumulated in the capacitor 135, and the potential of the transfer wiring 72 returns to the low potential Vlow.

Further, at time t14, the potential of the control wiring 133A changes from the low potential Vlow to the high potential Vhigh again, and returns from the high potential Vhigh to the low potential Vlow at time t4. As a result, charge is again slowly accumulated in the capacitor 135, and the potential of the transfer wiring 72 gradually rises from the low potential Vlow to the potential V.

At time t4, the potential of the control wiring 133B changes from the low potential Vlow to the high potential Vhigh, and returns from the high potential Vhigh to the low potential Vlow at time t5. As a result, charges are quickly accumulated in the capacitor 135, and the potential of the transfer wiring 72 rapidly rises from the potential V to the high potential Vhigh. At time t5, the potential of the transfer wiring 72 returns to the low potential Vlow.

As described above, in the transfer pulse generation circuit 130, the drive circuit 133 drives the low drive capability transistor 132 at the rising edge of the transfer pulse TRF, then stops the low drive capability transistor 132, and causes the high drive capability transistor 134 to Drive. Therefore, the rising edge of the transfer pulse TRF becomes gentle. Therefore, the well region 91 does not fluctuate and the overflow of noise charges to the charge storage layer 103 can be suppressed. As a result, it is possible to suppress deterioration in image quality of the captured image.

In the transfer pulse generation circuit 130, the voltages applied to the drains of the low drive capability transistor 132 and the high drive capability transistor 134 are the same. Therefore, even when the low drive capability transistor 132 and the high drive capability transistor 134 are turned on at the time of switching from the low drive capability transistor 132 to the high drive capability transistor 134, the low drive capability transistor 132 and the high drive capability transistor 134 No through current is generated between them. Therefore, it is not necessary to provide a period for stopping both the low drive capability transistor 132 and the high drive capability transistor 134 at the time of switching.

Furthermore, when the transfer pulse TRF falls, the well region 91 swings to the negative bias side, so that the potential energy of the potential barrier layer 102 becomes larger than a predetermined value. Therefore, since the charge that does not originally overflow does not overflow into the charge storage layer 103 as noise charge, the transfer pulse generation circuit 130 does not have a circuit that blunts the falling edge of the transfer pulse TRF. Thereby, the falling time of the transfer pulse TRF can be shortened. As a result, the imaging time can be shortened.

[Second Configuration Example of Transfer Pulse Generation Circuit]
FIG. 9 is a circuit diagram showing a second configuration example of the transfer pulse generation circuit that generates the transfer pulse TRF in the vertical drive circuit 33.

The transfer pulse generation circuit 150 in FIG. 9 includes a transistor 152 connected to the power supply wiring 151A and the control wiring 153A, and a transistor 154 connected to the power supply wiring 151B and the control wiring 153B connected in parallel to the capacitor 155. Composed.

Specifically, the power supply wiring 151A is connected to a power supply having an intermediate potential Vmid that is intermediate (half) between the high potential Vhigh and the low potential Vlow, and the power supply wiring 151B is connected to a power supply having a high potential Vhigh.

The transistor 152 has a drain connected to the power supply wiring 151A, a gate connected to the control wiring 153A, and a source connected to the capacitor 155. When a predetermined pulse is input to the gate of the control wiring 153A from the control wiring 153A, the transistor 152 is turned on and supplies a charge from the power source of the intermediate potential Vmid to the capacitor 155.

A driving circuit 153 that controls driving of the transistor 152 and the transistor 154 is connected to the control wiring 153A. The control wiring 153A supplies a predetermined pulse output from the drive circuit 153 to the transistor 152. A drive circuit 153 is connected to the control wiring 153B in the same manner as the control wiring 153A. The control wiring 153B supplies a predetermined pulse output from the drive circuit 153 to the transistor 154.

The transistor 154 has a drain connected to the power supply wiring 151B, a gate connected to the control wiring 153B, and a source connected to the capacitor 155. The transistor 154 is turned on when a predetermined pulse is input to the gate from the control wiring 153B, and supplies a charge from the power source of the high potential Vhigh to the capacitor 155.

The capacitor 155 generates a transfer pulse TRF by accumulating charges supplied from the transistor 152 and the transistor 154. That is, the transistor 152 and the transistor 154 generate the transfer pulse TRF via the capacitor 155. The generated transfer pulse TRF is supplied to the transfer wiring 72.

[Second example of transfer pulse]
FIG. 10 is a timing chart showing the transfer pulse TRF generated by the transfer pulse generation circuit 150 of FIG.

In FIG. 10, the horizontal axis represents time (t), and the vertical axis represents potential. In addition, the time t0, time t1, time t21, time t22, time t23, time t24, time t25, time t26, time t4, and time t5 are set in order of time. The time t0, time t1, time t4, and time t5 in FIG. 10 are the same as those in FIG.

In the example of FIG. 10, the selection pulse SEL and the reset pulse RST are generated as in the example of FIG. At time t21, the potential of the control wiring 153A changes from the low potential Vlow to the high potential Vhigh, and returns from the high potential Vhigh to the low potential Vlow at time t22.

That is, from time t21 to time t22, the drive circuit 153 drives the transistor 152 by supplying a pulse to the gate of the transistor 152 through the control wiring 153A. At time t 22, the driver circuit 153 stops supplying the pulse to the transistor 152 and stops the transistor 152.

As a result, during the period from time t21 to time t22, electric charges from the power source of the intermediate potential Vmid are accumulated in the capacitor 155, and the potential of the transfer wiring 72 changes from the low potential Vlow to the intermediate potential Vmid. At time t22, no charge is accumulated in the capacitor 155, and the potential of the transfer wiring 72 returns to the low potential Vlow.

Thereafter, from time t22 to time t23 (for example, time for one clock), the potentials of the control wiring 153A and the control wiring 153B are kept at the low potential Vlow. As a result, no charge is accumulated in the capacitor 155, and the potential of the transfer wiring 72 remains at the low potential Vlow.

At time t23, the potential of the control wiring 153B changes from the low potential Vlow to the high potential Vhigh, and returns from the high potential Vhigh to the low potential Vlow at time t24. That is, from time t23 to time t24, the drive circuit 153 drives the transistor 154 by supplying a pulse to the gate of the transistor 154 through the control wiring 153B. At time t 24, the driver circuit 153 stops supplying the pulse to the transistor 154 and stops the transistor 154.

As a result, during the period from time t23 to time t24, electric charges from the power source having the high potential Vhigh are accumulated in the capacitor 155, and the potential of the transfer wiring 72 changes from the low potential Vlow to the high potential Vhigh. At time t24, no charge is accumulated in the capacitor 155, and the potential of the transfer wiring 72 returns to the low potential Vlow.

Further, at time t25, the potential of the control wiring 153A again changes from the low potential Vlow to the high potential Vhigh, and returns from the high potential Vhigh to the low potential Vlow at time t26. Thereby, from time t25 to time t26, the electric charge from the power source of the intermediate potential Vmid is accumulated again in the capacitor 155, and the potential of the transfer wiring 72 rises from the low potential Vlow to the intermediate potential Vmid. At time t26, no charge is accumulated in the capacitor 155, and the potential of the transfer wiring 72 returns to the low potential Vlow.

And between time t26 and time t4 (for example, time for one clock), the potentials of the control wiring 153A and the control wiring 153B are kept at the low potential Vlow. As a result, no charge is accumulated in the capacitor 155, and the potential of the transfer wiring 72 remains at the low potential Vlow.

Thereafter, at time t4, the potential of the control wiring 153B changes from the low potential Vlow to the high potential Vhigh, and at time t5, the potential returns from the high potential Vhigh to the low potential Vlow. As a result, from time t4 to time t5, electric charges from the power source having the high potential Vhigh are accumulated in the capacitor 155, and the potential of the transfer wiring 72 changes from the low potential Vlow to the high potential Vhigh. At time t5, no charge is accumulated in the capacitor 155, and the potential of the transfer wiring 72 returns to the low potential Vlow.

As described above, in the transfer pulse generation circuit 150, the drive circuit 153 drives the transistor 152 to temporarily set the potential of the transfer pulse TRF to the intermediate potential Vmid when the transfer pulse TRF rises, and then stops the transistor 152. Then, the drive circuit 153 drives the transistor 154 to set the potential of the transfer pulse TRF to the high potential Vhigh. Therefore, since the potential of the transfer pulse TRF does not rise to the high potential Vhigh at one time, the well region 91 does not fluctuate and the overflow of noise charges to the charge storage layer 103 can be suppressed. As a result, it is possible to suppress deterioration in image quality of the captured image.

Further, the drive circuit 153 provides a period during which the transfer transistor 52 is turned off by setting the potentials of the control wiring 153A and the control wiring 153B to the low potential Vlow when the driving target is switched from the transistor 152 to the transistor 154. Accordingly, when the transistor 152 and the transistor 154 are turned on at the same time, it is possible to prevent a through current from being generated between the transistor 152 and the transistor 154.

Further, like the transfer pulse generation circuit 130, the transfer pulse generation circuit 150 does not have a circuit that blunts the falling edge of the transfer pulse TRF. Thereby, the falling time of the transfer pulse TRF can be shortened. As a result, the imaging time can be shortened.

Note that the embodiments of the present technology are not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the present technology.

For example, the number of transistors connected in parallel in the transfer pulse generation circuit 130 (150) is not limited to two, and may be two or more. In this case, the driving capability of each transistor provided in the transfer pulse generation circuit 130 is different. The potential of the power source connected to each transistor provided in the transfer pulse generation circuit 150 is a different potential between the low potential Vlow and the high potential Vhigh.

Further, the image sensor 12 may have a horizontal transfer path having a horizontal overflow structure instead of the vertical transfer path 96 having a vertical overflow structure.

Furthermore, the present technology can be configured as follows.

(1)
A low drive capability transistor for generating a signal to be input to the gate electrode of the transfer transistor of the pixel having an overflow structure;
A high drivability transistor connected in parallel with the low drivability transistor and generating a signal to be input to the gate electrode;
A solid-state imaging device comprising: a drive unit that drives the high drive capability transistor after stopping the low drive capability transistor after driving the low drive capability transistor.
(2)
A low drive capability transistor for generating a signal to be input to the gate electrode of the transfer transistor of the pixel having an overflow structure;
A solid-state imaging device comprising: a high drive capability transistor that is connected in parallel with the low drive capability transistor and generates a signal to be input to the gate electrode.
A driving method including a driving step of driving the low drive capability transistor, then stopping the low drive capability transistor and driving the high drive capability transistor.
(3)
A pixel having an overflow structure;
A low drivability transistor that generates a signal to be input to the gate electrode of the transfer transistor of the pixel;
A high drivability transistor connected in parallel with the low drivability transistor and generating a signal to be input to the gate electrode;
After driving the low drive capability transistor, stopping the low drive capability transistor and driving the high drive capability transistor;
An electronic device comprising: an output unit that outputs image data corresponding to an electrical signal generated by the pixel.
(4)
A first transistor that generates a first potential signal that is input to a gate electrode of a transfer transistor of a pixel having an overflow structure;
A second transistor connected in parallel with the first transistor and generating a signal having a second potential higher than the first potential inputted to the gate electrode;
A solid-state imaging device comprising: a driving unit that drives the second transistor after driving the first transistor and stopping the first transistor.
(5)
The solid-state imaging device according to (4), wherein the first potential is half of the second potential.
(6)
The solid-state imaging device according to (4) or (5), wherein the driving unit drives the second transistor after a predetermined period after stopping the first transistor.
(7)
A first transistor that generates a first potential signal that is input to a gate electrode of a transfer transistor of a pixel having an overflow structure;
A solid-state imaging device comprising: a second transistor connected in parallel with the first transistor and generating a signal having a second potential higher than the first potential input to the gate electrode.
A driving method comprising: a driving step of driving the second transistor after stopping the first transistor after driving the first transistor.
(8)
A pixel having an overflow structure;
A first transistor that generates a signal of a first potential that is input to a gate electrode of a transfer transistor of the pixel;
A second transistor connected in parallel with the first transistor and generating a signal having a second potential higher than the first potential inputted to the gate electrode;
A driving unit for driving the first transistor, stopping the first transistor, and driving the second transistor;
An electronic device comprising: an output unit that outputs image data corresponding to an electrical signal generated by the pixel.

10 electronic devices, 12 image sensors, 14 image data processing units, 31 pixels, 132 low drive capability transistors, 133 drive circuits, 134 high drive capability transistors, 152 transistors, 153 drive circuits, 154 transistors

Claims

A low drive capability transistor for generating a signal to be input to the gate electrode of the transfer transistor of the pixel having an overflow structure;
A high drivability transistor connected in parallel with the low drivability transistor and generating a signal to be input to the gate electrode;
A solid-state imaging device comprising: a drive unit that drives the high drive capability transistor after stopping the low drive capability transistor after driving the low drive capability transistor.
A low drive capability transistor for generating a signal to be input to the gate electrode of the transfer transistor of the pixel having an overflow structure;
A solid-state imaging device comprising: a high drive capability transistor that is connected in parallel with the low drive capability transistor and generates a signal to be input to the gate electrode.
A driving method including a driving step of driving the low drive capability transistor, then stopping the low drive capability transistor and driving the high drive capability transistor.
A pixel having an overflow structure;
A low drivability transistor that generates a signal to be input to the gate electrode of the transfer transistor of the pixel;
A high drivability transistor connected in parallel with the low drivability transistor and generating a signal to be input to the gate electrode;
After driving the low drive capability transistor, stopping the low drive capability transistor and driving the high drive capability transistor;
An electronic device comprising: an output unit that outputs image data corresponding to an electrical signal generated by the pixel.
A first transistor that generates a first potential signal that is input to a gate electrode of a transfer transistor of a pixel having an overflow structure;
A second transistor connected in parallel with the first transistor and generating a signal having a second potential higher than the first potential inputted to the gate electrode;
A solid-state imaging device comprising: a driving unit that drives the second transistor after driving the first transistor and stopping the first transistor.
The solid-state imaging device according to claim 4, wherein the first potential is half of the second potential.
The solid-state imaging device according to claim 4, wherein the driving unit drives the second transistor after a predetermined period after stopping the first transistor.
A first transistor that generates a first potential signal that is input to a gate electrode of a transfer transistor of a pixel having an overflow structure;
A solid-state imaging device comprising: a second transistor connected in parallel with the first transistor and generating a signal having a second potential higher than the first potential input to the gate electrode.
A driving method comprising: a driving step of driving the second transistor after stopping the first transistor after driving the first transistor.
A pixel having an overflow structure;
A first transistor that generates a signal of a first potential that is input to a gate electrode of a transfer transistor of the pixel;
A second transistor connected in parallel with the first transistor and generating a signal having a second potential higher than the first potential inputted to the gate electrode;
A driving unit for driving the first transistor, stopping the first transistor, and driving the second transistor;
An electronic device comprising: an output unit that outputs image data corresponding to an electrical signal generated by the pixel.