WO2013178730A1 - Eeprom memory cell as a memristive component - Google Patents

Eeprom memory cell as a memristive component Download PDF

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WO2013178730A1
WO2013178730A1 PCT/EP2013/061154 EP2013061154W WO2013178730A1 WO 2013178730 A1 WO2013178730 A1 WO 2013178730A1 EP 2013061154 W EP2013061154 W EP 2013061154W WO 2013178730 A1 WO2013178730 A1 WO 2013178730A1
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component
memory cell
eeprom memory
eeprom
control gate
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PCT/EP2013/061154
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German (de)
French (fr)
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Hermann Kohlstedt
Martin Ziegler
Maria OBERLÄNDER
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Christian-Albrechts-Universität Zu Kiel
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Publication of WO2013178730A1 publication Critical patent/WO2013178730A1/en

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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/685Hi-Lo semiconductor devices, e.g. memory devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881Programmable transistors with only two possible levels of programmation
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/10Resistive cells; Technology aspects
    • G11C2213/15Current-voltage curve
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/50Resistive cell structure aspects
    • G11C2213/53Structure wherein the resistive material being in a transistor, e.g. gate

Definitions

  • the invention relates to an EEPROM memory cell configured as a memristive device.
  • EEPROM cells for non-volatile information memories
  • a floating gate or a floating connection the so-called floating gate
  • It is not completely formed along the entire cell channel, wherein the uncovered part of the channel is controlled directly by the control gate, so that an active component - corresponding to a transistor - is formed in series with the actual cell. Thanks to this asymmetry, only one of the two diffusions can be programmed - on the drain side, so that the memory cell can be read from the source side.
  • This type of memory corresponds to the prematurely programmed content.
  • memristor - a passive, electrical device in the form of a resistor - whose electrical resistance is not constant but depends on its past.
  • One of the technical implementations of a transistor takes place in the thin-film composite in the form of two-layered metal conductor tracks, which are designed to store charge. The current resistance value of this component depends on how much the electric charge has flowed in which direction.
  • This charge storage element - the memristor - is defined as a device in that the flow a b and the electrical charge q are over a time invariant, generally nonlinear
  • o memristant function m (q) ab is defined by the rate of flux change of the charge
  • u (t) supplies the voltage potential according to the charge law.
  • the memressor which is considered a passive two-terminal, is similar to that of the other three passive two-terminal devices: reciprocal capacitance, resistivity and inductance in the form:
  • the unit ohm [ ⁇ ] has the relationship ⁇ / dq between the two-pole terminals of the device.
  • the current / voltage curve of a memristor shows a pronounced hyteresis behavior.
  • Memristive devices with ionic solid-state conductors form the research focus in the field of modern information storage technology [p. D. Ha and S. Ramanathan, J. Appl. Phys. 2011, p. 110].
  • Their special feature is that they change their resistance value depending on the electric charge that has flowed through them. Since this resistance value is retained even after switching off the previously applied voltage, memristive systems are predestined for use in non-volatile information memories - based on EPROM modules.
  • the known memristive devices can not be integrated into the prevailing silicon technology, which further complicates the large-scale production of memory cells and the design of more complex neural circuits, and the materials currently used for reflective systems are not CMOS-compatible, since the memristive materials be affected by the high temperature processes in whole system block fabrication processes such as backend annealing. Conversely, one would not want to contaminate the extremely expensive and contaminant-sensitive CMOS fabrication lines with new materials in the production lines. In this context, the EEPROM cell could offer a new, in this context not yet developed alternative.
  • the object of the invention is to provide an information-storing component that is not based on thin-film interconnects, but rather restructure known EEPROMs in such a way that the quadrupole system [three-electrode component] produces a two-pole system that behaves like a memristive component.
  • the object is achieved with the features of the main claim, the subclaims give preferred embodiments of the invention again.
  • the other components may electrode / is applied to a bipolar supply voltage Vi n, where V can take in the spaces V min ⁇ V in ⁇ V max. If the applied voltage V in rises positively to V in -, the electrical resistance of the memristor rises and reaches its highest value at V max .
  • the opposite polarity voltage V in reduces the resistance of the memristor until it reaches its lowest resistance value at the largest amount of V min .
  • the device By removing the applied voltage, the device retains its charge / electrical state, allowing it to be used as a storage element.
  • the u / i diagram of such a memristor passes through a hysteresis curve that intersects the coordinate zero point [pinched hysteresis loop] - paraphrased in FIG. 1 - indicating that a memristor is a passive device ,
  • V FG V c + k c + k ⁇ ⁇ D V D + k s ⁇ V s + k B ⁇ V B, wherein V F G, VC, V D, V S and V B to the on Control Gate (1), source (3), drain (4), floating gate (6) and bulk (11) applied electrode potential.
  • V FG - ⁇ - + k D ⁇ V D + k B ⁇ V B.
  • An important feature of the circuit is that the bulk terminal (10) must be set to the lowest potential occurring in the circuit to avoid short circuits between drain (4) and bulk (11).
  • the floating gate (6) is thus charged or discharged via the current through the gate oxide (7). This simultaneously changes the channel resistance R K and thus the total resistance of the two-pole component.
  • the drain and the control gate terminals (9, 8) can be connected to each other analogously to the described variant and placed on a common potential.
  • the bipolar voltage supply for driving the reduced EEPROM cell would be done in this case via a source terminal of the component.
  • the capacitive coupling kn is usually larger than the capacitive coupling ks, preference is given to the first variant.
  • the reduced EEPROM cell can be extended by an additional ohmic resistance (R) as a parallel resistor (15).
  • the ohmic resistance (R) is connected in parallel to the channel resistance R K - see Fig. 4 - wherein the ohmic resistance (R) is independent of the channel resistance R K and serves, even for the limiting case R K -> ° o a current flow in one guarantee technical interconnection of the two-pole component.
  • the described novel component with a memristic transmission characteristic consists of two independent circuit steps: By reducing the interconnection of a floating-gate EEPROM as described, all the layer terminals of the device are led out,

Abstract

The invention relates to an EEPROM memory cell which has a floating gate (6) and is configured as a memristive component such that it takes on the current-voltage characteristic of a memristor by means of reduced circuitry in the EEPROM cell, by virtue of the fact that the control gate (1) is connected to the source (3) and set to a common potential by the control gate connection (8) produced in this manner (e.g. mass potential V = 0 volts). This reduces the original three-poled component to a two-poled component. By applying a bipolar voltage to the drain connection (9) of the reduced EEPROM cell, a new component is produced that behaves, in its UI characteristic, like a memristive component classified as a passive electronic two-poled component. Said floating gate (6) allows the respective channel resistance value taken last to be preserved in the EEPROM cell even when no more external voltage is applied at the connections (9) and (8).

Description

EEPROM-Speicherzelle als memristives Bauelement  EEPROM memory cell as a memristive component
Die Erfindung bezieht sich auf eine EEPROM-Speicherzelle, die als memristives Bauelement konfiguriert ist. The invention relates to an EEPROM memory cell configured as a memristive device.
Bekannt ist die Verwendung von EEPROM-Zellen für nichtflüchtige Informationsspeicher, bei denen zusätzlich ein schwebendes Gate bzw. ein schwebender Anschluss, das sogenannte Floating-Gate, implementiert ist. Es ist entlang des gesamten Zellenkanals nicht vollständig ausgebildet, wobei der nichtüberdeckte Teil des Kanals direkt durch das Steuergate geregelt wird, sodass ein aktives Bauelement - einem Transistor entsprechend - in Serienschaltung mit der eigentlichen Zelle gebildet wird. Dank dieser Asymmetrie kann nur eine der beiden Diffusionen programmiert werden - und zwar drainseitig, sodass die Speicherzelle von der Sourceseite gelesen werden kann. Diese Art von Gedächtnis entspricht dem vorzeitig einprogrammierten Inhalt. The use of EEPROM cells for non-volatile information memories is known in which additionally a floating gate or a floating connection, the so-called floating gate, is implemented. It is not completely formed along the entire cell channel, wherein the uncovered part of the channel is controlled directly by the control gate, so that an active component - corresponding to a transistor - is formed in series with the actual cell. Thanks to this asymmetry, only one of the two diffusions can be programmed - on the drain side, so that the memory cell can be read from the source side. This type of memory corresponds to the prematurely programmed content.
Ebenfalls zum Stand der Technik gehört der Memristor - ein passives, elektrisches Bauelement in der Form eines Widerstandes - dessen elektrischer Widerstand nicht konstant ist, sondern von seiner Vergangenheit abhängt. Eine der technischen Realisierungen eines Mem- ristors erfolgt im Dünnschichtverbund in Form zweilagiger metallischer Leiterbahnen, die ladungsspeichernd ausgeführt sind. Der aktuelle Widerstandswert dieses Bauelementes ist davon abhängig, wie groß die elektrische Ladung in welche Richtung geflossen ist. Dieses ladungsspeichernde Element - der Memristor - ist definiert als ein Bauelement, indem der Fluss ab und die elektrische Ladung q über eine zeitinvariante, im Allgemeinen nichtlineare Also part of the prior art is the memristor - a passive, electrical device in the form of a resistor - whose electrical resistance is not constant but depends on its past. One of the technical implementations of a transistor takes place in the thin-film composite in the form of two-layered metal conductor tracks, which are designed to store charge. The current resistance value of this component depends on how much the electric charge has flowed in which direction. This charge storage element - the memristor - is defined as a device in that the flow a b and the electrical charge q are over a time invariant, generally nonlinear
Funktion Φώ = f(q) durch die Beziehungen Λ = Φ0 + \ u(t) - dt gekoppelt ist, wobei die Function Φ ώ = f (q) is coupled by the relations Λ = Φ 0 + \ u (t) - dt, where the
o memristante Funktion m(q) ab definiert ist über die Rate der Flussänderung der Ladung;  o memristant function m (q) ab is defined by the rate of flux change of the charge;
dq  dq
u(t) liefert das Spannungspotenzial entsprechend dem Ladungsgesetz. Der Memresistor, der als passiver Zweipol betrachtet wird, ähnelt dem der drei anderen passiven Zweipol-Bauelementen: reziproke Kapazität, Resistivität und Induktivität in der Form:u (t) supplies the voltage potential according to the charge law. The memressor, which is considered a passive two-terminal, is similar to that of the other three passive two-terminal devices: reciprocal capacitance, resistivity and inductance in the form:
1 duAt) άΦ n du(t) άΦ τ άΦ άΦ , . c.. ,. Λ (Γ . . . _ , . ,.1 duAt) άΦ n du (t) άΦ τ άΦ άΦ,. c ..,. Λ (Γ . .. _,.,.
— =— -— = ; Κ =—— = ; L = = ; wobei lur die Memristivitat m(q), die- = - - =; Κ = - =; L = =; where lur the memrity m (q), the
C dq dq di dq di dq C dq dq dq di dq
die Einheit Ohm [Ω] hat, zwischen den Zweipolanschlüssen des Bauelements die Beziehung άΦ/dq galt. Die Strom-/Spannungskurve eines Memristors zeigt ein ausgeprägtes Hyterese- verhalten. the unit ohm [Ω] has the relationship άΦ / dq between the two-pole terminals of the device. The current / voltage curve of a memristor shows a pronounced hyteresis behavior.
Memristive Bauelemente mit ionischen Festkörperleiteren bilden den Forschungsschwerpunkt im Bereich der modernen Informationsspeichertechnologie [S. D. Ha and S. Ramanathan, J. Appl. Phys. 2011, S. 110] . Ihre besondere Eigenschaft liegt darin, dass sie abhängig von der durch sie geflossenen elektrischen Ladung ihren Widerstandswert ändern. Da dieser Widerstandswert auch nach dem Abschalten der zuvor angelegten Spannung erhalten bleibt, sind memristive Systeme prädestiniert für den Einsatz in nichtflüchtigen Informationsspeichern - in Anlehnung an EPROM-Bausteine. Memristive devices with ionic solid-state conductors form the research focus in the field of modern information storage technology [p. D. Ha and S. Ramanathan, J. Appl. Phys. 2011, p. 110]. Their special feature is that they change their resistance value depending on the electric charge that has flowed through them. Since this resistance value is retained even after switching off the previously applied voltage, memristive systems are predestined for use in non-volatile information memories - based on EPROM modules.
Bedingt durch ihre überzeugenden Eigenschaften im Hinblick auf ihren geringen Leistungsverbrauch, ihrem einfachen strukturellen Aufbau, sowie ihrer einfachen dimensionalen Skalierbarkeit - welche zum Beispiel hohe Packungsdichten auf Wafern erlaubt - gelten diese Bauelemente als die Speichertechnologie der Zukunft. Due to their convincing properties in terms of their low power consumption, their simple structural design, as well as their simple dimensional scalability - which allows, for example, high packing densities on wafers - these devices are considered the storage technology of the future.
Neben den überzeugenden Eigenschaften von memristiven Systemen im Bereich der resisti- ven Informationsspeicher lassen sich auch interessante Analogien zu biologischen Synapsen erkennen. Diesbezüglich eröffnen diese bisher nicht erschlossenen Ansätze neue und komplexere technische Systemkonfigurationen - denn sie geben berechtigten Anlass dazu, neuronale Schaltungen aufzubauen, die ihrem biologischen Pendant näher kommen als alles bisher Entwickelte. Auch wenn Arbeiten an memristiven Bauelemente bereits seit mehreren Jahrzehnten erfolgen, steht der Einführung dieser Bauteile in marktreife Produkte noch ein langer Weg bevor. So stellen zum Beispiel die Ausfallsicherheit, die Datenstabilität, die Materialermüdung oder die Bandbreite an Kennwertparameter innerhalb einer Produktionsreihe zurzeit noch große Hürden zu einem marktreifen Produkt dar. Diesbezüglich können zum Stand der Technik die europäische Patentschrift EP 0 517 607 Ml und die amerikanischen Patentpublikation US 2011/0266513 AI gezählt werden. Apart from the convincing properties of memristive systems in the area of resistive information stores, interesting analogies to biological synapses can also be identified. In this regard, these previously untapped approaches open up new and more complex technical system configurations - as they give legitimate reason to build neural circuits that are closer to their biological equivalent than anything developed so far. Even though work has been done on memristive components for several decades, the introduction of these components into marketable products still has a long way to go. For example, reliability, data stability, material fatigue or the range of parameter parameters within a production series are currently still major hurdles to a marketable product. In this regard, the European Patent EP 0 517 607 M1 and the US Patent Publication US 2011/0266513 AI can be counted as prior art.
In der ersten Schrift wird unter anderem ein Herstellungsverfahren auch für nichtflüchtige Speicherzellen - anwendbar im Herstellungsprozess von MOS- und CMOS-Bauelementen - beschrieben, kommt aber wegen des erfinderischen Neuaufbaus mit einem schwebendem Gate in die Anwendungsperipherie memristischer Bauelemente. In the first document, among other things, a manufacturing method for non-volatile memory cells - applicable in the manufacturing process of MOS and CMOS devices - described, but comes because of the inventive rebuilding with a floating gate in the application periphery memristischer components.
In der US 2011/0266513 AI -Schrift wird eine Diodenkonfiguration offenbart, die als nichtflüchtiger Schalter - also als passives Zweipoltor - fungieren kann. In US 2011/0266513 AI font a diode configuration is disclosed, which can act as a non-volatile switch - ie as a passive Zweipoltor -.
Beiden Offenbarungen gemeinsam ist der Nachteil, dass sie als passives Zweipolelement ohne angelegtes Spannungspotenzial nicht memristisch im Anwendungsfall der vorgelegten Erfindung fungieren können. Common to both disclosures is the disadvantage that they can not function memristically as a passive two-pole element without applied voltage potential in the application of the presented invention.
Des Weiteren lassen sich die bekannten memristiven Bauelemente nicht in die vorherrschende Siliziumtechnologie einbinden, was die Großproduktion von Speicherzellen sowie das Design komplexerer neuronaler Schaltungen weiter deutlich verkompliziert, und die zurzeit für mem- ristive Systeme eingesetzten Materialien nicht CMOS-kompatibel sind, da die memristiven Materialien durch die Hochtemperaturprozesse bei Herstellungsverfahren ganzer Systemblöcke - wie das Backend annealing - in Mitleidenschaft gezogen werden. Umgekehrt möchte man die extrem teuren und auf Kontaminationen sensitiven CMOS-Fabrikationslinien nicht durch neue Materialien in den Fertigungslinien verunreinigen. In diesem Zusammenhang könnte die EEPROM-Zelle eine neue, in diesem Kontext noch nicht erschlossene Alternative bieten. Furthermore, the known memristive devices can not be integrated into the prevailing silicon technology, which further complicates the large-scale production of memory cells and the design of more complex neural circuits, and the materials currently used for reflective systems are not CMOS-compatible, since the memristive materials be affected by the high temperature processes in whole system block fabrication processes such as backend annealing. Conversely, one would not want to contaminate the extremely expensive and contaminant-sensitive CMOS fabrication lines with new materials in the production lines. In this context, the EEPROM cell could offer a new, in this context not yet developed alternative.
Aufgabe der Erfindung ist es, ein Information speicherndes Bauelement bereit zu stellen, das nicht auf Dünnschichtleiterbahnverbunde basiert, sondern bekannte EEPROMs so umzustrukturieren, dass aus dem Vierpolsystem [Dreielektrodenbauelement] ein Zweipolsystem entsteht, das sich wie ein memristives Bauelemente verhält. Die Aufgabe wird gelöst mit den Merkmalen des Hauptanspruchs, die Unteransprüche geben bevorzugte Ausführungen der Erfindung wieder. The object of the invention is to provide an information-storing component that is not based on thin-film interconnects, but rather restructure known EEPROMs in such a way that the quadrupole system [three-electrode component] produces a two-pole system that behaves like a memristive component. The object is achieved with the features of the main claim, the subclaims give preferred embodiments of the invention again.
Im Folgenden wird die Erfindung anhand von fünf Figuren erläutert. Dabei bedeuten: In the following the invention will be explained with reference to five figures. Where:
Fig. 1 Strom-Spannungscharakteristik eines Memristors, 1 current-voltage characteristic of a memristor,
Fig. 2a reduzierte EEPROM-Zelle, Fig. 2a reduced EEPROM cell,
Fig. 2b reduzierte EEPROM-Zelle in Zweipolschaltung, 2b reduced EEPROM cell in two-pole circuit,
Fig. 3 u/i-Charakteristik der Zweipol-EEPROM-Zelle Fig. 3 u / i characteristic of the two-terminal EEPROM cell
nach Fig. 2b und  to Fig. 2b and
Fig. 4 elektrische Schaltung der reduzierten EEPROM-Zelle mit einem ohm- schen Parallelwiderstand. 4 electrical circuit of the reduced EEPROM cell with an ohmic parallel resistor.
Zunächst soll anhand des Diagramms nach Fig. 1 die Speicherfunktion/Systemfunktion eines Memristors erläutert werden. Der Memristor, ein passives elektronisches Zweipolbauelement, wird mit einer seiner Anschlusselektroden an das Bezugspotenzial - meist Masse - gelegt [Potenzial V = 0 Volt]. Die andere Bauelementeelektrode kann/wird an eine bipolare Spannungsversorgung Vin gelegt, wobei Vin die Bereiche Vmin < Vin < Vmax einnehmen kann. Steigt die angelegte Spannung Vin positiv an Vin— , so steigt der elektrische Widerstand des Memristors und erreicht seinen höchsten Wert bei Vmax. Die entgegengesetzt gepolte Spannung Vin— hingegen reduziert den Widerstand des Memristors, bis er beim größten Betrag von Vmin wieder seinen geringsten Widerstandswert erreicht hat. Der aktuelle Widerstandswert dieses Zweipolbauelementes ist also davon abhängig, wie viel Ladungen in welche Richtung geflossen sind; der Widerstandswert ist somit über den zeitlichen Verlauf des ge- flossenen Stromes einstellbar und entspricht der Funktion q(t) = q(t0) + ^i(t)dt. Entfernt man die angelegte Spannung, so behält das Bauelement seine Ladung/seinen elektrischen Zustand, wodurch es als Speicherelement angewendet werden kann. Das u/i-Diagramm ein solcher Memristor durchläuft eine Hysteresekurve, die sich im Koor- dinatennullpunkt kreuzt [pinched hysteresis loop] - paraphrasierend in der Fig. 1 dargestellt - an der man erkennt, dass es sich bei einem Memristor um ein passives Bauelement handelt. First, the memory function / system function of a memristor will be explained with reference to the diagram of FIG. The memristor, a passive two-terminal electronic component, is connected to the reference potential - usually ground - with one of its connection electrodes [potential V = 0 volt]. The other components may electrode / is applied to a bipolar supply voltage Vi n, where V can take in the spaces V min <V in <V max. If the applied voltage V in rises positively to V in -, the electrical resistance of the memristor rises and reaches its highest value at V max . The opposite polarity voltage V in , however, reduces the resistance of the memristor until it reaches its lowest resistance value at the largest amount of V min . The current resistance value of this two-pole component is thus dependent on how much charges have flowed in which direction; the resistance value is thus adjustable over the time course of the current flow and corresponds to the function q (t) = q (t 0 ) + ^ i (t) dt. By removing the applied voltage, the device retains its charge / electrical state, allowing it to be used as a storage element. The u / i diagram of such a memristor passes through a hysteresis curve that intersects the coordinate zero point [pinched hysteresis loop] - paraphrased in FIG. 1 - indicating that a memristor is a passive device ,
Um eine ähnliche Strom-Spannungs-Charakteristik wie die eines Memristors mit einer EEPROM-Zelle zu erhalten, wird diese, wie in den Figuren 2a und 2b dargestellt, in ihrer Funktionsweise reduziert. Hierzu wird das Control-Gate (1) (die Steuerelektrode) mit dem Source (3) verbunden und auf ein gemeinsames Potenzial mittels des so entstandenen Control-Gate-Anschluss (8) gelegt (z. B. Massepotential, V = 0 Volt). Dies reduziert das ursprüngliche Dreipol-Bauelement zu einem Zweipol-Bauelement. Durch das Anlegen einer bipolaren Spannung am Drain- Anschluss (9) der reduzierten EEPROM-Zelle entsteht, wie die Grafik in Fig. 3 zeigt, ein neues Bauelement, das sich in seiner u-i-Charakteristik wie ein memristives Bauelement verhält [vergleiche Fig. 1]. Der jeweilige zuletzt eingenommene Kanalwiderstandswert bleibt aufgrund des Floating-Gates (6) in der EEPROM-Zelle auch dann erhalten, wenn an den Anschlüssen (9) und (12) keine äußere Spannung mehr anliegt. In order to obtain a current-voltage characteristic similar to that of a memristor with an EEPROM cell, this is reduced as shown in Figures 2a and 2b, in their operation. For this purpose, the control gate (1) (the control electrode) is connected to the source (3) and connected to a common potential by means of the resulting control gate connection (8) (eg ground potential, V = 0 volts). , This reduces the original three-terminal device to a two-terminal device. By applying a bipolar voltage at the drain terminal (9) of the reduced EEPROM cell arises, as the graph in Fig. 3 shows, a new device that behaves in its ui characteristic as a memristives device [see Fig. 1] ]. Due to the floating gate (6) in the EEPROM cell, the respective last channel resistance value is retained even if no external voltage is present at the terminals (9) and (12).
Das zugrundeliegende Konzept der reduzierten EEPROM-Zelle, welches die memristive Bauteilcharakteristik garantiert, lässt sich durch folgendes kapazitives Makromodell beschreiben: The underlying concept of the reduced EEPROM cell, which guarantees the memristive component characteristics, can be described by the following capacitive macro model:
VFG = + kc Vc + kD VD + ks Vs + kB VB , wobei es sich bei VFG, VC, VD, VS und VB um das am Control-Gate (1), Source (3), Drain (4), Floating-Gate (6) und Bulk (11) anliegende Elektrodenpotential handelt. QFG ist die Ladung des Floating-Gates (6) und k p = c, D, s und BJ V FG = V c + k c + k D V D + k s V s + k B V B, wherein V F G, VC, V D, V S and V B to the on Control Gate (1), source (3), drain (4), floating gate (6) and bulk (11) applied electrode potential. Q F G is the charge of the floating gate (6) and kp = c, D, s and BJ
C  C
sind die jeweiligen kapazitiven Kopplungsfaktoren k, die sich nach kt = -^-mit i=C, D, S, B bestimmen lassen. Hierbei bildet Cr die Summe aller Teilkapazitäten d (c, D. s undB)- Durch die vorgeschlagene bauteiltechnische Reduktion der EEPROM-Zelle werden Control-Gate (1) und Source (3) miteinander verbunden, was zur Folge hat, dass ihre Potenziale auf dem gleichen Wert liegen. are the respective capacitive coupling factors k, which can be determined after k t = - ^ - with i = C, D, S, B. In this case, Cr forms the sum of all partial capacitances d ( c, D. s and B). The proposed component-specific reduction of the EEPROM cell causes control gate (1) and source (3) to be interconnected, with the result that their potentials increase the same value.
Wird als gemeinsames Potenzial das Massepotential definiert, was ohne Beschränkung der Allgemeinheit auf V = 0 Volt gelegt werden kann, so ergibt sich nach der obigen Gleichung die Beziehung VFG =—^- + kD VD + kB VB . Ein wichtiges Merkmal der Schaltung besteht darin, dass der Bulk-Anschluss (10) auf das niedrigste in der Schaltung vorkommende Potenzial gelegt werden muss, um Kurzschlüsse zwischen Drain (4) und Bulk (11) zu vermeiden. If the common potential is defined as the common potential, which can be set to V = 0 volt without restricting the generality, the result is according to the above equation the relation V FG = - ^ - + k D V D + k B V B. An important feature of the circuit is that the bulk terminal (10) must be set to the lowest potential occurring in the circuit to avoid short circuits between drain (4) and bulk (11).
Für das hier beschriebene Makromodell kann in erster Näherung angenommen werden, dass die kapazitive Kopplung k zum Bulk (11) vernachlässigbar gering ist, womit sich der folgende funktionale Zusammenhang zwischen der Drain-Spannung und dem Ladungszustand des Floating-Gate-Potenzials zu kD - VD = -^^- + VFG ergibt. For the herein described macro model can be assumed in a first approximation that the capacitive coupling k to the bulk (11) is negligible, so the following functional relationship between the drain voltage and the charge state of the floating-gate potential to k D - V D = - ^^ - + V FG yields.
Durch das Anlegen eines bipolaren Spannungssignals am drainseitigen Anschluss der reduzierten EEPROM-Zelle wird somit das Floating-Gate (6) über den Strom durch das Gate-Oxid (7) geladen, beziehungsweise entladen. Dadurch ändert sich gleichzeitig der Kanalwiderstand RK und somit der Gesamtwiderstand des Zweipolbauelements. By applying a bipolar voltage signal at the drain-side connection of the reduced EEPROM cell, the floating gate (6) is thus charged or discharged via the current through the gate oxide (7). This simultaneously changes the channel resistance R K and thus the total resistance of the two-pole component.
Erfindungsgemäß können analog zu der beschriebenen Variante auch die Drain- und die Control-Gate- Anschlüsse (9, 8) miteinander verbunden werden und auf ein gemeinsames Potenzial gelegt werden. Die bipolare Spannungsversorgung zur Ansteuerung der reduzierten EEPROM-Zelle würde in diesem Fall über einen Source-Anschluss des Bauteils geschehen. Da jedoch bei den EEPROM-Bauelementen dieser Ausführung die kapazitive Kopplung kn meist größer ist als die kapazitive Kopplung ks wird der ersten Variante der Vorzug gegeben. According to the invention, the drain and the control gate terminals (9, 8) can be connected to each other analogously to the described variant and placed on a common potential. The bipolar voltage supply for driving the reduced EEPROM cell would be done in this case via a source terminal of the component. However, since in the EEPROM devices of this embodiment, the capacitive coupling kn is usually larger than the capacitive coupling ks, preference is given to the first variant.
Optional kann die reduzierte EEPROM-Zelle um einen zusätzlichen ohmschen Widerstand (R) als Parallelwiderstand (15) erweitert werden. Der ohmsche Widerstand (R) ist parallel zum Kanalwiderstand RK geschaltet - siehe Fig. 4 - wobei der ohmsche Widerstand (R) unabhängig vom Kanalwiderstand RK ist und dazu dient, auch für den Grenzfall RK—> °o einen Stromfluss in einer technischen Verschaltung des Zweipolbauelements zu garantieren. Optionally, the reduced EEPROM cell can be extended by an additional ohmic resistance (R) as a parallel resistor (15). The ohmic resistance (R) is connected in parallel to the channel resistance R K - see Fig. 4 - wherein the ohmic resistance (R) is independent of the channel resistance R K and serves, even for the limiting case R K -> ° o a current flow in one guarantee technical interconnection of the two-pole component.
Erfindungsgemäß entsteht - auf der Grundlage bekannter EEPROM-Zellen mit zusätzlichem Floating-Gate - das beschriebene neue Bauelement mit einer memristischen Übertragungscharakteristik aus zwei unabhängigen Schaltungsschritten: Indem eine EEPROM-Zelle mit Floating-Gate - wie beschrieben - reduziert verschaltet wird, so alle Schichtanschlüsse des Bauelementes herausgeführt sind, According to the invention, based on known EEPROM cells with an additional floating gate, the described novel component with a memristic transmission characteristic consists of two independent circuit steps: By reducing the interconnection of a floating-gate EEPROM as described, all the layer terminals of the device are led out,
- oder im Zuge der Produktion selbiger EEPROM-Zellen die Reduzierung der Schaltung bereits im Fertigungsprozess erfolgt; - or in the course of the production of the same EEPROM cells, the reduction of the circuit already takes place in the manufacturing process;
- jedoch beide technische Veränderungen führen dazu, dass die so reduzierte EEPROM- Zelle als Zweipolschaltung vorliegt und sich wie ein passives Bauelement verhält. - However, both technical changes cause the thus reduced EEPROM cell is present as a two-pole circuit and behaves like a passive device.
Bezugszeichenliste : List of reference numbers:
1 Control-Gate  1 control gate
2 Isolator-Floating-Gate-Elektrode 2 insulator floating gate electrode
3 Source 3 Source
4 Drain 4 drain
5 Control-Gate-Oxid 5 control gate oxide
6 Floating-Gate 6 floating gate
7 Gate-Oxid 7 gate oxide
8 Control-Gate-Anschluss 8 control gate connection
9 Drain-Anschluss 9 drain connection
10 Bulk-Anschluss 10 bulk connection
11 Bulk 11 bulk
12 Control-Gate-Source-Anschluss 12 Control gate-source connection
13 EEPROM-Zelle 13 EEPROM cell
14 gemeinsamer Potenzialpunkt Control-Gate/Source 14 common potential point control gate / source
15 Parallelwiderstand k kapazitiver Kopplungsfaktor R ohmscher Widerstand 15 parallel resistance k capacitive coupling factor R ohmic resistance
RK Kanalwiderstand R K channel resistance
V+ positive SpannungsversorgungV + positive power supply
V" negative SpannungsversorgungV " negative power supply
Vin Zweipol-Steuerspannung Vi n two-pole control voltage

Claims

Ansprüche claims
1. EEPROM-Speicherzelle mit einem Control-Gate (1), einem Souce (3), einem Drain (4), einem Bulk-Anschluss (10) und einem Floating-Gate (6), wobei die EEPROM- Speicherzelle in Zweipolschaltung zur Verwendung als passives elektronisches Bauelement mit memristischer Übertragungscharakteristik verschaltet ist, wobei 1. EEPROM memory cell with a control gate (1), a Souce (3), a drain (4), a bulk terminal (10) and a floating gate (6), wherein the EEPROM memory cell in Zweipolschaltung to Use is connected as a passive electronic component with memristic transmission characteristic, wherein
- das Control-Gate (1) mit dem Source (3) verbunden ist, the control gate (1) is connected to the source (3),
- die miteinander verbundenen Anschlüsse Control-Gate (1) und Source (3) auf ein gemeinsames Bezugspotenzial gelegt sind, the interconnected connections control gate (1) and source (3) are placed on a common reference potential,
- der Bulk-Anschluss (10) auf das niedrigste in der Schaltung vorkommende Potenzial gelegt ist, und - The bulk connector (10) is placed at the lowest potential occurring in the circuit, and
- das Drain (4) an eine Steuerspannung (Vin) gelegt ist. - The drain (4) to a control voltage (Vi n ) is placed.
2. EEPROM-Speicherzelle nach Anspruch 1, dadurch gekennzeichnet, dass der im spannungslosen Zustand vorhandene Kanalwiderstand (Rk) dem zu speichernden Zustand entspricht. 2. EEPROM memory cell according to claim 1, characterized in that the present in the de-energized state channel resistance (R k ) corresponds to the state to be stored.
3. EEPROM-Speicherzelle nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass die Steuerspannung (Vm) bipolar ist. 3. EEPROM memory cell according to claim 1 or 2, characterized in that the control voltage (V m ) is bipolar.
4. EEPROM-Speicherzelle nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, dass die EEPROM-Speicherzelle parallel zum Kanalwiderstand (Rk) mit einem Parallelwiderstand (15) beschaltet ist. 4. EEPROM memory cell according to one of claims 1 to 3, characterized in that the EEPROM memory cell is connected in parallel to the channel resistance (R k ) with a parallel resistor (15).
PCT/EP2013/061154 2012-06-01 2013-05-30 Eeprom memory cell as a memristive component WO2013178730A1 (en)

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