WO2013101136A1 - Dual composite field advanced encryption standard memory encryption engine - Google Patents

Dual composite field advanced encryption standard memory encryption engine Download PDF

Info

Publication number
WO2013101136A1
WO2013101136A1 PCT/US2011/068003 US2011068003W WO2013101136A1 WO 2013101136 A1 WO2013101136 A1 WO 2013101136A1 US 2011068003 W US2011068003 W US 2011068003W WO 2013101136 A1 WO2013101136 A1 WO 2013101136A1
Authority
WO
WIPO (PCT)
Prior art keywords
polynomials
encryption
storing instructions
medium
field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/US2011/068003
Other languages
French (fr)
Inventor
Sanu K. Mathew
Shay Gueron
Ram K. Krishnamurthy
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Priority to PCT/US2011/068003 priority Critical patent/WO2013101136A1/en
Priority to US13/993,545 priority patent/US20140229741A1/en
Priority to CN201180076150.5A priority patent/CN104011732B/en
Publication of WO2013101136A1 publication Critical patent/WO2013101136A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/72—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in cryptographic circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/60—Protecting data
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
    • H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
    • H04L2209/12—Details relating to cryptographic hardware or logic circuitry
    • H04L2209/122—Hardware reduction or efficient architectures

Definitions

  • This relates generally to a memory encryption engine.
  • a memory encryption engine is used to protect data as it is written to and read from memory.
  • the encryption uses the Advanced Encryption Standard (AES). See N 1ST Advanced Encryption Standard (FIP pub. 197, November 26, 2001 ).
  • AES Advanced Encryption Standard
  • the Advanced Encryption Standard is a symmetric-key encryption protocol used to encrypt and decrypt all read and write memory accesses. In order to prevent reads and writes from swamping processor performance, hardware accelerated AES encrypt and decrypt operations are desirable.
  • AES provides several modes of operations.
  • AES-128, AES-192 and AES- 256 modes of operation submit 128-bit input data to respectfully, ten, twelve, and fourteen iterations of an AES round operation.
  • the AES round operation includes successive Substitute Bytes, ShiftRow and MixedColumns transformations, followed by an AddRoundKey operation.
  • each 8-bits of the 128-bit input data is input into one of sixteen S-boxes.
  • Each S-box computes the multiplicative inverse of its respective 8-bit input in the Galois Field GF(2 8 ) .
  • implementations map the 8-bit input to a composite field, (GF(2 4 ) 2 ), compute the multiplicative inverse in GF(2 4 ) 2 , map the result back to a ground field GF(2 8 ), and proceed to the shift row transformation.
  • Figure 1 is a schematic depiction of a memory encryption engine
  • Figure 2 is an advanced encryption standard S-box according to one embodiment
  • Figure 3 is a depiction of the multiplier equations according to one
  • Figure 4 is a depiction of the GF(2 4 ) multiplier according to one embodiment
  • Figure 5 is a depiction of an S-box subblock for encrypt and decrypt according to one embodiment
  • Figure 6 is a depiction of an S-box subblock for encrypt and decrypt according to another embodiment
  • Figure 7 is a schematic depiction of MixColumn block for encrypt according to one embodiment
  • Figure 8 is a flow chart for one embodiment.
  • Figure 9 is a system depiction for one embodiment.
  • different sets of polynomials are selected for encryption and decryption accelerators. That is, different sets of polynomials are used for encryption and decryption, each set being chosen to use less area and deliver more power for a memory encryption engine. This is advantageous in some embodiments since memory read operations are typically more critical and latency sensitive than memory writes.
  • read data from memory 26 is provided to a two to one multiplexer in a memory encryption engine 10 and then to an AddRoundKey unit 14 in the memory read path. From there the data goes to a Substitute Bytes block 16, ShiftRows block 18 and MixColumns/AddRoundKey block 20. After ten iterations, according to one embodiment, the read data from the core 22 is output.
  • the core 22 may be a processor such as a central processing unit.
  • the plaintext operands in GF(2 8 ) are mapped to the composite-field of GF(2 4 ) 2 .
  • the corresponding two-term element in the composite field is represented as shx+sl, where the elements sh and si are terms in the field of GF(2 4 ) and the composite-field is defined by the polynomial x 2 + ⁇ + ⁇ .
  • Operations in the ground field of GF(2 4 ) are, on the other hand, defined by a ground-field polynomial. There are sixteen potential choices for the ground-field polynomial of order four, ranging from x 4 , x 4 +1 ...x 4 +x 3 +x 2 +x+1 .
  • the composite-field GF(2 4 ) 2 is an extension of the ground field GF(2 4 ). It is therefore associated with a generator polynomial known as the composite-field polynomial ⁇ 2 + ⁇ + ⁇ , where a and ⁇ are elements of GF(2 4 ). In some embodiments the polynomial may be irreducible (i.e. not have a root) in GF(2 4 ). There are 256 potential candidates for the composite-field polynomial, ranging from x 2 , x 2 +1 , x 2 +Fx+E, x 2 +Fx+F. The list of 4096 possible combinations of ground and composite- field polynomials is pruned down to 360 combinations by the test for irreducibility.
  • the element e y forms the basis of the composite-field.
  • mapping matrix [ ⁇ 7 , ⁇ 5 , ⁇ 4 , ⁇ 3 , y 2 , y, 1 ] and its inverse matrix.
  • RTL parameterized register transfer level
  • the design is further optimized by considering three options regarding addition of the affine constant Mb.
  • This constant can be added at the end of the affine transform or can be set to Oxff or 0x00. In the latter two cases, the affine constant is instead added to the RoundKey.
  • sh*a and the square*3 block in the S-box shown in Figure 2 use separate designs for encrypt and decrypt, since the designs of these blocks ( Figures 5 and 6) depend on the composite-field polynomial and hence depend on the choice of a and ⁇ .
  • the inverse-mix column block for decrypt is designed by computing the scaling factors *2, *3, *4, *5, *6, *7, *B and *E.
  • a decrypt block that operates at the same frequency and latency.
  • a memory encryption engine sequence 30 may be implemented in software, firmware, and/or hardware. In software and firmware embodiments, it may be implemented by computer executed instructions stored in a non-transitory computer readable medium such as a magnetic, optic or semiconductor storage.
  • Sequence 30 begins by using the first set of polynomials for encryption as indicated in block 32.
  • a different set of polynomials may be used for decryption as indicated in block 34.
  • encryption operations may be used for reading as indicated in block 36.
  • a system 40 may be a portable computing device, such as a laptop computer, a tablet computer, or a cellular telephone, or it may be a personal computer, to mention a few examples.
  • System 40 may include a processor or core 22 coupled to a chipset 44.
  • the chipset 44 may be in turn coupled to a system memory 26 and the solid state drive 51 .
  • a network interface card (“NIC") 50 may be coupled the chipset 44.
  • the chipset in one embodiment may include the memory encryption engine 10.
  • a wireless interface 62 having an antenna 64.
  • the wireless interface may be a cellular interface such as a Third Generation Partnership Project (3GPP) or Long Term Evolution (LTE) cellular interface.
  • 3GPP Third Generation Partnership Project
  • LTE Long Term Evolution
  • a display 60 is also coupled to the chipset 44.
  • the display 60 may be a touch screen.
  • the processor may be any processor or controller.
  • the processor 22 may be an application processor.
  • references throughout this specification to "one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present invention. Thus, appearances of the phrase “one embodiment” or “in an embodiment” are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be instituted in other suitable forms other than the particular embodiment illustrated and all such forms may be encompassed within the claims of the present application.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Security & Cryptography (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Health & Medical Sciences (AREA)
  • Bioethics (AREA)
  • General Health & Medical Sciences (AREA)
  • Storage Device Security (AREA)
  • Treating Waste Gases (AREA)

Description

DUAL COMPOSITE FIELD ADVANCED
ENCRYPTION STANDARD MEMORY ENCRYPTION ENGINE
Background
[0001 ] This relates generally to a memory encryption engine.
[0002] A memory encryption engine is used to protect data as it is written to and read from memory. Typically the encryption uses the Advanced Encryption Standard (AES). See N 1ST Advanced Encryption Standard (FIP pub. 197, November 26, 2001 ). The Advanced Encryption Standard is a symmetric-key encryption protocol used to encrypt and decrypt all read and write memory accesses. In order to prevent reads and writes from swamping processor performance, hardware accelerated AES encrypt and decrypt operations are desirable.
[0003] AES provides several modes of operations. AES-128, AES-192 and AES- 256 modes of operation submit 128-bit input data to respectfully, ten, twelve, and fourteen iterations of an AES round operation. The AES round operation includes successive Substitute Bytes, ShiftRow and MixedColumns transformations, followed by an AddRoundKey operation.
[0004] During the Substitute Bytes transformation, each 8-bits of the 128-bit input data is input into one of sixteen S-boxes. Each S-box computes the multiplicative inverse of its respective 8-bit input in the Galois Field GF(28) . Some
implementations map the 8-bit input to a composite field, (GF(24)2), compute the multiplicative inverse in GF(24)2, map the result back to a ground field GF(28), and proceed to the shift row transformation.
Brief Description Of The Drawings
[0005] Some embodiments are described with respect to the following figures:
Figure 1 is a schematic depiction of a memory encryption engine;
Figure 2 is an advanced encryption standard S-box according to one embodiment; Figure 3 is a depiction of the multiplier equations according to one
embodiment to the present invention;
Figure 4 is a depiction of the GF(24) multiplier according to one embodiment;
Figure 5 is a depiction of an S-box subblock for encrypt and decrypt according to one embodiment;
Figure 6 is a depiction of an S-box subblock for encrypt and decrypt according to another embodiment;
Figure 7 is a schematic depiction of MixColumn block for encrypt according to one embodiment;
Figure 8 is a flow chart for one embodiment; and
Figure 9 is a system depiction for one embodiment.
Detailed Description
[0006] In accordance with some embodiments, different sets of polynomials are selected for encryption and decryption accelerators. That is, different sets of polynomials are used for encryption and decryption, each set being chosen to use less area and deliver more power for a memory encryption engine. This is advantageous in some embodiments since memory read operations are typically more critical and latency sensitive than memory writes.
[0007] Referring to Figure 1 , read data from memory 26 is provided to a two to one multiplexer in a memory encryption engine 10 and then to an AddRoundKey unit 14 in the memory read path. From there the data goes to a Substitute Bytes block 16, ShiftRows block 18 and MixColumns/AddRoundKey block 20. After ten iterations, according to one embodiment, the read data from the core 22 is output. The core 22 may be a processor such as a central processing unit.
[0008] Work data from the core 22 is provided to a two to one multiplexer in the memory write path and then to an inverse MixColumn/AddRoundKey unit 20a. From here the data goes to an inverse Substitute Bytes unit 16a and an InverseShiftRows unit 18a. Finally the data is outputted from an AddRoundKey unit 14a of write data to memory 26 after ten iterations, according to one embodiment. [0009] In some embodiments, a trade-off is made to improve a read path by using simpler computations of AES-128 encrypt during a memory read, while using AES- 128 decrypt during memory writes. This avoids using more complex AES-128 decrypt memory reads. The presence of a larger number of read ports compared to write ports also makes this trade-off attractive from a silicon area use perspective.
[0010] The use of separate encrypt and decrypt hardware for simultaneous read and write operations makes the use of the same set of polynomials for both encrypt and decrypt suboptimal. Thus some embodiments use two sets of polynomials: one for encrypt and the other for decrypt.
[001 1 ] To facilitate inverse computation in the Substitute Bytes, the plaintext operands in GF(28)are mapped to the composite-field of GF(24)2 . The corresponding two-term element in the composite field is represented as shx+sl, where the elements sh and si are terms in the field of GF(24) and the composite-field is defined by the polynomial x2 +αχ+β. Operations in the ground field of GF(24) are, on the other hand, defined by a ground-field polynomial. There are sixteen potential choices for the ground-field polynomial of order four, ranging from x4, x 4 +1 ...x 4+x3 +x2+x+1 . The ground-field polynomial is a polynomial that is irreducible over GF(2), i.e. it does not have a root in GF(2)={0,1 }. This requirement eliminates most choices, leaving x4 +x+1 , x4+x3+1 and x4+x3+x2+x+1 as potential ground-field polynomials.
[0012] The composite-field GF(24)2 is an extension of the ground field GF(24). It is therefore associated with a generator polynomial known as the composite-field polynomial χ2+αχ+β, where a and β are elements of GF(24). In some embodiments the polynomial may be irreducible (i.e. not have a root) in GF(24). There are 256 potential candidates for the composite-field polynomial, ranging from x2, x2+1 , x2+Fx+E, x2+Fx+F. The list of 4096 possible combinations of ground and composite- field polynomials is pruned down to 360 combinations by the test for irreducibility. The next step involves the search for an element 'e' in GF(24)2 that is both a root of the composite-field (i.e e2+ae+3=0) and has some power y that is also a root of the original GF(28) generator polynomial (i.e. (ey)8+(ey)4+(ey)3+(ey)+ 1 = 0). The element ey forms the basis of the composite-field. The above tests yields eight potential bases in each of the 360 combinations, leading to 2880 valid representations for the composite-field.
Figure imgf000006_0001
Figure imgf000007_0001
Figure imgf000008_0001
Figure imgf000009_0001
Figure imgf000010_0001
Figure imgf000011_0001
[0013] The 2880 composite-field polynomials along with their basis element (y=ey) are shown above for ground-field polynomials x4+x+1 , x4+x3+1 and
x4+x3+x2+x+1 . The basis element γ, is used to generate mapping matrix [γ7, γ5, γ4, γ3, y2, y, 1 ] and its inverse matrix. Each of these polynomial pairs, along with the basis was used to automatically generate parameterized register transfer level (RTL) for AES encrypt and AES decrypt rounds as well as RTL for mapping and inverse- mapping hardware to convert operands between GF(28) and GF(24)2.
[0014] The process was automated to synthesize all 2880 polynomial-pairs and the lowest area solution is obtained. Pairs for the ground-field polynomial of x4+x3+1 and composite-field polynomial of x2 +Cx+C with Mix Column scaling factor of c7. This design uses a>1 as a choice in the composite-field polynomial. The use of a>1 requires the use of an additional multiplier in the AES S-box as shown in Figure 2. The overhead for this multiplier may be low, as seen in Figure 3, where this multiplier can be implemented with one exclusive OR gate for the lowest-area case of a=C.
[0015] The design is further optimized by considering three options regarding addition of the affine constant Mb. This constant can be added at the end of the affine transform or can be set to Oxff or 0x00. In the latter two cases, the affine constant is instead added to the RoundKey. The lowest-area solution changes to the case where Mb=0xFF and the new polynomial-pair of x4+x3+1 and x2+Cx+C with mixcol scaling factor of c2, resulting in a further reduction in area.
[0016] The lowest-area AES decrypt hardware is obtained with the ground-field polynomial of x4+x3+1 and composite-field polynomial of x2 +Cx+2, with Mix Column scaling factor of 13. We further explore the decrypt design space by synthesizing the design for the three choices of inverse-affince constant MAinvb
(MAinvb=MAinvb, MAinvbO and MAinvb=1 ). This yields the optimal decrypt polynomial pair of x4 +x3+1 and x2 +6x+4, with MixColumn scaling factor of 13 and a total area of 6060 sq.um, resulting in overall area improvement. Thus we have encrypt and decrypt hardware with two separate polynomials, each optimized separately to minimize area. [0017] Since both encrypt and decrypt hardware are optimal for the same ground- field of x4+x3+1 , the multiplier and inverse calculation in GF(24) will use identical designs, as shown in Figure 4, since the choice of composite-field polynomial has no impact on these blocks. However, the sh*a and the square*3 block in the S-box shown in Figure 2 use separate designs for encrypt and decrypt, since the designs of these blocks (Figures 5 and 6) depend on the composite-field polynomial and hence depend on the choice of a and β.
[0018] The use of separate composite-field polynomials for encrypt and decrypt also result in unique mix column/inverse-mix column blocks for encrypt and decrypt. The use of MixColumn scaling factors of 0xc2 and 0xc3 during encrypt result in simple multiplication factors of *2, *6, *3, *C, *4 and *5 which is implemented using 1 , 2, 3, 1 , 4 and 2 exclusive OR gate respectively (Figure 7). This results in a compact 28 exclusive OR implementation for each byte of the MixColumn block (Figure 7).
[0019] Similarly, the inverse-mix column block for decrypt is designed by computing the scaling factors *2, *3, *4, *5, *6, *7, *B and *E. Thus, we have an encrypt block with single cycle latency and a decrypt block that operates at the same frequency and latency. We also leverage the eight percent (8%) lower area of the encrypt block to use it for the performance-critical read operations and instead use the larger decrypt block during memory-writes.
[0020] We use the compact encrypt block for memory-reads which are more performance-critical compared to memory-writes. The presence of more read ports than write ports justifies the use of the lower-area encrypt design for read operations.
[0021 ] Referring to Figure 8, in accordance with some embodiments, a memory encryption engine sequence 30 may be implemented in software, firmware, and/or hardware. In software and firmware embodiments, it may be implemented by computer executed instructions stored in a non-transitory computer readable medium such as a magnetic, optic or semiconductor storage.
[0022] Sequence 30 begins by using the first set of polynomials for encryption as indicated in block 32. A different set of polynomials may be used for decryption as indicated in block 34. In some embodiments encryption operations may be used for reading as indicated in block 36.
[0023] Referring to Figure 9, a system 40 may be a portable computing device, such as a laptop computer, a tablet computer, or a cellular telephone, or it may be a personal computer, to mention a few examples. System 40 may include a processor or core 22 coupled to a chipset 44. The chipset 44 may be in turn coupled to a system memory 26 and the solid state drive 51 . A network interface card ("NIC") 50 may be coupled the chipset 44. The chipset, in one embodiment may include the memory encryption engine 10.
[0024] Also coupled to the chipset 44 is a wireless interface 62 having an antenna 64. The wireless interface may be a cellular interface such as a Third Generation Partnership Project (3GPP) or Long Term Evolution (LTE) cellular interface. Also coupled to the chipset 44 is a display 60. In one embodiment the display 60 may be a touch screen.
[0025] The processor may be any processor or controller. In one embodiment the processor 22 may be an application processor.
[0026] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present invention. Thus, appearances of the phrase "one embodiment" or "in an embodiment" are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be instituted in other suitable forms other than the particular embodiment illustrated and all such forms may be encompassed within the claims of the present application.
[0027] While the present invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous
modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this present invention.

Claims

What is claimed is:
1 . A method comprising:
using a first set of polynomials in a memory encryption engine for encryption and;
using a different set of polynomials in said engine for decryption.
2. The method of claim 1 including using encryption operations for reading.
3. The method of claim 1 including using Advanced Encryption Standard.
4. The method of claim 1 including selecting polynomials to optimize area usage.
5. The method of claim 1 including selecting polynomials to optimize power consumption.
6. The method of claim 1 including using Galois polynomials
7. The method of claim 1 including using irreducible polynomials.
8. The method of claim 1 including locating a primitive element that is both a generator and a root of a composite field.
9. The method of claim 8 including ensuring that an element exists in the field such that none of the powers of the element is one.
10. A non-transitory computer readable medium storing instructions to enable a processor to:
use a first set of polynomials for encryption and;
use a different set of polynomials for decryption.
1 1 . The medium of claim 10 further storing instructions to use encryption operations for reading.
12. The medium of claim 10 further storing instructions to use Advanced
Encryption Standard.
13. The medium of claim 10 further storing instructions to select polynomials to optimize area usage.
14. The medium of claim 10 further storing instructions to select polynomials to optimize power consumption.
15. The medium of claim 10 further storing instructions to use Galois polynomials.
16. The medium of claim 10 further storing instructions to use irreducible polynomials.
17. The medium of claim 10 further storing instructions to locate a primitive element that is both a generator and a root of a composite field.
18. The medium of claim 17 further storing instructions to ensure that an element exists in the field such that none of the powers of the element is one.
19. An apparatus comprising:
a memory write path to use a first set of polynomials; and a memory read path to use a different set of polynomials.
20. The apparatus of claim 19 said apparatus to use encryption operations for reading.
21 . The apparatus of claim 19 said apparatus to use Advanced Encryption Standard.
22. The apparatus of claim 19 said apparatus to select polynomials to optimize area usage.
23. The apparatus of claim 19 said apparatus to select polynomials to optimize power consumption.
24. The apparatus of claim 19 said apparatus to use Galois polynomials.
25. The apparatus of claim 19 said apparatus to use irreducible polynomials.
26. The apparatus of claim 19 said apparatus to locate a primitive element that is both a generator and a root of a composite field.
27. The apparatus of claim 26 said apparatus to ensure that an element exists in the field such that none of the powers of the element is one.
28. A system comprising:
a core;
a memory coupled to the core;
a memory encryption engine coupled to said core, said engine to use in first set of polynomials for encryption and a different set of polynomials for decryption; and
a network interface card coupled to said core.
29. The system of claim 28, said engine to use encryption operations for reading.
30. The system of claim 19, said engine to use irreducible polynomials.
PCT/US2011/068003 2011-12-30 2011-12-30 Dual composite field advanced encryption standard memory encryption engine Ceased WO2013101136A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
PCT/US2011/068003 WO2013101136A1 (en) 2011-12-30 2011-12-30 Dual composite field advanced encryption standard memory encryption engine
US13/993,545 US20140229741A1 (en) 2011-12-30 2011-12-30 Dual Composite Field Advanced Encryption Standard Memory Encryption Engine
CN201180076150.5A CN104011732B (en) 2011-12-30 2011-12-30 Double composite field Advanced Encryption Standard memory encryption engines

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2011/068003 WO2013101136A1 (en) 2011-12-30 2011-12-30 Dual composite field advanced encryption standard memory encryption engine

Publications (1)

Publication Number Publication Date
WO2013101136A1 true WO2013101136A1 (en) 2013-07-04

Family

ID=48698370

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2011/068003 Ceased WO2013101136A1 (en) 2011-12-30 2011-12-30 Dual composite field advanced encryption standard memory encryption engine

Country Status (3)

Country Link
US (1) US20140229741A1 (en)
CN (1) CN104011732B (en)
WO (1) WO2013101136A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5814880B2 (en) * 2012-07-31 2015-11-17 三菱電機株式会社 Encryption system, encryption method, encryption program, and decryption device
US9425961B2 (en) * 2014-03-24 2016-08-23 Stmicroelectronics S.R.L. Method for performing an encryption of an AES type, and corresponding system and computer program product
US9646175B2 (en) * 2014-11-26 2017-05-09 Synopsys, Inc. Two-way parity error detection for advanced encryption standard engines
US10103873B2 (en) * 2016-04-01 2018-10-16 Intel Corporation Power side-channel attack resistant advanced encryption standard accelerator processor
US9910792B2 (en) * 2016-04-11 2018-03-06 Intel Corporation Composite field scaled affine transforms-based hardware accelerator
US10218497B2 (en) * 2016-08-31 2019-02-26 Intel Corporation Hybrid AES-SMS4 hardware accelerator

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7177891B2 (en) * 2002-10-09 2007-02-13 Analog Devices, Inc. Compact Galois field multiplier engine
US20080019511A1 (en) * 2006-07-19 2008-01-24 Koichiro Akiyama Encryption apparatus, decryption apparatus, program, and method
US20090279691A1 (en) * 2008-05-09 2009-11-12 Farrugia Augustin J Secure distribution of data or content using keyless transformation
US20110010141A1 (en) * 2006-11-03 2011-01-13 Oxford Brookes University Polynomial synthesis

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020136401A1 (en) * 2000-07-25 2002-09-26 Jeffrey Hoffstein Digital signature and authentication method and apparatus
US7353204B2 (en) * 2001-04-03 2008-04-01 Zix Corporation Certified transmission system
US8155314B2 (en) * 2002-06-24 2012-04-10 Microsoft Corporation Systems and methods for securing video card output
CN1692600A (en) * 2002-10-09 2005-11-02 松下电器产业株式会社 Encryption device, decryption device and encryption system
US7197527B2 (en) * 2002-10-17 2007-03-27 Telefonaktiebolaget Lm Ericsson (Publ) Efficient arithmetic in finite fields of odd characteristic on binary hardware
US7415115B2 (en) * 2003-05-14 2008-08-19 Broadcom Corporation Method and system for disaster recovery of data from a storage device
US8103004B2 (en) * 2003-10-03 2012-01-24 Sony Corporation Method, apparatus and system for use in distributed and parallel decryption
US7860240B2 (en) * 2007-06-29 2010-12-28 Intel Corporation Native composite-field AES encryption/decryption accelerator circuit
US8923510B2 (en) * 2007-12-28 2014-12-30 Intel Corporation Method and apparatus for efficiently implementing the advanced encryption standard
DE102008024535A1 (en) * 2008-05-21 2009-12-03 Siemens Medical Instruments Pte. Ltd. Method for optimizing a multi-level filter bank and corresponding filter bank and hearing device
TWI416347B (en) * 2009-06-22 2013-11-21 Realtek Semiconductor Corp Method and processing circuit for dealing with galois field computation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7177891B2 (en) * 2002-10-09 2007-02-13 Analog Devices, Inc. Compact Galois field multiplier engine
US20080019511A1 (en) * 2006-07-19 2008-01-24 Koichiro Akiyama Encryption apparatus, decryption apparatus, program, and method
US20110010141A1 (en) * 2006-11-03 2011-01-13 Oxford Brookes University Polynomial synthesis
US20090279691A1 (en) * 2008-05-09 2009-11-12 Farrugia Augustin J Secure distribution of data or content using keyless transformation

Also Published As

Publication number Publication date
CN104011732B (en) 2018-06-15
CN104011732A (en) 2014-08-27
US20140229741A1 (en) 2014-08-14

Similar Documents

Publication Publication Date Title
Verbauwhede et al. Design and performance testing of a 2.29-GB/s Rijndael processor
US9843441B2 (en) Compact, low power advanced encryption standard circuit
Hanley et al. Hardware comparison of the ISO/IEC 29192-2 block ciphers
Samir et al. ASIC and FPGA comparative study for IoT lightweight hardware security algorithms
WO2013101136A1 (en) Dual composite field advanced encryption standard memory encryption engine
EP2822213A1 (en) Information processing device, information processing method, and programme
El Adib et al. AES encryption algorithm hardware implementation architecture: Resource and execution time optimization
US20120076294A1 (en) Arithmetic method and apparatus for supporting aes and aria encryption/decryption functions
EP4311158A1 (en) Efficient low-overhead side-channel protection for polynomial multiplication in post-quantum encryption
Paul et al. Partitioned security processor architecture on FPGA platform
Güneysu et al. High-performance cryptanalysis on RIVYERA and COPACOBANA computing systems
Gueron et al. Hardware implementation of AES using area-optimal polynomials for composite-field representation GF (2^ 4)^ 2 of GF (2^ 8)
US12519615B2 (en) Advanced encryption standard (AES) device
Tillich et al. Boosting AES performance on a tiny processor core
Hoang et al. A low power AES-GCM authenticated encryption core in 65nm SOTB CMOS process
Thongkhome et al. A FPGA design of AES core architecture for portable hard disk
Jacob et al. Feasibility and practicability of standardized cryptography on 4-bit micro controllers
Ege et al. Memory encryption for smart cards
Bani-Hani et al. Very compact and efficient 32-bit aes core design using FPGAS for small-footprint low-power embedded applications
Zhang et al. Efficient Table-Based Masking with Pre-processing
Burns et al. Efficient advanced encryption standard implementation using lookup and normal basis
Schneider et al. Cryptographic Algorithms on the GA144 Asynchronous Multi-Core Processor: Implementation and Side-Channel Analysis
Rajesh et al. Cryptography Algorithm
Tsekoura et al. Exploration of cryptographic ASIP designs for wireless sensor nodes
Benhadjyoussef et al. A compact 32-bit AES design for embedded system

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11878975

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 13993545

Country of ref document: US

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11878975

Country of ref document: EP

Kind code of ref document: A1