WO2013071892A1 - Method and apparatus for scalable low latency solid state drive interface - Google Patents
Method and apparatus for scalable low latency solid state drive interface Download PDFInfo
- Publication number
- WO2013071892A1 WO2013071892A1 PCT/CN2012/084823 CN2012084823W WO2013071892A1 WO 2013071892 A1 WO2013071892 A1 WO 2013071892A1 CN 2012084823 W CN2012084823 W CN 2012084823W WO 2013071892 A1 WO2013071892 A1 WO 2013071892A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- interface
- channel
- ssd
- interleaved
- data
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/409—Mechanical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Information Transfer Systems (AREA)
Abstract
A solid state drive (SSD) apparatus including a plurality of solid state drives, a channel- interleaved interface operably coupled to the solid state drives, and a Peripheral Component Interconnect Express (PCIe) bridge operably coupled to the channel-interleaved interface.
Description
Method and Apparatus for Scalable Low Latency Solid State Drive Interface
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This patent application claims priority to U.S. Provisional Application No. 61/561 ,160, filed on November 17, 2011, entitled "Method and Apparatus for Scalable Low Latency Solid State Drive Interface," and claims priority to U.S. Patent Application No. 13/ 460695 filed April 30, 2012, entitled "Method and Apparatus for Scalable Low Latency Solid State Drive Interface", which are incorporated herein by reference as if reproduced in their entirety.
FIELD OF INVENTION
[0002] The present invention relates to a method and apparatus for solid state drives, and, in particular embodiments, to a method and apparatus for a scalable low latency solid state drive (SSD) interface.
BACKGROUND
[0003] In recent years, NAND flash memory-based SSDs have been widely adopted in various applications where data access speed is needed. SSDs have reduced the traditional read latency from hard disk drive's multiple milliseconds to less than 100 microseconds. The traditional hard disk drive (HDD) interface like serial SCSI (SAS) or serial ATA (SATA) are no longer an appropriate fit for SSD due to their longer latency. Because of the increased speed of SSDs over HDDs, the traditional HDD interface is no longer suitable for SSD applications due to the low latency of SSDs.
SUMMARY
[0004] Technical advantages are generally achieved by embodiments of the present disclosure which provide a method and apparatus for solid state drive (SSD) storage access for improving SSD performance.
[0005] In an embodiment, a solid state drive (SSD) apparatus including a plurality of solid state drives, a channel-interleaved interface operably coupled to the solid state drives, and a Peripheral Component Interconnect Express (PCIe) bridge operably coupled to the channel- interleaved interface.
[0006] In an embodiment, a solid state drive (SSD) apparatus including a plurality of solid state drives, a channel-interleaved interface operably coupled to the solid state drives, and a plurality of Peripheral Component Interconnect Express (PCIe) bridges operably coupled to the channel-interleaved interface. Each of the PCIe bridges is configured to exchange data with each of the solid state drives through the channel-interleaved interface.
[0007] In an embodiment, a method of accessing data stored in a solid state drive includes interleaving a read command with a first portion of a write data command and a second portion of the write data command to form an interleaved command, sending the interleaved command to the solid state drive via an interleaved channel-based interface, and receiving the data from the solid state drive in response to the read command in the interleaved command.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
[0009] Figure 1 is a block diagram of an embodiment of a SSD system;
[0010] Figure 2 is a block diagram of another embodiment of a SSD system;
[0011] Figure 3 is a block diagram of another embodiment of a SSD system;
[0012] Figure 4 is a data frame format defined in order to use Interlaken interface as channel-interleaved interface for SSD applications; [0013] Figure 5 is a an interleaved command formed by interleaving a read command and a write data command;
[0014] Figure 6 is a block diagram illustrating a computing platform in which the methods and apparatuses described herein may be implemented, in accordance with various embodiments.
[0015] Figure 7 is a flowchart of a method of accessing data stored in a SSD. DETAILED DESCRIPTION
[0016] The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that may be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure. [0017] Solid state drives (SSDs) lately have been increasingly adopted for use in computer systems, either as a cache of the hard disk drive (HDD) or as a direct replacement of the HDD. In such architectures, SSDs are increasingly used to increase access speed to stored or cached data, to reduce the size, weight, and power consumption profile of the system, and to reduce the access latency to the stored or cached data. SSD read latency, however, is reduced quite dramatically relative to traditional HDD read latency, and therefore the traditional HDD interface does not efficiently utilize the faster SSDs.
[0018] Referring now to Figure 1 , an embodiment SSD apparatus 10 is illustrated. As will be more fully explained below, the SSD apparatus 10 reduces the read latency for SSDs by using a low latency interface. By using a switching protocol low latency interface design, an embodiment will reduce the read access latency and scale up in capacity. Such a low latency interface also enables SSD design to be modular and allows the SSD module to be hot pluggable. The SSD apparatus 10 further permits the scalability of SSDs to many modules and many hosts. In addition, the low latency interface for the SSD provides a modular solution and scales up in size and performance based on a fabric switch in the interface. As shown in Figure 1 , in an embodiment the SSD apparatus 10 includes several SSDs 12, a channel-interleaved interface 14, and a Peripheral Component Interconnect Express (PCIe) bridge 16. As used herein, the PCIe bridge 16 may represent or be referred to as PCIe, a PCIe bridge controller, and so on.
[0019] The SSDs 12 in Figure 1, which may also be referred to as a solid-state disk or electronic disk, are data storage devices that use integrated circuit assemblies as memory to store data persistently. The SSDs 12 do not employ any moving mechanical components, which distinguishes them from traditional magnetic disks such as hard disk drives (HDDs) or floppy disk, which are electromechanical devices containing spinning disks and movable read/write heads. Compared to electromechanical disks, the SSDs 12 are typically less susceptible to physical shock, are silent, have lower access time and latency, but are more expensive per unit of storage. [0020] Still referring to Figure 1 , the SSDs 12 may use NAND-based flash memory, which retains data without power. For applications requiring fast access, but not necessarily data persistence after power loss, the SSDs 12 may be constructed from random-access memory (RAM). Such devices may employ separate power sources, such as batteries, to maintain data
after power loss. The SSDs 12 may be organized using a redundant array of independent disks (RAID) format or scheme in nested levels such as, for example, RAID 16+1 and so on. While eight of the SSDs 12, which are labeled SS DO to SS D7, are illustrated in the SSD apparatus 10 of Figure 1, more or fewer of the SSDs 12 may be employed. [0021] Still referring to Figure 1, the channel-interleaved interface 14 is operably coupled to the SSDs 12. The channel-interleaved interface 14 functions as a low latency controller. As such, data and information retrieved from the SSDs 12 may be passed through the channel- interleaved interface 14. The channel-interleaved interface 14 may be otherwise known as or referred to as a fabric, a fabric switch, a switch, a switched fabric, and so on. [0022] In an embodiment, the channel-interleaved interface 14 is an Interlaken interface, which is used as a low latency interface for SSD implementations. The Interlaken interface is a royalty- free high speed interface protocol that is optimized for high-bandwidth and reliable packet transfers. The Interlaken interface was created to connect networking ASICs together. The Interlaken interface provides a narrow, high-speed, channelized packet interface. The Interlaken interface has lower latency than the current SATA or SAS latencies. In an
embodiment, the Interlaken interface is used to replace the traditional FIDD interface, such as SATA or SAS. As will be more fully explained below, the Interlaken interface provides the advantage of a channel interleaved mode, which enables the SSD apparatus 10 to shorten the read latency. [0023] The PCIe bridge 16 of Figure 1 supports Peripheral Component Interconnect Express (a.k.a., PCIE, PCIe, or PCI Express), which is a computer expansion bus standard designed to replace the older PCI, PCI-X, and AGP bus standards. PCIe has numerous improvements over the aforementioned bus standards, including higher maximum system bus throughput, lower I/O
pin count and smaller physical footprint, better performance-scaling for bus devices, a more detailed error detection and reporting mechanism, and native hot-plug functionality. More recent revisions of the PCIe standard support hardware I/O virtualization. As will be more fully explained below, the PCIe bridge 16 is operably coupled to, for example, a central processing unit (CPU) of a computer, server, tablet, smart phone, other electronic device.
[0024] While a single PCIe bridge 16 is illustrated in the SSD apparatus 10 of Figure 1, more or fewer of the PCIe bridges 16 may be employed. Indeed, referring now to Figure 2, in an embodiment several of the PCIe bridges 16 are incorporated into the SSD apparatus 10. In an embodiment, the PCIe bridges 16 are collectively controlled by or disposed on a PCIe bridge controller 18. In an embodiment, the PCIe bridge controller 18 is a generation 2 blade motherboard. In Figure 2, the PCIe bridge controller 18 has eight expansion slots. In other embodiments, different motherboards, controllers, and so on with more or fewer expansion slots may be employed.
[0025] The SSD apparatus 10 of Figure 2 is a switched system of SSDs 12. In Figure 2, there are multiple PCIe bridges 16 that each interface with one PCIe interface on one end and with one low latency switching interface of a fabric switch (i.e., the channel-interleaved interface 14) on the other end. The fabric switch may switch the read and write commands to the corresponding SSD 12 or the PCIe bridge controller 18.
[0026] Referring now to Figure 3, in an embodiment the SSD apparatus 10 includes several PCIe bridges 16 operably coupled to the channel-interleaved interface-based fabric switch 14. The channel-interleaved interface-based fabric switch 14 is also operably coupled to additional memory 20, a fiber channel network connection 22, and a network connection 24. The additional memory 20 may be, for example, static random access memory (SRAM), dynamic
random access memory (DRAM), synchronous DRAM (SDRAM), non-volatile RAM
(NVRAM), read-only memory (ROM), a combination thereof, or other types of memory.
[0027] The fiber channel network connection 22 may be, for example, an FC-HBA API (also called the SNIA Common HBA API). The FC-HBA API is an Application Programming Interface for Host Bus Adapters connecting computers to hard disks via a fiber channel network. The HBA API has been adopted by Storage Area Network vendors to help manage, monitor, and deploy storage area networks in an interoperable way. The network connection 24 may be, for example, an Ethernet network interface controller (NIC). The NIC, which is also known as a network interface card, network adapter, LAN adapter, and so on, is a computer hardware component that connects a computer to a computer network.
[0028] Referring now to Figure 4, in an embodiment in order to use the Interlaken interface as the channel-interleaved interface 14 for SSD applications, a data frame format 26 as illustrated in Figure 4 is defined. Indeed, the data frame format 26 permits the SSDs 12 to be switched using the Interlaken-based fabric switch. In an embodiment, the data frame format 26 includes a header region 28, a data region 30, and a cyclic redundancy check (CRC) region 32.
[0029] As shown in Figure 4, in an embodiment the header region 28 is disposed proximate a start of frame (SOF) 34 of the data frame format 26. In an embodiment, the header region 28 includes or identifies numerous parameters such as, for example, a command code (R CTL), a destination identification (DID), a quality of service (QOS), a type of command (CLASS), a source identification (SID), a command tag of the frame (CMD TAG), a command length
(LENGTH), a submission queue identification (SQ ID ), a command identification (CMD ID ), and a linear block address (LB A). The header region 28 may be configured to include more or fewer parameters or additional parameters relative to those illustrated in Figure 4.
[0030] In an embodiment, the data region 30 follows the header region 28 in the data frame format 26. The data region 30 represents the portion of the data frame format 26 occupying data being transferred or exchanged by the SSDs 12 and the PCIe bridge 16 through the channel- interleaved interface 14. In an embodiment, the data frame format 26 also includes a cyclic redundancy check (CRC) region 32 proximate the end of frame (EOF) 36. The CRC region 32 contains parity or error check information or data. As such, the CRC region 32 offers protection over the whole frame.
[0031] Because the SSD apparatus 10 has a data frame format 26 with a source
identification (SID) and a destination identification (DID), which can be used to switch the data to and from the proper sources and destinations, the SSD apparatus 10 may be described and utilized as a switched system.
[0032] Referring now to Figure 5, in an embodiment the channel-interleaved interface 14 (e.g., the Interlaken interface) interleaves a read command 38 and between a first portion of a write data command 40 and a second portion of a write data command 42 to collectively form an interleaved command 44. Indeed, because the write command is issued or sent in multiple bursts (e.g., the first and second portions of the write command 40, 42), the read command 38 may be inserted between the first and second portions of the write command 40, 42. This generally allows the read data to be obtained as soon as possible. By doing so, read access latency is reduced. [0033] Embodiments of the SSD apparatus 10 may be used in PCIe SSDs, NVM express, PCIe storage blades in CDN iStream products, enterprise storage, and the like. An embodiment provides scalability that allows multiple host CPUs access to the PCIe SSD. Moreover, and the
SSD apparatus 10 becomes switch friendly so that the SSDs 12 may be scaled up to multiple hosts and multiple devices by using a switch architecture.
[0034] Figure 6 is a block diagram of an embodiment computer system 46 in which the devices and methods disclosed herein may be implemented. Specific devices may utilize all of the components shown or only a subset of the components. In addition, levels of integration may vary from device to device. Furthermore, a device may contain multiple instances of a component, such as multiple processing units, processors, memories, transmitters, receivers, and so on.
[0035] The processing system 48 may be operably coupled to one or more input/output devices 50, such as a speaker, microphone, mouse, touchscreen, keypad, keyboard, printer, display, and the like. The processing system 48 may include a central processing unit (CPU) 52, memory 54, a mass storage device 56, a video adapter 58, an input/output (I/O) interface 60, and a network interface 62 connected to a bus 64.
[0036] The bus 64 may be one or more of any type of several bus architectures, such as PCIe, including a memory bus or memory controller, a peripheral bus, video bus, or the like.
The CPU 52 may comprise any type of electronic data processor. The memory 54 may comprise any type of system memory such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), non-volatile RAM (NVRAM), readonly memory (ROM), a combination thereof, or the like. In an embodiment, the memory 54 may include ROM for use at boot-up, and DRAM for program and data storage for use while executing programs.
[0037] The mass storage device 56 comprises one or more of the SSDs 12 or SSD apparatuses described above in Figures 1-3, and may be configured to store data, programs, and
other information and to make the data, programs, and other information accessible via the bus 64. The mass storage 56 device may also comprise, for example, one or more of a hard disk drive, a magnetic disk drive, an optical disk drive, or the like.
[0038] The video adapter 58 and the I/O interface 60 provide interfaces to couple external I/O devices 50 to the processing system 48. As illustrated, examples of I/O devices 50 include the display coupled to the video adapter 58 and the mouse/keyboard/printer coupled to the I/O interface 60. Other devices may be coupled to the processing system 48, and additional or fewer interface cards may be utilized. For example, a serial interface card (not shown) may be used to provide a serial interface for a printer. [0039] The processing system 48 also includes one or more network interfaces, which may comprise wired links, such as an Ethernet cable or the like, and/or wireless links to access nodes or different networks 66. The network interface 62 allows the processing system 48 to communicate with remote units via the networks. For example, the network interface 62 may provide wireless communication via one or more transmitters/transmit antennas and one or more receivers/receive antennas. In an embodiment, the processing system 48 is coupled to a local- area network or a wide-area network for data processing and communications with remote devices, such as other processing units, the Internet, remote storage facilities, or the like.
[0040] Referring now to Figure 7, an embodiment of a method 68 of accessing data stored in a SSD 12 is illustrated. In block 70, a read command 38 (Figure 5) is interleaved with the first portion of the write data command 40 and the second portion of the write data command 42 to form the interleaved command 44 (e.g., Figure 5). In block 72, the interleaved command 44 is sent to the SSD 12 via an interleaved channel-based interface 14 as described herein and
illustrated in Figures 1-3. Thereafter, in block 74, the data from the SSD 12 is received in response to the read command 38 embedded or incorporated in the interleaved command 44.
While the disclosure has been made with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.
Claims
1. A solid state drive (SSD) apparatus, comprising:
a plurality of solid state drives;
a channel-interleaved interface operably coupled to the solid state drives; and
a Peripheral Component Interconnect Express (PCIe) bridge operably coupled to the channel-interleaved interface.
2. The SSD apparatus of claim 1 , wherein the channel-interleaved interface utilizes a data frame format including a frame header, frame data, and a frame cyclic redundancy check (CRC).
3. The SSD apparatus of claim 1, wherein the channel- interleaved interface interleaves a read command between portions of write commands.
4. The SSD apparatus of claim 1, wherein the channel-interleaved interface issues write commands in multiple bursts.
5. The SSD apparatus of claim 1 , wherein the PCIe bridge is operably coupled to a PCIe bridge controller.
6. The SSD apparatus of claim 1 , wherein a plurality of PCIe bridges are operably coupled to the channel-interleaved interface.
7. The SSD apparatus of claim 6, wherein the PCIe bridges are operably coupled to a blade motherboard.
8. The SSD apparatus of claim 1, wherein the channel-interleaved interface comprises a fabric switch.
9. The SSD apparatus of claim 1, wherein the channel-interleaved interface is operably coupled to a fiber channel network connection.
10. The SSD apparatus of claim 1, wherein the channel- interleaved interface is operably coupled to a network connection.
11. A solid state drive (SSD) apparatus, comprising:
a plurality of solid state drives;
a channel-interleaved interface operably coupled to the solid state drives; and
a plurality of Peripheral Component Interconnect Express (PCIe) bridges operably coupled to the channel-interleaved interface, each of the PCIe bridges configured to exchange data with each of the solid state drives through the channel-interleaved interface.
12. The SSD apparatus of claim 11 , wherein the channel-interleaved interface inserts a read command after a first portion of a write command and before a second portion of the write command.
13. The SSD apparatus of claim 11 , wherein the channel-interleaved interface sends write commands to the solid state drives in discrete segment bursts.
14. The SSD apparatus of claim 11 , wherein the plurality of PCIe bridges are operably coupled to a blade motherboard.
15. The SSD apparatus of claim 11 , wherein the channel-interleaved interface comprises a fabric switch.
16. The SSD apparatus of claim 11 , wherein the channel-interleaved interface is configured to exchange with the solid state drives data frames having a frame header.
17. The SSD apparatus of claim 11 , wherein the channel-interleaved interface is configured to exchange with the solid state drives data frames having a frame cyclic redundancy check (CRC) frame.
18. The SSD apparatus of claim 11 , wherein the channel-interleaved interface is operably coupled to a fiber channel network connection.
19. The SSD apparatus of claim 11, wherein the channel-interleaved interface is operably coupled to a network connection.
20. A method of accessing data stored in a solid state drive, the method comprising:
interleaving a read command with a first portion of a write data command and a second portion of the write data command to form an interleaved command;
sending the interleaved command to the solid state drive via an interleaved channel-based interface; and
receiving the data from the solid state drive in response to the read command in the interleaved command.
21. The method of claim 20, further comprising formatting a data frame to include a frame header.
22. The method of claim 21, further comprising formatting the data frame to include a cyclic redundancy check (CRC) header.
23. The method of claim 22, further comprising formatting the data into data frames disposed between the frame header and the CRC header.
24. The method of claim 20, further comprising sending the data received from the solid state drive to a PCIe bridge.
25. The method of claim 20, further comprising accessing a fiber channel network connection through the interleaved channel-based interface.
26. The method of claim 20, further comprising accessing a network connection through the interleaved channel-based interface.
27. A computing system, comprising:
a Peripheral Component Interconnect Express (PCIe) bridge unit and a plurality of solid state drive (SSD) units;
wherein the PCIe bridge unit is configured to convert a PCIe interface to a first low latency interface, wherein each of the SSD unit includes a second low latency interface, the SSD unit is configured to couple to the PCIE bridge using the first low latency interface and the second low latency interface.
the SSD unit is configured to communicate with the PCIE bridge thought the first low latency interface and the second low latency interface.
28. The system of claim 27, wherein the first low latency interface and the second low latency interface are fabric interfaces.
29. The system of claim 27, wherein the second low latency interface enables the SSD to be modular and allows the SSD unit to be hot pluggable, and further permits the scalability of the SSD unit to many modules and many hosts.
30. The system of claim 27, wherein the second low latency interface is configured to communicate with the first low latency interface by a fabric switch.
31. The system of claim 27, wherein the first low latency interface is a channel- interleaved interface.
32. A data transmission method, comprising:
receiving, by a Peripheral Component Interconnect Express (PCIe) bridge unit, PCIe data,
converting, by the PCIe bridge unit, the PCIe data into low latency interface format data; sending, by the PCIe bridge unit, the low latency interface format data;
receiving, by a solid state drive (SSD) unit, the low latency interface format data.
33. The method of claim 32, wherein the low latency interface format data is converted to read/write command or data by the SSD unit.
34. The method of claim 32, further comprising: transmitting, by a switch unit, the low latency interface format data transmitted by the PCIe bridge unit to the SSD unit.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP12848997.8A EP2780791A4 (en) | 2011-11-17 | 2012-11-19 | Method and apparatus for scalable low latency solid state drive interface |
CN201280053366.4A CN103907088A (en) | 2011-11-17 | 2012-11-19 | Method and apparatus for scalable low latency solid state drive interface |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201161561160P | 2011-11-17 | 2011-11-17 | |
US61/561,160 | 2011-11-17 | ||
US13/460,695 US9767058B2 (en) | 2011-11-17 | 2012-04-30 | Method and apparatus for scalable low latency solid state drive interface |
US13/460,695 | 2012-04-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2013071892A1 true WO2013071892A1 (en) | 2013-05-23 |
Family
ID=48428063
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2012/084823 WO2013071892A1 (en) | 2011-11-17 | 2012-11-19 | Method and apparatus for scalable low latency solid state drive interface |
Country Status (4)
Country | Link |
---|---|
US (2) | US9767058B2 (en) |
EP (1) | EP2780791A4 (en) |
CN (1) | CN103907088A (en) |
WO (1) | WO2013071892A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018125433A1 (en) * | 2016-12-28 | 2018-07-05 | Intel Corporation | Method, apparatus and system for handling non-posted memory write transactions in a fabric |
Families Citing this family (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9251059B2 (en) * | 2011-09-23 | 2016-02-02 | Avalanche Technology, Inc. | Storage system employing MRAM and redundant array of solid state disk |
US20130135816A1 (en) * | 2011-11-17 | 2013-05-30 | Futurewei Technologies, Inc. | Method and Apparatus for Scalable Low Latency Solid State Drive Interface |
WO2013101209A1 (en) * | 2011-12-30 | 2013-07-04 | Intel Corporation | Thin translation for system access of non volatile semicondcutor storage as random access memory |
US10102170B2 (en) * | 2012-05-18 | 2018-10-16 | Dell Products, Lp | System and method for providing input/output functionality by an I/O complex switch |
WO2014115257A1 (en) * | 2013-01-23 | 2014-07-31 | 株式会社 日立製作所 | Storage device employing pci-express connection solid-state drive |
US9430412B2 (en) * | 2013-06-26 | 2016-08-30 | Cnex Labs, Inc. | NVM express controller for remote access of memory and I/O over Ethernet-type networks |
US8732633B1 (en) * | 2013-07-02 | 2014-05-20 | Tamba Networks, Inc. | Tunable design of an ethernet region of an integrated circuit |
US8832613B1 (en) | 2013-07-02 | 2014-09-09 | Tamba Networks, Inc. | Tunable design of an interlaken region of an integrated circuit |
US9529710B1 (en) | 2013-12-06 | 2016-12-27 | Western Digital Technologies, Inc. | Interleaved channels in a solid-state drive |
US9678910B2 (en) | 2014-04-25 | 2017-06-13 | Liqid Inc. | Power handling in a scalable storage system |
US10467166B2 (en) | 2014-04-25 | 2019-11-05 | Liqid Inc. | Stacked-device peripheral storage card |
US9645902B2 (en) | 2014-06-23 | 2017-05-09 | Liqid Inc. | Modular switched fabric for data storage systems |
EP3158455B1 (en) * | 2014-06-23 | 2020-03-18 | Liqid Inc. | Modular switched fabric for data storage systems |
US10362107B2 (en) | 2014-09-04 | 2019-07-23 | Liqid Inc. | Synchronization of storage transactions in clustered storage systems |
US9653124B2 (en) | 2014-09-04 | 2017-05-16 | Liqid Inc. | Dual-sided rackmount storage assembly |
US10198183B2 (en) | 2015-02-06 | 2019-02-05 | Liqid Inc. | Tunneling of storage operations between storage nodes |
US10156994B2 (en) | 2015-02-27 | 2018-12-18 | Western Digital Technologies, Inc. | Methods and systems to reduce SSD IO latency |
US10108422B2 (en) | 2015-04-28 | 2018-10-23 | Liqid Inc. | Multi-thread network stack buffering of data frames |
US10019388B2 (en) | 2015-04-28 | 2018-07-10 | Liqid Inc. | Enhanced initialization for data storage assemblies |
US10191691B2 (en) | 2015-04-28 | 2019-01-29 | Liqid Inc. | Front-end quality of service differentiation in storage system operations |
CN105045526A (en) * | 2015-05-08 | 2015-11-11 | 湖南国科微电子有限公司 | Method for improving transmission reliability of PCIe solid-state disk |
CN105335103B (en) * | 2015-10-22 | 2017-05-03 | 湖南国科微电子股份有限公司 | PCIE SSD array data writing method and system |
CN105204787B (en) * | 2015-10-22 | 2017-03-08 | 湖南国科微电子股份有限公司 | A kind of data of PCIE SSD array reads method, system and reading/writing method |
US10216419B2 (en) | 2015-11-19 | 2019-02-26 | HGST Netherlands B.V. | Direct interface between graphics processing unit and data storage unit |
US10206297B2 (en) * | 2015-11-23 | 2019-02-12 | Liqid Inc. | Meshed architecture rackmount storage assembly |
CN106919531B (en) * | 2015-12-25 | 2020-02-21 | 华为技术有限公司 | Interaction method and device based on nonvolatile storage bus protocol |
US10255215B2 (en) | 2016-01-29 | 2019-04-09 | Liqid Inc. | Enhanced PCIe storage device form factors |
US11880326B2 (en) | 2016-08-12 | 2024-01-23 | Liqid Inc. | Emulated telemetry interfaces for computing units |
US20180046338A1 (en) | 2016-08-12 | 2018-02-15 | Liqid Inc. | Disaggregated Fabric-Switched Computing User Interfaces |
US11294839B2 (en) | 2016-08-12 | 2022-04-05 | Liqid Inc. | Emulated telemetry interfaces for fabric-coupled computing units |
CN106844244B (en) * | 2017-01-16 | 2021-05-18 | 联想(北京)有限公司 | Device and method for realizing data interaction of solid state disk |
WO2018200761A1 (en) | 2017-04-27 | 2018-11-01 | Liqid Inc. | Pcie fabric connectivity expansion card |
US10180924B2 (en) | 2017-05-08 | 2019-01-15 | Liqid Inc. | Peer-to-peer communication for graphics processing units |
KR102637166B1 (en) | 2018-04-17 | 2024-02-16 | 삼성전자주식회사 | Network storage device storing large amount of data |
US10660228B2 (en) | 2018-08-03 | 2020-05-19 | Liqid Inc. | Peripheral storage card with offset slot alignment |
US10585827B1 (en) | 2019-02-05 | 2020-03-10 | Liqid Inc. | PCIe fabric enabled peer-to-peer communications |
EP3959860A4 (en) | 2019-04-25 | 2023-01-25 | Liqid Inc. | Multi-protocol communication fabric control |
EP3959604A4 (en) | 2019-04-25 | 2023-01-18 | Liqid Inc. | Machine templates for predetermined compute units |
US11010095B2 (en) | 2019-07-25 | 2021-05-18 | Western Digital Technologies, Inc. | Dynamic and adaptive data read request scheduling |
US11921649B1 (en) * | 2019-09-12 | 2024-03-05 | Kioxia Corporation | Multiple parallel mode flash channels with serial link |
US11442776B2 (en) | 2020-12-11 | 2022-09-13 | Liqid Inc. | Execution job compute unit composition in computing clusters |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1149664A (en) * | 1995-08-02 | 1997-05-14 | Dbt德国采矿技术有限公司 | Hydraulic shield support |
CN101763221A (en) * | 2008-12-24 | 2010-06-30 | 成都市华为赛门铁克科技有限公司 | Storing method, storing system and controller |
US20110185114A1 (en) * | 2010-01-28 | 2011-07-28 | Sony Ericsson Mobile Communications Ab | System and method for read-while-write with nand memory device |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5388237A (en) | 1991-12-30 | 1995-02-07 | Sun Microsystems, Inc. | Method of and apparatus for interleaving multiple-channel DMA operations |
US20020071321A1 (en) | 2000-11-29 | 2002-06-13 | International Business Machines Corporation | System and method of maintaining high bandwidth requirement of a data pipe from low bandwidth memories |
US20080320209A1 (en) * | 2000-01-06 | 2008-12-25 | Super Talent Electronics, Inc. | High Performance and Endurance Non-volatile Memory Based Storage Systems |
US8266367B2 (en) | 2003-12-02 | 2012-09-11 | Super Talent Electronics, Inc. | Multi-level striping and truncation channel-equalization for flash-memory system |
DE60019081D1 (en) * | 2000-01-31 | 2005-05-04 | St Microelectronics Srl | Interleaved burst memory with burst access on synchronous read cycles, where the two subordinate memory arrays are independently readable with random access during asynchronous read cycles |
US8176238B2 (en) * | 2003-12-02 | 2012-05-08 | Super Talent Electronics, Inc. | Command queuing smart storage transfer manager for striping data to raw-NAND flash modules |
US7676694B2 (en) | 2006-03-31 | 2010-03-09 | Emc Corporation | Managing system components |
US8774215B2 (en) | 2006-09-01 | 2014-07-08 | Emulex Corporation | Fibre channel over Ethernet |
US7669000B2 (en) | 2007-10-23 | 2010-02-23 | Brocade Communication Systems, Inc. | Host bus adapter with multiple hosts |
CN101149664A (en) | 2007-10-26 | 2008-03-26 | 华为技术有限公司 | Solid state hard disc and method for processing its management data |
WO2009078069A1 (en) * | 2007-12-14 | 2009-06-25 | Fujitsu Limited | Semiconductor device |
JP5272442B2 (en) | 2008-02-20 | 2013-08-28 | 日本電気株式会社 | Blade server and switch blade |
US9876735B2 (en) * | 2009-10-30 | 2018-01-23 | Iii Holdings 2, Llc | Performance and power optimized computer system architectures and methods leveraging power optimized tree fabric interconnect |
US20110113426A1 (en) | 2009-11-09 | 2011-05-12 | Hsiang-Tsung Kung | Apparatuses for switching the running of a virtual machine between multiple computer devices belonging to the same computer platform and the associated switching methods |
US8589723B2 (en) * | 2010-12-22 | 2013-11-19 | Intel Corporation | Method and apparatus to provide a high availability solid state drive |
US10089017B2 (en) | 2011-07-20 | 2018-10-02 | Futurewei Technologies, Inc. | Method and apparatus for SSD storage access |
US8954700B2 (en) | 2011-08-02 | 2015-02-10 | Cavium, Inc. | Method and apparatus for managing processing thread migration between clusters within a processor |
US8966172B2 (en) | 2011-11-15 | 2015-02-24 | Pavilion Data Systems, Inc. | Processor agnostic data storage in a PCIE based shared storage enviroment |
US20130135816A1 (en) | 2011-11-17 | 2013-05-30 | Futurewei Technologies, Inc. | Method and Apparatus for Scalable Low Latency Solid State Drive Interface |
US9829935B2 (en) | 2012-04-23 | 2017-11-28 | Microsoft Technology Licensing, Llc | SAS integration with tray and midplane server architecture |
US20130335907A1 (en) | 2012-06-13 | 2013-12-19 | Microsoft Corporation | Tray and chassis blade server architecture |
-
2012
- 2012-04-30 US US13/460,695 patent/US9767058B2/en not_active Expired - Fee Related
- 2012-11-19 EP EP12848997.8A patent/EP2780791A4/en not_active Withdrawn
- 2012-11-19 CN CN201280053366.4A patent/CN103907088A/en active Pending
- 2012-11-19 WO PCT/CN2012/084823 patent/WO2013071892A1/en active Application Filing
-
2017
- 2017-08-23 US US15/683,903 patent/US20170371825A1/en not_active Abandoned
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1149664A (en) * | 1995-08-02 | 1997-05-14 | Dbt德国采矿技术有限公司 | Hydraulic shield support |
CN101763221A (en) * | 2008-12-24 | 2010-06-30 | 成都市华为赛门铁克科技有限公司 | Storing method, storing system and controller |
US20110264833A1 (en) | 2008-12-24 | 2011-10-27 | Chengdu Huawei Symantec Technologies Co., Ltd. | Storage method, storage system, and controller |
US20110185114A1 (en) * | 2010-01-28 | 2011-07-28 | Sony Ericsson Mobile Communications Ab | System and method for read-while-write with nand memory device |
Non-Patent Citations (1)
Title |
---|
See also references of EP2780791A4 * |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2018125433A1 (en) * | 2016-12-28 | 2018-07-05 | Intel Corporation | Method, apparatus and system for handling non-posted memory write transactions in a fabric |
US10846126B2 (en) | 2016-12-28 | 2020-11-24 | Intel Corporation | Method, apparatus and system for handling non-posted memory write transactions in a fabric |
US11372674B2 (en) | 2016-12-28 | 2022-06-28 | Intel Corporation | Method, apparatus and system for handling non-posted memory write transactions in a fabric |
Also Published As
Publication number | Publication date |
---|---|
US20130132643A1 (en) | 2013-05-23 |
EP2780791A1 (en) | 2014-09-24 |
US20170371825A1 (en) | 2017-12-28 |
US9767058B2 (en) | 2017-09-19 |
EP2780791A4 (en) | 2014-11-19 |
CN103907088A (en) | 2014-07-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20170371825A1 (en) | Method and Apparatus for Scalable Low Latency Solid State Drive Interface | |
US20130135816A1 (en) | Method and Apparatus for Scalable Low Latency Solid State Drive Interface | |
US9298648B2 (en) | Method and system for I/O flow management using RAID controller with DMA capabilitiy to directly send data to PCI-E devices connected to PCI-E switch | |
CN109582614B (en) | NVM EXPRESS controller for remote memory access | |
US9569209B2 (en) | Method for non-volatile data storage and retrieval | |
KR101491484B1 (en) | Scalable storage devices | |
TWI452469B (en) | Pcie mass storage device, system having the same, and method for operating the same | |
US20160259568A1 (en) | Method and apparatus for storing data | |
US7984252B2 (en) | Storage controllers with dynamic WWN storage modules and methods for managing data and connections between a host and a storage device | |
TW201720123A (en) | NVM express controller for remote access of memory and I/O over ethernet-type networks | |
CN111417935A (en) | Automatic data chip address sequencer for address/command chip synchronization for distributed buffer memory systems | |
US7089379B1 (en) | Large high bandwidth memory system | |
US11853162B2 (en) | Controller and storage device | |
US8032674B2 (en) | System and method for controlling buffer memory overflow and underflow conditions in storage controllers | |
US20080222500A1 (en) | Data relay apparatus, data relay method and data relay integrated circuit | |
WO2006019770A2 (en) | System and method for transmitting data in storage controllers | |
US20230280917A1 (en) | Storage system and method of operating the same | |
KR20160005646A (en) | Electronic system with memory network mechanism and method of operation thereof | |
US8856404B2 (en) | Primitive group data encoding in a data storage fabric | |
US11733872B2 (en) | Storage device and system of controlling operation through flow control monitoring | |
CN114518838A (en) | Efficient PCIe utilization through PCIe TLP merging |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 12848997 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2012848997 Country of ref document: EP |