WO2013037300A1 - 并行模拟多个处理器的方法及系统、调度器 - Google Patents

并行模拟多个处理器的方法及系统、调度器 Download PDF

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Publication number
WO2013037300A1
WO2013037300A1 PCT/CN2012/081353 CN2012081353W WO2013037300A1 WO 2013037300 A1 WO2013037300 A1 WO 2013037300A1 CN 2012081353 W CN2012081353 W CN 2012081353W WO 2013037300 A1 WO2013037300 A1 WO 2013037300A1
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Prior art keywords
scheduler
simulated
processor
interface
debugged
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PCT/CN2012/081353
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English (en)
French (fr)
Inventor
叶寒栋
曹炯
叶笑春
王达
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP12832221.1A priority Critical patent/EP2672388B1/en
Publication of WO2013037300A1 publication Critical patent/WO2013037300A1/zh
Priority to US14/142,567 priority patent/US9703905B2/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation

Definitions

  • the SIMICS Simulator is a high performance system simulator that emulates single processor systems and multiprocessor systems.
  • the SIMICS simulator uses a single processor scheduling method to schedule, that is, each processor is scheduled to execute corresponding instructions to implement serial simulation of multiple processors.
  • each processor is scheduled to execute corresponding instructions to implement serial simulation of multiple processors.
  • it is impossible to implement parallel simulation of multiple processors, resulting in a reduction in simulation efficiency, and the prior art cannot perform debugging when simulating multiple processors in parallel.
  • Embodiments of the present invention provide a method and system for simulating multiple processors in parallel, and a scheduler, which are used to improve simulation efficiency and implement debugging when multiple processors are simulated in parallel.
  • a method for simulating multiple processors in parallel including: a scheduler mapping debug interface information of a processor to be simulated that needs to be debugged to the scheduler Upper
  • the scheduler creates at least one slave thread by using a main thread, and determines a processor to be simulated corresponding to the master thread and the at least one slave thread, to obtain a determined corresponding processor to be simulated, where the master
  • the processor to be simulated corresponding to the thread includes the processor to be simulated that needs to be debugged; the scheduler uses the main thread and the at least one slave thread to invoke the determined corresponding to-before through the first running interface.
  • the simulated processor executes the corresponding instruction, and uses the main thread to debug the processor to be simulated that needs to be debugged through the debugging interface of the processor to be simulated that needs to be debugged, and the first operating interface passes through the The determined corresponding processor to be simulated registers with the scheduler, and the debug interface information points to the debug interface.
  • Another aspect provides a scheduler, including:
  • mapping unit configured to map debug interface information of a processor to be simulated that needs to be debugged to the scheduler
  • a creating unit configured to create at least one slave thread by using a main thread, and determine a processor to be simulated corresponding to the main thread and the at least one slave thread, to obtain a determined corresponding processor to be simulated, where
  • the processor to be simulated corresponding to the main thread includes the processor to be simulated that needs to be debugged;
  • a calling unit configured to invoke, by using the first thread and the at least one slave thread created by the creating unit, a corresponding processor to be simulated determined by the creating unit by using a first running interface, and executing a corresponding instruction, and utilizing
  • the main thread is configured to debug the processor to be simulated that needs to be debugged by using the debug interface of the processor to be simulated that needs to be debugged, and the first operating interface passes the determined corresponding processor to be simulated
  • the scheduler registers, and the debug interface information mapped by the mapping unit points to the debug interface.
  • the scheduler uses the main thread to create at least one slave thread, and determines the processor to be simulated corresponding to the master thread and the at least one slave thread, so that the scheduler can utilize the master thread and the at least one slave. Threading, by using the corresponding first to be simulated processor to be determined by the processor to be simulated, calling the corresponding processor to be simulated to execute the corresponding instruction, because each time the main thread and at least one can be utilized
  • the processor to be simulated is scheduled from the thread, so that multiple processors can be simulated in parallel, which avoids the problem that the parallel simulation of multiple processors cannot be realized due to the scheduling of one processor to be simulated each time in the prior art.
  • the simulation efficiency is improved; at the same time, the processor resources of the host machine where the scheduler is located can be fully utilized, thereby improving resource utilization efficiency.
  • the debug interface information of the processor to be simulated that needs to be debugged is mapped to the scheduler by the scheduler, so that the scheduler can utilize the main thread, and the debug of the processor to be simulated that needs to be debugged by the debug interface information
  • the interface debugs the processor to be simulated that needs to be debugged, and realizes debugging when simulating multiple processors in parallel.
  • FIG. 1 is a schematic flowchart of a method for simulating multiple processors in parallel according to an embodiment of the present invention
  • FIG. 2 is a schematic flow chart of a method for simulating multiple processors in parallel according to another embodiment of the present invention
  • FIG. 3 is a schematic diagram of a system architecture applicable to the embodiment corresponding to FIG. 2;
  • FIG. 4 is a schematic structural diagram of a scheduler according to another embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of a scheduler according to another embodiment of the present disclosure.
  • FIG. 6 is a schematic structural diagram of a scheduler according to another embodiment of the present invention.
  • FIG. 7 is a schematic structural diagram of a system for simulating multiple processors in parallel according to another embodiment of the present invention.
  • FIG. 8 is a schematic structural diagram of a system for simulating multiple processors in parallel according to another embodiment of the present invention.
  • FIG. 9 is a schematic structural diagram of a system for simulating multiple processors in parallel according to another embodiment of the present invention.
  • FIG. 10 is a schematic structural diagram of a system for simulating multiple processors in parallel according to another embodiment of the present invention. detailed description
  • FIG. 1 is a schematic flowchart of a method for simulating multiple processors in parallel according to an embodiment of the present invention. As shown in FIG. 1, the method for simulating multiple processors in parallel according to this embodiment may include:
  • the scheduler maps debug interface information of the processor to be simulated that needs to be debugged to the scheduler.
  • the scheduler uses the main thread to create at least one slave thread, and determines the main thread and the at least one slave thread corresponding to the processor to be simulated, to obtain a determined corresponding processor to be simulated;
  • the processor to be simulated corresponding to the main thread includes the processor to be simulated that needs to be debugged.
  • processors from the thread can be equal to the number of processors of the host where the scheduler is located, so that each thread corresponds to a host processor.
  • the scheduler may create at least one slave thread by using the main thread according to the configuration file, and determine the processor to be simulated corresponding to the master thread and the at least one slave thread.
  • the configuration file may include, but is not limited to, the number of created threads, the number information of the processor to be simulated that needs to be debugged, and the mapping relationship between the thread (main thread or slave thread) and the processor to be simulated.
  • the above-mentioned scheduler uses the above-mentioned main thread and the at least one slave thread to call the corresponding processor to be simulated to execute the corresponding instruction through the first execution interface (execution interface), and uses the above-mentioned main thread to pass the above-mentioned needs.
  • Debugging the debug interface of the processor to be simulated Debugs the processor to be simulated that needs to be debugged.
  • the first operating interface is registered with the debugger by the corresponding processor to be simulated, and the debug interface information is directed to the debug interface.
  • each thread can correspond to a processor to be simulated, or can also correspond The processor to be simulated is not limited in this embodiment. However, the processor to be simulated corresponding to the main thread must include a processor to be simulated that needs to be debugged. If each thread corresponds to a plurality of processors to be simulated, in 102, each time the scheduler executes a corresponding instruction through the main thread and the processor scheduled by the thread to be simulated, one of each thread may be scheduled in parallel first. The processor to be simulated, and then serially schedule other processors in the thread to be simulated within each thread. Instruction, an instruction to access the same memory or different memory; an instruction to access a peripheral, an instruction to access the same peripheral or a different peripheral.
  • the foregoing instruction may also be an atomic instruction.
  • the scheduler may specifically use a mutex operation, and invoke the corresponding determined processor to be simulated to execute a corresponding instruction.
  • the scheduler may further use the foregoing main thread and the at least one slave thread to deliver a period parameter to the determined corresponding processor to be simulated by using a first cycle interface.
  • the corresponding main processor and the at least one slave thread synchronously call the corresponding processor to be simulated, thereby ensuring the scheduling consistency between the processors to be simulated.
  • the first periodic interface is registered with the scheduler by using the determined corresponding processor to be simulated.
  • the execution subject scheduler of 101 to 103 above may be a scheduling unit in the SIMICS simulator. Accordingly, the scheduler can assign the address of the debug interface of the processor to be simulated that needs to be debugged to the debug interface pointer of the scheduler. Specifically, it may include, but is not limited to, at least one of the following cases:
  • the scheduler assigns the address of the step interface of the processor to be simulated that needs to be debugged to the single-step running interface pointer of the scheduler;
  • the scheduler assigns the address of the breakpoint query interface of the processor to be simulated that needs to be debugged to the breakpoint query interface pointer of the scheduler;
  • the scheduler assigns the address of the breakpoint trigger interface of the processor to be simulated that needs to be debugged to the physical memory trigger interface pointer of the scheduler.
  • the scheduler may further further configure a breakpoint change interface of the processor to be simulated that needs to be debugged.
  • the address is assigned to the scheduler's breakpoint control interface pointer, so that the scheduler uses the breakpoint control interface pointer to call the processor to be simulated that needs to be debugged to notify the breakpoint update operation, for example: setting a breakpoint, canceling the break Point and so on.
  • the scheduler may further assign the address of the scheduler's breakpoint query interface to the breakpoint query interface pointer of the processor to be simulated that needs to be debugged, so as to enable The debugged processor to be simulated uses the breakpoint query interface pointer to call the scheduler to obtain breakpoint information, such as: breakpoint start address, breakpoint termination address, breakpoint trigger attribute, and so on.
  • the scheduler may further assign the address of the scheduler's breakpoint trigger interface to the processor to be simulated that needs to be debugged.
  • the point triggers the interface pointer so that the processor to be simulated that needs to be debugged uses the breakpoint to trigger the interface pointer, and the scheduler is called to trigger the scheduler to stop calling the processor to be simulated that needs to be debugged.
  • the processor to be simulated that needs to be debugged obtains the breakpoint information, in each operation cycle, it can further check whether the current running state meets the condition corresponding to the breakpoint information. If not, the debug to be simulated is required.
  • the processor continues to run for the next cycle; if it is, the processor to be simulated that needs to be debugged uses the breakpoint to trigger the interface pointer and invokes the scheduler.
  • the execution subject scheduler of the foregoing 101-103 may also be an independently set control unit.
  • the scheduler can assign the address of the debug interface of the processor to be simulated that needs to be debugged to the debug interface pointer of the scheduler, and assign the debug interface pointer of the scheduler to the debug interface pointer of the SIMICS simulator.
  • the method may include, but is not limited to, at least one of the following situations: the scheduler assigns an address of the single-step running interface of the processor to be simulated that needs to be debugged to the single-step running interface pointer of the scheduler, and the scheduling The single-step interface pointer of the device is assigned to the single-step interface pointer of the SIMICS simulator;
  • the scheduler assigns the address of the state query interface of the processor to be simulated that needs to be debugged to the state query interface pointer of the scheduler, and assigns the state query interface pointer of the scheduler to the state query interface pointer of the SIMICS simulator;
  • the scheduler assigns the address of the state setting interface of the processor to be simulated that needs to be debugged to the state setting interface pointer of the scheduler, and assigns the state set interface pointer of the scheduler to the state setting interface pointer of the SIMICS simulator.
  • the scheduler may further assign the address of the breakpoint control interface of the processor to be simulated that needs to be debugged to the The scheduler's breakpoint controls the interface pointer, and assigns the scheduler's breakpoint control interface pointer to the SIMICS simulator's breakpoint control interface pointer, so that the SIMICS simulator uses the breakpoint control interface pointer to call the simulation to be simulated.
  • the processor to notify the breakpoint update operation, for example: set breakpoints, cancel breakpoints, and so on.
  • the scheduler may further assign the address of the breakpoint query interface of the SIMICS simulator to the scheduler's breakpoint query interface pointer, so that the scheduler uses the breakpoint query interface pointer to invoke SIMICS. Simulator, to obtain breakpoint information, for example: breakpoint start address, Breakpoint termination address, breakpoint trigger attribute, etc.
  • the scheduler may further assign the address of the breakpoint trigger interface of the SIMICS simulator to the breakpoint trigger interface pointer of the scheduler, so that the scheduler utilizes The breakpoint triggers the interface pointer and calls the SIMICS simulator to trigger the scheduler to stop calling the processor to be simulated that needs to be debugged.
  • the scheduler obtains the breakpoint information, in each operation cycle, it is further possible to further check whether the current running state of the processor to be simulated that needs to be debugged meets the condition corresponding to the breakpoint information, and if it does not, it needs to be debugged.
  • the processor to be simulated continues to run for the next cycle; if it is, the scheduler uses the breakpoint to trigger the interface pointer and invokes the SIMICS simulator.
  • the scheduler may further assign the address of the breakpoint query interface of the SIMICS simulator to the breakpoint query interface pointer of the scheduler, and assign the scheduler's breakpoint query interface pointer to the need Debugging the breakpoint query interface pointer of the processor to be simulated, so that the processor to be simulated that needs to be debugged uses the breakpoint query interface pointer, and calls the SIMICS simulator to obtain breakpoint information, for example: breakpoint start address, Breakpoint termination address, breakpoint trigger attribute, etc.
  • the scheduler may further assign the address of the breakpoint trigger interface of the SIMICS simulator to the breakpoint trigger interface pointer of the scheduler, and the scheduler
  • the breakpoint trigger interface pointer is assigned to the breakpoint trigger interface pointer of the processor to be simulated that needs to be debugged, so that the processor to be simulated that needs to be debugged uses the breakpoint to trigger the interface pointer, and the SIMICS simulator is called to trigger the SIMICS simulator to stop. Call the processor to be simulated that needs to be debugged.
  • the processor to be simulated that needs to be debugged can further check whether the current running state meets the condition corresponding to the breakpoint information. If not, the debug to be simulated is required. The processor continues to run for the next cycle; if it does, The processor to be simulated that needs to be debugged uses the breakpoint to trigger the interface pointer and calls the SIMICS simulator. Further, the scheduler may further register a corresponding second running interface with the scheduling unit in the SIMICS simulator, so that the scheduling unit schedules the scheduler to create at least one slave thread by using the main thread by using the second running interface.
  • the scheduler may further register a corresponding second periodic interface with the scheduling unit in the SIMICS simulator, so that the scheduling unit uses the main thread to send a periodic parameter to the scheduler through the second periodic interface.
  • the scheduler uses the foregoing main thread and the at least one slave thread to deliver the periodic parameter to the determined corresponding processor to be simulated through the first periodic interface, so as to control the scheduler to utilize the main thread and the at least A processor that is to be simulated is called from a thread synchronously, and the first periodic interface registers with the scheduler by using the corresponding processor to be simulated determined above.
  • the scheduler uses the main thread to create at least one slave thread, and determines the processor to be simulated corresponding to the master thread and the at least one slave thread, so that the scheduler can utilize the master thread and the at least one slave thread. Determining, by using the above-mentioned determined first processor to be simulated to the first operation interface registered by the scheduler, the corresponding processor to be simulated to execute the corresponding instruction, because each time the main thread and the at least one slave can be utilized
  • the thread schedules the processor to be simulated, so that multiple processors can be simulated in parallel, which avoids the problem that the parallel simulation of multiple processors cannot be realized due to the scheduling of one processor to be simulated each time in the prior art, thereby improving The simulation efficiency; at the same time, the processor resources of the host machine where the scheduler is located can be fully utilized, thereby improving resource utilization efficiency.
  • the debug interface information of the processor to be simulated that needs to be debugged is mapped to the scheduler by the scheduler, so that the scheduler can utilize the main thread, and the debug of the processor to be simulated that needs to be debugged by the debug interface information
  • the interface debugs the processor to be simulated that needs to be debugged, and realizes debugging when parallelizing multiple processors.
  • an execution subject controller of 101 to 103 is taken as an independently set controller unit as an example.
  • 2 is a schematic flowchart of a method for simulating multiple processors in parallel according to another embodiment of the present invention.
  • the system architecture applicable to this embodiment may be as shown in FIG. 3 .
  • the method for simulating multiple processors in parallel in this embodiment may include:
  • the control unit creates a debug object, the data structure of the debug object is consistent with the data structure of the processor to be simulated, and assigns the address of the debug interface of the processor to be simulated that needs to be debugged to the debug object created by the control unit
  • the debug interface pointer and the debug interface pointer of the debug object created by the control unit are assigned to the debug interface pointer of the SIMICS simulator;
  • the debug interface may include, but is not limited to, at least one of a single step operation interface, a status query interface, and a status setting interface.
  • control unit may further assign the address of the breakpoint control interface of the processor to be simulated that needs to be debugged to the breakpoint control interface pointer of the scheduler, and assign the breakpoint control interface pointer of the scheduler to the scheduler
  • the breakpoint of the SIMICS simulator controls the interface pointer so that the SIMICS simulator uses the breakpoint control interface pointer to call the processor to be simulated that needs to be debugged to notify the breakpoint update operation, for example: setting a breakpoint, canceling a breakpoint, and so on.
  • control unit may further assign the address of the breakpoint query interface of the SIMICS simulator to the breakpoint query interface pointer of the control unit, and assign the breakpoint query interface pointer of the control unit to the process to be simulated that needs to be debugged.
  • the breakpoint of the device queries the interface pointer so that the processor to be simulated that needs to be debugged uses the breakpoint query interface pointer to call the SIMICS simulator to obtain breakpoint information, such as: breakpoint start address, breakpoint termination address, break Point trigger properties, etc.
  • control unit can further activate the address of the breakpoint trigger interface of the SIMICS simulator
  • the breakpoint assigned to the control unit triggers the interface pointer, and assigns the breakpoint trigger interface pointer of the control unit to the breakpoint trigger interface pointer of the processor to be simulated that needs to be debugged, so that the processor to be simulated that needs to be debugged utilizes the break
  • the point triggers the interface pointer and calls the SIMICS simulator to trigger the SIMICS simulator to stop calling the processor to be simulated that needs to be debugged.
  • the processor to be simulated that needs to be debugged obtains the breakpoint information, in each operation cycle, it can further check whether the current running state meets the condition corresponding to the breakpoint information. If not, the debug to be simulated is required. The processor continues to run for the next cycle; if it is, the processor to be simulated that needs to be debugged uses the breakpoint to trigger the interface pointer and invokes the SIMICS simulator.
  • the control unit registers a running interface and a periodic interface corresponding to the control unit with a scheduling unit in the SIMICS simulator.
  • the processor to be simulated registers an operation interface and a periodic interface corresponding to the processor to be simulated to the control unit.
  • the control unit creates at least one slave thread by using a main thread according to the configuration file, and determines the processor to be simulated corresponding to the main thread and the at least one slave thread, and applies for memory for the processor to be simulated on the host machine. ;
  • the main thread corresponds to the processor 0 to be simulated and the processor 6 to be simulated, wherein the processor 0 to be simulated is a processor to be simulated that needs to be debugged, that is, it can be recorded as a processor to be simulated that needs to be debugged. ;
  • From thread 1 corresponds to the processor 1 to be simulated and the processor 3 to be simulated;
  • the slave thread 3 corresponds to the processor 5 to be simulated and the processor 7 to be simulated.
  • control unit can apply for the same internal processor on the host machine to be simulated.
  • the memory is used to simulate multiple processors to be simulated to access the same memory, or to apply for different memory for the processor to be simulated on the host machine to simulate multiple processors to be simulated to access different memory. .
  • the scheduling unit uses the main thread to invoke a running interface registered by the control unit.
  • the control unit uses the main thread and the created at least one slave thread to call the running interface registered by the processor to be simulated, and invokes the corresponding processor to be simulated to execute the corresponding instruction.
  • control unit utilizes the main thread, invokes the operation interface registered by the processor 0 to be simulated that needs to be debugged, and then calls the operation interface registered by the processor 6 to be simulated;
  • the control unit uses the running interface registered by the processor 1 to be simulated from the thread 1, and then calls the running interface registered by the processor 3 to be simulated;
  • the control unit utilizes the running interface registered from the thread 2 to call the processor 2 to be simulated, and then invokes the running interface registered by the processor 4 to be simulated;
  • the control unit utilizes the running interface registered from the thread 3 to call the processor 5 to be simulated, and then calls the running interface registered by the processor 7 to be simulated.
  • the processor to be simulated that needs to be debugged checks whether the current running state meets the condition corresponding to the breakpoint information, and if not, needs The debugged processor to be simulated continues to run for the next cycle; if it is, the processor to be simulated that needs to be debugged uses the breakpoint to trigger the interface pointer, and the SIMICS simulator is called to trigger the SIMICS simulator to stop calling the simulation to be debugged.
  • control unit calls in 206 that is not the processor to be simulated that needs to be debugged, the process ends.
  • the scheduling unit of the SIMICS simulator uses a single step according to the operator's single step execution instruction.
  • the control unit is invoked by running at least one of the interface pointer, the state query pointer, and the state setting pointer; 209.
  • the control unit uses the above-mentioned main thread to debug the processor to be simulated that needs to be debugged by using the corresponding interface pointer.
  • the SIMICS simulator can use the breakpoint control interface pointer to call the processor to be simulated that needs to be debugged to notify the breakpoint setting operation.
  • the processor to be simulated that needs to be debugged uses the breakpoint query interface pointer to call the SIMICS simulator to obtain breakpoint information, such as: breakpoint start address, breakpoint termination address, breakpoint trigger attribute, and the like.
  • breakpoint information such as: breakpoint start address, breakpoint termination address, breakpoint trigger attribute, and the like.
  • the scheduling unit of the SIMICS simulator debugs the processor to be simulated that needs to be debugged according to the operator's single-step execution instruction, using at least one of the single-step operation interface pointer, the state query pointer, and the state setting pointer.
  • the scheduling unit may further utilize the main thread to invoke a periodic interface registered by the control unit to deliver a periodic parameter to the control unit (for example, a processor switching time (cpu-switch-time) parameter, Instructing the execution unit to specify the number of execution instructions, etc., so that the control unit further utilizes the main thread and the created at least one slave thread to invoke the periodic interface registered by the processor to be simulated, to issue a time advancement to the processor to be simulated.
  • the target value is used to control the synchronization between the main thread and the at least one processor to be simulated corresponding to the above-mentioned thread, for example: after the execution of the specified number of instructions from the processor on the thread, the main thread is notified. Control unit and go to sleep; the control unit on the main thread receives all notifications from the processor on the thread to be simulated After that, exit the running interface and wait for re-execution 205.
  • the at least one slave thread is created by using the master thread, and the master thread and the at least one slave thread corresponding to the processor to be simulated are determined, so that the control unit can Using the above-mentioned main thread and the at least one slave thread, through the first operation interface registered by the processor to be simulated to the control unit, calling the corresponding processor to be simulated to execute the corresponding instruction, because each time the main command can be utilized
  • the thread and the at least one slave thread schedule the processor to be simulated, so that multiple processors can be simulated in parallel, and the parallel simulation of multiple processors cannot be realized due to the scheduling of one processor to be simulated each time in the prior art.
  • the problem is to improve the simulation efficiency; at the same time, the processor resources of the host machine where the scheduler is located can be fully utilized, thereby improving the resource utilization efficiency.
  • the debugging interface information of the processor to be simulated that needs to be debugged is mapped to the debugging object created by the control unit by the control unit, so that the control unit can utilize the main thread, and the debugging interface to be simulated by the debugging interface information
  • the debug interface of the processor debugs the processor to be debugged that needs to be debugged, and realizes debugging when simulating multiple processors in parallel.
  • FIG. 4 is a schematic structural diagram of a scheduler according to another embodiment of the present invention, as shown in FIG.
  • the scheduler of the embodiment may include a mapping unit 41, a creating unit 42, and a calling unit 43.
  • the mapping unit 41 is configured to map the debug interface information of the processor to be simulated that needs to be debugged to the scheduler;
  • the creating unit 42 is configured to create at least one slave thread by using the main thread, and determine the main thread and the at least one And determining, by the processor corresponding to the thread, the corresponding processor to be simulated, where the processor to be simulated corresponding to the main thread includes the processor to be simulated that needs to be debugged;
  • the calling unit 43 is configured to utilize The above-mentioned main thread and the at least one slave thread created by the above-mentioned creating unit call the corresponding processor to be simulated determined by the above-mentioned creating unit through the first running interface to execute a corresponding instruction, and use the above-mentioned main thread to
  • the first running interface is registered with the debugger by the corresponding processor to be simulated, and the debug interface information mapped by the mapping unit points to the debug interface.
  • the invoking unit 43 in this embodiment invokes the corresponding instruction to be cached determined by the above-mentioned creating unit, and is used to access an instruction of the same memory or different memory; accessing a peripheral instruction for accessing the same peripheral or Instructions for different peripherals.
  • the invoking unit 43 in this embodiment invokes the corresponding processor to be simulated determined by the above-mentioned creating unit to execute the corresponding instruction, and may also be an atomic instruction, and the calling unit 43 may specifically use the mutex operation to invoke the above creation.
  • the corresponding processor to be simulated determined by the unit executes the corresponding instruction.
  • the calling unit 43 may further utilize the foregoing main thread and the at least one slave line. And sending, by the first cycle interface, a periodic parameter to the corresponding processor to be simulated, to control the scheduler to use the foregoing main thread and the at least one slave thread to synchronously invoke corresponding processing to be simulated.
  • the first periodic interface is registered with the scheduler by using the determined corresponding processor to be simulated.
  • the scheduler provided in this embodiment may be a scheduling unit in the SIMICS simulator.
  • the mapping unit 41 in this embodiment may specifically assign the address of the debugging interface of the processor to be simulated that needs to be debugged to the debug interface pointer of the scheduler.
  • mapping unit 41 may include, but is not limited to, at least one of the following subunits:
  • a first mapping subunit 51 configured to assign an address of the single-step running interface of the processor to be simulated that needs to be debugged to the single-step running interface pointer of the scheduler;
  • a second mapping sub-unit 52 configured to assign an address of a state query interface of the processor to be simulated that needs to be debugged to a state query interface pointer of the scheduler;
  • the third mapping subunit 53 is configured to assign an address of the state setting interface of the processor to be simulated that needs to be debugged to the state setting interface pointer of the scheduler.
  • mapping sub-unit 51 the second mapping sub-unit 52, and the third mapping sub-unit 53 are included in FIG. 5, and in an optional embodiment, only the foregoing may be included. Any one or two of the three subunits.
  • the mapping unit 41 in this embodiment may further include a fourth mapping subunit 61, configured to assign an address of a breakpoint control interface of the processor to be simulated that needs to be debugged to the The breakpoint control interface pointer of the scheduler.
  • a fourth mapping subunit 61 configured to assign an address of a breakpoint control interface of the processor to be simulated that needs to be debugged to the The breakpoint control interface pointer of the scheduler.
  • mapping unit 41 in this embodiment may be further used to disconnect the scheduler.
  • the address of the point query interface is assigned to the breakpoint query interface pointer of the processor to be simulated that needs to be debugged; and the address of the breakpoint trigger interface of the scheduler is assigned to the breakpoint trigger interface of the processor to be simulated that needs to be debugged pointer.
  • the scheduler provided in this embodiment may also be an independently set control unit.
  • the mapping unit 41 in this embodiment may specifically assign the address of the debug interface of the processor to be simulated that needs to be debugged to the debug interface pointer of the scheduler, and assign the debug interface pointer of the scheduler to the SIMICS emulation. Debug interface pointer.
  • mapping unit 41 may include, but is not limited to, at least one of the following subunits:
  • a fifth mapping sub-unit 71 configured to assign an address of the single-step running interface of the processor to be simulated that needs to be debugged to the single-step running interface pointer of the scheduler, and assign the single-step running interface pointer of the scheduler to Single-step operation interface pointer of SIMICS simulator;
  • the sixth mapping sub-unit 72 is configured to assign an address of the state query interface of the processor to be simulated that needs to be debugged to the state query interface pointer of the scheduler, and assign the state query interface pointer of the scheduler to the SIMICS simulator.
  • Status query interface pointer ;
  • a seventh mapping sub-unit 73 configured to assign an address of a state setting interface of the processor to be simulated that needs to be debugged to a state setting interface pointer of the scheduler, and assign a state setting interface pointer of the scheduler to the SIMICS simulator The state sets the interface pointer.
  • mapping sub-unit 71 the sixth mapping sub-unit 72, and the seventh mapping sub-unit 73 are simultaneously included in FIG. 7. In an optional embodiment, only the foregoing may be included. Any one or two of the three subunits.
  • the mapping unit 41 in this embodiment may further include an eighth mapping sub-unit 81, where the breakpoint control interface of the processor to be simulated that needs to be debugged is used.
  • the breakpoint control interface pointer assigned to the scheduler, and the breakpoint control interface pointer of the scheduler is assigned to the breakpoint control interface pointer of the SIMICS simulator.
  • the mapping unit 41 in this embodiment may further assign the address of the breakpoint query interface of the SIMICS simulator to the breakpoint query interface pointer of the scheduler; and the breakpoint trigger interface of the SIMICS simulator
  • the breakpoint assigned to the scheduler triggers the interface pointer, so that the scheduler checks whether the running state of the processor to be simulated that needs to be debugged meets the condition corresponding to the breakpoint information.
  • the mapping unit 41 in this embodiment may further assign a breakpoint query interface pointer of the scheduler to a breakpoint query interface pointer of a processor to be simulated that needs to be debugged; and
  • the breakpoint trigger interface pointer is assigned to the scheduler's breakpoint trigger interface pointer, so that the processor to be simulated that needs to be debugged checks whether its running state meets the condition corresponding to the breakpoint information.
  • the scheduler provided in this embodiment may further include a registration unit 91, configured to register a corresponding second operation interface with the scheduling unit in the SIMICS simulator, so that the scheduling unit passes the foregoing
  • the second run interface scheduler uses the main thread to create at least one slave thread.
  • the registration unit 91 may further register a corresponding second periodic interface with the scheduling unit in the SIMICS simulator, so that the scheduling unit uses the primary thread to deliver periodic parameters to the scheduler through the second periodic interface.
  • the calling unit by using the foregoing main thread and the at least one slave thread, to issue the cycle parameter to the determined corresponding processor to be simulated through the first periodic interface, to control the calling unit to utilize the main thread and the foregoing At least one of the corresponding processors to be simulated is called synchronously from the thread.
  • the first periodic interface registers with the scheduler by using the determined corresponding processor to be simulated.
  • the scheduler creates at least one slave thread by using the main thread by creating the unit, and Determining, by the main thread, the processor to be simulated corresponding to the at least one slave thread, so that the calling unit can use the foregoing main thread and the at least one slave thread to pass the corresponding processor to be simulated determined by the creating unit to the scheduler Registering the first running interface, calling the corresponding processor to be simulated determined by the above creating unit to execute the corresponding instruction, since each time the main thread and the at least one slave thread can be used to schedule the processor to be simulated, the parallel simulation can be realized.
  • the processor avoids the problem that the parallel simulation of multiple processors cannot be realized due to the scheduling of one processor to be simulated each time in the prior art, thereby improving the simulation efficiency; and fully utilizing the host machine of the scheduler Processor resources, thereby improving resource utilization efficiency.
  • the debugging interface information of the processor to be simulated that needs to be debugged is mapped to the debugging object created by the control unit by the mapping unit, so that the calling unit can utilize the main thread, and the debugging interface needs to be debugged by the debugging interface information.
  • the debug interface of the processor debugs the processor to be debugged that needs to be debugged, and realizes debugging when simulating multiple processors in parallel.
  • FIG. 10 is a schematic structural diagram of a system for simulating multiple processors in parallel according to another embodiment of the present invention.
  • the system for simulating multiple processors in parallel in this embodiment may include a processor 1001 to be simulated and Scheduler 1002.
  • the scheduler may be the scheduler provided in any one of the embodiments corresponding to FIG. 4, FIG. 5, FIG. 6, FIG. 7, FIG. 8 and FIG. 9.
  • FIG. 10 refers to related content in the corresponding embodiment. I won't go into details here.
  • the scheduler uses the main thread to create at least one slave thread, and determines the processor to be simulated corresponding to the master thread and the at least one slave thread, so that the scheduler can utilize the master thread and the at least one slave thread.
  • the corresponding first processor that is to be simulated by the above-mentioned scheduler to register with the scheduler, and the corresponding processor to be simulated determined by the scheduler is executed to execute a corresponding instruction, because the main thread can be utilized each time.
  • the processor can realize the parallel simulation of multiple processors, and avoids the problem that the parallel simulation of multiple processors cannot be realized due to the scheduling of one processor to be simulated each time in the prior art, thereby improving the simulation efficiency; At the same time, the processor resources of the host machine where the scheduler is located can be fully utilized, thereby improving resource utilization efficiency.
  • the debug interface information of the processor to be simulated that needs to be debugged is mapped to the scheduler by the scheduler, so that the scheduler can utilize the main thread, and the debug of the processor to be simulated that needs to be debugged by the debug interface information
  • the interface debugs the processor to be simulated that needs to be debugged, and realizes debugging when simulating multiple processors in parallel.
  • the disclosed systems, devices, and methods may be implemented in other ways.
  • the device embodiments described above are merely illustrative.
  • the division of the unit is only a logical function division.
  • there may be another division manner for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not executed.
  • the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be electrical, mechanical or otherwise.
  • the components displayed by the unit may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the solution of the embodiment.
  • each functional unit in various embodiments of the present invention may be integrated in one processing unit. It is also possible that each unit physically exists alone, or two or more units may be integrated in one unit.
  • the above integrated unit can be implemented in the form of hardware or in the form of hardware plus software functional units.
  • the above-described integrated unit implemented in the form of a software functional unit can be stored in a computer readable storage medium.
  • the above software functional units are stored in a storage medium and include a number of instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to perform part of the steps of the method of the various embodiments of the present invention.
  • the foregoing storage medium includes: a USB flash drive, a removable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, and the like, which can store program codes. Medium.

Abstract

本发明提供一种并行模拟多个处理器的方法及系统、调度器，本实施例能够实现在并行模拟多个处理器中，通过调度器将需要调试的待模拟的处理器的调试接口信息映射到该调度器上，使得调度器能够利用主线程，通过该调试接口信息指向的需要调试的待模拟的处理器的调试接口调试该需要调试的待模拟的处理器，实现了并行模拟多个处理器时的调试。

Description

并行模拟多个处理器的方法及系统、 调度器 本申请要求于 2011 年 9 月 13 日提交中国专利局、 申请号为 201110269208.X, 发明名称为 "并行模拟多个处理器的方法及系统、 调度器" 的中国专利申请优先权， 上述专利的全部内容通过引用结合在本申请中。 技术领域 本发明实施例涉及模拟技术，尤其涉及一种并行模拟多个处理器的方法及 系统、 调度器。
背景技术
SIMICS模拟器是一款高性能的系统模拟器， 可以模拟单处理器系统和多 处理器系统。 SIMICS模拟器模拟多处理器系统时， 釆用单一处理器调度方式 进行调度， 即每次调度一个处理器执行相应的指令， 以实现串行模拟多个处理 器。 然而， 由于每次调度一个处理器， 所以无法实现并行模拟多个处理器， 导 致了模拟效率的降低，同时现有技术中也无法实现并行模拟多个处理器时的调 试。
发明内容 本发明实施例提供一种并行模拟多个处理器的方法及系统、 调度器， 用 以提高模拟效率和实现并行模拟多个处理器时的调试。 一方面提供了一种并行模拟多个处理器的方法， 包括： 调度器将需要调试的待模拟的处理器的调试接口信息映射到所述调度器 上；
所述调度器利用主线程创建至少一个从线程，并确定所述主线程和所述至 少一个从线程对应的待模拟的处理器，得到确定的对应的待模拟的处理器， 其 中， 所述主线程对应的待模拟的处理器包括所述需要调试的待模拟的处理器； 所述调度器利用所述主线程和所述至少一个从线程， 通过第一运行接 口调用所述确定的对应的待模拟的处理器执行相应的指令， 并利用所述主 线程， 通过所述需要调试的待模拟的处理器的调试接口调试所述需要调试 的待模拟的处理器， 所述第一运行接口通过所述确定的对应的待模拟的处 理器向所述调度器注册， 所述调试接口信息指向所述调试接口。
另一方面提供了一种调度器， 包括：
映射单元，用于将需要调试的待模拟的处理器的调试接口信息映射到所述 调度器上；
创建单元， 用于利用主线程创建至少一个从线程， 并确定所述主线程和所 述至少一个从线程对应的待模拟的处理器， 得到确定的对应的待模拟的处理 器， 其中， 所述主线程对应的待模拟的处理器包括所述需要调试的待模拟的处 理器；
调用单元， 用于利用所述主线程和所述创建单元创建的所述至少一个 从线程， 通过第一运行接口调用所述创建单元确定的对应的待模拟的处理 器执行相应的指令， 并利用所述主线程， 通过所述需要调试的待模拟的处 理器的调试接口调试所述需要调试的待模拟的处理器， 所述第一运行接口 通过所述确定的对应的待模拟的处理器向所述调度器注册， 所述映射单元 映射的调试接口信息指向所述调试接口。 另一方面提供了一种并行模拟多个处理器的系统， 包括待模拟的处理器 和上述调度器。
由上述技术方案可知， 通过调度器利用主线程创建至少一个从线程， 并 确定上述主线程和上述至少一个从线程对应的待模拟的处理器， 使得调度 器能够利用上述主线程和上述至少一个从线程， 通过上述确定的对应的待 模拟的处理器向上述调度器注册的第一运行接口， 调用上述确定的对应的 待模拟的处理器执行相应的指令， 由于每次能够利用主线程和至少一个从 线程调度待模拟的处理器， 所以能够实现并行模拟多个处理器， 避免了现 有技术中由于每次调度一个待模拟的处理器而导致的无法实现并行模拟多 个处理器的问题， 从而提高了模拟效率； 同时能够充分利用调度器所在宿 主机的处理器资源， 从而提高了资源利用效率。 另外， 通过调度器将需要 调试的待模拟的处理器的调试接口信息映射到该调度器上， 使得调度器能 够利用主线程， 通过该调试接口信息指向的需要调试的待模拟的处理器的 调试接口调试该需要调试的待模拟的处理器， 实现了并行模拟多个处理器 时的调试。 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施 例或现有技术描述中所需要使用的附图作一简单地介绍， 显而易见地， 下面描 述中的附图是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出 创造性劳动的前提下， 还可以根据这些附图获得其他的附图。
图 1 为本发明一实施例提供的并行模拟多个处理器的方法的流程示意 图；
图 2为本发明另一实施例提供的并行模拟多个处理器的方法的流程示意 图；
图 3为图 2对应的实施例所适用的系统架构示意图；
图 4为本发明另一实施例提供的调度器的结构示意图；
图 5为本发明另一实施例提供的调度器的结构示意图；
图 6为本发明另一实施例提供的调度器的结构示意图；
图 7为本发明另一实施例提供的并行模拟多个处理器的系统的结构示意 图；
图 8为本发明另一实施例提供的并行模拟多个处理器的系统的结构示意 图；
图 9为本发明另一实施例提供的并行模拟多个处理器的系统的结构示意 图；
图 10 为本发明另一实施例提供的并行模拟多个处理器的系统的结构示 意图。 具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚， 下面将结合本发明 实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然， 所描述的实施例是本发明一部分实施例， 而不是全部的实施例。基于本发明中 的实施例 ,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其 他实施例， 都属于本发明保护的范围。 图 1为本发明一实施例提供的并行模拟多个处理器的方法的流程示意图， 如图 1所示， 本实施例的并行模拟多个处理器的方法可以包括：
101、 调度器将需要调试的待模拟的处理器的调试接口信息映射到该调度 器上；
102、 上述调度器利用主线程创建至少一个从线程， 并确定上述主线程和 上述至少一个从线程对应的待模拟的处理器，得到确定的对应的待模拟的处理 器；
其中，上述主线程对应的待模拟的处理器包括上述需要调试的待模拟的处 理器。
其中， 主线程只有一个，从线程最多可以等于调度器所在宿主机的处理器 的个数减去 1 , 以使得每个线程对应一个宿主机的处理器。
具体地， 调度器可以根据配置文件， 利用主线程创建至少一个从线程， 并 确定上述主线程和上述至少一个从线程对应的待模拟的处理器。配置文件中可 以包括但不限于创建从线程的个数、需要调试的待模拟的处理器的编号信息和 线程（主线程或从线程）与待模拟的处理器的映射关系。
103、 上述调度器利用上述主线程和上述至少一个从线程， 通过第一运行 接口 （ execute interface )调用上述确定的对应的待模拟的处理器执行相应的 指令， 并利用上述主线程， 通过上述需要调试的待模拟的处理器的调试接口调 试该需要调试的待模拟的处理器。
其中，上述第一运行接口通过上述确定的对应的待模拟的处理器向上述调 度器注册； 上述调试接口信息指向上述调试接口。
可以理解的是： 每个线程可以对应一个待模拟的处理器， 或者还可以对应 多个待模拟的处理器， 本实施例对此不进行限定， 但是， 主线程所对应的待模 拟的处理器中必须包含需要调试的待模拟的处理器。如果每个线程对应多个待 模拟的处理器， 在 102 中， 调度器每次通过主线程和从线程调度待模拟的处 理器执行相应的指令时， 则可以先并行调度每个线程中的一个待模拟的处理 器， 然后在每个线程内部再串行调度该线程中的其他待模拟的处理器。 指令， 用于访问同一内存或不同内存的指令； 访问外设的指令， 用于访问同一 外设或不同外设的指令。
可选地， 上述指令还可以为原子指令， 则在 102 中， 调度器具体可以利 用互斥锁操作， 调用上述确定的对应的待模拟的处理器执行相应的指令。
可选地， 本实施例中，调度器还可以进一步利用上述主线程和上述至少一 个从线程， 通过第一周期接口 （cycle interface ) 向上述确定的对应的待模拟 的处理器下发周期参数，以控制上述调度器利用上述主线程和上述至少一个从 线程同步调用对应的待模拟的处理器，从而保证了待模拟的处理器之间的调度 一致。其中， 上述第一周期接口通过上述确定的对应的待模拟的处理器向上述 调度器注册。
可选地， 上述 101 ~103的执行主体调度器可以为 SIMICS模拟器中的调 度单元。相应地，调度器可以将需要调试的待模拟的处理器的调试接口的地址 赋给该调度器的调试接口指针。 具体地， 可以包括但不限于下列情况中的至少 一项：
调度器将需要调试的待模拟的处理器的单步运行接口（ step interface )的 地址赋给该调度器的单步运行接口指针； 调度器将需要调试的待模拟的处理器的断点查询接口 （breakpoint query interface ) 的地址赋给该调度器的断点查询接口指针；
调度器将需要调试的待模拟的处理器的断点触发接口 （ breakpoint trigger interface ) 的地址赋给该调度器的物理内存触发器接口指针。
可选地，为了将操作者所设置的断点更新操作通知给需要调试的待模拟的 处理器， 调度器还可以进一步将需要调试的待模拟的处理器的断点控制接口 ( breakpoint change interface ) 的地址赋给该调度器的断点控制接口指针， 以使得调度器利用断点控制接口指针， 调用需要调试的待模拟的处理器， 以通 知断点更新操作， 例如： 设置断点、 取消断点等。
可选地， 为了获得断点信息，调度器还可以进一步将调度器的断点查询接 口 （ breakpoint query interface ) 的地址赋给需要调试的待模拟的处理器的断 点查询接口指针， 以使得需要调试的待模拟的处理器利用断点查询接口指针， 调用调度器， 以获得断点信息， 例如： 断点起始地址、 断点终止地址、 断点触 发属性等。
相应地， 为了触发调度器停止调用需要调试的待模拟的处理器， 调度器还 可以进一步将调度器的断点触发接口 （breakpoint trigger interface )的地址赋 给需要调试的待模拟的处理器的断点触发接口指针，以使得需要调试的待模拟 的处理器利用断点触发接口指针，调用调度器， 以触发调度器停止调用需要调 试的待模拟的处理器。 例如： 需要调试的待模拟的处理器获得断点信息之后， 在每个运行周期中，还可以进一步检查当前的运行状态是否符合断点信息所对 应的条件， 如果不符合， 需要调试的待模拟的处理器则继续运行下一个周期； 如果符合，需要调试的待模拟的处理器则利用断点触发接口指针，调用调度器。 可选地， 上述 101 ~103的执行主体调度器还可以为一个独立设置的控制 单元。相应地，调度器可以将需要调试的待模拟的处理器的调试接口的地址赋 给该调度器的调试接口指针，并将该调度器的调试接口指针赋给 SIMICS模拟 器的调试接口指针。 具体地， 可以包括但不限于下列情况中的至少一项： 调度器将需要调试的待模拟的处理器的单步运行接口的地址赋给该调度 器的单步运行接口指针，并将该调度器的单步运行接口指针赋给 SIMICS模拟 器的单步运行接口指针；
调度器将需要调试的待模拟的处理器的状态查询接口的地址赋给该调度 器的状态查询接口指针，并将该调度器的状态查询接口指针赋给 SIMICS模拟 器的状态查询接口指针；
调度器将需要调试的待模拟的处理器的状态设置接口的地址赋给该调度 器的状态设置接口指针，并将该调度器的状态设置接口指针赋给 SIMICS模拟 器的状态设置接口指针。
可选地，为了将操作者所设置的断点更新操作通知给需要调试的待模拟的 处理器，调度器还可以进一步将需要调试的待模拟的处理器的断点控制接口的 地址赋给该调度器的断点控制接口指针，并将该调度器的断点控制接口指针赋 给 SIMICS模拟器的断点控制接口指针，以使得 SIMICS模拟器利用断点控制 接口指针， 调用需要调试的待模拟的处理器， 以通知断点更新操作， 例如： 设 置断点、 取消断点等。
可选地， 为了获得断点信息， 调度器还可以进一步将 SIMICS模拟器的断 点查询接口的地址赋给调度器的断点查询接口指针，以使得调度器利用断点查 询接口指针， 调用 SIMICS模拟器， 以获得断点信息， 例如： 断点起始地址、 断点终止地址、 断点触发属性等。
相应地， 为了触发调度器停止调用需要调试的待模拟的处理器， 调度器还 可以进一步将 SIMICS模拟器的断点触发接口的地址赋给调度器的断点触发 接口指针， 以使得调度器利用断点触发接口指针， 调用 SIMICS模拟器， 以触 发调度器停止调用需要调试的待模拟的处理器。例如： 调度器获得断点信息之 后，在每个运行周期中，还可以进一步检查需要调试的待模拟的处理器当前的 运行状态是否符合断点信息所对应的条件，如果不符合， 需要调试的待模拟的 处理器则继续运行下一个周期； 如果符合， 调度器则利用断点触发接口指针， 调用 SIMICS模拟器。
可选地， 为了获得断点信息， 调度器还可以进一步将 SIMICS模拟器的断 点查询接口的地址赋给调度器的断点查询接口指针，并将调度器的断点查询接 口指针赋给需要调试的待模拟的处理器的断点查询接口指针，以使得需要调试 的待模拟的处理器利用断点查询接口指针， 调用 SIMICS模拟器， 以获得断点 信息， 例如： 断点起始地址、 断点终止地址、 断点触发属性等。
相应地， 为了触发调度器停止调用需要调试的待模拟的处理器， 调度器还 可以进一步将 SIMICS模拟器的断点触发接口的地址赋给调度器的断点触发 接口指针，并将调度器的断点触发接口指针赋给需要调试的待模拟的处理器的 断点触发接口指针， 以使得需要调试的待模拟的处理器利用断点触发接口指 针， 调用 SIMICS模拟器， 以触发 SIMICS模拟器停止调用需要调试的待模拟 的处理器。 例如： 需要调试的待模拟的处理器获得断点信息之后， 在每个运行 周期中， 还可以进一步检查当前的运行状态是否符合断点信息所对应的条件， 如果不符合， 需要调试的待模拟的处理器则继续运行下一个周期； 如果符合， 需要调试的待模拟的处理器则利用断点触发接口指针， 调用 SIMICS模拟器。 进一步地，调度器还可以进一步向 SIMICS模拟器中的调度单元注册对应 的第二运行接口，以使上述调度单元通过上述第二运行接口调度上述调度器利 用主线程创建至少一个从线程。 相应地， 调度器还可以进一步向上述 SIMICS 模拟器中的调度单元注册对应的第二周期接口，以使上述调度单元利用上述主 线程，通过上述第二周期接口向上述调度器下发周期参数， 以使上述调度器利 用上述主线程和上述至少一个从线程，通过第一周期接口向上述确定的对应的 待模拟的处理器下发上述周期参数，以控制上述调度器利用上述主线程和上述 至少一个从线程同步调用对应的待模拟的处理器，上述第一周期接口通过上述 确定的对应的待模拟的处理器向上述调度器注册。
本实施例中，通过调度器利用主线程创建至少一个从线程， 并确定上述主 线程和上述至少一个从线程对应的待模拟的处理器，使得调度器能够利用上述 主线程和上述至少一个从线程，通过上述确定的对应的待模拟的处理器向上述 调度器注册的第一运行接口，调用上述确定的对应的待模拟的处理器执行相应 的指令， 由于每次能够利用主线程和至少一个从线程调度待模拟的处理器， 所 以能够实现并行模拟多个处理器，避免了现有技术中由于每次调度一个待模拟 的处理器而导致的无法实现并行模拟多个处理器的问题， 从而提高了模拟效 率； 同时能够充分利用调度器所在宿主机的处理器资源，从而提高了资源利用 效率。 另外， 通过调度器将需要调试的待模拟的处理器的调试接口信息映射到 该调度器上，使得调度器能够利用主线程，通过该调试接口信息指向的需要调 试的待模拟的处理器的调试接口调试该需要调试的待模拟的处理器，实现了并 行模拟多个处理器时的调试。 为使得本发明实施例提供的方法更加清楚， 下面将以 101 ~103的执行主 体调度器为一个独立设置的控制 （Controller )单元作为举例。 图 2为本发明 另一实施例提供的并行模拟多个处理器的方法的流程示意图，本实施例所适用 的系统架构可以如图 3所示。如图 2所示，本实施例的并行模拟多个处理器的 方法可以包括：
201、 控制单元创建一个调试对象， 该调试对象的数据结构与待模拟的处 理器的数据结构一致，并将需要调试的待模拟的处理器的调试接口的地址赋给 该控制单元创建的调试对象的调试接口指针，以及将该控制单元创建的调试对 象的调试接口指针赋给 SIMICS模拟器的调试接口指针；
其中，调试接口可以包括但不限于单步运行接口、状态查询接口和状态设 置接口中的至少一项。
可选地，控制单元还可以进一步将需要调试的待模拟的处理器的断点控制 接口的地址赋给该调度器的断点控制接口指针，并将该调度器的断点控制接口 指针赋给 SIMICS模拟器的断点控制接口指针，以使得 SIMICS模拟器利用断 点控制接口指针， 调用需要调试的待模拟的处理器， 以通知断点更新操作， 例 如： 设置断点、 取消断点等。
可选地，控制单元还可以进一步将 SIMICS模拟器的断点查询接口的地址 赋给控制单元的断点查询接口指针，并将控制单元的断点查询接口指针赋给需 要调试的待模拟的处理器的断点查询接口指针，以使得需要调试的待模拟的处 理器利用断点查询接口指针， 调用 SIMICS模拟器， 以获得断点信息， 例如： 断点起始地址、 断点终止地址、 断点触发属性等。
相应地，控制单元还可以进一步将 SIMICS模拟器的断点触发接口的地址 赋给控制单元的断点触发接口指针，并将控制单元的断点触发接口指针赋给需 要调试的待模拟的处理器的断点触发接口指针，以使得需要调试的待模拟的处 理器利用断点触发接口指针， 调用 SIMICS模拟器， 以触发 SIMICS模拟器停 止调用需要调试的待模拟的处理器。例如： 需要调试的待模拟的处理器获得断 点信息之后，在每个运行周期中，还可以进一步检查当前的运行状态是否符合 断点信息所对应的条件， 如果不符合， 需要调试的待模拟的处理器则继续运行 下一个周期；如果符合，需要调试的待模拟的处理器则利用断点触发接口指针， 调用 SIMICS模拟器。
202、 控制单元向 SIMICS模拟器中的调度单元注册该控制单元对应的运 行接口和周期接口；
203、 待模拟的处理器向控制单元注册该待模拟的处理器对应的运行接口 和周期接口；
204、 控制单元根据配置文件， 利用主线程创建至少一个从线程， 并确定 上述主线程和上述至少一个从线程对应的待模拟的处理器，以及在所在宿主机 上为待模拟的处理器申请内存；
例如： 主线程对应待模拟的处理器 0和待模拟的处理器 6, 其中， 待模拟 的处理器 0为需要调试的待模拟的处理器，即可以记为需要调试的待模拟的处 理器 0;
从线程 1对应待模拟的处理器 1和待模拟的处理器 3;
从线程 2对应待模拟的处理器 2和待模拟的处理器 4;
从线程 3对应待模拟的处理器 5和待模拟的处理器 7。
可选地， 控制单元可以在所在宿主机上为待模拟的处理器申请同一个内 存， 用以实现模拟多个待模拟的处理器共同访问同一内存， 或者还可以在所在 宿主机上为待模拟的处理器申请不同内存，用以实现模拟多个待模拟的处理器 访问不同内存。
205、 调度单元利用主线程， 调用控制单元注册的运行接口；
206、 控制单元利用主线程和创建的至少一个从线程， 调用待模拟的处理 器注册的运行接口， 以调用对应的待模拟的处理器执行相应的指令；
例如：控制单元利用主线程，调用需要调试的待模拟的处理器 0注册的运 行接口， 再调用待模拟的处理器 6注册的运行接口；
控制单元利用从线程 1 , 调用待模拟的处理器 1注册的运行接口， 再调用 待模拟的处理器 3注册的运行接口；
控制单元利用从线程 2, 调用待模拟的处理器 2注册的运行接口， 再调用 待模拟的处理器 4注册的运行接口；
控制单元利用从线程 3, 调用待模拟的处理器 5注册的运行接口， 再调用 待模拟的处理器 7注册的运行接口。
207、 如果控制单元在 206中所调用的是需要调试的待模拟的处理器， 该 需要调试的待模拟的处理器检查当前的运行状态是否符合断点信息所对应的 条件， 如果不符合， 需要调试的待模拟的处理器则继续运行下一个周期； 如果 符合， 需要调试的待模拟的处理器则利用断点触发接口指针， 调用 SIMICS模 拟器， 以触发 SIMICS模拟器停止调用需要调试的待模拟的处理器；
如果控制单元在 206 中所调用的不是需要调试的待模拟的处理器， 结束 流程。
208、 SIMICS模拟器的调度单元根据操作者的单步执行指令， 利用单步 运行接口指针、 状态查询指针和状态设置指针中的至少一个， 调用控制单元； 209、 控制单元利用上述主线程， 利用对应的接口指针， 调试该需要调试 的待模拟的处理器。
例如： 操作者通过 SIMICS模拟器的调度单元设置断点后， SIMICS模拟 器则可以利用断点控制接口指针，调用需要调试的待模拟的处理器， 以通知断 点设置操作。 相应地， 需要调试的待模拟的处理器则利用断点查询接口指针， 调用 SIMICS模拟器， 以获得断点信息， 例如： 断点起始地址、断点终止地址、 断点触发属性等。 需要调试的待模拟的处理器获得断点信息之后，在每个运行 周期中， 检查当前的运行状态是否符合断点信息所对应的条件， 如果不符合， 需要调试的待模拟的处理器则继续运行下一个周期； 如果符合， 需要调试的待 模拟的处理器则利用断点触发接口指针，调用 SIMICS模拟器，以触发 SIMICS 模拟器停止调用需要调试的待模拟的处理器。 然后， SIMICS模拟器的调度单 元根据操作者的单步执行指令， 利用单步运行接口指针、状态查询指针和状态 设置指针中的至少一个， 调试该需要调试的待模拟的处理器。
可选地， 在 205 中， 调度单元还可以进一步利用主线程， 调用控制单元 注册的周期接口， 以向控制单元下发周期参数 （例如： 处理器切换时间 ( cpu-switch-time )参数， 用于指示执行指令的指定条数等）， 以使该控制单 元进一步利用主线程和创建的至少一个从线程，调用待模拟的处理器注册的周 期接口， 以向待模拟的处理器下发时间推进的目标值， 用以控制上述主线程和 上述至少一个从线程调用对应的待模拟的处理器的同步， 例如： 从线程上的待 模拟的处理器执行完指定条数的指令之后通知主线程上的控制单元，并进入睡 眠状态；主线程上的控制单元接收到全部的从线程上的待模拟的处理器的通知 之后， 退出运行接口， 等待重新执行 205。
本实施例中，通过控制单元被 SIMICS模拟器中的调度单元调用之后利用 主线程创建至少一个从线程 ,并确定上述主线程和上述至少一个从线程对应的 待模拟的处理器， 使得控制单元能够利用上述主线程和上述至少一个从线程， 通过待模拟的处理器向上述控制单元注册的第一运行接口，调用上述确定的对 应的待模拟的处理器执行相应的指令，由于每次能够利用主线程和至少一个从 线程调度待模拟的处理器， 所以能够实现并行模拟多个处理器，避免了现有技 术中由于每次调度一个待模拟的处理器而导致的无法实现并行模拟多个处理 器的问题，从而提高了模拟效率； 同时能够充分利用调度器所在宿主机的处理 器资源， 从而提高了资源利用效率。 另外， 通过控制单元将需要调试的待模拟 的处理器的调试接口信息映射到该控制单元创建的调试对象上，使得控制单元 能够利用主线程，通过该调试接口信息指向的需要调试的待模拟的处理器的调 试接口调试该需要调试的待模拟的处理器，实现了并行模拟多个处理器时的调 试。
需要说明的是： 对于前述的各方法实施例， 为了简单描述， 故将其都表述 为一系列的动作组合，但是本领域技术人员应该知悉， 本发明并不受所描述的 动作顺序的限制，因为依据本发明，某些步骤可以釆用其他顺序或者同时进行。 其次， 本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施 例， 所涉及的动作和模块并不一定是本发明所必须的。
在上述实施例中，对各个实施例的描述都各有侧重， 某个实施例中没有详 述的部分， 可以参见其他实施例的相关描述。
图 4为本发明另一实施例提供的调度器的结构示意图，如图 4所示，本实 施例的调度器可以包括映射单元 41、 创建单元 42和调用单元 43。 其中， 映 射单元 41用于将需要调试的待模拟的处理器的调试接口信息映射到该调度器 上； 创建单元 42用于利用主线程创建至少一个从线程， 并确定上述主线程和 上述至少一个从线程对应的待模拟的处理器，得到确定的对应的待模拟的处理 器， 其中， 上述主线程对应的待模拟的处理器包括上述需要调试的待模拟的处 理器； 调用单元 43用于利用上述主线程和上述创建单元创建的上述至少一个 从线程，通过第一运行接口调用上述创建单元确定的对应的待模拟的处理器执 行相应的指令， 并利用上述主线程，通过上述需要调试的待模拟的处理器的调 试接口调试该需要调试的待模拟的处理器。
其中，上述第一运行接口通过上述确定的对应的待模拟的处理器向上述调 度器注册， 上述映射单元映射的调试接口信息指向上述调试接口。
上述图 1 对应的实施例中调度器的功能可以由本实施例提供的调度器实 现。
可选地， 本实施例中的调用单元 43调用上述创建单元确定的对应的待模 存的指令， 用于访问同一内存或不同内存的指令； 访问外设的指令， 用于访问 同一外设或不同外设的指令。
可选地， 本实施例中的调用单元 43调用上述创建单元确定的对应的待模 拟的处理器执行相应的指令还可以为原子指令， 则调用单元 43具体可以利用 互斥锁操作， 调用上述创建单元确定的对应的待模拟的处理器执行相应的指 令。
可选地， 调用单元 43还可以进一步利用上述主线程和上述至少一个从线 程， 通过第一周期接口 （cycle interface ) 向上述确定的对应的待模拟的处理 器下发周期参数，以控制上述调度器利用上述主线程和上述至少一个从线程同 步调用对应的待模拟的处理器， 从而保证了待模拟的处理器之间的调度一致。 其中，上述第一周期接口通过上述确定的对应的待模拟的处理器向上述调度器 注册。
可选地， 本实施例提供的调度器可以为 SIMICS模拟器中的调度单元。相 应地， 本实施例中的映射单元 41具体可以将需要调试的待模拟的处理器的调 试接口的地址赋给该调度器的调试接口指针。 例如： 如图 5 所示， 映射单元 41可以包括但不限于下列子单元中的至少一个：
第一映射子单元 51 , 用于将需要调试的待模拟的处理器的单步运行接口 的地址赋给上述调度器的单步运行接口指针；
第二映射子单元 52 , 用于将需要调试的待模拟的处理器的状态查询接口 的地址赋给上述调度器的状态查询接口指针；
第三映射子单元 53 , 用于将需要调试的待模拟的处理器的状态设置接口 的地址赋给上述调度器的状态设置接口指针。
需要指出的是， 图 5中仅示出了同时包括第一映射子单元 51、 第二映 射子单元 52和第三映射子单元 53的情况， 在可选的实施例中， 也可以仅 包括上述三个子单元中的任意一个和两个。
可选地， 如图 6所示， 本实施例中的映射单元 41还可以进一步包括第 四映射子单元 61 , 用于将需要调试的待模拟的处理器的断点控制接口的地 址赋给所述调度器的断点控制接口指针。
可选地， 本实施例中的映射单元 41还可以进一步用于将所述调度器的断 点查询接口的地址赋给需要调试的待模拟的处理器的断点查询接口指针；以及 将所述调度器的断点触发接口的地址赋给需要调试的待模拟的处理器的断点 触发接口指针。
可选地， 本实施例提供的调度器还可以为一个独立设置的控制单元。相应 地， 本实施例中的映射单元 41具体可以将需要调试的待模拟的处理器的调试 接口的地址赋给该调度器的调试接口指针，并将该调度器的调试接口指针赋给 SIMICS模拟器的调试接口指针。 例如： 如图 7所示， 映射单元 41可以包括 但不限于下列子单元中的至少一个：
第五映射子单元 71 , 用于将需要调试的待模拟的处理器的单步运行接口 的地址赋给上述调度器的单步运行接口指针，并将该调度器的单步运行接口指 针赋给 SIMICS模拟器的单步运行接口指针；
第六映射子单元 72, 用于将需要调试的待模拟的处理器的状态查询接口 的地址赋给上述调度器的状态查询接口指针，并将该调度器的状态查询接口指 针赋给 SIMICS模拟器的状态查询接口指针；
第七映射子单元 73, 用于将需要调试的待模拟的处理器的状态设置接口 的地址赋给上述调度器的状态设置接口指针，并将该调度器的状态设置接口指 针赋给 SIMICS模拟器的状态设置接口指针。
需要指出的是， 图 7中仅示出了同时包括第五映射子单元 71、 第六映 射子单元 72和第七映射子单元 73的情况， 在可选的实施例中， 也可以仅 包括上述三个子单元中的任意一个和两个。
可选地， 如图 8所示， 本实施例中的映射单元 41还可以进一步包括第 八映射子单元 81 , 用于将需要调试的待模拟的处理器的断点控制接口的地 址赋给所述调度器的断点控制接口指针， 并将该调度器的断点控制接口指 针赋给 SIMICS模拟器的断点控制接口指针。
可选地， 本实施例中的映射单元 41还可以进一步将 SIMICS模拟器的断 点查询接口的地址赋给所述调度器的断点查询接口指针；以及将 SIMICS模拟 器的断点触发接口的地址赋给所述调度器的断点触发接口指针，以使得调度器 检查需要调试的待模拟的处理器的运行状态是否符合断点信息所对应的条件。
可选地， 本实施例中的映射单元 41还可以进一步将所述调度器的断点查 询接口指针赋给需要调试的待模拟的处理器的断点查询接口指针；以及将所述 调度器的断点触发接口指针赋给该调度器的断点触发接口指针，以使得需要调 试的待模拟的处理器检查自身的运行状态是否符合断点信息所对应的条件。
进一步地，如图 9所示，本实施例提供的调度器还可以进一步包括注册单 元 91 , 用于向 SIMICS模拟器中的调度单元注册对应的第二运行接口， 以使 上述调度单元通过上述第二运行接口调度上述调度器利用主线程创建至少一 个从线程。
相应地， 注册单元 91还可以进一步向上述 SIMICS模拟器中的调度单元 注册对应的第二周期接口， 以使上述调度单元利用上述主线程， 通过上述第二 周期接口向上述调度器下发周期参数，以使上述调用单元利用上述主线程和上 述至少一个从线程，通过第一周期接口向上述确定的对应的待模拟的处理器下 发上述周期参数，以控制上述调用单元利用上述主线程和上述至少一个从线程 同步调用对应的待模拟的处理器。其中， 上述第一周期接口通过上述确定的对 应的待模拟的处理器向上述调度器注册。
本实施例中，调度器通过创建单元利用主线程创建至少一个从线程， 并确 定上述主线程和上述至少一个从线程对应的待模拟的处理器，使得调用单元能 够利用上述主线程和上述至少一个从线程，通过上述创建单元确定的对应的待 模拟的处理器向上述调度器注册的第一运行接口，调用上述创建单元确定的对 应的待模拟的处理器执行相应的指令，由于每次能够利用主线程和至少一个从 线程调度待模拟的处理器， 所以能够实现并行模拟多个处理器，避免了现有技 术中由于每次调度一个待模拟的处理器而导致的无法实现并行模拟多个处理 器的问题，从而提高了模拟效率； 同时能够充分利用调度器所在宿主机的处理 器资源， 从而提高了资源利用效率。 另外， 通过映射单元将需要调试的待模拟 的处理器的调试接口信息映射到该控制单元创建的调试对象上，使得调用单元 能够利用主线程，通过该调试接口信息指向的需要调试的待模拟的处理器的调 试接口调试该需要调试的待模拟的处理器，实现了并行模拟多个处理器时的调 试。
图 10 为本发明另一实施例提供的并行模拟多个处理器的系统的结构示 意图， 如图 10所示， 本实施例的并行模拟多个处理器的系统可以包括待模 拟的处理器 1001和调度器 1002。 其中， 调度器可以为图 4、 图 5、 图 6、 图 7、 图 8和图 9对应的实施例中任一实施例提供的调度器， 详细描述可以参见 对应实施例中的相关内容， 此处不再赘述。
本实施例中，通过调度器利用主线程创建至少一个从线程， 并确定上述主 线程和上述至少一个从线程对应的待模拟的处理器，使得调度器能够利用上述 主线程和上述至少一个从线程，通过上述调度器确定的对应的待模拟的处理器 向上述调度器注册的第一运行接口，调用上述调度器确定的对应的待模拟的处 理器执行相应的指令，由于每次能够利用主线程和至少一个从线程调度待模拟 的处理器， 所以能够实现并行模拟多个处理器，避免了现有技术中由于每次调 度一个待模拟的处理器而导致的无法实现并行模拟多个处理器的问题，从而提 高了模拟效率； 同时能够充分利用调度器所在宿主机的处理器资源，从而提高 了资源利用效率。 另外，通过调度器将需要调试的待模拟的处理器的调试接口 信息映射到该调度器上，使得调度器能够利用主线程，通过该调试接口信息指 向的需要调试的待模拟的处理器的调试接口调试该需要调试的待模拟的处理 器， 实现了并行模拟多个处理器时的调试。
所属领域的技术人员可以清楚地了解到， 为描述的方便和简洁， 上述描述 的系统 ,装置和单元的具体工作过程 ,可以参考前述方法实施例中的对应过程 , 在此不再赘述。
在本申请所提供的几个实施例中， 应该理解到， 所揭露的系统， 装置和方 法， 可以通过其它的方式实现。 例如， 以上所描述的装置实施例仅仅是示意性 的， 例如， 所述单元的划分， 仅仅为一种逻辑功能划分， 实际实现时可以有另 外的划分方式， 例如多个单元或组件可以结合或者可以集成到另一个系统， 或 一些特征可以忽略， 或不执行。 另一点， 所显示或讨论的相互之间的耦合或直 接耦合或通信连接可以是通过一些接口， 装置或单元的间接耦合或通信连接， 可以是电性， 机械或其它的形式。 单元显示的部件可以是或者也可以不是物理单元， 即可以位于一个地方， 或者 也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部 单元来实现本实施例方案的目的。
另外， 在本发明各个实施例中的各功能单元可以集成在一个处理单元中， 也可以是各个单元单独物理存在 ,也可以两个或两个以上单元集成在一个单元 中。上述集成的单元既可以釆用硬件的形式实现， 也可以釆用硬件加软件功能 单元的形式实现。
上述以软件功能单元的形式实现的集成的单元，可以存储在一个计算机可 读取存储介质中。 上述软件功能单元存储在一个存储介质中， 包括若干指令用 以使得一台计算机设备（可以是个人计算机， 服务器， 或者网络设备等）执行 本发明各个实施例所述方法的部分步骤。 而前述的存储介质包括： U盘、 移动 硬盘、 只读存储器 （Read-Only Memory, 简称 ROM )、 随机存取存储器 ( Random Access Memory, 简称 RAM )、磁碟或者光盘等各种可以存储程序 代码的介质。
最后应说明的是： 以上实施例仅用以说明本发明的技术方案， 而非对其限 制； 尽管参照前述实施例对本发明进行了详细的说明， 本领域的普通技术人员 应当理解： 其依然可以对前述各实施例所记载的技术方案进行修改， 或者对其 中部分技术特征进行等同替换； 而这些修改或者替换， 并不使相应技术方案的 本质脱离本发明各实施例技术方案的精神和范围。

Claims

权 利 要 求
1、 一种并行模拟多个处理器的方法， 其特征在于， 包括：
调度器将需要调试的待模拟的处理器的调试接口信息映射到所述调度器 上；
所述调度器利用主线程创建至少一个从线程，并确定所述主线程和所述至 少一个从线程对应的待模拟的处理器，得到确定的对应的待模拟的处理器， 其 中， 所述主线程对应的待模拟的处理器包括所述需要调试的待模拟的处理器； 所述调度器利用所述主线程和所述至少一个从线程，通过第一运行接口调 用所述确定的对应的待模拟的处理器执行相应的指令， 并利用所述主线程，通 过所述需要调试的待模拟的处理器的调试接口调试所述需要调试的待模拟的 处理器，所述第一运行接口通过所述确定的对应的待模拟的处理器向所述调度 器注册， 所述调试接口信息指向所述调试接口。
2、根据权利要求 1所述的方法， 其特征在于， 所述指令包括下列指令中的 至少一个：
访问内存的指令， 用于访问同一内存或不同内存的指令；
访问外设的指令， 用于访问同一外设或不同外设的指令。
3、 根据权利要求 1所述的方法， 其特征在于， 所述指令为原子指令， 所述 调度器调用所述确定的对应的待模拟的处理器执行相应的指令， 包括：
所述调度器利用互斥锁操作，调用所述确定的对应的待模拟的处理器执行 相应的指令。
4、 根据权利要求 1所述的方法， 其特征在于， 所述方法还包括： 所述调度器利用利用所述主线程和所述至少一个从线程，通过第一周期接 口向所述确定的对应的待模拟的处理器下发周期参数，以控制所述调度器利用 所述主线程和所述至少一个从线程同步调用所述确定的对应的待模拟的处理 器，所述第一周期接口通过所述确定的对应的待模拟的处理器向所述调度器注 册。
5、 根据权利要求 1至 4任一权利要求所述的方法， 其特征在于， 所述调度 器为 SIMICS模拟器中的调度单元。
6、根据权利要求 5所述的方法， 其特征在于， 所述调度器将需要调试的待 模拟的处理器的调试接口信息映射到所述调度器上，包括下列情况中的至少一 项：
所述调度器将需要调试的待模拟的处理器的单步运行接口的地址赋给所 述调度器的单步运行接口指针；
所述调度器将需要调试的待模拟的处理器的状态查询接口的地址赋给所 述调度器的状态查询接口指针；
所述调度器将需要调试的待模拟的处理器的状态设置接口的地址赋给所 述调度器的状态设置接口指针。
7、根据权利要求 6所述的方法， 其特征在于， 所述调度器将需要调试的待 模拟的处理器的调试接口信息映射到所述调度器上， 进一步包括：
所述调度器将需要调试的待模拟的处理器的断点控制接口的地址赋给所 述调度器的断点控制接口指针。
8、 根据权利要求 7所述的方法， 其特征在于， 所述方法还包括： 所述调度器将所述调度器的断点查询接口的地址赋给需要调试的待模拟 的处理器的断点查询接口指针； 以及 所述调度器将所述调度器的断点触发接口的地址赋给需要调试的待模拟 的处理器的断点触发接口指针。
9、 根据权利要求 1至 4任一权利要求所述的方法， 其特征在于， 所述调度 器将需要调试的待模拟的处理器的调试接口信息映射到所述调度器上，包括下 列情况中的至少一项：
所述调度器将需要调试的待模拟的处理器的单步运行接口的地址赋给所 述调度器的单步运行接口指针， 并将所述调度器的单步运行接口指针赋给 SIMICS模拟器的单步运行接口指针；
所述调度器将需要调试的待模拟的处理器的状态查询接口的地址赋给所 述调度器的状态查询接口指针， 并将所述调度器的状态查询接口指针赋给 SIMICS模拟器的状态查询接口指针；
所述调度器将需要调试的待模拟的处理器的状态设置接口的地址赋给所 述调度器的状态设置接口指针， 并将所述调度器的状态设置接口指针赋给 SIMICS模拟器的状态设置接口指针。
10、 根据权利要求 9所述的方法， 其特征在于， 所述调度器将需要调试的 待模拟的处理器的调试接口信息映射到所述调度器上， 进一步包括：
所述调度器将需要调试的待模拟的处理器的断点控制接口的地址赋给所 述调度器的断点控制接口指针， 并将所述调度器的断点控制接口指针赋给 SIMICS模拟器的断点控制接口指针。
1 1、 根据权利要求 10所述的方法， 其特征在于， 所述方法还包括： 所述调度器将 SIMICS模拟器的断点查询接口的地址赋给所述调度器的断 点查询接口指针； 以及 所述调度器将 SIMICS模拟器的断点触发接口的地址赋给所述调度器的断 点触发接口指针。
12、 根据权利要求 1 1所述的方法， 其特征在于， 所述方法还包括： 所述调度器将所述调度器的断点查询接口指针赋给需要调试的待模拟的 处理器的断点查询接口指针； 以及
所述调度器将所述调度器的断点触发接口指针赋给所述调度器的断点触 发接口指针。
13、 根据权利要求 1至 4任一权利要求所述的方法， 其特征在于， 所述方 法还包括：
所述调度器向 SIMICS模拟器中的调度单元注册对应的第二运行接口， 以 使所述调度单元通过所述第二运行接口调度所述调度器利用主线程创建至少 一个从线程。
14、 根据权利要求 13所述的方法， 其特征在于， 所述方法还包括： 所述调度器向所述 SIMICS模拟器中的调度单元注册对应的第二周期接 口， 以使所述调度单元利用所述主线程，通过所述第二周期接口向所述调度器 下发周期参数， 以使所述调度器利用所述主线程和所述至少一个从线程，通过 第一周期接口向所述确定的对应的待模拟的处理器下发所述周期参数，以控制 所述调度器利用所述主线程和所述至少一个从线程同步调用所述确定的对应 的待模拟的处理器，所述第一周期接口通过所述确定的对应的待模拟的处理器 向所述调度器注册。
15、 根据权利要求 1至 4任一权利要求所述的方法， 其特征在于， 所述方 法还包括： 所述调度器获得断点信息，用以当所述需要调试的待模拟的处理器的运行 状态满足所述断点信息时，触发所述调度器利用所述主线程，通过所述需要调 试的待模拟的处理器的调试接口调试所述需要调试的待模拟的处理器； 或者 所述需要调试的待模拟的处理器获得断点信息，用以当所述需要调试的待 模拟的处理器的运行状态满足所述断点信息时，触发所述调度器利用所述主线 程，通过所述需要调试的待模拟的处理器的调试接口调试所述需要调试的待模 拟的处理器。
16、 一种调度器， 其特征在于， 包括：
映射单元，用于将需要调试的待模拟的处理器的调试接口信息映射到所述 调度器上；
创建单元， 用于利用主线程创建至少一个从线程， 并确定所述主线程和所 述至少一个从线程对应的待模拟的处理器， 得到确定的对应的待模拟的处理 器， 其中， 所述主线程对应的待模拟的处理器包括所述需要调试的待模拟的处 理器；
调用单元，用于利用所述主线程和所述创建单元创建的所述至少一个从线 程，通过第一运行接口调用所述创建单元确定的对应的待模拟的处理器执行相 应的指令， 并利用所述主线程，通过所述需要调试的待模拟的处理器的调试接 口调试所述需要调试的待模拟的处理器，所述第一运行接口通过所述确定的对 应的待模拟的处理器向所述调度器注册，所述映射单元映射的调试接口信息指 向所述调试接口。
17、 根据权利要求 16所述的调度器， 其特征在于， 所述调用单元调用所 述创建单元确定的对应的待模拟的处理器执行相应的指令包括下列指令中的 至少一个：
访问内存的指令， 用于访问同一内存或不同内存的指令；
访问外设的指令， 用于访问同一外设或不同外设的指令。
18、 根据权利要求 16所述的调度器， 其特征在于， 所述调用单元调用所 述创建单元确定的对应的待模拟的处理器执行相应的指令为原子指令，所述调 用单元具体用于
利用互斥锁操作，调用所述创建单元确定的对应的待模拟的处理器执行相 应的指令。
19、 根据权利要求 16所述的调度器， 其特征在于， 所述调用单元还用于 利用所述主线程和所述至少一个从线程，通过第一周期接口向所述确定的 对应的待模拟的处理器下发周期参数，以控制所述调度器利用所述主线程和所 述至少一个从线程同步调用所述确定的对应的待模拟的处理器，所述第一周期 接口通过所述确定的对应的待模拟的处理器向所述调度器注册。
20、 根据权利要求 16至 19任一权利要求所述的调度器， 其特征在于， 所 述调度器为 SIMICS模拟器中的调度单元。
21、 根据权利要求 20所述的调度器， 其特征在于， 所述映射单元包括下 列子单元中的至少一个：
第一映射子单元，用于将需要调试的待模拟的处理器的单步运行接口的地 址赋给所述调度器的单步运行接口指针；
第二映射子单元，用于将需要调试的待模拟的处理器的状态查询接口的地 址赋给所述调度器的状态查询接口指针；
第三映射子单元，用于将需要调试的待模拟的处理器的状态设置接口的地 址赋给所述调度器的状态设置接口指针。
22、 根据权利要求 21所述的调度器， 其特征在于， 所述映射单元还包括： 第四映射子单元，用于将需要调试的待模拟的处理器的断点控制接口的地 址赋给所述调度器的断点控制接口指针。
23、 根据权利要求 22所述的调度器， 其特征在于， 所述映射单元还用于 将所述调度器的断点查询接口的地址赋给需要调试的待模拟的处理器的 断点查询接口指针； 以及
将所述调度器的断点触发接口的地址赋给需要调试的待模拟的处理器的 断点触发接口指针。
24、 根据权利要求 16至 19任一权利要求所述的调度器， 其特征在于， 所 述映射单元包括下列子单元中的至少一个：
第五映射子单元，用于将需要调试的待模拟的处理器的单步运行接口的地 址赋给所述调度器的单步运行接口指针，并将所述调度器的单步运行接口指针 赋给 S I M I CS模拟器的单步运行接口指针；
第六映射子单元，用于将需要调试的待模拟的处理器的状态查询接口的地 址赋给所述调度器的状态查询接口指针，并将所述调度器的状态查询接口指针 赋给 S I M I CS模拟器的状态查询接口指针；
第七映射子单元，用于将需要调试的待模拟的处理器的状态设置接口的地 址赋给所述调度器的状态设置接口指针，并将所述调度器的状态设置接口指针 赋给 S I M I CS模拟器的状态设置接口指针。
25、 根据权利要求 24所述的调度器， 其特征在于， 所述映射单元还包括： 第八映射子单元，用于将需要调试的待模拟的处理器的断点控制接口的地 址赋给所述调度器的断点控制接口指针，并将所述调度器的断点控制接口指针 赋给 SIMICS模拟器的断点控制接口指针。
26、 根据权利要求 25所述的调度器， 其特征在于， 所述映射单元还用于 将 SIMICS模拟器的断点查询接口的地址赋给所述调度器的断点查询接口 指针； 以及
将 SIMICS模拟器的断点触发接口的地址赋给所述调度器的断点触发接口 指针。
27、 根据权利要求 26所述的调度器， 其特征在于， 所述映射单元还用于 将所述调度器的断点查询接口指针赋给需要调试的待模拟的处理器的断 点查询接口指针； 以及
将所述调度器的断点触发接口指针赋给所述调度器的断点触发接口指针。
28、 根据权利要求 16至 19任一权利要求所述的调度器， 其特征在于， 所 述调度器还包括注册单元， 用于
向 SIMICS模拟器中的调度单元注册对应的第二运行接口， 以使所述调度 单元通过所述第二运行接口调度所述调度器利用主线程创建至少一个从线程。
29、 根据权利要求 28所述的调度器， 其特征在于， 所述注册单元还用于 向所述 SIMICS模拟器中的调度单元注册对应的第二周期接口， 以使所述 调度单元利用所述主线程， 通过所述第二周期接口向所述调度器下发周期参 数， 以使所述调用单元利用所述主线程和所述至少一个从线程， 通过第一周期 接口向所述确定的对应的待模拟的处理器下发所述周期参数，以控制所述调度 器利用所述主线程和所述至少一个从线程同步调用所述确定的对应的待模拟 的处理器，所述第一周期接口通过所述确定的对应的待模拟的处理器向所述调 度器注册。
30、 根据权利要求 16至 19任一权利要求所述的调度器， 其特征在于， 调 用单元还用于 获得断点信息，用以当所述需要调试的待模拟的处理器的运行状态满足所 述断点信息时，触发所述调度器利用所述主线程， 通过所述需要调试的待模拟 的处理器的调试接口调试所述需要调试的待模拟的处理器； 或者
31、一种并行模拟多个处理器的系统，包括待模拟的处理器，其特征在于， 还包括权利要求 16~30任一权利要求所述的调度器。
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